Planar gate power devices and their manufacturing methods

Abstract

This invention discloses a planar gate power device, comprising: a JFET region doped with a first conductivity type formed in a semiconductor epitaxial layer doped with a first conductivity type, and well regions doped with a second conductivity type formed on both sides of the JFET region. A trench is formed in the JFET region, and a trench dielectric layer is formed on the inner surface of the trench. A gate dielectric layer is formed on the top surface of the JFET region outside the trench and extends to the top surface of the well region. A gate conductive material layer is formed on the top surfaces of the gate dielectric layer and the trench dielectric layer and completely fills the trench. A source region is formed in the surface region of the well region. The surface of the well region covered by the gate conductive material layer is used to form a conductive channel. The gate conductive material layer covers the sides of the trench through the trench dielectric layer and forms a current path in the JFET region on the sides of the trench. This invention also discloses a method for manufacturing a planar gate power device. This invention can overcome the adverse effects of JFET region size reduction on on-resistance and thus reduce on-resistance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a planar gate power device. This invention also relates to a method for manufacturing a planar gate power device. Background Technology

[0002] In existing planar gate SiC MOSFETs, each unit cell (device cell) has a JFET region located between well regions with opposite doping types. The JFET region and the drift region have the same doping type, but the JFET region has a higher doping concentration. This increased doping concentration prevents excessive depletion of the JFET region by the well regions on either side. The surface of the well region covered by the planar gate forms a conduction channel. After carriers in the conduction channel enter the JFET region, they flow into the drift region at the bottom of the JFET region through the current path formed within the JFET region.

[0003] The current path in the JFET region is formed by the area not depleted by the well regions on both sides. As the cell size shrinks, the width of the JFET region also shrinks. As a result, the proportion of the JFET region depleted by the well regions on both sides increases, and the width of the current path formed in the JFET region shrinks. This causes the on-resistance of the device to increase instead of decrease, which can actually reduce the performance of the device in small sizes. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a planar gate power device that can overcome the adverse effects of JFET region size reduction on on-resistance and thereby reduce on-resistance. The present invention also provides a method for manufacturing the planar gate power device.

[0005] To solve the above-mentioned technical problems, the planar gate power device provided by the present invention includes: Semiconductor epitaxial layer doped with the first conductivity type.

[0006] A JFET region with a first conductivity type doped is formed in the semiconductor epitaxial layer, and the doping concentration of the JFET region is greater than the doping concentration of the semiconductor epitaxial layer at the bottom of the JFET region.

[0007] A well region doped with a second conductivity type is formed in the semiconductor epitaxial layer on both sides of the JFET region.

[0008] A trench is formed in the JFET region, and a trench dielectric layer is formed on the inner surface of the trench.

[0009] A gate dielectric layer is formed on the top surface of the JFET region outside the trench and extends to the top surface of the well region.

[0010] A gate conductive material layer is formed on the top surface of the gate dielectric layer and the top surface of the trench dielectric layer, and the gate conductive material layer completely fills the trench.

[0011] A heavily doped source region of the first conductivity type is formed in the surface region of the well region and aligned with the side of the corresponding gate conductive material layer.

[0012] The planar gate is formed by stacking the gate dielectric layer outside the trench and the gate conductive material layer, and the surface of the well region covered by the gate conductive material layer is used to form a conductive channel.

[0013] The gate conductive material layer covers the sides of the trench through the trench dielectric layer and forms a current path in the JFET region on the sides of the trench, thereby reducing the on-resistance.

[0014] A further improvement is that the sides of the groove are either vertical or inclined at an acute angle to the top surface of the groove.

[0015] A further improvement is that the material of the semiconductor epitaxial layer includes Si or SiC.

[0016] A further improvement is that the thickness of the trench dielectric layer is greater than the thickness of the gate dielectric layer.

[0017] A further improvement is that the material of the trench medium layer includes an oxide layer.

[0018] The material of the gate dielectric layer includes an oxide layer.

[0019] A further improvement is that the material of the gate conductive material layer includes polycrystalline silicon.

[0020] A further improvement is that the center position of the trench is aligned with the center position of the JFET region along the width direction of the trench.

[0021] A further improvement is that the planar gate power device includes a planar gate power MOSFET.

[0022] A heavily doped drain region of a first conductivity type is formed on the back side of the semiconductor epitaxial layer.

[0023] To solve the above-mentioned technical problems, the manufacturing method of the planar gate power device provided by the present invention includes the following steps: A semiconductor epitaxial layer doped with a first conductivity type is provided, and a well region doped with a second conductivity type, a JFET region doped with the first conductivity type, and a source region heavily doped with the first conductivity type are formed in the semiconductor epitaxial layer; the JFET region is located between two adjacent well regions, and the source region is formed in the surface region of the well region; the doping concentration of the JFET region is greater than the doping concentration of the semiconductor epitaxial layer at the bottom of the JFET region.

[0024] An etching window is defined in the JFET region and an etching process is performed to form a trench.

[0025] A trench medium layer is formed on the inner surface of the trench.

[0026] A gate dielectric layer is formed on the top surface of the JFET region outside the trench and extends to the top surface of the well region.

[0027] A gate conductive material layer is formed on the top surface of the gate dielectric layer and the top surface of the trench dielectric layer, and the gate conductive material layer completely fills the trench. The gate conductive material layer is patterned, and the side surface of the patterned gate conductive material layer is aligned with the side surface of the source region. The planar gate is formed by stacking the gate dielectric layer and the gate conductive material layer outside the trench. The surface of the well region covered by the gate conductive material layer is used to form a conductive channel. The gate conductive material layer covers the side surface of the trench through the trench dielectric layer and forms a current path in the JFET region on the side surface of the trench, thereby reducing the on-resistance.

[0028] A further improvement is that the sides of the groove are either vertical or inclined at an acute angle to the top surface of the groove.

[0029] A further improvement is that the material of the semiconductor epitaxial layer includes Si or SiC.

[0030] A further improvement is that the thickness of the trench dielectric layer is greater than the thickness of the gate dielectric layer.

[0031] A further improvement is that the material of the trench dielectric layer includes an oxide layer; the material of the gate dielectric layer includes an oxide layer.

[0032] A further improvement is that the material of the gate conductive material layer includes polycrystalline silicon.

[0033] A further improvement is that the step of forming the trench medium layer on the inner surface of the trench includes: The trench medium layer is formed by growing a medium, and the trench medium layer is formed simultaneously on the inner surface of the trench and the outer surface of the trench. The thickness of the trench medium layer is adjusted by growing the medium.

[0034] CMP is performed to remove the trench medium layer outside the trench.

[0035] This invention forms a trench in the JFET region, simultaneously filling the trench with a gate conductive material layer and forming a trench dielectric layer between the gate conductive material layer and the inner surface of the trench. When the device is turned on, since the gate conductive material layer is connected to the gate potential, a carrier accumulation effect of the first conductivity type is formed on the side of the trench, thereby forming a current path in the JFET region on the side of the trench. The current path on the side of the trench is not affected by the size reduction of the JFET region, thus reducing the on-resistance when the size of the JFET region is reduced. This also makes this invention well applicable to planar gate SiC power MOSFET devices when the unit cell size is reduced.

[0036] In addition, the carrier concentration of the current channel on the side of the trench in this invention is greater than the doping concentration of the JFET region itself, and it can also improve the carrier mobility. Therefore, this invention can effectively reduce the on-resistance of the JFET region, thereby reducing the on-resistance of the entire device.

[0037] In addition, when the device is reverse biased, the trench dielectric layer and the gate conductive material layer filling the trench can also deplete the JFET region, thereby increasing the device's blocking voltage.

[0038] In addition, the morphology of the trench of the present invention is easy to adjust. The on-resistance of the device can be further adjusted by adjusting the inclination angle of the side of the trench. For example, the on-resistance of the device can be further reduced by increasing the inclination of the side of the trench.

[0039] In addition, the present invention can be implemented simply by adding a trench and a trench dielectric layer formation process in the JFET region, so the present invention also has the advantages of simple process and easy implementation. Attached Figure Description

[0040] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a schematic diagram of the planar gate power device according to the first embodiment of the present invention; Figure 2 This is a schematic diagram of the planar gate power device according to the second embodiment of the present invention; Figures 3-8 A schematic diagram of the device structure in each step of the manufacturing method of the planar gate power device according to an embodiment of the present invention. Detailed Implementation

[0041] like Figure 1 The diagram shown is a structural schematic of a planar gate power device according to a first embodiment of the present invention; the planar gate power device according to the first embodiment of the present invention includes: Semiconductor epitaxial layer 101 doped with the first conductivity type.

[0042] A JFET region 102 with a first conductivity type doped is formed in the semiconductor epitaxial layer 101, and the doping concentration of the JFET region 102 is greater than the doping concentration of the semiconductor epitaxial layer 101 at the bottom of the JFET region 102.

[0043] A well region 103 doped with a second conductivity type is formed in the semiconductor epitaxial layer 101 on both sides of the JFET region 102.

[0044] exist Figure 1 In this case, the junction depth of the JFET region 102 is greater than the junction depth of the well region 103.

[0045] Figure 1 The image shows a region where a device cell structure is formed. A planar gate power device is composed of multiple device cell structures connected in parallel, each of which has a corresponding JFET region 102. The JFET region 102 is formed by ion implantation, and the ion-implanted region of the JFET region 102 is located on the top surface region of the semiconductor epitaxial layer 101 in the entire planar gate power device formation region. In the top surface region of the semiconductor epitaxial layer 101 where the well region 103 is formed, the doping of the ion-implanted region of the JFET region 102 is superimposed with the dopant of the well region 103, and the doping is determined by the doping of the well region 103. Below the bottom surface of the well region 103, a portion of the ion-implanted region of the JFET region 102 is also shown. In other embodiments, the ion-implanted region of the JFET region 102 can also be defined by photolithography, such that the ion-implanted region of the JFET region 102 is located only between adjacent well regions 103.

[0046] The semiconductor epitaxial layer 101 at the bottom of the well region 103 is part of the drift region, and the JFET region 102 is also part of the drift region.

[0047] A trench 105a is formed in the JFET region 102, and a trench dielectric layer 106 is formed on the inner surface of the trench 105a.

[0048] A gate dielectric layer 107 is formed on the top surface of the JFET region 102 outside the trench 105a and extends to the top surface of the well region 103.

[0049] A gate conductive material layer 108 is formed on the top surface of the gate dielectric layer 107 and the top surface of the trench dielectric layer 106, and the gate conductive material layer 108 completely fills the trench 105a.

[0050] A heavily doped source region 104 of the first conductivity type is formed in the surface region of the well region 103 and aligned with the side of the corresponding gate conductive material layer 108.

[0051] The planar gate is formed by stacking the gate dielectric layer 107 outside the trench 105a and the gate conductive material layer 108. The surface of the well region 103 covered by the gate conductive material layer 108 is used to form a conductive channel.

[0052] The gate conductive material layer 108 covers the side of the trench 105a through the trench dielectric layer 106 and forms a current path in the JFET region 102 on the side of the trench 105a, thereby reducing the on-resistance.

[0053] In the first embodiment of the present invention, the side of the groove 105a is a vertical structure.

[0054] Along the width direction of the trench 105a, the center position of the trench 105a is aligned with the center position of the JFET region 102.

[0055] In the first embodiment of the present invention, the material of the semiconductor epitaxial layer 101 is SiC. In other embodiments, the material of the semiconductor epitaxial layer 101 may also be Si or other semiconductor materials.

[0056] In the first embodiment of the present invention, the thickness of the trench dielectric layer 106 is greater than the thickness of the gate dielectric layer 107.

[0057] The trench dielectric layer 106 is made of an oxide layer, such as silicon dioxide. The gate dielectric layer 107 is also made of an oxide layer, such as silicon dioxide. The trench dielectric layer 106 and the gate dielectric layer 107 are made of the same material. In other embodiments, the trench dielectric layer 106 and the gate dielectric layer 107 may also be made of other materials; the materials may be the same or different, depending on the actual needs.

[0058] In the first embodiment of the present invention, the gate conductive material layer 108 is made of polycrystalline silicon. In other embodiments, the gate conductive material layer 108 may also be made of other conductive materials such as metals, depending on the actual needs.

[0059] In a first embodiment of the present invention, the planar gate power device includes a planar gate power MOSFET.

[0060] A heavily doped drain region of a first conductivity type (not shown) is formed on the back side of the semiconductor epitaxial layer 101.

[0061] The semiconductor epitaxial layer 101 is typically formed on the top surface of a semiconductor substrate. In some embodiments, the semiconductor substrate is heavily doped with a first conductivity type, and the drain region is obtained by thinning the semiconductor substrate. In other embodiments, the drain region can also be obtained by back-side implantation with heavy doping of the first conductivity type after thinning the semiconductor substrate.

[0062] In the first embodiment of the present invention, the front structure of the planar gate power device further includes: A heavily doped well exit region 109 of the second conductivity type passes through the source region 104 and contacts the well region 103.

[0063] Interlayer 110, contact holes through the interlayer 110, and gate and source formed by patterning of the front metal layer (not shown).

[0064] Figure 1 The diagram shows that the interlayer film 110 covers the gate conductive material layer 108, which also covers a portion of the source region 104. Contact hole openings are formed on the top of the source region 104 and the well exit region 109, which are not covered by the interlayer film 110. These contact hole openings are filled with metal (not shown) to form contact holes. The source region 104 and the well exit region 109 are connected to the source electrode through the corresponding contact holes at the top; the gate conductive material layer 108 is connected to the gate electrode through the corresponding contact hole (not shown) at the top.

[0065] In the first embodiment of the present invention, the planar gate power device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the planar gate power device may also be a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0066] In the first embodiment of the present invention, a trench 105a is formed in the JFET region 102, and a gate conductive material layer 108 is simultaneously filled in the trench 105a and a trench dielectric layer 106 is formed between the gate conductive material layer 108 and the inner surface of the trench 105a. When the device is turned on, since the gate conductive material layer 108 is connected to the gate potential, a carrier accumulation effect of the first conductivity type is formed on the side of the trench 105a, thereby forming a current path in the JFET region 102 on the side of the trench 105a. The current path on the side of the trench 105a is not affected by the size reduction of the JFET region 102, so the on-resistance can be reduced when the size of the JFET region 102 is reduced. This also makes the first embodiment of the present invention well applicable to planar gate SiC power MOSFET devices when the unit cell size is reduced.

[0067] In addition, the carrier concentration of the current channel on the side of the trench 105a in the first embodiment of the present invention is greater than the doping concentration of the JFET region 102 itself, and it can also improve the carrier mobility. Therefore, the first embodiment of the present invention can effectively reduce the on-resistance of the JFET region 102, thereby reducing the on-resistance of the entire device.

[0068] In addition, when the device is reverse biased, the trench dielectric layer 106 and the gate conductive material layer 108 filled in the trench 105a can also deplete the JFET region 102, thereby increasing the blocking voltage of the device.

[0069] In addition, the first embodiment of the present invention can be achieved simply by adding a trench 105a and a trench dielectric layer 106 to the JFET region 102. Therefore, the present invention also has the advantages of simple process and easy implementation.

[0070] like Figure 2 The diagram shown is a schematic diagram of the structure of the planar gate power device according to the second embodiment of the present invention. The difference between the planar gate power device and the first embodiment of the present invention is that in the planar gate power device of the second embodiment of the present invention, the side of the trench 105b is an inclined structure with an acute angle to the top surface of the trench 105b.

[0071] and Figure 1 Compared to the trench 105a shown, the inclined side structure of the trench 105b can further increase the current flow area, thus further reducing the on-resistance. Therefore, in this application, the morphology of the trench is easy to adjust, and the on-resistance of the device can be further adjusted by adjusting the inclination angle of the trench side. For example, the on-resistance of the device can be further reduced by increasing the inclination of the trench side.

[0072] like Figures 3 to 8The diagram shows a schematic representation of the device structure in each step of the manufacturing method of the planar gate power device according to an embodiment of the present invention; the manufacturing method of the planar gate power device according to an embodiment of the present invention can manufacture... Figure 1 The planar gate power device of the first embodiment of the present invention shown can also be manufactured. Figure 2 The second embodiment of the planar gate power device of the present invention shown below will be manufactured using [further details regarding its fabrication]. Figure 1 The first embodiment of the present invention, a planar gate power device, is illustrated below. The manufacturing method of the planar gate power device of the present invention includes the following steps: Step 1, such as Figure 3 As shown, a semiconductor epitaxial layer 101 doped with a first conductivity type is provided, and a well region 103 doped with a second conductivity type, a JFET region 102 doped with a first conductivity type, and a source region 104 heavily doped with a first conductivity type are formed in the semiconductor epitaxial layer 101; the JFET region 102 is located between two adjacent well regions 103, and the source region 104 is formed in the surface region of the well region 103; the doping concentration of the JFET region 102 is greater than the doping concentration of the semiconductor epitaxial layer 101 at the bottom of the JFET region 102.

[0073] In the method of this embodiment of the invention, the JFET region 102, the well region 103 and the source region 104 are all formed by photolithography and ion implantation. Figure 3 The image shows the formation area of ​​a device unit structure. A planar gate power device is formed by multiple device unit structures connected in parallel, and each of the device unit structures has a corresponding JFET region 102. Figure 3 In this embodiment, the ion-implanted region of the JFET region 102 is located on the top surface region of the semiconductor epitaxial layer 101 covering the entire planar gate power device formation area. In the top surface region of the semiconductor epitaxial layer 101 where the well region 103 is formed, the doping of the ion-implanted region of the JFET region 102 is superimposed with the doped impurities of the well region 103, and the doping is determined by the doping of the well region 103. Below the bottom surface of the well region 103, a portion of the ion-implanted region of the JFET region 102 is also shown. In other embodiments, the ion-implanted region of the JFET region 102 can also be defined by photolithography, such that the ion-implanted region of the JFET region 102 is located only between adjacent well regions 103.

[0074] The method in this embodiment of the invention further includes: A heavily doped well extraction region 109 of the second conductivity type is formed by photolithography and ion implantation. The well extraction region 109 passes through the source region 104 and contacts the well region 103.

[0075] In the method of this embodiment, the material of the semiconductor epitaxial layer 101 is SiC. In other embodiments, the material of the semiconductor epitaxial layer 101 may also be Si or other semiconductor materials.

[0076] Step 2, as follows Figure 4 As shown, an etching window is defined in the JFET region 102 and an etching process is performed to form a trench 105a.

[0077] In the method of this embodiment of the invention, the side of the groove 105a has a vertical structure, which enables the formation of Figure 1 The first embodiment of the present invention shown is a planar gate power device.

[0078] In other embodiments, the trench 105b can also have its side surface inclined at an acute angle to its top surface, thus forming... Figure 2 The second embodiment of the planar gate power device of the present invention is shown. In the method of the present invention, the morphology of the trench is easily adjusted, and the on-resistance of the device can be further adjusted by adjusting the tilt angle of the side of the trench. For example, the on-resistance of the device can be further reduced by increasing the tilt angle of the side of the trench.

[0079] Step 3, as follows Figure 6 As shown, a trench medium layer 106 is formed on the inner surface of the trench 105a.

[0080] In the implementation method of the present invention, the step of forming the trench medium layer 106 on the inner surface of the trench 105a includes: like Figure 5 As shown, the trench medium layer 106 is formed by medium growth. The trench medium layer 106 is formed on both the inner surface of the trench 105a and the outer surface of the trench 105a. The thickness of the trench medium layer 106 is adjusted by the medium growth.

[0081] like Figure 6 As shown, CMP is performed to remove the trench medium layer 106 outside the trench 105a.

[0082] Step 4, as follows Figure 7 As shown, a gate dielectric layer 107 is formed on the top surface of the JFET region 102 outside the trench 105a and extends to the top surface of the well region 103.

[0083] In the method of this embodiment of the invention, the thickness of the trench dielectric layer 106 is greater than the thickness of the gate dielectric layer 107.

[0084] The trench dielectric layer 106 is made of an oxide layer, such as silicon dioxide. The gate dielectric layer 107 is also made of an oxide layer, such as silicon dioxide. The trench dielectric layer 106 and the gate dielectric layer 107 are made of the same material. In other embodiments, the trench dielectric layer 106 and the gate dielectric layer 107 may also be made of other materials; the materials may be the same or different, depending on the actual needs.

[0085] Step 5, as follows Figure 8 As shown, a gate conductive material layer 108 is formed on the top surface of the gate dielectric layer 107 and the top surface of the trench dielectric layer 106, and the gate conductive material layer 108 completely fills the trench 105a. The gate conductive material layer 108 is patterned, and the side of the patterned gate conductive material layer 108 is aligned with the side of the source region 104. The planar gate is formed by stacking the gate dielectric layer 107 and the gate conductive material layer 108 outside the trench 105a. The surface of the well region 103 covered by the gate conductive material layer 108 is used to form a conductive channel. The gate conductive material layer 108 covers the side of the trench 105a through the trench dielectric layer 106 and forms a current path in the JFET region 102 on the side of the trench 105a, thereby reducing the on-resistance.

[0086] In the method of this embodiment, the gate conductive material layer 108 is made of polycrystalline silicon. In other embodiments, the gate conductive material layer 108 may be made of other conductive materials such as metals, depending on the specific needs.

[0087] The method in this embodiment of the invention also includes the following front-side process: like Figure 1 As shown, an interlayer membrane 110 is formed.

[0088] Photolithography is performed to define and etch contact holes that pass through the interlayer film 110. Figure 1 The image shows that the interlayer film 110 covers the gate conductive material layer 108, which also covers a portion of the source region 104; contact hole openings are formed on the top of the source region 104 and the well lead-out region 109, which are not covered by the interlayer film 110.

[0089] Then, metal (not shown) is filled into the contact hole opening to form a contact hole.

[0090] A front metal layer (not shown) is formed and the front metal layer is patterned to form the gate and source.

[0091] The source region 104 and the well lead-out region 109 are connected to the source electrode through the corresponding contact hole at the top; the gate conductive material layer 108 is connected to the gate through the corresponding contact hole at the top (not shown).

[0092] In the method of this embodiment of the invention, the planar gate power device includes a planar gate power MOSFET. Then, the back-side process is performed: A heavily doped drain region of a first conductivity type (not shown) is formed on the back side of the semiconductor epitaxial layer 101.

[0093] In the methods of this invention, the semiconductor epitaxial layer 101 is typically formed on the top surface of a semiconductor substrate. In some embodiments, the semiconductor substrate is heavily doped with a first conductivity type, and the drain region is obtained by thinning the semiconductor substrate. In other embodiments, the drain region may be obtained by further back-side implantation with heavy doping of the first conductivity type after thinning the semiconductor substrate.

[0094] In the method of this embodiment, the planar gate power device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the planar gate power device can also be a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0095] This application can further reduce the on-resistance while keeping the blocking voltage unchanged, under the condition that the JFET region is smaller. Simulation results show that the trench structure in the JFET region of this application can improve the electron mobility in the drift region, thereby reducing the on-resistance (Rdson). For example, it can reduce the Rdson from 7.8mΩ in the existing structure to 7.0mΩ in the first embodiment of this invention, an optimization of up to 10.3%.

[0096] The blocking voltage of this application is improved compared with the existing structures. Whether it is the structure of the first embodiment of the present invention or the structure of the second embodiment of the present invention, such as the structure with a groove having a side tilt angle of 70°, the blocking voltage can be improved by an average of about 50V.

[0097] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A planar gate power device, characterized in that, include: Semiconductor epitaxial layer doped with the first conductivity type; A JFET region doped with a first conductivity type is formed in the semiconductor epitaxial layer, and the doping concentration of the JFET region is greater than the doping concentration of the semiconductor epitaxial layer at the bottom of the JFET region; A well region doped with a second conductivity type is formed in the semiconductor epitaxial layer on both sides of the JFET region; A trench is formed in the JFET region, and a trench dielectric layer is formed on the inner surface of the trench. A gate dielectric layer is formed on the top surface of the JFET region outside the trench and extends to the top surface of the well region; A gate conductive material layer is formed on the top surface of the gate dielectric layer and the top surface of the trench dielectric layer, and the gate conductive material layer completely fills the trench; A source region heavily doped with the first conductivity type is formed in the surface region of the well region and aligned with the side of the corresponding gate conductive material layer; The planar gate is formed by stacking the gate dielectric layer outside the trench and the gate conductive material layer, and the surface of the well region covered by the gate conductive material layer is used to form a conductive channel; The gate conductive material layer covers the sides of the trench through the trench dielectric layer and forms a current path in the JFET region on the sides of the trench, thereby reducing the on-resistance.

2. The planar gate power device as described in claim 1, characterized in that: The sides of the trench are either vertical or inclined at an acute angle to the top surface of the trench.

3. The planar gate power device as described in claim 2, characterized in that: The material of the semiconductor epitaxial layer includes Si or SiC.

4. The planar gate power device as described in claim 1, characterized in that: The thickness of the trench dielectric layer is greater than the thickness of the gate dielectric layer.

5. The planar gate power device as described in claim 3, characterized in that: The material of the trench medium layer includes an oxide layer; The material of the gate dielectric layer includes an oxide layer.

6. The planar gate power device as described in claim 3, characterized in that: The material of the gate conductive material layer includes polycrystalline silicon.

7. The planar gate power device as described in claim 1, characterized in that: Along the width direction of the trench, the center position of the trench is aligned with the center position of the JFET region.

8. The planar gate power device as described in claim 1, characterized in that: Planar gate power devices include planar gate power MOSFETs; A heavily doped drain region of a first conductivity type is formed on the back side of the semiconductor epitaxial layer.

9. A method for manufacturing a planar gate power device, characterized in that, Includes the following steps: A semiconductor epitaxial layer doped with a first conductivity type is provided, and a well region doped with a second conductivity type, a JFET region doped with the first conductivity type, and a source region heavily doped with the first conductivity type are formed in the semiconductor epitaxial layer; the JFET region is located between two adjacent well regions, and the source region is formed in the surface region of the well region; the doping concentration of the JFET region is greater than the doping concentration of the semiconductor epitaxial layer at the bottom of the JFET region; An etching window is defined in the JFET region and an etching process is performed to form a trench; A trench medium layer is formed on the inner surface of the trench; A gate dielectric layer is formed on the top surface of the JFET region outside the trench and extends to the top surface of the well region; A gate conductive material layer is formed on the top surface of the gate dielectric layer and the top surface of the trench dielectric layer, and the gate conductive material layer completely fills the trench. The gate conductive material layer is patterned, and the side surface of the patterned gate conductive material layer is aligned with the side surface of the source region; The planar gate is formed by stacking the gate dielectric layer outside the trench and the gate conductive material layer, and the surface of the well region covered by the gate conductive material layer is used to form a conductive channel; The gate conductive material layer covers the sides of the trench through the trench dielectric layer and forms a current path in the JFET region on the sides of the trench, thereby reducing the on-resistance.

10. The method for manufacturing a planar gate power device as described in claim 9, characterized in that: The sides of the trench are either vertical or inclined at an acute angle to the top surface of the trench.

11. The method for manufacturing a planar gate power device as described in claim 10, characterized in that: The material of the semiconductor epitaxial layer includes Si or SiC.

12. The method for manufacturing a planar gate power device as described in claim 9, characterized in that: The thickness of the trench dielectric layer is greater than the thickness of the gate dielectric layer.

13. The method for manufacturing a planar gate power device as described in claim 11, characterized in that: The material of the trench dielectric layer includes an oxide layer; the material of the gate dielectric layer includes an oxide layer.

14. The method for manufacturing a planar gate power device as described in claim 11, characterized in that: The material of the gate conductive material layer includes polycrystalline silicon.

15. The method for manufacturing a planar gate power device as described in claim 12, characterized in that, The step of forming the trench medium layer on the inner surface of the trench includes: The trench medium layer is formed by growing a medium, and the trench medium layer is formed simultaneously on the inner surface of the trench and the outer surface of the trench. The thickness of the trench medium layer is adjusted by growing the medium. CMP is performed to remove the trench medium layer outside the trench.

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