Ferroelectric all-around gate transistor and preparation method and application thereof
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SOUTH CHINA NORMAL UNIV
- Filing Date
- 2026-03-16
- Publication Date
- 2026-07-14
Smart Images
Figure CN122396027A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology, and more specifically, relates to a ferroelectric all-around gate transistor, its fabrication method, and its application. Background Technology
[0002] Deploying artificial intelligence at the network edge requires localized data processing under strict power and area constraints. While edge computing alleviates the latency and bandwidth limitations of cloud-based systems, its progress depends on ultra-efficient hardware, such as transistors, that delivers high performance, ultra-low power consumption, and compact integration. Recently, various emerging transistors have been developed to increase computing power and reduce device footprint, but they still lag far behind the full potential predicted by theory. Summary of the Invention
[0003] To address the shortcomings and drawbacks of the existing technology and overcome challenges in performance, scale, and efficiency, the primary objective of this invention is to provide a ferroelectric all-around gate transistor. This transistor includes a SiO2 / Si substrate, a bottom gate electrode disposed on the SiO2 / Si substrate, a first ferroelectric dielectric layer CuInP2S6, a channel layer MoS2, two graphene layers, a second ferroelectric dielectric layer CuInP2S6 sequentially stacked on the gate electrode, source and drain electrodes respectively disposed at both ends of the two graphene layers, and a top gate electrode disposed on the second ferroelectric dielectric layer CuInP2S6.
[0004] Another object of the present invention is to provide a method for fabricating the above-mentioned ferroelectric all-around gate transistor. This method is simple, technologically mature, uses readily available equipment, and is inexpensive.
[0005] Another object of the present invention is to provide an application of the above-described ferroelectric all-around gate transistor.
[0006] The objective of this invention is achieved through the following technical solution: A ferroelectric all-around gate transistor includes a bottom gate electrode disposed on a SiO2 / Si substrate. A first ferroelectric dielectric layer CuInP2S6, a channel layer MoS2, two graphene sheets, and a second ferroelectric dielectric layer CuInP2S6 are sequentially stacked on the bottom gate electrode. A gap is provided between the two graphene sheets. The source electrode and the drain electrode are respectively disposed at the two ends of the two graphene sheets and are not in contact with the second ferroelectric dielectric layer CuInP2S6. A top gate electrode is disposed on the second ferroelectric dielectric layer CuInP2S6, forming a vertical heterostructure.
[0007] Preferably, the thickness of the first ferroelectric dielectric layer and the second ferroelectric dielectric layer CuInP2S6 is 60~70nm; the thickness of the channel layer MoS2 is 25~65nm; and the thickness of the graphene layer is 12~16nm.
[0008] Preferably, the source electrode, drain electrode, and gate electrode are all Au layers, and the thickness of the Au layers is 45~65nm.
[0009] Preferably, the spacing between the two graphene sheets is 4~6μm.
[0010] The method for fabricating the ferroelectric all-around gate transistor includes the following steps: S1. Fabrication of the bottom gate electrode on a SiO2 / Si substrate; S2. Using mechanical peeling and dry transfer methods, single-crystal tapes were obtained by bonding CuInP2S6 single crystals, MoS2 single crystals, and graphene with Nitto blue tape. The first ferroelectric dielectric layer CuInP2S6 was sequentially transferred to the bottom gate electrode using a transfer platform; then the channel layer MoS2 was transferred to the first ferroelectric dielectric layer CuInP2S6; then two graphene sheets were transferred to the channel layer MoS2; finally, the second ferroelectric dielectric layer CuInP2S6 was transferred to the channel layer MoS2. S3. Source and drain electrodes are deposited on both ends of the two graphene sheets, respectively. A top gate electrode is then deposited on the second ferroelectric dielectric layer CuInP2S6 to obtain CuInP2S6 / MoS2 / graphene. / CuInP2S6 ferroelectric all-around gate transistor.
[0011] Preferably, the channel layer MoS2 in step S2 does not extend beyond the first ferroelectric dielectric layer CuInP2S6.
[0012] Preferably, in step S2, the second ferroelectric dielectric layer CuInP2S6 completely covers the channel layer MoS2.
[0013] Preferably, the two graphene sheets in step S2 are symmetrically distributed.
[0014] Preferably, the bottom gate electrode and the top gate electrode mentioned in steps S1 and S3 are both in contact with the contacting ferroelectric dielectric layer CuInP2S6.
[0015] The application of the ferroelectric full-around-gate transistor in the field of artificial neurons. This ferroelectric full-around-gate transistor features a two-dimensional ferroelectric layer with asymptotic polarization and negative capacitance effect, achieving superior electrostatic control, ultra-steep logic switching, and energy-efficient artificial neurons on the same hardware platform. It shows great potential in energy-efficient electronics and neuromorphic edge computing applications. This device architecture provides new opportunities for edge computing systems, especially in scenarios with strict power and space constraints.
[0016] Compared with the prior art, the present invention has the following beneficial effects: The ferroelectric all-around gate structure transistor of this invention breaks the Boltzmann limit of traditional complementary metal-oxide-semiconductor (CMOS) devices through the ferroelectric negative capacitance effect, achieving a high on / off ratio (10). 8 The lowest subthreshold swing is 25.3 mV / dec, and the maximum field-effect mobility is 310 cm⁻¹. 2 V -1 s -1 .
[0017] This invention utilizes the ferroelectric polarization dynamics of CuInP2S6 to further demonstrate its application prospects in realizing binary logic operations and neuromorphic edge computing on the same hardware platform. The artificial neuron simulates leak-integration-ignition (LIF) behavior, eliminating the need for additional capacitors and external reset circuits, significantly reducing power consumption and hardware footprint. This invention establishes a new paradigm for multifunctional edge intelligent processors, transcending traditional power-area tradeoffs, offering advantages of low power consumption and multifunctionality. Furthermore, the fabrication process is simple, the technology is mature, the equipment is readily available, and the cost is low.
[0018] 3. The ferroelectric fully-around-gate transistor fabricated in this invention also possesses artificial neuron functionality. Due to the progressive polarization dynamics of the CuInP2S6 layer, in continuous V... gs Under pulse, I ds The integration process simulates this behavior. Upon pulse removal, spontaneous depolarization occurs, restoring the device to its initial state. This avoids the multi-component interconnections found in traditional neurons, eliminating the need for additional capacitors and external reset circuitry, thus significantly reducing power consumption and hardware footprint. Attached Figure Description
[0019] Figure 1 This is a schematic diagram of the structure of the ferroelectric all-around gate transistor of the present invention.
[0020] Figure 2 This is an optical microscope image of the ferroelectric fully encircled gate transistor prepared in Example 1.
[0021] Figure 3 (a) is the transfer curve of the ferroelectric all-around gate transistor prepared in Example 1; (b) is the subthreshold swing of the ferroelectric all-around gate transistor; (c) is the field-effect mobility of the ferroelectric all-around gate transistor.
[0022] Figure 4 This is a test of the ferroelectric fully-around-gate transistor prepared in this invention for the function of artificial neurons. Detailed Implementation
[0023] The present invention will be further described below with reference to specific embodiments, but these should not be construed as limiting the invention. Unless otherwise specified, the technical means used in the embodiments are conventional means well known to those skilled in the art. Unless otherwise specified, the reagents, methods, and equipment used in the present invention are conventional reagents, methods, and equipment in this technical field.
[0024] This specification uses spatially relative terms such as “below,” “under,” “down,” “above,” “above,” and “upper” to explain the positioning of one element relative to a second element. These terms are intended to cover different orientations of the device, except for those different from those shown in the figures.
[0025] Furthermore, the use of terms such as "first" and "second" to describe various elements, layers, regions, and sections is not intended to be restrictive. The use of terms such as "having," "containing," "including," and "comprises" are open-ended terms, indicating the presence of the stated elements or features, but not excluding additional elements or features, unless the context explicitly states otherwise. Example 1
[0026] A ferroelectric all-around gate transistor, such as Figure 1 As shown, the structure includes a SiO2 / Si substrate and a bottom gate electrode (G). A first ferroelectric dielectric layer (CuInP2S6), a channel layer (MoS2), two graphene layers, and a second ferroelectric dielectric layer (CuInP2S6) are sequentially stacked on the bottom gate electrode. A gap is provided between the two graphene layers. The source electrode (S) and drain electrode (D) are respectively disposed at the two ends of the two graphene layers and do not contact the second ferroelectric dielectric layer (CuInP2S6). A top gate electrode is disposed on the second ferroelectric dielectric layer (CuInP2S6), forming a vertical heterostructure. The thickness of the ferroelectric dielectric layer (CuInP2S6) is 60–70 nm, the thickness of the channel layer (MoS2) is 25–65 nm, and the thickness of the graphene is 12–16 nm. The source electrode, drain electrode, and gate electrode are all Au layers with a thickness of 45–65 nm.
[0027] The fabrication method of a ferroelectric all-around gate transistor includes the following steps: 1. Use ethanol solution and deionized water to sonicate the SiO2 / Si substrate, respectively, for 5 minutes each time; use ultraviolet lithography to lithographically form the bottom gate electrode on the SiO2 / Si substrate, and evaporate an Au layer of 45~65nm. After evaporation, place it in acetone for 10 minutes to dissolve the photoresist and remove the excess Au layer to obtain the bottom gate electrode.
[0028] 2. Using mechanical exfoliation and dry transfer processes, CuInP2S6 single crystals were adhered to Nitto blue tape to obtain single-crystal tape, and CuInP2S6 / PDMS was obtained by adhering single-crystal tape to PDMS. CuInP2S6 nanosheets of 60-70 nm were selected under an optical microscope. The first ferroelectric dielectric layer CuInP2S6 obtained by this exfoliation method is easier to control in terms of thickness and shape compared to the CuInP2S6 layer obtained by directly exfoliating single-crystal tape to the substrate, and leaves less adhesive residue. The PDMS surface with CuInP2S6 nanosheets was covered on the bottom gate electrode using a transfer platform. Taking advantage of the difference in material adhesion, the CuInP2S6 nanosheets were transferred to the bottom gate electrode.
[0029] 3. Using the peeling method and dry transfer process in step 2, MoS2 single crystals are bonded together with Nitto blue tape to obtain single crystal tape, and MoS2 / PDMS is obtained by bonding the single crystal tape together with PDMS. MoS2 nanosheets of 25~65nm are selected under an optical microscope and transferred to the middle region of the first ferroelectric dielectric layer CuInP2S6, without exceeding the CuInP2S6 layer, to obtain the channel layer MoS2 with a thickness of 25~65nm.
[0030] 4. Using mechanical exfoliation and dry transfer processes, single-crystal graphene was adhered to the single-crystal tape using blue adhesive tape to obtain single-crystal tape. Graphene with a thickness of 12-16 nm was selected, and PDMS was used to adhere the single-crystal tape to obtain graphene / PDMS. The graphene was then transferred to both ends of the channel layer MoS2 to make the two graphene sheets as symmetrical as possible, and the distance between the two graphene sheets was controlled to be 4-6 μm. Subsequently, the same mechanical exfoliation and dry transfer processes were used to transfer the second ferroelectric dielectric layer CuInP2S6 onto the channel layer MoS2. The thickness of the second ferroelectric dielectric layer CuInP2S6 was 60-70 nm.
[0031] 5. Select positive photoresist and spin coat at 4000 rpm for 60 seconds; then bake at 100℃ for 5-10 minutes on a heating stage; use an ultraviolet laser lithography source to form electrode pattern windows at both ends of the two graphene sheets and on the second ferroelectric dielectric layer CuInP2S6.
[0032] 6. A 45-65 nm Au layer was deposited using a thermal evaporation process at a deposition rate of 0.01 nm / s. After deposition, the layer was placed in acetone for 10 min to dissolve the photoresist and remove excess Au layer, resulting in a CuInP2S6 / MoS2 / graphene / CuInP2S6 ferroelectric all-around gate transistor.
[0033] Figure 2CuInP2S6 / MoS2 / Graphene prepared in Example 1 An optical microscope image of a CuInP2S6 ferroelectric all-around gate transistor. The source and drain electrodes are respectively disposed at the two ends of two graphene sheets, while the bottom and top gate electrodes are disposed on the substrate and the second ferroelectric dielectric layer CuInP2S6, respectively. The scale bar of the microscope image is 10 μm. Figure 2 As can be seen, the bottom gate electrode and the top gate electrode completely overlap with the first and second ferroelectric dielectric layers to achieve good electrostatic control.
[0034] Figure 3 In Figure (a), the transfer curve of the CuInP2S6 / MoS2 / Graphene / CuInP2S6 ferroelectric all-around gate transistor prepared in Example 1 is shown. Figure 3 (a) It can be seen that when the source-drain bias voltages are set to 0.1V, 0.5V, and 1V, the transfer curves are counterclockwise, indicating that the all-around gate transistor is dominated by ferroelectric regulation and the current switching ratio is approximately 10. 8 (b) represents the subthreshold swing of the ferroelectric all-around gate transistor, with source-drain bias voltages set to 0.1, 0.5, and 1V. From Figure 3 (b) shows that the subthreshold swing (SS) of this transistor breaks the room-temperature Boltzmann limit of 60 mV / dec, with the lowest SS being 25.3 mV / dec. This indicates that this structure can achieve good gate control and reduce transistor power consumption. (c) represents the field-effect mobility of the ferroelectric all-around gate transistor. The source-drain bias voltages are set to 0.1, 0.5, and 1V. Figure 3 (c) shows that the maximum field-effect mobility (μ) of this transistor reaches 310 cm⁻¹. 2 V -1 s -1 This indicates that the all-around gate structure can enhance the driving capability of transistors.
[0035] Figure 4 This paper presents the testing results of the ferroelectric all-around gate transistor (FOTG) fabricated in this invention for use in artificial neurons. In F(a), the conductance is modulated by electrical pulses of different amplitudes. The source-drain bias voltage is set to 0.1V, the threshold current is set to 100nA, the pulse duration and interval are 100μs, and the voltage amplitudes are 0.5V, 0.8V, and 1V. Figure 4As shown in (a), pulse amplitudes of 1V and 0.8V are sufficient to bring the device to the threshold, indicating that larger pulse amplitudes make it easier for the device to reach the threshold. (b) shows the effect of different pulse durations on conductance. The threshold current is set to 100nA, the pulse voltage amplitude is 0.6V, the pulse interval is 100μs, and the pulse durations are 100μs, 200μs, and 300μs. From... Figure 4 As shown in (b), pulse widths of 300 μs and 200 μs are sufficient to bring the device to the threshold, indicating that a larger pulse width makes it easier for the device to reach the threshold. (c) shows the effect of different pulse intervals on conductance. The threshold current is set to 100 nA, the voltage amplitude of the pulse is 1.2 V, and the pulse duration is 100 μs. Pulse durations of 500 μs, 400 μs, and 200 μs are also shown. From... Figure 4 As shown in (c), pulse intervals of 200μs and 400μs can make the device reach the threshold, indicating that the smaller the pulse interval, the easier it is for the device to reach the threshold.
[0036] The CuInP2S6 / MoS2 / Graphene / CuInP2S6 ferroelectric all-around gate transistor of this invention breaks the Boltzmann limit of traditional complementary metal-oxide-semiconductor CMOS devices through the ferroelectric negative capacitance effect, achieving a high on / off ratio (10). 8 The lowest subthreshold swing is 25.3 mV / dec, and the maximum field-effect mobility is 310 cm⁻¹. 2 V -1 s -1 By utilizing the ferroelectric polarization dynamics of CuInP2S6, its application prospects in binary logic operations and neuromorphic computing on the same hardware platform are further demonstrated. The artificial neuron simulates leakage-integration-ignition (LIF) behavior, eliminating the need for additional capacitors and external reset circuits, significantly reducing power consumption and hardware footprint. The all-around gate structure transistor of this invention establishes a new paradigm for multifunctional edge intelligent processors, transcending traditional power-area tradeoffs, offering advantages of low power consumption and multifunctionality, and is simple to fabricate, technologically mature, with readily available equipment and low cost.
[0037] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations and simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.
Claims
1. A ferroelectric all-around gate transistor, characterized in that, The ferroelectric all-around gate transistor includes a bottom gate electrode disposed on a SiO2 / Si substrate. A first ferroelectric dielectric layer CuInP2S6, a channel layer MoS2, two graphene layers, and a second ferroelectric dielectric layer CuInP2S6 are sequentially stacked on the bottom gate electrode. A gap is provided between the two graphene layers. The source electrode and the drain electrode are respectively disposed at the two ends of the two graphene layers and are not in contact with the second ferroelectric dielectric layer CuInP2S6. A top gate electrode is disposed on the second ferroelectric dielectric layer CuInP2S6, forming a vertical heterostructure.
2. The ferroelectric all-around gate transistor according to claim 1, characterized in that, The thickness of the first ferroelectric dielectric layer and the second ferroelectric dielectric layer CuInP2S6 is 60~70nm; the thickness of the channel layer MoS2 is 25~65nm; and the thickness of the graphene layer is 12~16nm.
3. The ferroelectric all-around gate transistor according to claim 1, characterized in that, The source electrode, drain electrode, and gate electrode are all Au layers, and the thickness of the Au layers is 45~65nm.
4. The ferroelectric all-around gate transistor according to claim 1, characterized in that, The distance between the two graphene sheets is 4~6μm.
5. The method for fabricating a ferroelectric all-around gate transistor according to any one of claims 1-4, characterized in that, Includes the following steps: S1. Fabrication of the bottom gate electrode on a SiO2 / Si substrate; S2. Using mechanical peeling and dry transfer methods, single-crystal tapes were obtained by bonding CuInP2S6 single crystals, MoS2 single crystals, and graphene with Nitto blue tape. The first ferroelectric dielectric layer CuInP2S6 was sequentially transferred to the bottom gate electrode using a transfer platform; then the channel layer MoS2 was transferred to the first ferroelectric dielectric layer CuInP2S6; then two graphene sheets were transferred to the channel layer MoS2; finally, the second ferroelectric dielectric layer CuInP2S6 was transferred to the channel layer MoS2. S3. Source and drain electrodes are deposited on both ends of the two graphene sheets respectively, and top gate electrodes are deposited on the second ferroelectric dielectric layer CuInP2S6 to obtain a CuInP2S6 / MoS2 / graphene / CuInP2S6 ferroelectric all-around gate transistor.
6. The method for fabricating a ferroelectric all-around gate transistor according to claim 5, characterized in that, In step S2, the channel layer MoS2 does not extend beyond the first ferroelectric dielectric layer CuInP2S6.
7. The method for fabricating a ferroelectric all-around gate transistor according to claim 5, characterized in that, In step S2, the second ferroelectric dielectric layer CuInP2S6 completely covers the channel layer MoS2.
8. The method for fabricating a ferroelectric all-around gate transistor according to claim 5, characterized in that, The two graphene sheets mentioned in step S2 are symmetrically distributed.
9. The method for fabricating a ferroelectric all-around gate transistor according to claim 5, characterized in that, In steps S1 and S3, both the bottom gate electrode and the top gate electrode are in contact with the ferroelectric dielectric layer CuInP2S6.
10. The application of the ferroelectric all-around gate transistor according to any one of claims 1-4 in the field of artificial neurons.