A surge protection device and a method of manufacturing a surge protection device

Abstract

The application provides a surge protection device and a preparation method thereof. The surge protection device comprises a MOS tube structure and a TVS structure arranged in sequence in a vertical direction. The MOS tube structure comprises a first semiconductor material layer and a second dielectric layer arranged in sequence. The first semiconductor material layer is provided with a source region and a drain region arranged in a horizontal direction, and a channel region between the source region and the drain region. The second dielectric layer is provided with a gate oxide region and a gate region arranged in sequence at a position corresponding to the channel region. The TVS structure comprises a third dielectric layer. The third dielectric layer is provided with a PN junction structure arranged in a horizontal direction, and the PN junction structure comprises a first N region and a P region. The third dielectric layer is bonded to the second dielectric layer in a specified manner. The P region is opposite to the gate region in the vertical direction. The surge protection device has a high response speed.

Description

Technical Field

[0001] This application relates to the field of surge protection technology, and in particular to a surge protection device and a method for preparing the surge protection device. Background Technology

[0002] In power systems and electronic equipment, surge phenomena have become a major hidden danger affecting the safe and stable operation of equipment. Factors such as lightning strikes, switching operations, or equipment start-up and shutdown can generate transient high voltages of up to several kilovolts and lasting for microseconds. Such transient high voltages may break down semiconductor devices, burn out PCB circuits, or cause permanent damage to equipment in a very short time.

[0003] Surge protection technology aims to suppress transient overvoltages in power lines or signal lines, thereby effectively protecting downstream electronic equipment. In the circuit protection design of modern electronic equipment, the selection of appropriate surge protection components directly affects system reliability. Currently, varistors and similar devices are commonly used to construct protection circuits; however, varistors have limitations in response speed, resulting in unsatisfactory surge protection performance. Summary of the Invention

[0004] In view of this, this application provides a surge protection device and a method for manufacturing the surge protection device, so as to improve the response speed of the surge protection device and improve the surge protection effect.

[0005] The first aspect of this application provides a surge protection device, which includes a MOS transistor structure and a TVS structure stacked sequentially along a vertical direction; wherein...

[0006] The MOS transistor structure includes a first semiconductor material layer and a second dielectric layer stacked together; the first semiconductor material layer has a source region and a drain region arranged in a horizontal direction, and a channel region located between the source region and the drain region; the second dielectric layer has a gate oxide region and a gate region stacked sequentially at the position corresponding to the channel region.

[0007] The TVS structure includes a third dielectric layer; a PN junction structure arranged in a horizontal direction is disposed within the third dielectric layer, the PN junction structure including a first N region and a P region;

[0008] The third dielectric layer is bonded to the second dielectric layer in a specified manner; the specified manner is that the P region and the gate region are opposite each other in the vertical direction.

[0009] A second aspect of this application provides a method for manufacturing a surge protection device, the method being used to manufacture the surge protection device according to any one of the claims in the first aspect of this application, the method comprising:

[0010] A TVS structure is fabricated; wherein the TVS structure includes a third dielectric layer; a PN junction structure arranged in a horizontal direction is disposed within the third dielectric layer, the PN junction structure including a first N region and a P region;

[0011] A MOS transistor structure is fabricated; wherein the MOS transistor structure includes a first semiconductor material layer and a second dielectric layer stacked together; the first semiconductor material layer has a source region and a drain region arranged in a horizontal direction, and a channel region located between the source region and the drain region; the second dielectric layer has a gate oxide region and a gate region stacked sequentially at a position corresponding to the channel region;

[0012] The third dielectric layer of the TVS structure and the second dielectric layer of the MOS transistor structure are bonded together with the P region and the gate region facing each other in the vertical direction to form a surge protection device.

[0013] The surge protection device and its fabrication method provided in this application integrate a MOSFET structure and a TVS structure in a vertically stacked manner, with the gate region of the MOSFET structure and the P-region of the TVS structure vertically opposite each other. This allows for capacitive coupling between the output terminal of the TVS structure and the gate region of the MOSFET structure via a dielectric layer. Thus, when a transient surge voltage or surge current occurs, the TVS structure can turn on first within nanoseconds, rapidly coupling the surge energy to the gate region of the MOSFET structure, driving the MOSFET structure to quickly enter the conducting state. A low-impedance discharge channel is formed between the protected terminal and the drain region of the MOSFET structure, enabling timely and efficient discharge of the surge current. This allows for rapid clamping at the initial stage of a surge, significantly improving surge response speed and protection efficiency, and effectively preventing overvoltage damage to subsequent circuits.

[0014] Details of one or more embodiments of this application are set forth in the following drawings and description to make other features, objects and advantages of this application more readily apparent. Attached Figure Description

[0015] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0016] Figure 1 A schematic diagram of a surge protection device according to a first embodiment of the present application;

[0017] Figure 2 A schematic diagram of Embodiment 2 of the surge protection device provided in this application;

[0018] Figure 3A flowchart illustrating a method for manufacturing a surge protection device as an exemplary embodiment of this application;

[0019] Figure 4 A schematic diagram illustrating the implementation principle of fabricating a TVS structure, as shown in an exemplary embodiment of this application;

[0020] Figure 5 A schematic diagram illustrating the formation principle of a PN junction structure, as shown in an exemplary embodiment of this application;

[0021] Figure 6 This is a schematic diagram illustrating the implementation principle of fabricating a MOS transistor structure, as shown in an exemplary embodiment of this application.

[0022] Figure 7 A transient response curve of a surge protection device under surge action, as shown in an exemplary embodiment of this application;

[0023] Figure 8 The diagram illustrates, for an exemplary embodiment, the clamping voltage variation curves of the surge protection device provided in this application under different ambient temperature conditions.

[0024] Explanation of reference numerals in the attached figures:

[0025] 1: MOS transistor structure;

[0026] 11: First semiconductor material layer;

[0027] 12: Second dielectric layer;

[0028] 13: First passivation layer;

[0029] 2: TVS structure;

[0030] 21: Third dielectric layer;

[0031] 211: PN junction structure;

[0032] 22: Second passivation layer. Detailed Implementation

[0033] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0034] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used herein are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0035] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0036] Several specific embodiments are given below to illustrate the technical solutions of this application in detail.

[0037] Figure 1 This is a schematic diagram of an embodiment of the surge protection device provided in this application. Please refer to... Figure 1 The surge protection device includes a MOS transistor structure 1 and a TVS structure 2 arranged sequentially in a vertical direction; wherein,

[0038] The MOS transistor structure 1 includes a first semiconductor material layer 11 and a second dielectric layer 12 stacked together; the first semiconductor material layer 11 has a source region and a drain region arranged in a horizontal direction, and a channel region located between the source region and the drain region; the second dielectric layer 12 has a gate oxide region and a gate region stacked sequentially at the position corresponding to the channel region.

[0039] The TVS structure 2 includes a third dielectric layer 21; a PN junction structure 211 arranged in a horizontal direction is provided in the third dielectric layer 21, and the PN junction structure includes a first N region and a P region.

[0040] The third dielectric layer 21 is bonded to the second dielectric layer 12 in a specified manner; the specified manner is that the P region and the gate region are opposite each other in the vertical direction.

[0041] Specifically, the thicknesses of the first semiconductor material layer 11 and the second dielectric layer 12 are set according to actual needs, and are not limited in this embodiment. It can be understood that thickness refers to... Figure 1 The dimensions shown are in the vertical direction.

[0042] Furthermore, the materials of the first semiconductor material layer 11 and the second dielectric layer 12 are determined according to actual needs, and are not limited in this embodiment. For example, in one possible implementation, the first semiconductor material layer 11 can be a silicon substrate, and the second dielectric layer 12 can be a silicon dioxide layer.

[0043] Please continue to refer to Figure 1 The first semiconductor material layer 11 contains a drain region, a channel region, and a source region. It is understood that the source and drain regions are made of doped semiconductor materials. For example, in one possible implementation, the MOS transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, or MOS for short) is an N-type MOS transistor structure, and its source and drain regions can be made of N-type semiconductor materials. Specifically, for an N-type MOS transistor structure, the source and drain regions may be silicon doped with elements such as phosphorus or arsenic. These dopants provide free electrons, giving the material negative charge characteristics.

[0044] Furthermore, the channel region is the area between the source and drain regions, where current flows when the MOSFET is turned on. Additionally, the channel region is typically made of silicon.

[0045] Please refer to Figure 1 It should be noted that, along the thickness direction, the source region, channel region, and drain region penetrate the entire first semiconductor material layer 11, meaning that the thickness of the source region, channel region, and drain region is equal to the thickness of the first semiconductor material layer 11. Furthermore, the widths of the source region, channel region, and drain region (…) Figure 1 The dimensions shown (in the left and right directions) are set according to actual needs, and are not limited in this embodiment. Furthermore, the lengths of the source region, channel region, and drain region (…) Figure 1 The direction perpendicular to the paper (as shown) can be equal to the length of the first semiconductor material layer 11.

[0046] Please continue to refer to Figure 1 Within the second dielectric layer 12, a gate oxide region and a gate region are sequentially stacked opposite the channel region. The gate oxide region can be made of silicon dioxide, and the gate region can be made of metal or polysilicon. In this embodiment, these are not limited.

[0047] Furthermore, the thicknesses of the gate oxide region and the gate region are set according to actual needs, and are not limited in this embodiment. Additionally, the sum of the thicknesses of the gate oxide region and the gate region can be less than the thickness of the second dielectric layer 12. Furthermore, the widths of the gate oxide region and the gate region can be the same or different, and are not limited in this embodiment. For example, in one possible implementation, the width of the gate oxide region is greater than the width of the gate region. Furthermore, the widths of the gate oxide region and the gate region can be less than or equal to the width of the channel region, and are not limited in this embodiment. Furthermore, the lengths of the gate oxide region and the gate region can be equal to the length of the second dielectric layer 12.

[0048] Please continue to refer to Figure 1 It is understood that a first passivation layer 13 is covered under the first semiconductor material layer 11; the source region is ohmically connected to the first electrode through a via on the first passivation layer 13; and the drain region is ohmically connected to the second electrode through a via on the first passivation layer 13.

[0049] The thickness and material of the first passivation layer 13 are determined according to actual needs, and are not limited in this embodiment. Optionally, in one possible implementation, the first passivation layer 13 is a Si3N4 layer.

[0050] The first and second electrodes are metal electrodes. For example, in one possible implementation, the materials of the first and second electrodes are typically titanium, copper, etc.

[0051] Please continue to refer to Figure 1 The MOSFET structure 1 is stacked with a TVS structure 2 (Transient Voltage Suppressor, or TVS for short). The TVS structure 2 will be introduced below.

[0052] Specifically, the TVS structure 2 includes a third dielectric layer 21, in which adjacent first N-regions and P-regions are disposed, and the first N-regions and P-regions constitute a PN structure.

[0053] The thickness and material of the third dielectric layer 21 are determined according to actual needs, and are not limited in this embodiment. For example, in one possible implementation, the material of the third dielectric layer 21 can be silicon dioxide (SiO2). (or other high dielectric constant materials).

[0054] Furthermore, the first N-region is typically composed of phosphorus-doped silicon, and the P-region is typically composed of boron-doped silicon. Additionally, the thickness of the first N-region and the P-region is less than the thickness of the third dielectric layer 21; their thicknesses may be the same or different, and this embodiment does not limit them. Furthermore, the widths of the first N-region and the P-region are also set according to actual needs, and this embodiment does not limit them.

[0055] For further details, please refer to [link / reference]. Figure 1 The third dielectric layer 21 is covered with a second passivation layer 22. The first N region forms an ohmic connection with the third electrode through a via on the second passivation layer 22, and the P region forms an ohmic connection with the fourth electrode through a via on the second passivation layer.

[0056] Specifically, the thickness and material of the second passivation layer 22 are determined according to actual needs, and are not limited in this embodiment. Optionally, in one possible implementation, the second passivation layer includes sequentially stacked Al2O3 and HfO2 layers in a direction away from the third dielectric layer.

[0057] In practical implementation, for example, the Al2O3 layer has a thickness of 2 nm and the HfO2 layer has a thickness of 3 nm, in order to reduce the interface state density to... the following.

[0058] For further details, please refer to [link / reference]. Figure 1 The TVS structure 2 and the MOS transistor structure 1 are bonded together. Specifically, the TVS structure 2 bonds the third dielectric layer 21 and the second dielectric layer 12 together with the P region of the TVS structure 2 and the gate region of the MOS transistor structure 1 facing each other in the vertical direction.

[0059] The working principle of this surge protection device will be briefly introduced below.

[0060] Optionally, in one possible implementation, one of the third or fourth electrodes is connected to a positive voltage, the other electrode is connected to a negative voltage, the second electrode is connected to a negative voltage, and the first electrode is connected to a positive voltage.

[0061] Please refer to Figure 1 It is understandable that there is a second dielectric layer and a third dielectric layer between the gate region and the P region. Both the gate region and the P region are conductive, and they form a capacitive coupling connection.

[0062] When a transient high voltage occurs at the input of the TVS structure, the TVS structure quickly turns on. Because its P-region is capacitively coupled to the gate region of the MOSFET structure, when the TVS structure turns on, charge is injected into the gate region of the MOSFET structure through the third and second dielectric layers, causing the gate voltage to rapidly rise to the turn-on threshold. When the gate voltage of the MOSFET structure rises to the turn-on voltage, the MOSFET structure turns on, forming a low-impedance discharge path from the P-region of the TVS structure to the gate region of the MOSFET structure and then to the drain region of the MOSFET structure. Through this path, surge current is efficiently discharged, effectively protecting the circuit from the effects of transient high voltage, exhibiting advantages such as fast response and low conduction loss.

[0063] The surge protection device provided in this embodiment integrates and stacks a MOSFET structure and a TVS structure vertically, with the gate region of the MOSFET structure and the P-region of the TVS structure vertically opposite each other. This allows for capacitive coupling between the output terminal of the TVS structure and the gate region of the MOSFET structure via a dielectric layer. Thus, when a transient surge voltage or surge current occurs, the TVS structure can turn on first within nanoseconds, rapidly coupling the surge energy to the gate region of the MOSFET structure, driving the MOSFET structure to quickly enter the conducting state. A low-impedance discharge channel is formed between the protected terminal and the drain region of the MOSFET structure, allowing the surge current to be discharged promptly and efficiently. This enables rapid clamping at the initial stage of a surge, significantly improving surge response speed and protection efficiency, and effectively preventing overvoltage damage to subsequent circuits.

[0064] Figure 2 This is a schematic diagram of Embodiment 2 of the surge protection device provided in this application. Please refer to... Figure 2 Based on the above embodiments, the surge protection device provided in this embodiment further includes a second N region in the PN junction structure; the second N region is adjacent to the P region, and the first N region, the P region and the second N region form a bidirectional PN junction structure.

[0065] See Figure 2 It is understandable that a bidirectional PN junction structure refers to a structure consisting of two N-regions ( Figure 2 The structure consists of a first N-region and a second N-region, and a P-region, wherein the first N-region and the P-region form a PN junction, and the second N-region and the P-region form another PN junction. The bidirectional PN junction structure enables bidirectional current control and current discharge functions.

[0066] It should be noted that when the PN junction structure includes a second N-region, the second N-region is ohmically connected to the third electrode through a via on the second passivation layer.

[0067] Specifically, in this bidirectional PN junction structure, the PN junction between the first N-region and the P-region can conduct current in one direction, while the PN junction between the second N-region and the P-region can conduct current in the other direction. Since the two PN junctions are adjacent and face opposite directions, this structure can effectively handle current from both directions simultaneously, enhancing its ability to suppress surge currents and its rapid response capability.

[0068] Specifically, when a transient high voltage occurs at the input terminal, the first PN junction and the second PN junction can respond quickly and rapidly guide the surge current into a low-impedance discharge channel, ensuring the stability of the surge protection.

[0069] The surge protection device provided in this embodiment, by setting a bidirectional PN junction structure in the TVS structure, enables the surge protection device to handle more complex current waveforms. It is particularly suitable for high-frequency, high-power, and transient voltage surge scenarios, and can further improve the protection performance of the surge protection device.

[0070] Optionally, in one possible implementation, the width of the gate region along the horizontal direction is equal to the width of the P region along the horizontal direction.

[0071] Specifically, the surge protection device provided in this embodiment, by making the width of the gate region along the horizontal direction equal to the width of the P region along the horizontal direction, can form a spatially aligned parallel structure between the two, thereby establishing a stable capacitive coupling connection between the gate region and the P region. Through this capacitive coupling, the potential change generated in the P region under surge action can be quickly and uniformly coupled to the gate region, improving the transient response speed and conduction consistency of the MOSFET, thereby enhancing the device's ability to suppress transient surges, and helping to reduce parasitic effects and improve the overall reliability of the device.

[0072] Furthermore, the surge protection device provided in this application, by integrating a TVS structure and a MOSFET structure, can improve compatibility and expand the application range of the surge protection device. Moreover, by vertically stacking the TVS and MOSFET, they are electrically connected through a short, face-to-face vertical conduction path. Compared to traditional planar parallel or discrete package structures, this structure significantly shortens the surge current conduction path, effectively reducing the length of the interconnect metal and the loop area, thereby significantly reducing parasitic inductance and parasitic resistance. Furthermore, it can avoid voltage ringing and energy reflection problems caused by parasitic parameters. Especially in surge impacts with nanosecond-level rising edges, the smaller parasitic inductance can effectively suppress transient overshoot voltage, improving clamping response speed and stability.

[0073] Corresponding to the aforementioned embodiment of a surge protection device, this application also provides a method for preparing a surge protection device. The method for preparing the surge protection device provided in this application will be described below.

[0074] Figure 3 This is a flowchart illustrating a method for fabricating a surge protection device, as shown in an exemplary embodiment of this application. Please refer to... Figure 3 In one possible implementation, the method for fabricating the surge protection device provided in this embodiment includes:

[0075] S301. Fabricate a TVS structure; wherein the TVS structure includes a third dielectric layer; a PN junction structure arranged in a horizontal direction is disposed in the third dielectric layer, and the PN junction structure includes a first N region and a P region.

[0076] It should be noted that in this embodiment, the execution order of S301 and S302 is not limited, and they can be executed simultaneously.

[0077] Optionally, in one possible implementation, the process of fabricating the TVS structure may include:

[0078] (1) A third dielectric layer is formed on the second silicon substrate.

[0079] (2) A PN junction structure arranged in a horizontal direction is formed in the third dielectric layer; wherein the PN junction structure includes a first N region and a P region.

[0080] (3) Remove the second silicon substrate.

[0081] Specifically, Figure 4 This is a schematic diagram illustrating the implementation principle of fabricating a TVS structure, as shown in an exemplary embodiment of this application. Please refer to... Figure 4 In step (1), a third dielectric layer (silicon dioxide layer) with a thickness of 150±5nm can be generated on the second silicon substrate by wet oxidation. The conditions for wet oxidation are set according to actual needs, and are not limited in this embodiment. For example, in one possible implementation, the conditions for wet oxidation can be: temperature controlled at 1100℃±50℃, oxygen partial pressure controlled at 5±2%, and 5% HCl applied.

[0082] It should be noted that in the second silicon substrate, the resistivity of silicon... In addition, the second silicon substrate can be subjected to RCA-standardized cleaning before step (1).

[0083] Figure 5 This is a schematic diagram illustrating the formation principle of a PN junction structure, as shown in an exemplary embodiment of this application. Please refer to... Figure 5 In step (2), a first type of groove corresponding to the N region can be photolithographically formed in the third dielectric layer, and an N-type material can be deposited in the first type of groove; then a second type of groove corresponding to the P region can be photolithographically formed in the third dielectric layer, and a P-type material can be deposited in the second type of groove.

[0084] It should be noted that the depths of the first type of groove and the second type of groove are... The spacing between the first type of groove and the second type of groove can be .

[0085] Furthermore, when depositing N-type material within the first type of groove, the N-type material can be... Polycrystalline silicon. In one possible implementation, the reaction conditions for depositing the N-type material can be: a temperature of 510℃~530℃. and The gas flow ratio is 100:1, and the phosphorus doping concentration is... .

[0086] Please refer to Figure 5 Figures (B) and (C) illustrate that after depositing the N-type material, an etching technique is used to remove excess N-type material, exposing the third dielectric layer. Further, refer to... Figure 5 In Figures (D) and (E), a second type of groove is formed on the third dielectric layer, and a P-type material is deposited on the second type of groove.

[0087] Furthermore, when depositing P-type material in the first type of groove, the reaction conditions for depositing P-type material can be: a temperature of 510℃~530℃. and The mixed gas flow ratio is 80:1, and the boron doping concentration is... .

[0088] For further details, please refer to Figure 5 In Figure (F), after the P-type material is deposited, the excess P-type material can be etched away using etching technology to expose the third dielectric layer.

[0089] Thus, after step (2), a PN junction structure arranged in the horizontal direction can be formed in the third dielectric layer.

[0090] For further details, please refer to Figure 4 In the (E) and (F) diagrams, the second silicon substrate can be removed in step (3) by techniques such as chemical polishing and etching.

[0091] It should be noted that while removing the silicon substrate, part of the third dielectric layer may also be removed; however, this embodiment does not limit this process.

[0092] Please continue to refer to Figure 4 In Figures (C), (D), and (E), after step (2) to form the PN junction structure, a second passivation layer can be further deposited on the third dielectric layer. For example, the second passivation layer can be formed by deposition. Specifically, for example, in one embodiment, atomic layer deposition is used to grow a stacked passivation layer at 330°C, with the first layer being... of Layer, the next layer is of Layers to reduce interface state density to the following.

[0093] Further, electrode patterning is performed to form the electrodes. Specifically, electron beam lithography can be used first to define the vias corresponding to the electrodes, with an alignment accuracy of ±5nm; then, selective etching is performed using ion etching to form the vias corresponding to the electrodes on the second passivation layer. It should be noted that a mixed gas is selected for ion etching. Selectivity > 50:1.

[0094] After forming the vias corresponding to the electrodes, electrodes are deposited using deposition techniques. In this embodiment, the third electrode, which is ohmically connected to the N-region, and the fourth electrode, which is ohmically connected to the P-region, can be composite electrodes. The formation process of this composite electrode is as follows: first, a 2nm TiN layer is deposited as a diffusion barrier layer, and then two graphene layers are grown to reduce the contact resistance to a minimum. Finally, a top layer is deposited, which can be a Pt layer or a Ti layer. It should be noted that the top layer is deposited by pulsed laser deposition, with a laser energy of 150 mJ, a post-pulse energy of 50 mJ, and a frequency of 15 Hz.

[0095] It should be noted that in the formation Figure 4 Following the structure shown in Figure (E), the structure can be annealed to create ohmic contacts between the electrodes and each region, optimizing the contact surface resistance. Specifically, the annealing conditions can be: 2.45 GHz (microwave frequency), 500 W (power). Plasma annealing was performed in a microwave environment with a mixed atmosphere at a temperature of 380±10℃ for 60 seconds.

[0096] The fabrication method provided in this embodiment allows for the rapid fabrication of a TVS structure by forming a third dielectric layer on a second silicon substrate and arranging a horizontally oriented PN junction structure within the third dielectric layer. Furthermore, arranging the PN junction horizontally significantly reduces device thickness and parasitic capacitance, thereby improving transient response speed. Moreover, removing the second silicon substrate further reduces substrate parasitic effects, enhancing the integration of the TVS structure with the underlying MOS transistor structure, thus improving surge suppression efficiency.

[0097] S302. Fabricate a MOS transistor structure; wherein the MOS transistor structure includes a first semiconductor material layer and a second dielectric layer stacked together; the first semiconductor material layer has a source region and a drain region arranged in a horizontal direction, and a channel region located between the source region and the drain region; the second dielectric layer has a gate oxide region and a gate region stacked sequentially at positions corresponding to the channel region.

[0098] Optionally, in one possible implementation, the process of fabricating the MOS transistor structure may include:

[0099] (1) A gate oxide layer and a gate layer are sequentially formed on a first silicon substrate, and the gate oxide layer and the gate layer are etched to form a gate oxide region and a gate region on the first silicon substrate.

[0100] (2) A source region and a drain region arranged in a horizontal direction and a channel region located between the source region and the drain region are formed in the first silicon substrate; wherein the channel region and the gate region are opposite each other in the vertical direction.

[0101] (3) Deposit a second dielectric layer on the first silicon substrate so that the second dielectric layer covers the gate oxide region and the gate region.

[0102] Specifically, Figure 6 This is a schematic diagram illustrating the implementation principle of fabricating a MOS transistor structure, as shown in an exemplary embodiment of this application. Please refer to... Figure 6 In Figures (A), (B), and (C), in step (1), a gate oxide layer can be formed on the first silicon substrate by means of deposition or oxidation, and a gate layer can be formed on the gate oxide layer by deposition.

[0103] Understandably, the gate oxide layer is made of silicon dioxide. Furthermore, the gate layer can be made of a metal or polysilicon.

[0104] For further details, please refer to Figure 6 In Figure (D), in step (1), the gate layer and gate oxide layer can be patterned by photolithography and etching techniques to form the gate oxide region and gate region on the first silicon substrate.

[0105] Please refer to Figure 6 In Figure (E), step (2) involves further processing of the first silicon substrate to form a source region, a drain region, and a channel region within it. Specifically, the first silicon substrate is a lightly doped silicon substrate or an epitaxial silicon layer. Below the gate region coverage area, due to the shielding effect of the gate region and the gate oxide region, subsequent doping impurities are difficult to enter this region, thus retaining the original doping type and forming a channel region. Further, in the exposed silicon regions on both sides of the gate region, impurity ions with the same or opposite conductivity type as the channel region are introduced through an ion implantation process, and the implanted impurity ions are activated and diffused into the silicon lattice through annealing, thereby forming a source region and a drain region on both sides of the gate region, respectively. In a specific implementation, in one embodiment, the annealing conditions can be: annealing at 1000±20℃ for 1 hour.

[0106] As described above, the gate region acts as a self-aligning mask in this process, ensuring precise spatial alignment between the source and drain regions and the channel region, thus reducing parasitic resistance and capacitance. Through these process steps, a transistor structure is formed within the first silicon substrate, with the channel region at its center and the source and drain regions symmetrically distributed, achieving effective control over the carrier conduction path.

[0107] For further details, please refer to Figure 6 In Figure (F), in step (3), a second dielectric layer can be deposited on the first silicon substrate using a deposition technique. For example, the second dielectric layer can typically be deposited using chemical vapor deposition (CVD) or physical vapor deposition (PVD) techniques. After the second dielectric layer is deposited, it covers the gate oxide region and the gate region.

[0108] Optionally, in the specific implementation, after obtaining Figure 6 Following the intermediate structure shown in Figure (F), a first passivation layer can be further deposited on the first silicon substrate. For example, the first passivation layer can be formed by deposition.

[0109] See Figure 6 In the (H) diagram, further electrode patterning is performed to form the electrodes. Specifically, electron beam lithography can be used to define the vias corresponding to the electrodes, with an alignment accuracy of ±5nm; then, selective etching is performed using ion etching to form the vias corresponding to the electrodes on the first passivation layer. After forming the vias corresponding to the electrodes, the electrodes are deposited using deposition techniques.

[0110] S303. The third dielectric layer of the TVS structure and the second dielectric layer of the MOS transistor structure are bonded together with the P region and the gate region facing each other in the vertical direction to form a surge protection device.

[0111] Specifically, after fabricating the MOSFET and TVS structures, this step involves integrating and stacking the top-layer TVS structure with the bottom-layer MOSFET structure. In practice, the MOSFET and TVS structures are first subjected to surface treatment. For example, the third dielectric layer of the TVS structure and the second dielectric layer of the MOSFET structure are chemically mechanically polished to ensure a surface roughness of <1 nm.

[0112] Furthermore, a low-temperature bonding technique is used to bond the MOSFET structure and the TVS structure together.

[0113] As described above, it is understood that both the second and third dielectric layers are... In this step, the third dielectric layer and the second dielectric layer are stacked together in the vertical direction with the P region in the third dielectric layer and the gate region in the second dielectric layer facing each other in the vertical direction. They are then bonded at 360°C and 1.5MPa for 30 minutes to form a stable interface between them.

[0114] The surge protection device fabrication method provided in this embodiment involves fabricating a TVS structure and a MOS transistor structure separately. Finally, the third dielectric layer in the TVS structure and the second dielectric layer in the MOS transistor structure are bonded together with the P-region in the TVS structure and the gate region in the MOS transistor structure facing each other in the vertical direction. This achieves vertical integration of the TVS structure and the MOS transistor structure, and fabricates a surge protection device integrating the TVS structure and the MOS transistor structure. This surge protection device enables the potential change generated by the TVS structure during a surge to be quickly applied to the gate region of the MOS transistor through the capacitive coupling between the dielectric layers, thereby shortening the gate response time and improving the device's suppression speed and clamping effect for transient surges.

[0115] It should be noted that this application also verified the advantages of the surge protection device through verification experiments, which are briefly introduced below.

[0116] Figure 7 The transient response curve of a surge protection device under surge action is shown in an exemplary embodiment of this application. Please refer to... Figure 7 The x-axis represents time, and the y-axis represents clamping voltage. Clamping voltage refers to the maximum voltage value that a surge protection device limits (clamps) the voltage of the protected node when it is conducting and providing protection.

[0117] Please refer to Figure 7 The surge protection device described in this application does not exhibit significant spike interference voltage during the initial conduction phase under surge action.

[0118] Specifically, as described above, the surge protection device provided in this application forms a low-impedance discharge path with a TVS structure and a MOSFET structure. When a surge voltage arrives, the TVS structure responds first and generates a potential change. This potential is rapidly applied to the gate region of the MOSFET structure through capacitive coupling between the dielectric layers, enabling the MOSFET structure to quickly conduct in the initial stage of the surge, significantly reducing the overall on-resistance of the device. Since the discharge path is established within a nanosecond timescale, surge energy can be promptly diverted and absorbed, avoiding the voltage accumulation phenomenon of traditional transient suppression diodes. This effectively suppresses transient voltage spikes between the operating voltage and the clamping voltage, ultimately achieving a smooth clamping effect without significant spikes.

[0119] Understandably, traditional transient voltage suppressor diodes are prone to microsecond-level voltage spikes between their operating voltage and clamping voltage. The surge protection device provided in this application, by integrating a TVS structure and a MOSFET structure, achieves a rapid and smooth voltage transition at the initial stage of a surge through their synergistic effect. This effectively eliminates voltage spikes at the initial operating voltage, achieving a nanosecond-level surge absorption response. The voltage of the protected node is stably limited to a lower clamping voltage range, preventing voltage spikes from impacting subsequent circuits. This significantly improves the reliability of subsequent circuits under high integration and low withstand voltage conditions.

[0120] Furthermore, it is understandable that this low-impedance path can promptly divert surge current in the initial stage of a surge, preventing energy accumulation within the device and suppressing residual voltage rise and fluctuations caused by conduction hysteresis and parasitic parameters. Simultaneously, the vertically integrated structure shortens the current path, reducing the impact of parasitic inductance and capacitance, making the clamping process smoother and more stable. This significantly reduces the voltage fluctuation amplitude of the protected node, decreases the risk of cascading failures caused by surge impacts, and thus improves the stability and reliability of the overall protection design.

[0121] Figure 8 The diagram illustrates, for an exemplary embodiment, the clamping voltage variation curves of the surge protection device provided in this application under different ambient temperature conditions. Figure 8 In the graph, the horizontal axis represents temperature, and the vertical axis represents clamping voltage. Please refer to [reference needed]. Figure 8 The surge protection device of this embodiment has a clamping voltage fluctuation range of less than 3% within the temperature range of -20 to 120°C.

[0122] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A surge protection device, characterized in that, The surge protection device includes a MOSFET structure and a TVS structure stacked sequentially in a vertical direction; wherein, The MOS transistor structure includes a first semiconductor material layer and a second dielectric layer stacked together; the first semiconductor material layer has a source region and a drain region arranged in a horizontal direction, and a channel region located between the source region and the drain region; the second dielectric layer has a gate oxide region and a gate region stacked sequentially at the position corresponding to the channel region. The TVS structure includes a third dielectric layer; a PN junction structure arranged in a horizontal direction is disposed within the third dielectric layer, the PN junction structure including a first N region and a P region; The third dielectric layer is bonded to the second dielectric layer in a specified manner; the specified manner is that the P region and the gate region are opposite each other in the vertical direction.

2. The surge protection device according to claim 1, characterized in that, The PN junction structure further includes a second N region; the second N region is adjacent to the P region, and the first N region, the P region and the second N region form a bidirectional PN junction structure.

3. The surge protection device according to claim 1, characterized in that, A first passivation layer is covered beneath the first semiconductor material layer; the source region is ohmically connected to the first electrode through a via on the first passivation layer; the drain region is ohmically connected to the second electrode through a via on the first passivation layer. The third dielectric layer is covered with a second passivation layer; the first N region is ohmically connected to the third electrode through a via on the second passivation layer, and the P region is connected to the fourth electrode through a via on the second passivation layer.

4. The surge protection device according to claim 1, characterized in that, The width of the gate region along the horizontal direction is equal to the width of the P region along the horizontal direction.

5. The surge protection device according to claim 3, characterized in that, Along a direction away from the third dielectric layer, the second passivation layer comprises sequentially stacked Al2O3 and HfO2 layers; And / or, The first passivation layer is a Si3N4 layer.

6. The surge protection device according to claim 3, characterized in that, The third electrode and the fourth electrode are a composite electrode; wherein... Along the direction away from the third dielectric layer, the composite electrode includes a TiN2 layer, a first graphene layer, a second graphene layer, and a top layer stacked in sequence; wherein the top layer is a Pt layer or a Ti layer.

7. A method for preparing a surge protection device, characterized in that, The preparation method is used to prepare the surge protection device according to any one of claims 1 to 6, and the preparation method includes: A TVS structure is fabricated; wherein the TVS structure includes a third dielectric layer; a PN junction structure arranged in a horizontal direction is disposed within the third dielectric layer, the PN junction structure including a first N region and a P region; A MOS transistor structure is fabricated; wherein the MOS transistor structure includes a first semiconductor material layer and a second dielectric layer stacked together; the first semiconductor material layer has a source region and a drain region arranged in a horizontal direction, and a channel region located between the source region and the drain region; the second dielectric layer has a gate oxide region and a gate region stacked sequentially at a position corresponding to the channel region; The third dielectric layer of the TVS structure and the second dielectric layer of the MOS transistor structure are bonded together with the P region and the gate region facing each other in the vertical direction to form a surge protection device.

8. The preparation method according to claim 7, characterized in that, The preparation of the TVS structure includes: A third dielectric layer is formed on the second silicon substrate; A PN junction structure arranged in a horizontal direction is formed within the third dielectric layer; wherein the PN junction structure includes a first N-region and a P-region; Remove the second silicon substrate.

9. The preparation method according to claim 7 or 8, characterized in that, The fabrication of the MOS transistor structure includes: A gate oxide layer and a gate layer are sequentially formed on a first silicon substrate, and the gate oxide layer and the gate layer are etched to form a gate oxide region and a gate region on the first silicon substrate. A source region and a drain region, arranged horizontally, and a channel region located between the source region and the drain region are formed within the first silicon substrate; wherein the channel region is vertically opposite to the gate region. A second dielectric layer is deposited on the first silicon substrate such that the second dielectric layer covers the gate oxide region and the gate region.

10. The preparation method according to claim 8, characterized in that, The formation of a horizontally arranged PN junction structure within the third dielectric layer includes: The first type of groove corresponding to the N region is photolithographically formed in the third dielectric layer; N-type material is deposited within the first type of groove; wherein the deposition conditions for the N-type material are: a temperature of 510℃~530℃. and The gas flow ratio is 100:1, and the phosphorus doping concentration is... ; The second type of groove corresponding to the P region is photolithographically formed in the third dielectric layer; P-type material is deposited within the second type of groove; wherein the deposition conditions for the P-type material are: a temperature of 510℃~530℃. and The mixed gas flow ratio is 80:1, and the boron doping concentration is... .

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