Semiconductor structure and method of manufacturing the same
By employing a double-layer gate insulating layer structure in the semiconductor structure, the problems of circuit crosstalk and thickness non-uniformity in semiconductor manufacturing are solved, resulting in higher circuit reliability and electrical performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NAN YA TECH
- Filing Date
- 2026-04-17
- Publication Date
- 2026-07-14
AI Technical Summary
In the current semiconductor manufacturing process, as the size shrinks, the crosstalk problem between circuits becomes increasingly serious, and the uneven thickness of the gate insulating layer leads to a decrease in circuit reliability.
A double-layer gate insulating layer structure is adopted. By forming an insulating layer and an insulating oxide layer on the semiconductor substrate, the insulating oxide layer is formed at high temperature using an in-situ vapor generation process, which ensures the uniformity of the insulating layer and the gradual reduction of its thickness, thereby reducing the consumption of semiconductor substrate.
It effectively reduces crosstalk between adjacent gate structures, improves the reliability of semiconductor structures, especially time-dependent dielectric breakdown reliability, and enhances electrical performance.
Smart Images
Figure CN122396032A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor structure and a method for manufacturing the same. Background Technology
[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have spurred generation after generation of ICs, each generation featuring smaller and more complex circuits than the last. Functional density (the number of interconnects per unit wafer area) has generally increased. Simultaneously, geometric dimensions (the smallest components (or lines) that a manufacturing process can produce) have shrunk. This shrinking process typically benefits production efficiency and reduces associated costs. However, shrinking dimensions also increases the complexity of IC processing and manufacturing. For example, reduced spacing between circuits can lead to crosstalk. Summary of the Invention
[0003] This invention provides a semiconductor structure comprising a semiconductor substrate, a gate structure, and a gate insulating layer. The gate structure is embedded in the semiconductor substrate. The gate insulating layer is located between the gate structure and the semiconductor substrate, and includes an insulating layer and an insulating oxide layer. The insulating layer covers the gate structure. The insulating oxide layer is located between the insulating layer and the semiconductor substrate, and has a thickness that gradually decreases from top to bottom.
[0004] In some embodiments, the semiconductor substrate includes a semiconductor material, and the insulating oxide layer includes an oxide of the semiconductor material.
[0005] In some implementations, the bottom thickness of the gate insulating layer is 3.5 nm to 4 nm.
[0006] In some embodiments, the insulating oxide layer has a minimum thickness and a maximum thickness, the ratio of the minimum thickness to the maximum thickness being 0.9 to less than 1.
[0007] In some embodiments, the semiconductor structure further includes an insulating capping layer located on the semiconductor substrate, wherein the insulating capping layer has a side surface located on an insulating oxide layer, and the insulating oxide layer has an outer surface located away from the gate structure and offset from the side surface of the insulating capping layer.
[0008] In some embodiments, the semiconductor structure further includes an insulating capping layer on the semiconductor substrate, wherein the insulating capping layer has a side surface on an insulating oxide layer, and the insulating oxide layer has an inner surface facing the gate structure and offset from the side surface of the insulating capping layer.
[0009] In some embodiments, the semiconductor structure further includes an insulating capping layer located on the semiconductor substrate, wherein the insulating capping layer directly contacts the insulating oxide layer.
[0010] In some embodiments, the semiconductor structure also includes a hard mask located on the gate structure and in direct contact with a plurality of upper surfaces of the insulating layer and the insulating oxide layer.
[0011] In some implementations, the insulating layer has a substantially uniform thickness.
[0012] In some implementations, the gate structure includes a barrier layer and a gate layer located on the barrier layer.
[0013] This invention provides a method for manufacturing a semiconductor structure, the method comprising the following operations: forming a first trench in a semiconductor substrate; forming an insulating layer to cover the inner surface of the first trench; oxidizing a portion of the semiconductor substrate by a thermal oxidation process to form an insulating oxide layer between the insulating layer and the semiconductor substrate; and forming a gate structure in the first trench and on the insulating layer.
[0014] In some implementations, the insulating layer is formed by atomic layer deposition (ALD).
[0015] In some implementations, the insulating layer is formed at a temperature of 68°C to 82°C.
[0016] In some implementations, the thermal oxidation process is an in-situ steam generation (ISSG) process.
[0017] In some implementations, the thermal oxidation process is performed at a temperature of 900°C to 1100°C.
[0018] In some embodiments, the insulating oxide layer has a thickness that gradually decreases from top to bottom.
[0019] In some embodiments, the insulating oxide layer has a minimum thickness and a maximum thickness, the ratio of the minimum thickness to the maximum thickness being 0.9 to less than 1.
[0020] In some embodiments, the method further includes the following operations: Before forming the first trench in the semiconductor substrate, an insulating capping layer is formed on the semiconductor substrate, and a second trench is formed to penetrate the insulating capping layer. An insulating layer is formed to cover the insulating capping layer.
[0021] In some embodiments, the method further includes removing a portion of the insulating layer to expose the insulating overlay before oxidizing this portion of the semiconductor substrate by a thermal oxidation process.
[0022] In some implementations, the insulating cover layer is in direct contact with the insulating oxide layer. Attached Figure Description
[0023] The present invention can be more fully understood by reading the following detailed description of the embodiments and referring to the accompanying drawings.
[0024] Figure 1 This is a flowchart of a method for manufacturing a semiconductor structure according to various embodiments of the present invention.
[0025] Figures 2 to 12 This is a cross-sectional schematic diagram of an intermediate stage in the manufacture of a semiconductor structure according to various embodiments of the present invention. Detailed Implementation
[0026] Embodiments of the invention will now be described in detail, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.
[0027] The following embodiments are described and disclosed in detail with reference to the accompanying drawings. For clarity, many practical details will be set forth in the following description. However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not essential. Furthermore, for the sake of simplicity, some existing structures and elements will be illustrated schematically in the drawings.
[0028] This invention provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a semiconductor substrate, a gate structure, and a gate insulating layer, wherein the gate structure is embedded in the semiconductor substrate and separated from it by the gate insulating layer. The gate insulating layer comprises a double layer manufactured through two processes. First, an insulating layer is formed on the inner surface of a trench in the semiconductor substrate. Next, a portion of the semiconductor substrate is oxidized by a thermal oxidation process to form an insulating oxide layer, thereby forming a gate insulating layer comprising the insulating layer and the insulating oxide layer. Compared to forming the gate insulating layer using only a single thermal oxidation process, the method of this invention reduces the consumption of the semiconductor substrate and forms a gate insulating layer with a larger bottom thickness. Reducing the consumption of the semiconductor substrate can reduce crosstalk between adjacent gate structures, i.e., interference between circuit signals, thereby avoiding circuit logic errors. Furthermore, the thicker bottom thickness of the gate insulating layer can improve the reliability of the semiconductor structure (e.g., time-dependent dielectric breakdown (TDDB) reliability). Therefore, the semiconductor structure of this invention exhibits better electrical performance.
[0029] This invention provides a semiconductor structure and a method for manufacturing the same. Please refer to [link / reference]. Figures 1 to 12 . Figure 1This is a flowchart of a method 100 for manufacturing a semiconductor structure according to various embodiments of the present invention. Method 100 includes operations S1, S2, S3, S4, S5, S6, S7, and S8. Figures 2 to 12 This is a cross-sectional schematic diagram of an intermediate stage in the manufacturing of a semiconductor structure according to various embodiments of the present invention. Operations S1 to S8 described above will be discussed later. Figures 2 to 12 Describe it.
[0030] In operation S1, such as Figure 2 As shown, a receiving semiconductor substrate 110 is included. The semiconductor substrate 110 comprises a semiconductor material. In some embodiments, the semiconductor material includes Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, InP, carbon-doped silicon (Si:C), silicon carbide germanium, or other suitable semiconductor materials. In some embodiments, the semiconductor substrate 110 includes doped regions 112 (or active regions). Doped regions 112 may include N-type or P-type dopants. In some embodiments, the semiconductor substrate 110 includes a plurality of isolation regions 114 adjacent to the doped regions 112, such as shallow trench isolation (STI) regions. In some embodiments, the isolation regions 114 include silicon dioxide, silicon nitride, silicon oxynitride, fluorine-doped silica glass (FSG), or other low-k dielectric materials.
[0031] In operation S2, such as Figure 2 As shown, an insulating capping layer 120 is formed on the semiconductor substrate 110. In some embodiments, the insulating capping layer 120 includes an insulating oxide or an insulating nitride, such as silicon dioxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon carbide, or combinations thereof.
[0032] In operation S3, such as Figure 3 As shown, multiple trenches T are formed in the insulating capping layer 120 and the semiconductor substrate 110. The number of trenches T is not limited to... Figure 3 As shown, it can be adjusted arbitrarily according to design requirements. The doped region 112 is divided into multiple parts that can serve as source / drain regions. For example... Figure 2 and Figure 3As shown, the doped region 112 can be formed before or after the formation of the trench T. Each trench T includes a first trench T1 located in the semiconductor substrate 110 and a second trench T2 located in the insulating capping layer 120. More specifically, forming the trench T in the insulating capping layer 120 and the semiconductor substrate 110 includes forming the second trench T2 through the insulating capping layer 120, and then forming the first trench T1 in the semiconductor substrate 110. In some embodiments, the trench T can be formed by dry etching or wet etching. In some embodiments, the aspect ratio (AR) of the first trench T1 is 7 to 30, such as 7, 10, 15, 20, 25, or 30, but is not limited thereto.
[0033] In operation S4, such as Figure 4 As shown, an insulating layer 130 is formed to cover the inner surface of the trench T and the insulating capping layer 120. More specifically, the insulating layer 130 covers the inner surfaces of the first trench T1 and the second trench T2 and the upper surface of the insulating capping layer 120. In some embodiments, the insulating layer 130 conformally covers the inner surface of the trench T and the insulating capping layer 120. In some embodiments, the insulating layer 130 is formed by a deposition process (e.g., atomic layer deposition). In some embodiments, the insulating layer 130 is formed at a temperature of 68°C to 82°C, for example, 68, 70, 72, 74, 76, 78, 80, or 82°C. When the temperature falls within this range, the insulating layer 130 can have good coverage. In some embodiments, the insulating layer 130 has a substantially uniform thickness. A substantially uniform thickness can be from 1 nm to 2.5 nm, for example, 1, 1.2, 1.4, 1.6, 1.8, 2, 2.2, 2.4, or 2.5 nm.
[0034] In operating S5, such as Figure 5 As shown, multiple portions of the insulating layer 130 are removed to expose the insulating capping layer 120. More specifically, the insulating layer 130 is partially removed, for example, by dry etching, to expose the upper and side surfaces of the insulating capping layer 120. After the partial removal of the insulating layer 130, the remaining portions of the insulating layer 130 remain on the inner surface of the first trench T1.
[0035] In operation S6, such as Figure 6As shown, multiple portions of the semiconductor substrate 110 are oxidized by a thermal oxidation process to form multiple insulating oxide layers 140 between the insulating layer 130 and the semiconductor substrate 110. More specifically, the insulating oxide layers 140 are grown from the semiconductor substrate 110, thus pushing the insulating layer 130 inward. In some embodiments, the insulating oxide layer 140 comprises an oxide of a semiconductor material, such as silicon dioxide or germanium dioxide, but is not limited thereto. In some embodiments, the thermal oxidation process is an in-situ vapor generation process. When the thermal oxidation process is performed, the insulating layer 130 can be densified simultaneously to improve its film quality. In some embodiments, the thermal oxidation process is performed at a temperature between 900°C and 1100°C, for example, 900, 950, 1000, 1050, or 1100°C. When the temperature falls within this range, the semiconductor substrate 110 can be partially oxidized without excessive wear, while the insulating layer 130 can also be densified to improve its film quality. Both the insulating layer 130 and the insulating oxide layer 140 have good coverage.
[0036] like Figure 6 As shown, each insulating oxide layer 140 has a thickness that gradually decreases from top to bottom. In some embodiments, each insulating oxide layer 140 has a minimum thickness t1 and a maximum thickness t2, the ratio of the minimum thickness t1 to the maximum thickness t2 being 0.9 to less than 1, for example 0.9, 0.92, 0.94, 0.96, or 0.98, which represents good thickness uniformity of the insulating oxide layer 140. This ratio is calculated by dividing the minimum thickness t1 by the maximum thickness t2. In some embodiments, the maximum thickness t2 is 1 nm to 2.5 nm, for example 1, 1.2, 1.4, 1.6, 1.8, 2, 2.2, 2.4, or 2.5 nm. When the maximum thickness t2 falls within the above range, the insulating oxide layer 140 can possess good dielectric strength.
[0037] Please see Figure 6Multiple gate insulating layers GI cover the inner surface of the first trench T1. Each gate insulating layer GI includes an insulating oxide layer 140 and an insulating layer 130. Compared to forming the gate insulating layers using only a single thermal oxidation process, operations S4 and S6 can reduce the consumption of the semiconductor substrate 110, thereby ensuring sufficient spacing SP1 between the gate insulating layers GI and forming a gate insulating layer GI with a larger bottom thickness. Since subsequent operations will form gate structures (or word lines) in the first trench T1, reducing the consumption of the semiconductor substrate 110 can prevent the spacing SP1 between the gate insulating layers GI from being excessively reduced, thereby reducing crosstalk between adjacent gate structures. In some embodiments, the bottom thickness t3 of the gate insulating layer GI of the present invention is 3.5 nm to 4 nm, for example 3.5, 3.6, 3.7, 3.8, 3.9, or 4 nm. When the bottom thickness t3 falls within this range, the gate insulating layer GI can have good TDDB reliability. For example, the TDDB voltage of the gate insulating layer GI can be, for example, about 4.3 V. When the first trench T1 has a high aspect ratio (AR), such as 7 to 30, for example 7, 10, 15, 20, 25, or 30, operations S4 and S6 can still form a gate insulating layer GI with good coverage and a relatively thick bottom thickness t3 (e.g., 3.5 nm to 4 nm). However, if the gate insulating layer is formed by a single thermal oxidation process, its thickness may be only 2 nm or less due to the high aspect ratio of the first trench T1.
[0038] Please continue reading. Figure 6 The insulating capping layer 120 directly contacts the insulating oxide layer 140 and has a side surface 122 on the insulating oxide layer 140. In some embodiments, each insulating oxide layer 140 has an outer surface 142 that is misaligned with the side surface 122 of the insulating capping layer 120; in other words, the outer surface 142 is not aligned with the side surface 122. In some embodiments, each insulating oxide layer 140 has an inner surface 144 that is misaligned with the side surface 122 of the insulating capping layer 120; in other words, the inner surface 144 is not aligned with the side surface 122.
[0039] In operating S7, such as Figures 7 to 11 As shown, multiple gate structures G are formed in the trench T and on the insulating layer 130. In other words, operation S7 is performed to form a buried gate structure G (also called a buried word line). Figure 7As shown, a barrier layer 150 is formed to cover the insulating capping layer 120 and the gate insulating layer GI. In some embodiments, the barrier layer 150 is formed by atomic layer deposition, chemical vapor deposition, physical vapor deposition, electron beam evaporation, or other suitable deposition methods. In some embodiments, the barrier layer 150 comprises a conductive material, such as titanium, tantalum, tungsten, titanium nitride, tungsten nitride, tantalum nitride, titanium silicon nitride, tantalum silicon nitride, silicon tungsten nitride, or combinations thereof, but is not limited thereto.
[0040] like Figure 8 As shown, the barrier layer 150 is partially removed to expose the side and top surfaces of the insulating cover layer 120. In some embodiments, the barrier layer 150 is partially removed by dry etching.
[0041] like Figure 9 As shown, the barrier layer 150 is recessed to reduce its thickness. After the barrier layer 150 is recessed, a plurality of grooves are formed on the barrier layer 150 and in the trench T. In some embodiments, the barrier layer 150 is recessed by dry etching. In some embodiments, the lower surface of the doped region 112 is lower than the upper surface of the barrier layer 150.
[0042] like Figure 10 As shown, a gate layer 160 is formed in the trench T and on the insulating capping layer 120. More specifically, the gate layer 160 is formed to cover the insulating capping layer 120, the gate insulating layer GI, and the barrier layer 150. In some embodiments, the gate layer 160 is formed by atomic layer deposition, chemical vapor deposition, physical vapor deposition, electron beam evaporation, or other suitable deposition methods. In some embodiments, the gate layer 160 is made of a different material than the barrier layer 150. In some embodiments, the gate layer 160 comprises polysilicon or a metal, such as tungsten, aluminum, copper, molybdenum, titanium, tantalum, ruthenium, or combinations thereof.
[0043] like Figure 11 As shown, the gate layer 160 is partially removed to reduce its thickness. After the gate layer 160 is partially removed, the gate insulating layer GI and the insulating capping layer 120 are exposed, and multiple grooves are formed on the gate layer 160 and in the trench T. Figure 11 Multiple gate structures G are shown, each gate structure G including a barrier layer 150 and a gate layer 160 located on the barrier layer 150.
[0044] In operation S8, such as Figure 12 As shown, a hard mask 170 is formed on the gate structure G. The hard mask 170 directly contacts the upper surfaces of the insulating layer 130 and the insulating oxide layer 140. In some embodiments, the hard mask 170 is formed by atomic layer deposition, chemical vapor deposition, physical vapor deposition, or other suitable deposition methods.
[0045] like Figure 12 As shown, the semiconductor structure 1200 includes a semiconductor substrate 110, an insulating capping layer 120, a gate structure G, a gate insulating layer GI, and a hard mask 170. The insulating capping layer 120 is located on the semiconductor substrate 110. The gate structure G is embedded in the semiconductor substrate 110. The gate insulating layer GI is located between the gate structure G and the semiconductor substrate 110, and between the hard mask 170 and the semiconductor substrate 110, and each gate insulating layer GI includes an insulating layer 130 and an insulating oxide layer 140. The insulating layer 130 covers the gate structure G. The insulating oxide layer 140 is located between the insulating layer 130 and the semiconductor substrate 110, and has a thickness that gradually decreases from top to bottom. In some embodiments, the semiconductor structure 1200 is part of a dynamic random access memory (DRAM), and the gate structure G is a word line (WL) in a DRAM array region.
[0046] Please continue reading. Figure 12 The insulating capping layer 120 directly contacts the insulating oxide layer 140 and has a side surface 122 on the insulating oxide layer 140. In some embodiments, each insulating oxide layer 140 has an outer surface 142 away from the gate structure G, and the outer surface 142 is misaligned with the side surface 122 of the insulating capping layer 120; in other words, the outer surface 142 is not aligned with the side surface 122. In some embodiments, each insulating oxide layer 140 has an inner surface 144 facing the gate structure G, and the inner surface 144 is misaligned with the side surface 122 of the insulating capping layer 120; in other words, the inner surface 144 is not aligned with the side surface 122.
[0047] like Figure 12 As shown, each insulating oxide layer 140 has a thickness that gradually decreases from top to bottom. In some embodiments, each insulating oxide layer 140 has a minimum thickness t1 and a maximum thickness t2, the ratio of the minimum thickness t1 to the maximum thickness t2 being 0.9 to less than 1, for example 0.9, 0.92, 0.94, 0.96, or 0.98. The portions of the insulating oxide layer 140 and the insulating layer 130 located below the gate structure G ensure that the gate insulating layer GI has a sufficient breakdown voltage.
[0048] like Figure 12 As shown, each gate insulating layer GI comprises a double layer fabricated through two processes. This is in contrast to forming the gate insulating layer using only a single thermal oxidation process. Figure 1Operations S4 and S6 reduce the consumption of the semiconductor substrate 110 to ensure sufficient spacing SP2 between the gate structures G and to form a gate insulating layer GI with a relatively thick bottom thickness t3. Reducing the consumption of the semiconductor substrate 110 avoids excessive reduction of the spacing SP2 between the gate structures G, thereby reducing crosstalk between them. In some embodiments, the bottom thickness t3 of the gate insulating layer GI is 3.5 nm to 4 nm, such as 3.5, 3.6, 3.7, 3.8, 3.9, or 4 nm. When the bottom thickness t3 falls within this range, the gate insulating layer GI can have good TDDB reliability. For example, the TDDB voltage of the gate insulating layer GI can be, for example, about 4.3 V.
[0049] In summary, this invention provides a semiconductor structure and its manufacturing method. The semiconductor structure includes a semiconductor substrate, a gate structure, and a gate insulating layer. The gate insulating layer comprises a double layer manufactured through two processes. The manufacturing method of this invention reduces the consumption of the semiconductor substrate during the formation of the gate insulating layer and forms a gate insulating layer with a larger bottom thickness. Therefore, the semiconductor structure avoids crosstalk interference and achieves excellent reliability.
[0050] Although the invention has been described in considerable detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments included herein.
[0051] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from the scope or spirit of the invention. In view of the foregoing, the present invention is intended to cover modifications and variations of the invention falling within the appended claims.
[0052] [Symbol Explanation] 100: Method 110: Semiconductor substrate 112: Doped region 114: Quarantine Zone 120: Insulation Covering 122: Side surface 130: Insulation layer 140: Insulating oxide layer 142: Outer surface 144: Inner surface 150: Barrier Layer 160: Gate layer 170: Hard Mask 1200: Semiconductor Structure G: Gate structure GI: Gate insulating layer S1, S2, S3, S4, S5, S6, S7, S8: Operations SP1, SP2: Spacing t1: Minimum thickness t2: Maximum thickness t3: Bottom thickness T: Trench T1: First trench T2: Second groove.
Claims
1. A semiconductor structure, characterized in that, include: Semiconductor substrate; A gate structure is embedded in the semiconductor substrate; as well as A gate insulating layer, located between the gate structure and the semiconductor substrate, and comprising: An insulating layer covers the gate structure; as well as An insulating oxide layer is located between the insulating layer and the semiconductor substrate, and has a thickness that gradually decreases from top to bottom.
2. The semiconductor structure according to claim 1, wherein the semiconductor substrate comprises a semiconductor material, and the insulating oxide layer comprises an oxide of the semiconductor material.
3. The semiconductor structure according to claim 1, wherein the bottom thickness of the gate insulating layer is 3.5 nm to 4 nm.
4. The semiconductor structure according to claim 1, wherein the insulating oxide layer has a minimum thickness and a maximum thickness, the ratio of the minimum thickness to the maximum thickness being 0.9 to less than 1.
5. The semiconductor structure according to claim 1, wherein, It also includes: an insulating capping layer located on the semiconductor substrate, wherein the insulating capping layer has a side surface located on the insulating oxide layer, and the insulating oxide layer has an outer surface that is away from the gate structure and misaligned with the side surface of the insulating capping layer.
6. The semiconductor structure according to claim 1, wherein, It also includes: an insulating capping layer located on the semiconductor substrate, wherein the insulating capping layer has a side surface located on the insulating oxide layer, and the insulating oxide layer has an inner surface facing the gate structure and offset from the side surface of the insulating capping layer.
7. The semiconductor structure according to claim 1, wherein, It also includes an insulating capping layer located on the semiconductor substrate, wherein the insulating capping layer is in direct contact with the insulating oxide layer.
8. The semiconductor structure according to claim 1, wherein, It also includes a hard mask located on the gate structure and in direct contact with multiple upper surfaces of the insulating layer and the insulating oxide layer.
9. The semiconductor structure of claim 1, wherein the insulating layer has a substantially uniform thickness.
10. The semiconductor structure of claim 1, wherein the gate structure includes a barrier layer and a gate layer located on the barrier layer.
11. A method for manufacturing a semiconductor structure, characterized in that, include: A first trench is formed in the semiconductor substrate; An insulating layer is formed to cover the inner surface of the first trench; A portion of the semiconductor substrate is oxidized by a thermal oxidation process to form an insulating oxide layer between the insulating layer and the semiconductor substrate; as well as A gate structure is formed in the first trench and on the insulating layer.
12. The method of claim 11, wherein the insulating layer is formed by atomic layer deposition.
13. The method of claim 12, wherein the insulating layer is formed at a temperature of 68°C to 82°C.
14. The method according to claim 11, wherein the thermal oxidation process is an in-situ steam generation process.
15. The method of claim 14, wherein the thermal oxidation process is performed at a temperature of 900°C to 1100°C.
16. The method of claim 11, wherein the insulating oxide layer has a thickness that gradually decreases from top to bottom.
17. The method of claim 11, wherein the insulating oxide layer has a minimum thickness and a maximum thickness, the ratio of the minimum thickness to the maximum thickness being 0.9 to less than 1.
18. The method according to claim 11, wherein, Also includes: Before forming the first trench in the semiconductor substrate, an insulating capping layer is formed on the semiconductor substrate, and a second trench is formed to pass through the insulating capping layer; as well as The insulating layer is formed to cover the insulating covering layer.
19. The method according to claim 18, wherein, Also includes: Before oxidizing this portion of the semiconductor substrate through the thermal oxidation process, a portion of the insulating layer is removed to expose the insulating cover layer.
20. The method of claim 18, wherein the insulating cover layer is in direct contact with the insulating oxide layer.