A semiconductor structure and a method of fabricating the same

Abstract

The application provides a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a drift region and a body region which are arranged at intervals in a semiconductor substrate, a local oxidation layer is formed above the drift region of the semiconductor substrate near the body region, the local oxidation layer has a beak structure, the beak structure is arranged at the end of the local oxidation layer near the body region, the drift region is provided with a reverse type doped region, part of the reverse type doped region is located below the beak structure, part of the reverse type doped region is located near the body region on the side of the beak structure, and the reverse type doped region is connected with the surface of the beak structure; wherein the drift region is doped with first type doped ions, the body region and the reverse type doped region are doped with second type doped ions, and the doped types of the first type doped ions and the second type doped ions are opposite, so as to inhibit the hot carrier injection (HCI) effect and improve the reliability of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and its preparation method. Background Technology

[0002] In the field of integrated circuit manufacturing, the BCD (Bipolar-CMOS-DMOS) process platform is widely used in high-voltage power integrated circuits, especially in power management, LCD driving, and other fields with stringent requirements for high voltage and high reliability. High-voltage NLDMOS (Laterally Diffused Metal-Oxide Semiconductor) devices, as one of the key components in the BCD platform, typically employ N-type injection combined with LOCOS (Local Oxidation) technology in their drift regions to extend the current path, increase the breakdown voltage, and achieve the turn-on and turn-off functions under high-voltage conditions.

[0003] Currently, the drift region of high-voltage NLDMOS is typically formed only through two N-type injections (such as NDR and HNDR), lacking fine-grained control over the surface electric field distribution of the drift region. Because the LOCOS process forms a bird's beak structure A on the source side, this area is prone to forming a collisional ionization concentration region during device operation, leading to a significant hot carrier injection (HCI) effect. The HCI effect causes carrier injection into the gate oxide layer, resulting in reliability issues such as threshold voltage drift and transconductance degradation, and in severe cases, device failure.

[0004] To address these issues, the electric field distribution is typically optimized by adjusting the dose, energy, or distribution of N-type injection (such as NDR and HNDR). However, such adjustments simultaneously affect the overall doping concentration in the drift region, thereby impacting key electrical parameters such as the device's on-resistance and breakdown voltage. Furthermore, they can negatively influence the performance of other parasitic LDMOS devices, making it difficult to achieve compatible optimization of the performance and reliability of multiple devices at the platform level.

[0005] Therefore, how to effectively suppress the HCI effect of high-voltage NLDMOS devices and improve device reliability without significantly changing the existing process structure or increasing manufacturing costs has become a pressing technical problem in this field. Summary of the Invention

[0006] The purpose of this invention is to provide a semiconductor structure and its fabrication method, which can solve the problem of severe HCI effect and poor reliability caused by the concentration of collisional ionization on the surface of the drift region.

[0007] To solve the above technical problems, the present invention provides a semiconductor structure including a drift region and a body region disposed at intervals in a semiconductor substrate. A local oxide layer is formed above the drift region on the side of the semiconductor substrate near the body region. The local oxide layer has a bird's beak structure, which is disposed at the end of the local oxide layer near the body region. The drift region has an inversion doped region, part of which is located below the bird's beak structure and part of which is located on the side of the bird's beak structure near the body region. The inversion doped region is in contact with the surface of the bird's beak structure.

[0008] The drift region is doped with a first type of dopant ions, and both the body region and the inversion dopant region are doped with a second type of dopant ions, wherein the doping types of the first type of dopant ions and the second type of dopant ions are opposite.

[0009] In some embodiments, the first type of doped ion is an N-type ion, and the second type of doped ion is a P-type ion.

[0010] In some embodiments, the width of the inversion doped region located below the beak structure is typically 0.2 μm to 0.6 μm.

[0011] In some embodiments, the width of the inversion doped region located below the beak structure is typically 0.4 μm.

[0012] In some embodiments, the implanted ions in the inversion doped region are boron, indium, or elements from the fifth group of the fourth element in the periodic table.

[0013] In some embodiments, the semiconductor structure is a high-voltage NLDMOS device.

[0014] On the other hand, the present invention also provides a method for preparing a semiconductor structure, comprising the following steps:

[0015] A first well region consisting of a drift region and a body region spaced apart is formed in a semiconductor substrate. A local oxide layer is formed above the drift region on the side of the semiconductor substrate near the body region. The local oxide layer has a bird's beak structure, which is located at the end of the local oxide layer near the body region. The drift region is doped with a first type of dopant ions, and the first well region is doped with a second type of dopant ions. The doping types of the first type of dopant ions and the second type of dopant ions are opposite.

[0016] A patterned mask layer is formed, the patterned mask layer having a first opening and a second opening, the first opening exposing the first well region and the semiconductor substrate surrounding the first well region, and the second opening exposing the bird beak structure and the drift region near the bird beak structure;

[0017] Using the patterned mask layer and bird beak structure as a mask, a second type of ion implantation is performed on the semiconductor substrate at the first opening and the second opening to form a second well region of the body region at the first opening and an inversion doped region at the second opening, wherein the inversion doped region is in contact with the surface of the bird beak structure of the local oxide layer.

[0018] In some embodiments, the dopant element implanted when forming the inversion doped region is boron, indium, or a group 5 element in the periodic table.

[0019] In some embodiments, when the implanted dopant element is boron or indium, the implantation energy ranges from 100keV to 280keV, and the total dose ranges from 3×10¹² atoms / cm² to 3×10¹³ atoms / cm².

[0020] In some embodiments, the width of the inversion doped region located below the beak structure is typically 0.2 μm to 0.6 μm.

[0021] Compared with the prior art, the present invention has the following unexpected technical effects:

[0022] This invention provides a semiconductor structure and its fabrication method. The semiconductor structure includes a drift region and a body region spaced apart in a semiconductor substrate. A local oxide layer is formed above the drift region on the side of the semiconductor substrate near the body region. The local oxide layer has a bird's beak structure, which is located at the end of the local oxide layer near the body region. The drift region has an inversion doped region, part of which is located below the bird's beak structure and part of which is located on the side of the bird's beak structure near the body region. The inversion doped region is in contact with the surface of the bird's beak structure. The drift region is doped with a first type of dopant ion, and both the body region and the inversion doped region are doped with a second type of dopant ion. The doping types of the first and second types of dopant ions are opposite to suppress the hot carrier injection (HCI) effect and improve device reliability. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a semiconductor structure.

[0024] Figure 2 This is a schematic diagram of the structure of a semiconductor substrate provided in an embodiment of the present invention.

[0025] Figure 3 This is a schematic diagram of the structure of a graphical mask layer provided in an embodiment of the present invention.

[0026] Figure 4 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present invention.

[0027] Figure 5 The diagram shows the collision ionization curves of semiconductor structures in the prior art and semiconductor structures in embodiments of the present invention.

[0028] Explanation of reference numerals in the attached figures:

[0029] 101-Substrate; 102-First buried layer; 103-First deep well layer; 104-Second buried layer; 105-Second deep well layer; 106-Isolation structure; 107-First implantation region; 108-First well region; 109-Second well region; 110-Inversion doped region; 111-Second implantation region; 113-Isolation structure; 106-Doped region; 114-Drain; 115-First heavily doped region; 116-Second heavily doped region; 200-Local oxide layer; 201-Bird's beak structure; 210-Mask layer; 211-First opening; 212-Second opening. Detailed Implementation

[0030] The following will provide a more detailed description of a semiconductor structure and its fabrication method according to the present invention. The invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0031] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not detailed in detail, as they would obscure the invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific objectives, such as changes from one embodiment to another according to limitations related to the system or business. Furthermore, it should be understood that such development work may be complex and time-consuming, but is merely routine work for those skilled in the art.

[0032] To make the objectives and features of the present invention more apparent and understandable, the specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to conveniently and clearly assist in illustrating the objectives of the embodiments of the present invention.

[0033] As described in the background section, in high-voltage NLDMOS devices, the LOCOS beak region A near the source is the area with the most concentrated electric field. Since the drift region consists only of N-type injection, a high electric field peak easily forms in this region, causing carriers to be accelerated under the combined action of the transverse and longitudinal electric fields of the channel, resulting in violent collisional ionization with the crystal lattice. The high-energy hot carriers (electrons or holes) generated by collisional ionization may cross the Si-SiO2 interface barrier and be injected into the gate oxide layer, causing the device's threshold voltage (Vth) to drift and transconductance to decrease, and in severe cases, causing the entire circuit to fail. With the continuous shrinking of device size and the continuous increase in operating voltage, the HCI effect has become one of the key bottlenecks restricting the reliability of high-voltage LDMOS.

[0034] To address the HCI (High-Input Compatibility) problem, the conventional approach is to adjust the N-type injection dose and energy in the drift region to optimize the electric field distribution. However, in complex BCD platforms, high-voltage NLDMOS devices often share some injection processes with other types of LDMOS devices (such as medium-voltage and low-voltage devices). Simply adjusting the N-type injection at either the NDR or HNDR stages is insufficient for precisely optimizing the bird's beak structure of high-voltage devices, and the degree of adjustment is strictly limited by the overall platform compatibility. This limitation means that it is impossible to simultaneously meet the electrical performance (such as on-state current Idlin and breakdown voltage BV) and reliability (HCI) requirements of all NLDMOS devices on the platform, often requiring a trade-off between sacrificing some performance aspect for a balance.

[0035] To address the above technical problems, the present invention provides a semiconductor structure, particularly a high-voltage NLDMOS device, suitable for BCD platforms, for example, with a rated operating voltage of 120V (e.g., the NLD120V_HS device).

[0036] like Figure 4As shown, the semiconductor structure includes a drift region and a body region spaced apart in a semiconductor substrate. A local oxide layer 200 is formed above the drift region on the side of the semiconductor substrate near the body region. The local oxide layer 200 has a bird's beak structure 201, which is located at the end of the local oxide layer 200 near the body region. The drift region has an inversion doped region 110, part of which is located below the bird's beak structure 201 and part is located on the side of the bird's beak structure 201 near the body region, and the inversion doped region 110 is in contact with the surface of the bird's beak structure 201. The drift region is doped with a first type of dopant ions, and both the body region and the inversion doped region 110 are doped with a second type of dopant ions, with the doping types of the first and second types of dopant ions being opposite. This embodiment of the semiconductor structure, by providing an inversion injection region with an inverse doping type opposite to that of the drift region in the drift region near the bird's beak structure 201 of the local oxide layer 200, suppresses the hot carrier injection (HCI) effect and improves device reliability.

[0037] like Figure 4 As shown, the semiconductor structure (high-voltage NLDMOS device) includes a semiconductor substrate, which comprises a base 101 and an epitaxial layer disposed on the base 101. The base 101 is typically a P-type silicon substrate, which provides mechanical support and electrical grounding reference for the device. The epitaxial layer serves as the carrier of the device's active electrode, for example, an N-type epitaxial silicon layer.

[0038] A first buried layer 102 and a second buried layer 104 are disposed in the substrate 101, with the second buried layer 104 spaced above the first buried layer 102. The first buried layer 102 is used to reduce parasitic resistance and prevent latch-up effects, and is doped with a first type of dopant ions. The second buried layer 104 is used for electrical isolation of high-voltage devices, and is doped with a second type of dopant ions, with the doping type of the first type of dopant ions being the opposite of that of the second type of dopant ions. In this embodiment, the first type of dopant ions are N-type ions, and the second type of dopant ions are P-type ions.

[0039] A first deep well layer 103 is disposed outside the first buried layer 102, and a second deep well layer 105 is disposed above the first deep well layer 103. The first deep well layer 103 is located at the end of the first buried layer 102 in the direction from the source to the drain 114, and the second deep well layer 105 is disposed at a distance from the second buried layer 104 in the direction from the source to the drain 114. Both the first deep well layer 103 and the second deep well layer 105 are doped with type I doped ions, and the ion doping concentration of the first deep well layer 103 is greater than that of the second deep well layer 105. The first deep well layer 103 can optimize the electric field distribution in the vertical direction of the drift region, which helps to distribute the current and electric field more uniformly, reduce local hot spots, and improve the safe operating area of ​​the device. The second deep well layer 105 is used for isolation and withstand voltage. The first deep well layer 103 and the second deep well layer 105 cooperate to form a vertical low-resistance channel, further reducing the resistance when the device is turned on.

[0040] The epitaxial layer comprises a drift region and a body region, which are adjacent to each other and spaced apart. A source electrode is disposed within the body region, and a drain electrode 114 is disposed within the drift region. A local oxide layer 200 is disposed on the epitaxial layer near the body region of the drift region. The local oxide layer 200 has a beak structure 201 at its end near the body region. An inversion doped region 110 is disposed in the drift region near the beak structure 201. The drift region is doped with first-type dopant ions, while both the body region and the inversion doped region 110 are doped with second-type dopant ions. The inversion doped region 110 is located on the surface region of the drift region and is in contact with the surface of the beak structure 201 of the local oxide layer 200. A gate structure is formed on the substrate at the boundary between the drift region and the body region.

[0041] The drift region, used to withstand high voltage and provide a current conduction path, includes a first implantation region 107 and a second implantation region 111, which together constitute the drift region. The second implantation region 111 is located in the shallow layer of the drift region (i.e., close to the surface of the semiconductor substrate), with a relatively low doping concentration, primarily serving a breakdown voltage function. The first implantation region 107 surrounds the second implantation region 111, employing high-energy implantation for a greater junction depth and a slightly higher doping concentration than the second implantation region 111, primarily reducing the on-resistance (Rdson) of the drift region. The combination of the first implantation region 107 and the second implantation region 111 results in a gradually varying doping distribution in the vertical direction of the drift region, which is beneficial for the full longitudinal expansion of the depletion layer and improves the breakdown voltage. In one embodiment, both the first implantation region 107 and the second implantation region 111 are implanted with phosphorus ions, with the implantation energy range of the second implantation region 111 being 200 keV to 1800 keV, and a total dose of 3 × 10¹² atoms / cm².

[0042] An isolation structure 106 is provided within the drift region. The isolation structure 106 is located on the side of the second injection region 111 away from the body region, and forms an isolation structure 106 region in the drift region.

[0043] The doping concentration of the body region is higher than that of the substrate 101, and it is used to form a channel and serve as the source contact region of the device. The body region includes a first well region 108 (PB) and a second well region 109 (PW). Both the first well region 108 and the second well region 109 are doped with second-type dopant ions. The length of the first well region 108 from the source to the drain 114 is less than the length of the second well region 109 in that direction, and the first well region 108 is located inside the second well region 109 in that direction. The length of the first well region 108 in the vertical direction (i.e., the epitaxial layer height direction) is greater than the length of the second well region 109 in that direction, such that the bottom of the first well region 108 extends beyond the bottom of the second well region 109.

[0044] The source electrode is formed by the interpenetration of the first heavily doped region 115 and the second heavily doped region 116. For example, the first heavily doped region 115 is doped with N-type ions and the second heavily doped region 116 is doped with P-type ions. That is, the NPN doped region is formed by the interpenetration of the heavily doped N-type region and the heavily doped P-type region, which is used to provide charge carriers. The source electrode is in contact with the metal to form the source electrode.

[0045] The drain 114 is located in the second injection region 111, which is also a heavily doped N-type region, and is used to collect charge carriers. The drain 114 is in contact with the metal to form a drain electrode.

[0046] The local oxide layer 200 is located on the epitaxial layer of the first implantation region 107, outside the second implantation region 111 and close to the body region. The local oxide layer 200 is formed into a thick oxide layer through a LOCOS (Local Oxidation of Silicon) process. The local oxide layer 200 has a bird's beak structure 201 at its end near the body region in the direction extending from the source to the drain 114. The bird's beak structure 201 is a wedge-shaped region where the oxide layer gradually thins at the edge and penetrates into the silicon. The shape and size of the bird's beak structure 201 depend on the oxidation process conditions.

[0047] The inversion-doped region 110 is located within the first implantation region 107, extending downwards from the surface of the epitaxial layer. Part of the inversion-doped region 110 is located below the bird's beak structure 201, and part is located on the side of the bird's beak structure 201 closer to the body region. The inversion-doped region 110 is a localized, small-sized P-type doped region, and its planar layout shape can be rectangular, hexagonal, or circular, etc., to avoid sharp corner electric field concentration.

[0048] In this embodiment, the inversion-doped region 110 is formed using the mask used to form the second well region 109 in the CMOS process, and is performed synchronously with the implantation of the second well region 109 in the CMOS device. Therefore, the depth of the inversion-doped region 110 is the same as the depth of the second well region 109. Furthermore, the formation of the inversion-doped region 110 does not require an additional photolithography mask, thus incurring no additional cost.

[0049] In one embodiment, the width (along the source-drain direction) of the inversion doped region 110 located below the beak structure 201 is typically 0.2 μm to 0.6 μm, preferably 0.4 μm. The dopant ions in the inversion doped region 110 can be boron or indium, with an implantation energy ranging from 100 keV to 280 keV and a total dose ranging from 3 × 10¹² atoms / cm² to 3 × 10¹³ atoms / cm². In a preferred embodiment, the implantation energy is 180 keV and the implantation dose is 1 × 10¹³ atoms / cm². The P-type doping in the inversion doped region 110 and the N-type doping in the drift region form an anti-doped structure, i.e., locally compensating for the N-type doping, thus reducing the net doping concentration in this region or even turning it into P-type (if the P-type dose is sufficiently high). This anti-doped structure alters the electric field distribution and collisional ionization rate below the beak structure 201. Boron is the most commonly used P-type impurity, with a moderate diffusion coefficient, and is easily achieved through ion implantation.

[0050] In other embodiments, the dopant ions of the inversion doped region 110 can be elements of the fifth group in the fourth periodic table (such as P, As, Sb, etc.).

[0051] Due to its large atomic weight, indium forms a shallower doping distribution after implantation and has a very low diffusion coefficient, making it suitable for forming ultra-shallow junctions. In this embodiment, because the implantation region is very shallow (near the surface), using indium allows for better control of the doping peak position, avoiding excessive diffusion during post-implantation annealing. Implantation energy: For boron, the energy is 100 keV to 200 keV; for indium, the energy is 200 keV to 280 keV (because indium has a large mass, higher energy is required to achieve the same depth). Total dose: 3 × 10¹² to 3 × 10¹³ atoms / cm². If the dose is too low (<3 × 10¹²), the anti-doping effect is not significant and cannot effectively reduce collisional ionization; if the dose is too high (>3 × 10¹³), it may cause the region to become overly p-type, resulting in an excessively low net doping concentration in the drift region or even inversion, increasing the on-resistance or reducing the breakdown voltage.

[0052] The gate structure is located on the epitaxial layer at the boundary between the drift region and the body region, and is partially disposed on the local oxide layer 200. The gate structure includes a stacked gate oxide layer and a polysilicon gate, as well as sidewalls located outside the gate oxide layer and the polysilicon gate.

[0053] In this embodiment, the HCI (hot carrier injection) effect mainly occurs at the junction of the channel end and the drift region, i.e., on the semiconductor substrate surface below the edge of the gate structure. Due to the presence of the local oxide layer 200, there is a geometrically abrupt change region on the semiconductor substrate surface at the bird's beak structure 201 on the source side, where the oxide layer thickness transitions from the thin region of the gate oxide layer to the thick region of the local oxide layer 200. When the device is in saturation operation, the drain voltage 114 is very high (e.g., 120V), and the channel lateral electric field reaches its peak in the bird's beak structure 201 region. Electrons are accelerated into hot carriers, colliding with the silicon lattice to generate electron-hole pairs. Some of the electrons generated by collisional ionization are injected into the gate oxide layer, leading to threshold voltage shift (Vt shift) and transconductance degradation. This embodiment, through TCAD simulation, shows that the location of the most concentrated collisional ionization is precisely on the semiconductor substrate surface below the bird's beak structure 201. Therefore, by introducing P-type implantation (i.e., inversion doped region 110) at this specific location, the surface electric field can be locally adjusted and the collisional ionization rate reduced without significantly affecting the overall doping distribution of the drift region.

[0054] according to Figure 5 The collisional ionization curves a and b of the semiconductor structure in this embodiment show that after the addition of the inversion doped region 110, the collisional ionization region shifts downwards from the surface. This is because the P-type implantation region causes the maximum electric field point to shift from the silicon surface to the interior (PN junction interface). The surface collisional ionization rate decreases significantly, and the overall collisional ionization integral decreases by approximately 10%. Figure 5 The horizontal axis represents the horizontal distance from the source to the drain of the device in the 114 direction, and the vertical axis represents the collisional ionization generation rate, which is the number of electron-hole pairs generated per second per unit volume due to collisional ionization.

[0055] This embodiment also provides a method for forming a semiconductor structure, including the following steps:

[0056] Step S1: A first well region consisting of a drift region and a body region spaced apart is formed in a semiconductor substrate. A local oxide layer is formed above the drift region on the side of the semiconductor substrate near the body region. The local oxide layer has a bird's beak structure, which is located at the end of the local oxide layer near the body region. The drift region is doped with a first type of dopant ions, and the first well region is doped with a second type of dopant ions. The doping types of the first type of dopant ions and the second type of dopant ions are opposite.

[0057] Step S2: Form a patterned mask layer having a first opening and a second opening, the first opening exposing the first well region and the semiconductor substrate surrounding the first well region, and the second opening exposing the bird beak structure and the drift region near the bird beak structure.

[0058] Step S3: Using the patterned mask layer and bird beak structure as a mask, perform second type ion implantation on the semiconductor substrate at the first opening and the second opening to form a second well region of the body region at the first opening and an inversion doped region at the second opening, wherein the inversion doped region is in contact with the surface of the bird beak structure of the local oxide layer.

[0059] The following combination Figures 2-4 The method for forming the semiconductor structure provided in this embodiment will be described in detail.

[0060] like Figure 2 As shown, step S1 is first performed, in which a first well region 108, consisting of a drift region and a body region spaced apart, is formed in a semiconductor substrate. A local oxide layer 200 is formed above the drift region on the side of the semiconductor substrate near the body region. The local oxide layer 200 has a bird's beak structure 201, which is located at the end of the local oxide layer 200 near the body region. The drift region is doped with a first type of dopant ions, and the first well region 108 is doped with a second type of dopant ions. The doping types of the first type of dopant ions and the second type of dopant ions are opposite.

[0061] The semiconductor substrate includes a substrate 101 and an epitaxial layer disposed on the substrate 101. A first buried layer 102 and a second buried layer 104 are disposed in the substrate 101. The second buried layer 104 is disposed above the first buried layer 102 at a distance. A first deep well layer 103 is disposed outside the first buried layer 102. A second deep well layer 105 is disposed above the first deep well layer 103. The first deep well layer 103 is disposed at the end of the first buried layer 102 in the direction from the source to the drain 114. The second deep well layer 105 is disposed outside the second buried layer 104 in the direction from the source to the drain 114 at a distance. A first well region 108 with a drift region and a body region is provided in the epitaxial layer. The drift region and the body region are adjacent and spaced apart. A local oxide layer 200 is provided on the epitaxial layer near the body region of the drift region. The local oxide layer 200 has a bird's beak structure 201 at the end near the body region. An isolation structure 106 is provided in the drift region. The isolation structure 106 is located on the side of the second implantation region 111 away from the body region and forms an isolation structure region in the drift region. An isolation structure doped region 113 is formed in the isolation structure region. The isolation structure doped region 113 is doped with second type ions.

[0062] In some embodiments, the drift region may consist only of the first implantation region 107, and the second implantation region 111 may be formed after the inversion doping region 110 is completed; the drift region may also consist of the first implantation region 107 and the second implantation region 111. This embodiment uses the drift region consisting only of the first implantation region 107 as an example.

[0063] like Figure 3As shown, step S2 is then performed to form a patterned mask layer 210. The patterned mask layer 210 has a first opening 211 and a second opening 212. The first opening 211 exposes the first well region 108 and the semiconductor substrate surrounding the first well region 108, and the second opening 212 exposes the bird beak structure 201 and the drift region near the bird beak structure 201.

[0064] In this embodiment, a PW mask (i.e., the mask required for the second well region 109) of CMOS process is used for photolithography to form a patterned photoresist layer. The patterned photoresist layer exposes the implantation region (i.e., the first opening 211) of the second well region 109, and also exposes the implantation region (i.e., the second opening 212) of the inversion doped region 110.

[0065] like Figure 4 As shown, step S3 is then performed, using the patterned mask layer 210 and bird beak structure 201 as a mask, and performing second type ion implantation on the semiconductor substrate at the first opening 211 and the second opening 212 to form a second well region 109 of the body region at the first opening 211 and an inversion doped region 110 at the second opening 212, wherein the inversion doped region 110 is in contact with the surface of the bird beak structure 201 of the local oxide layer 200.

[0066] The mask for forming the inversion doped region 110 in this step shares the same mask with the P-well implantation (i.e., the second well region 109) of the CMOS device, and is completed in the same implantation step, without adding process steps or process costs.

[0067] In one embodiment, the width (along the source-drain direction) of the inversion doped region 110 located below the beak structure 201 is typically 0.2 μm to 0.6 μm, preferably 0.4 μm.

[0068] The dopant element implanted in this step is boron or indium, with an implantation energy range of 100 keV to 280 keV and a total dose range of 3 × 10¹² atoms / cm² to 3 × 10¹³ atoms / cm². In a preferred embodiment, the implantation energy is 180 keV and the implantation dose is 1 × 10¹³ atoms / cm².

[0069] Next, the photoresist layer is removed.

[0070] Next, heavy doping of the first type of ions is performed in the first implantation region 107 near the source side to form the second implantation region 111, further forming a complete drift region. The first type of ions are heavily doped in the isolation structure 106 region of the first implantation region 107, the second implantation region 111, and the first well region 108 to form an isolation structure doped region 113 in the isolation structure 106 region, a drain 114 in the second implantation region 111, and a first heavily doped region 115 in the bulk region.

[0071] Next, a second type of ion is injected into the middle region of the first heavily doped region 115 to form a second heavily doped region 116, which further forms the source.

[0072] Finally, a gate structure is formed on the epitaxial layer at the junction of the drift region and the body region.

[0073] In summary, this invention provides a semiconductor structure and its fabrication method. The semiconductor structure includes a drift region and a body region spaced apart in a semiconductor substrate. A local oxide layer is formed above the drift region on the side of the semiconductor substrate near the body region. The local oxide layer has a bird's beak structure, which is located at the end of the local oxide layer near the body region. The drift region has an inversion doped region, part of which is located below the bird's beak structure and part of which is located on the side of the bird's beak structure near the body region. The inversion doped region is in contact with the surface of the bird's beak structure. The drift region is doped with a first type of dopant ion, and both the body region and the inversion doped region are doped with a second type of dopant ion. The doping types of the first and second types of dopant ions are opposite to suppress the hot carrier injection (HCI) effect and improve device reliability.

[0074] Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are used only to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.

[0075] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A semiconductor structure, characterized in that, The invention includes a drift region and a body region spaced apart in a semiconductor substrate. A local oxide layer is formed above the drift region on the side of the semiconductor substrate near the body region. The local oxide layer has a bird's beak structure, which is located at the end of the local oxide layer near the body region. The drift region has an inversion doped region, part of which is located below the bird's beak structure and part of which is located on the side of the bird's beak structure near the body region. The inversion doped region is in contact with the surface of the bird's beak structure. The drift region is doped with a first type of dopant ions, and both the body region and the inversion dopant region are doped with a second type of dopant ions, wherein the doping types of the first type of dopant ions and the second type of dopant ions are opposite.

2. The semiconductor structure as described in claim 1, characterized in that, The first type of doped ion is an N-type ion, and the second type of doped ion is a P-type ion.

3. The semiconductor structure as described in claim 1, characterized in that, The width of the inversion doped region located below the beak structure is typically 0.2 μm to 0.6 μm.

4. The semiconductor structure as described in claim 3, characterized in that, The width of the inversion doped region located below the beak structure is typically 0.4 μm.

5. The semiconductor structure as described in claim 1, characterized in that, The implanted ions in the inversion doped region are boron, indium, or elements from the fifth group of the fourth element in the periodic table.

6. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure is a high-voltage NLDMOS device.

7. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A first well region consisting of a drift region and a body region spaced apart is formed in a semiconductor substrate. A local oxide layer is formed above the drift region on the side of the semiconductor substrate near the body region. The local oxide layer has a bird's beak structure, which is located at the end of the local oxide layer near the body region. The drift region is doped with a first type of dopant ions, and the first well region is doped with a second type of dopant ions. The doping types of the first type of dopant ions and the second type of dopant ions are opposite. A patterned mask layer is formed, the patterned mask layer having a first opening and a second opening, the first opening exposing the first well region and the semiconductor substrate surrounding the first well region, and the second opening exposing the bird beak structure and the drift region near the bird beak structure; Using the patterned mask layer and bird beak structure as a mask, a second type of ion implantation is performed on the semiconductor substrate at the first opening and the second opening to form a second well region of the body region at the first opening and an inversion doped region at the second opening, wherein the inversion doped region is in contact with the surface of the bird beak structure of the local oxide layer.

8. The method for preparing a semiconductor structure as described in claim 7, characterized in that, The doping element injected during the formation of the inversion doped region is boron, indium, or a group 5 element in the periodic table.

9. The method for preparing a semiconductor structure as described in claim 7, characterized in that, When the implanted dopant is boron or indium, the implantation energy range is 100keV to 280keV, and the total dose range is 3×10¹² atoms / cm² to 3×10¹³ atoms / cm².

10. The method for preparing the semiconductor structure according to claim 7, characterized in that, The width of the inversion doped region located below the beak structure is typically 0.2 μm to 0.6 μm.

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