Integrated circuit device

Abstract

An integrated circuit device includes a plurality of first source / drain regions; a plurality of second source / drain regions spaced apart from the plurality of first source / drain regions in a first direction and stacked above the plurality of first source / drain regions in the first direction; a first contact disposed on a lower surface of each of the plurality of first source / drain regions in the first direction; a second contact disposed on an upper surface of each of the plurality of second source / drain regions in the first direction; a conductive rail electrically connected to the first contact or the second contact and extending in the first direction; a first diffusion break structure disposed alongside the conductive rail in a second direction that intersects the first direction; and a second diffusion break structure spaced apart from the first diffusion break structure in the second direction, and the conductive rail is between the second diffusion break structure and the first diffusion break structure.

Description

Technical Field

[0001] This disclosure relates to integrated circuit devices. Specifically, this disclosure relates to an integrated circuit device including a field-effect transistor. Background Technology

[0002] The increasing demand for miniaturization, multifunctionality, and high performance in electronic products necessitates high-capacity integrated circuit (IC) devices. To provide these devices, higher integration density is required. For example, smaller field-effect transistors (FETs) can reduce the area of ​​the IC. However, the complexity of the wiring structures used in these smaller devices reduces operating speed. Therefore, designing IC devices while considering both integration density and performance is crucial for achieving the required functionality and operating speed. Summary of the Invention

[0003] On the one hand, an integrated circuit including field-effect transistors with improved integration density and electrical performance is provided.

[0004] However, the objectives to be achieved by the exemplary embodiments of this disclosure are not limited to those described above, and other objectives will be clearly understood by those skilled in the art from the following exemplary embodiments.

[0005] According to one aspect, an integrated circuit device is provided, the integrated circuit device comprising: a plurality of first source / drain regions; a plurality of second source / drain regions, the plurality of second source / drain regions being spaced apart from the plurality of first source / drain regions in a first direction and stacked above the plurality of first source / drain regions in the first direction; a first contact disposed on a lower surface of each of the plurality of first source / drain regions in the first direction; a second contact disposed on an upper surface of each of the plurality of second source / drain regions in the first direction; a conductive rail electrically connected to the first contact or the second contact and extending in the first direction; a first diffusion blocking structure disposed adjacent to the conductive rail in a second direction intersecting the first direction; and a second diffusion blocking structure spaced apart from the first diffusion blocking structure in the second direction, and the conductive rail being located between the second diffusion blocking structure and the first diffusion blocking structure, and the conductive rail overlapping the first diffusion blocking structure and the second diffusion blocking structure in the second direction.

[0006] According to another aspect, an integrated circuit device is also provided, the integrated circuit device comprising: a plurality of first transistors, the plurality of first transistors including a plurality of first source / drain regions, a plurality of lower nanosheets connected to the plurality of first source / drain regions and spaced apart from each other in a first direction, a first gate line surrounding the plurality of lower nanosheets, and a first contact disposed on the lower surface of each of the plurality of first source / drain regions in the first direction; a plurality of second transistors, the plurality of second transistors including a plurality of second source / drain regions, a plurality of upper nanosheets connected to the plurality of second source / drain regions and spaced apart from each other in the first direction, a second gate line surrounding the plurality of upper nanosheets, and a second contact disposed on the upper surface of each of the plurality of second source / drain regions in the first direction; a plurality of conductive rails, wherein the plurality of conductive rails comprises... Each extends in the first direction to connect one of the plurality of first transistors and one of the plurality of second transistors; a first diffusion blocking structure is disposed next to one of the plurality of conductive rails in a second direction intersecting the first direction; a second diffusion blocking structure is spaced apart from the first diffusion blocking structure in the second direction, and the one of the plurality of conductive rails is located between the second diffusion blocking structure and the first diffusion blocking structure; and a gate separator structure is located between pairs of adjacent second transistors in a third direction, the third direction intersecting the first direction and the second direction, and the plurality of conductive rails overlap with the first diffusion blocking structure and the second diffusion blocking structure in the second direction.

[0007] According to another aspect, an integrated circuit device is provided, the integrated circuit device comprising: a plurality of first source / drain regions; a first contact disposed on a lower surface of each of the plurality of first source / drain regions in a first direction; a plurality of lower nanosheets connected to the plurality of first source / drain regions and spaced apart from each other in the first direction; a first gate line surrounding the plurality of lower nanosheets and extending in a second direction intersecting the first direction; a plurality of second source / drain regions spaced apart from the plurality of first source / drain regions in the first direction and stacked above the plurality of first source / drain regions in the first direction; a second contact disposed on a lower surface of each of the plurality of second source / drain regions in the first direction; and a plurality of upper nanosheets connected to... The plurality of second source / drain regions are spaced apart from each other in the first direction; a second gate line surrounds the plurality of upper nanosheets and extends in the second direction; a conductive rail electrically connected to the first contact and the second contact and extending in the first direction; a first diffusion blocking structure disposed next to the conductive rail in a third direction and in contact with the side surfaces of the first gate line and the second gate line in the second direction, the third direction intersecting the first direction and the second direction; and a second diffusion blocking structure spaced apart from the first diffusion blocking structure in the third direction, and the conductive rail is located between the second diffusion blocking structure and the first diffusion blocking structure, and the conductive rail completely overlaps the first diffusion blocking structure and the second diffusion blocking structure in the third direction.

[0008] According to another aspect, a method for manufacturing an integrated circuit is also provided, the method comprising: forming a plurality of lower nanosheets and a plurality of second upper nanosheets spaced apart from the plurality of lower nanosheets in a first direction; forming a plurality of first source / drain regions and a plurality of second source / drain regions, the plurality of first source / drain regions being positioned from the plurality of lower nanosheets in a second direction intersecting the first direction, the plurality of second source / drain regions being positioned from the plurality of upper nanosheets in the second direction; forming a first gate electrode and a second gate electrode, the first gate electrode surrounding the plurality of lower nanosheets and extending upward in a third direction intersecting the first and second directions, the second gate electrode surrounding the plurality of upper nanosheets and extending upward in the third direction; forming a gate partition structure intersecting the first gate electrode and the second gate electrode in the second direction; forming a first diffusion blocking structure and a second diffusion blocking structure overlapping the gate partition structure in the first direction and spaced apart from each other in the second direction; etching a portion of the gate partition structure by using etch selectivity between the gate partition structure, the first diffusion blocking structure and the second diffusion blocking structure to form an opening; and forming a conductive rail by filling the opening with a conductive material. Attached Figure Description

[0009] These and / or other aspects, features, and advantages of the invention will become clear and more readily understood from the following description of exemplary embodiments taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic layout diagram illustrating an integrated circuit device according to an exemplary embodiment of the present disclosure; Figure 2 It shows along Figure 1 Example diagram of the cross section intercepted by line A1-A1'; Figure 3 It shows along Figure 1 Example diagram of the cross section intercepted by line A2-A2'; Figure 4 It shows along Figure 1 Example diagram of the cross section intercepted by line B1-B1'; Figure 5 It shows along Figure 1 Example diagram of the cross section intercepted by line B2-B2'; Figure 6 It shows along Figure 1 Example diagram of the cross section intercepted by line B3-B3'; Figure 7 It shows along Figure 1 Another example diagram of the cross section intercepted by line A2-A2'; Figure 8It shows along Figure 1 Another example diagram of the cross section intercepted by line A2-A2'; Figure 9 This is a schematic layout diagram illustrating an integrated circuit device according to another exemplary embodiment of the present disclosure; Figure 10 This is a schematic layout diagram illustrating an integrated circuit device according to another exemplary embodiment of the present disclosure; Figure 11 , Figure 12 , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B Figure 17 C Figure 17D , Figure 17E , Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 18E , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 21C , Figure 22A , Figure 22B , Figure 23 , Figure 24A , Figure 24B , Figure 25A and Figure 25B This is a cross-sectional view showing a method of manufacturing an integrated circuit device according to an exemplary embodiment of the present disclosure, arranged in process sequence; Figure 15A , Figure 16A , Figure 18A , Figure 20A and Figure 21A It is a layout diagram; Figure 11 , Figure 12 , Figure 13A , Figure 14A as well as Figure 15B , Figure 17B , Figure 18B , Figure 22A , Figure 23 , Figure 24A and Figure 25A Is along Figure 1 The diagram corresponding to the cross section intercepted by line A1-A1'; Figure 16B , Figure 17C , Figure 18C , Figure 19B , Figure 20B and Figure 21B Is along Figure 1 The diagram corresponding to the cross section intercepted by line A2-A2'; Figure 15C , Figure 17D and Figure 18D Is along Figure 1 The diagram corresponding to the cross section intercepted by line B1-B1'; Figure 17E and Figure 18E Is along Figure 1 The diagram corresponding to the cross section intercepted by line B2-B2', and Figure 13B , Figure 14B , Figure 16C , Figure 19C , Figure 21C , Figure 22B , Figure 24B and Figure 25B Is along Figure 1 The diagram corresponding to the cross section intercepted by line B3-B3'. Detailed Implementation

[0010] In the following description, exemplary embodiments of the present disclosure will be illustrated with reference to the accompanying drawings. The same elements in the drawings will be indicated by the same reference numerals, and redundant descriptions will be omitted.

[0011] Figure 1 This is a schematic layout diagram illustrating an integrated circuit device according to an exemplary embodiment of the present disclosure. Figure 2 It shows along Figure 1 Example diagram of the cross section taken by line A1-A1'. Figure 3 It shows along Figure 1 Example diagram of the cross section taken by line A2-A2'. Figure 4 It shows along Figure 1 Example diagram of the cross section taken by line B1-B1'. Figure 5 It shows along Figure 1 Example diagram of the cross section taken by line B2-B2'. Figure 6 It shows along Figure 1 Example diagram of the cross section taken by line B3-B3'.

[0012] refer to Figures 1 to 6The integrated circuit device 10 may include multiple units CR. Each unit CR may include multiple first transistors LTR and multiple second transistors UTR disposed at different heights in a first direction D1. To aid in understanding this disclosure, the relative positions in the first direction D1 may be shown as vertical up or down positions, and the relative positions in the second direction D2 or the third direction D3 may be shown as horizontal left or right positions.

[0013] According to an example embodiment, the first transistor LTR can be referred to as the lower transistor. The second transistor UTR can be referred to as the upper transistor. The first source / drain region SD1 can be referred to as the lower source / drain region. The second source / drain region SD2 can be referred to as the upper source / drain region. Additionally, according to an example embodiment of this disclosure, the first gate line GL1 can be referred to as the lower gate line. The second gate line GL2 can be referred to as the upper gate line. The first gate insulating layer 122 can be referred to as the lower gate insulating layer. The second gate insulating layer 124 can be referred to as the upper gate insulating layer. Furthermore, according to an example embodiment of this disclosure, the first contact CA1 can be referred to as the lower contact. The second contact CA2 can be referred to as the upper contact. The first passage VA1 can be referred to as the lower passage. The second passage VA2 can be referred to as the upper passage.

[0014] According to an example embodiment, a plurality of second transistors UTRs may be positioned at a height higher than a plurality of first transistors LTRs in a first direction D1. Each of the plurality of cells CRs may be located in a region where various types of logic cells included in the logic circuit are disposed.

[0015] According to an example embodiment, the integrated circuit device 10 may further include a front-side wiring structure (FWS) and a back-side wiring structure (BWS). The front-side wiring structure (FWS) is disposed at a height higher than the plurality of second transistor UTRs in the first direction D1, and the back-side wiring structure (BWS) is disposed at a height lower than the plurality of first transistor LTRs in the first direction D1. In the example embodiment, the front-side wiring structure (FWS) may be configured to apply a signal voltage to the plurality of first transistor LTRs and the plurality of second transistor UTRs, and the back-side wiring structure (BWS) may be configured to apply a power supply voltage and a ground voltage to the plurality of first transistor LTRs and the plurality of second transistor UTRs.

[0016] According to an example embodiment, the integrated circuit device 10 can form a logic cell including a multi-bridge channel field-effect transistor (MBCFET) device. However, the technical concept of this disclosure is not limited thereto. The integrated circuit device 10 may include a planar field-effect transistor (planar FET) device, a gate-all-around FET device, a fin field-effect transistor (finFET) device, a FET device based on two-dimensional materials (such as a molybdenum disulfide (MoS2) semiconductor gate electrode), etc.

[0017] According to an example embodiment, each of the plurality of first transistors LTRs may include: a plurality of lower nanosheets NS1 spaced apart in a first direction D1, a first source / drain region SD1 connected to the plurality of lower nanosheets NS1, a first gate line GL1 surrounding the plurality of lower nanosheets NS1, and a first contact CA1 disposed on the lower surface of the first source / drain region SD1.

[0018] According to an example embodiment, each of the plurality of second transistors UTRs may include: a plurality of upper nanosheets NS2 spaced apart in a first direction D1, a second source / drain region SD2 connected to the plurality of upper nanosheets NS2, a second gate line GL2 surrounding the plurality of upper nanosheets NS2, and a second contact CA2 disposed on the upper surface of the second source / drain region SD2.

[0019] According to an example embodiment, the plurality of first transistor LTRs may be p-channel metal-oxide-semiconductor (PMOS) transistors, and the plurality of second transistor UTRs may be n-channel metal-oxide-semiconductor (NMOS) transistors. According to an example embodiment, the plurality of first transistor LTRs may be NMOS transistors, and the plurality of second transistor UTRs may be PMOS transistors. In other example embodiments, the plurality of first transistor LTRs may be NMOS transistors having a first threshold voltage, and the plurality of second transistor UTRs may be NMOS transistors having a second threshold voltage different from the first threshold voltage. In other example embodiments, the plurality of first transistor LTRs may be PMOS transistors having a first threshold voltage, and the plurality of second transistor UTRs may be PMOS transistors having a second threshold voltage different from the first threshold voltage.

[0020] According to an example embodiment, the plurality of lower nanosheets NS1 and the plurality of upper nanosheets NS2 may each include: group IV semiconductors, such as silicon (Si) or germanium (Ge); group IV-IV compound semiconductors, such as silicon-germanium (SiGe) or silicon carbide (SiC); or group III-V compound semiconductors, such as gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The plurality of lower nanosheets NS1 may include a first lower nanosheet NS11, a second lower nanosheet NS12, and a third lower nanosheet NS13 spaced apart in a first direction D1. The plurality of upper nanosheets NS2 may include a first upper nanosheet NS21, a second upper nanosheet NS22, and a third upper nanosheet NS23 spaced apart in the first direction D1.

[0021] According to an example embodiment, a first source / drain region SD1 may be connected to two sides of a plurality of lower nanosheets NS1 along a second direction D2. In this disclosure, the second direction D2 may be a direction in which the first source / drain region SD1 and the plurality of lower nanosheets NS1 are alternately arranged and intersect the first direction D1. The first source / drain region SD1 may have an upper surface and a lower surface, the upper surface being disposed at a height higher than the upper surface of the uppermost lower nanosheet NS1 (e.g., the third lower nanosheet NS13), and the lower surface being disposed at a height lower than the lower surface of the lowermost lower nanosheet NS1 (e.g., the first lower nanosheet NS11). In an example embodiment, the first source / drain region SD1 may include a doped silicon-germanium (SiGe) film, a doped germanium (Ge) film, a doped silicon carbide (SiC) film, or a doped indium gallium arsenide (InGaAs) film, but this is merely an example.

[0022] According to an example embodiment, a first gate line GL1 may extend in a third direction D3 to surround a plurality of lower nanosheets NS1. In this disclosure, the third direction D3 may be a direction intersecting the first direction D1 and the second direction D2. Multiple first gate lines GL1 may be provided. The multiple first gate lines GL1 may be arranged to be spaced apart in the second direction D2. A first gate insulating layer 122 may be disposed between the first gate line GL1 and each of the plurality of lower nanosheets NS1, and between the first source / drain region SD1 and the first gate line GL1. Figure 2 and Figure 4 As shown in the example, the upper and lower surfaces and two sidewalls of each of the plurality of lower nanosheets NS1 can be surrounded by a first gate insulating layer 122 and a first gate line GL1.

[0023] According to an example embodiment, the second source / drain region SD2 can be connected to two sides of a plurality of upper nanosheets NS2 in the second direction D2. The second source / drain region SD2 can be configured to be spaced apart from the first source / drain region SD1 in the first direction D1 at a position where it overlaps with the first source / drain region SD1 along the first direction D1. The second source / drain region SD2 can have an upper surface and a lower surface, the upper surface being configured at a height higher than the uppermost upper nanosheet NS2 (e.g., the third upper nanosheet NS23), and the lower surface being configured at a height lower than the lowermost upper nanosheet NS2 (e.g., the first upper nanosheet NS21). In the example embodiment, the second source / drain region SD2 may include a doped silicon-germanium (SiGe) film, a doped germanium (Ge) film, a doped silicon carbide (SiC) film, or a doped indium gallium arsenide (InGaAs) film, but this is merely an example.

[0024] According to an example embodiment, a second gate line GL2 may extend in the third direction D3 to surround a plurality of upper nanosheets NS2. Multiple second gate lines GL2 may be provided. The multiple second gate lines GL2 may be spaced apart in the second direction D2. The second gate lines GL2 may be disposed at locations overlapping with the first gate line GL1 along the first direction D1. A second gate insulating layer 124 may be disposed between the second gate line GL2 and each of the plurality of upper nanosheets NS2, and between the second source / drain region SD2 and the second gate line GL2. Figure 2 and Figure 4 As shown in the example, the upper and lower surfaces and two sidewalls of each of the plurality of upper nanosheets NS2 can be surrounded by a second gate insulating layer 124 and a second gate line GL2.

[0025] According to an example embodiment, the second gate line GL2 may include a main gate portion GL2M disposed on the upper surface of the third upper nanosheet NS23. Spacers 126 may be disposed on the two sidewalls of the main gate portion GL2M. A gate capping layer 128 may be disposed on the upper surface of the main gate portion GL2M. An upper gate insulating layer 124 may be disposed between the lower surface of the main gate portion GL2M and the third upper nanosheet NS23 and extends in a first direction D1 between the spacers 126 and the sidewalls of the main gate portion GL2M.

[0026] According to an example embodiment, the first gate line GL1 and the second gate line GL2 can be integrally formed to be electrically connected to each other. Therefore, a voltage can be simultaneously applied to the first gate line GL1 and the second gate line GL2 through the gate contact CB. However, in other example embodiments, an insulating film can be disposed between the first gate line GL1 and the second gate line GL2, such that the first gate line GL1 and the second gate line GL2 can be electrically driven independently. Although not shown in the figures, in this case, the insulating film can be disposed between the upper surface of the first gate line GL1 and the lower surface of the second gate line GL2. Based on the independent electrical drive of the first gate line GL1 and the second gate line GL2, independent electrical drive of the first transistor LTR and the second transistor UTR can be achieved.

[0027] According to an example embodiment, the first gate line GL1 and the second gate line GL2 may include doped polysilicon, metal, conductive metal nitride, conductive metal carbide, conductive metal silicide, or combinations thereof. For example, the first gate line GL1 and the second gate line GL2 may include aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), titanium nitride (TiN), tungsten nitride (WN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), or combinations thereof, but this is merely an example. In an example embodiment, the first gate line GL1 and the second gate line GL2 may include: a layer (not shown) containing a work function metal and a gap-filling metal film (not shown). The layer containing the work function metal may include at least one metal selected from titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), and palladium (Pd). The gap-filling metal film may include a tungsten (W) film or an aluminum (Al) film. In the example embodiment, the first gate line GL1 and the second gate line GL2 may include a stacked structure of titanium aluminum carbide (TiAlC) / titanium nitride (TiN) / tungsten (W), a stacked structure of titanium nitride (TiN) / tantalum nitride (TaN) / titanium aluminum carbide (TiAlC) / titanium nitride (TiN) / tungsten (W), or a stacked structure of titanium nitride (TiN) / tantalum nitride (TaN) / titanium nitride (TiN) / titanium aluminum carbide (TiAlC) / titanium nitride (TiN) / tungsten (W), but this is just an example.

[0028] According to an example embodiment, the lower gate insulating layer 122 and the upper gate insulating layer 124 may comprise a silicon oxide film, a silicon oxynitride film, a high dielectric film with a dielectric constant higher than that of the silicon oxide film, or a combination thereof. The high dielectric film may comprise a metal oxide or a metal oxynitride. For example, the high dielectric film that can be used as the lower gate insulating layer 122 and the upper gate insulating layer 124 may comprise hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), or a combination thereof, but this is merely an example.

[0029] According to an example embodiment, spacer 126 may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon carbonitride (SiCxNy), silicon carbonitride (SiOxCyNz), or combinations thereof. In an example embodiment, gate capping layer 128 may include silicon nitride or silicon oxynitride.

[0030] According to an example embodiment, the first contact CA1 may be disposed on the lower surface of the first source / drain region SD1 (e.g., as shown in the example embodiment). Figure 2 As shown, it is located below the first source / drain region SD1 or at a height lower than the first source / drain region SD1 in the first direction D1. According to an example embodiment, the second contact CA2 may be disposed on the upper surface of the second source / drain region SD2 (e.g., as shown). Figure 2 As shown, the first contact CA1 and the second contact CA2 are at a height higher than the second source / drain region SD2 in the first direction D1. In an example embodiment, the first contact CA1 and the second contact CA2 may include at least one of tungsten (W), cobalt (Co), molybdenum (Mo), nickel (Ni), ruthenium (Ru), copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium silicon nitride (TiSiN), titanium silicide (TiSi), or tungsten silicide (WSi).

[0031] According to an example embodiment, the integrated circuit device 10 may include a separating portion 130 that physically separates a first source / drain region SD1 and a second source / drain region SD2. The separating portion 130 may electrically separate the first source / drain region SD1 and the second source / drain region SD2. For example, the separating portion 130 located between the first source / drain region SD1 and the second source / drain region SD2 may electrically separate the first source / drain region SD1 and the second source / drain region SD2. The separating portion 130 may serve as an insulating film between the first source / drain region SD1 and the second source / drain region SD2.

[0032] According to an example embodiment, a conductive rail (VL) can extend along a first direction D1 between two first transistors (LTRs) adjacently disposed along a third direction D3 and between two second transistors (UTRs) adjacently disposed along a third direction D3. Multiple conductive rails (VLs) can be provided. Figure 1 As shown, multiple conductive rails VL can be spaced apart from each other in the second direction D2. The conductive rails VL can be disposed in a channel trench VH extending along the first direction D1. According to an example embodiment, the conductive rails VL may not overlap with the first diffusion breaker 210 and the second diffusion breaker 220 in the third direction D3.

[0033] According to an example embodiment, the conductive rail VL can be a wiring structure used to transmit signal voltage, power supply voltage, ground voltage, etc. from the front wiring structure FWS and the back wiring structure BWS to the first transistor LTR and the second transistor UTR.

[0034] According to an example embodiment, the conductive rail VL may include a conductor VC and an insulating pad VI. The insulating pad VI may extend conformally to the inner wall of the vertical passage trench VH. The conductor VC may fill the space in the vertical passage trench VH on the insulating pad VI.

[0035] In an example embodiment, the vertical passage trench VH may have sidewalls that are angled such that the upper width is greater than the lower width. The conductive rail VL disposed in the vertical passage trench VH may also have sidewalls that are angled such that the upper width is greater than the lower width.

[0036] In an example embodiment, the conductive rail VL can be electrically connected to a second contact CA2 adjacent to the conductive rail VL among a plurality of second contacts CA2. The second contacts CA2 can be connected by penetrating at least a portion of the conductive rail VL. In such an example embodiment, the conductive rail VL can serve as a conductive path for electrically connecting the second contacts CA2 to the back-side wiring structure BWS. In another example embodiment, the conductive rail VL can serve as a conductive path for electrically connecting the second contact CA1 to the front-side wiring structure FWS.

[0037] According to an example embodiment, the back-side insulating structure 140 can be disposed on the lower surface of the first source / drain region SD1 and below the lower surface of the lower nanosheet NS1 (e.g., Figure 2 As shown, below the first source / drain region SD1 and the lower nanosheet NS1. The back-side insulating structure 140 may include a first substrate insulating layer 142 and a second substrate insulating layer 144. The first substrate insulating layer 142 may be disposed on the lower surface of the first source / drain region SD1 and below the lower surface of the lower nanosheet NS1. The second substrate insulating layer 144 may be disposed on the lower surface of the first substrate insulating layer 142 (e.g., below the first source / drain region SD1 and below the lower nanosheet NS1). Figure 2 As shown, below the first substrate insulating layer 142).

[0038] According to an example embodiment, the first path VA1 can be electrically connected to the first contact CA1 by penetrating the second substrate insulation layer 144.

[0039] According to an example embodiment, the back-side wiring structure (BWS) can be disposed on the lower surface of the back-side insulating layer structure 140 (e.g., Figure 2As shown, below the back-side insulation structure 140. The back-side wiring structure BWS may include a first wiring line BML and a first overlay insulation layer BIL. The first wiring line BML may include a plurality of conductive patterns disposed at different vertical heights and a plurality of conductive paths for interconnecting the plurality of conductive patterns. The first overlay insulation layer BIL may include a plurality of insulating layers surrounding the plurality of conductive patterns and the plurality of conductive paths.

[0040] According to an example embodiment, the front insulating structure 160 may be disposed on the upper surface of the second source / drain region SD2 and above the second gate line GL2. The front insulating structure 160 may include a first insulating layer 162 and a second insulating layer 164. The first insulating layer 162 may cover the upper part of the second source / drain region SD2 and the sidewall of the spacer 126. The second insulating layer 164 may be disposed on the first insulating layer 162, the spacer 126, the gate capping layer 128, the second contact CA2, the first diffusion blocking structure 210, and the second diffusion blocking structure.

[0041] According to an example embodiment, the second path VA2 can be electrically connected to the second contact CA2 by penetrating the second insulating layer 164. The gate contact CB can be configured to connect to the second gate line GL2 by penetrating the second insulating layer 264 and the gate capping layer 128. The second contact CA2 can be configured to connect to the second source / drain region SD2 by penetrating the first insulating layer 162.

[0042] According to an example embodiment, the front wiring structure (FWS) may be disposed on the upper surface of the front insulation structure 160. The front wiring structure (FWS) may include a second wiring line (FML) and a second covering insulation layer (FIL). The second wiring line (FML) may include a plurality of conductive patterns disposed at different vertical heights and a plurality of conductive paths for interconnecting the plurality of conductive patterns. The second covering insulation layer (FIL) may include a plurality of insulating layers surrounding the plurality of conductive patterns and the plurality of conductive paths.

[0043] According to the example embodiment, the first contact CA1, the second contact CA2, the gate contact CB, the first passage VA1 and the second passage VA2 may include metals, such as copper (Cu), aluminum (Al) or tungsten (W), but this is just an example.

[0044] According to example embodiments, the first wiring line BML and the second wiring line FML may include metals such as copper (Cu), aluminum (Al), or tungsten (W), but this is merely an example. A barrier film may be located between the first wiring line BML and the first overlay insulating layer BIL, or between the second wiring line FML and the second overlay insulating layer FIL. The thickness of the barrier film may be from 50 angstroms (Å) to 1000 angstroms (Å). The barrier film may include titanium (Ti), tantalum (Ta), titanium nitride (TiN), or tantalum nitride (TaN). The first overlay insulating layer BIL and the second overlay insulating layer FIL may include silicon oxide, silicon nitride, silicon oxynitride, an insulating material with a permittivity lower than that of silicon oxide, or combinations thereof. In some example embodiments, the first overlay insulating layer BIL and the second overlay insulating layer FIL may include a tetraethyl orthosilicate (TEOS) film or an ultra-low K (ULK) film having an ultra-low dielectric constant K of about 2.2 to 2.4. The ULK film may include a silicon oxycarbide (SiOC) film or a silicon carbide carbon oxide (SiCOH) film.

[0045] According to an example embodiment, the first diffusion blocking structure 210 may be disposed adjacent to the conductive rails VL in the second direction D2. Multiple conductive rails VL may be provided. The multiple conductive rails VL may be embedded in the gate separator structure 150. The first diffusion blocking structure 210 may be disposed between adjacent pairs of conductive rails VL spaced apart along the second direction D2. The first diffusion blocking structure 210 may be embedded in the gate separator structure 150. A portion of the first diffusion blocking structure 210 may be embedded in the gate separator oxide film 154, and the lower surface of the first diffusion blocking structure 210 may be positioned spaced apart from the gate separator pad 152 in the first direction D1. According to an example embodiment, the first diffusion blocking structure 210 may completely overlap with the gate separator structure 150 in the second direction D2. The two sidewalls of the first diffusion blocking structure 210 facing in the third direction D3 may be aligned with the two sidewalls of the gate separator pad 152 facing in the third direction D3.

[0046] According to the example embodiment, such as Figure 4As shown, the first diffusion blocking structure 210 can contact the first gate line GL1 and the second gate line GL2. The first diffusion blocking structure 210 can serve as a gate cutout for the first gate line GL1 and the second gate line GL2 extending in the third direction D3. In other words, the first diffusion blocking structure 210 can be used to electrically insulate the first gate line GL1 and the second gate line GL2, which are spaced apart in the third direction D3, from each other. The first diffusion blocking structure 210 can have a tapered shape whose width narrows from an upper portion (i.e., the portion located at a high height in the first direction D1) to a lower portion (i.e., the portion located at a low height in the first direction D1). However, this is merely an example. In some example embodiments, the first diffusion blocking structure 210 can have a shape with a constant width in the first direction D1. The gate separation structure 150 can be located between pairs of adjacent second transistors in the third direction D3 of a plurality of second transistor UTRs.

[0047] According to an example embodiment, the first diffusion blocking structure 210 or the second diffusion blocking structure 220 may be located between a plurality of first gate lines GL1 spaced apart on the third direction D3, thereby preventing the conductive rail VL from contacting the plurality of first gate lines GL1. That is, the first diffusion blocking structure 210 and the second diffusion blocking structure 220 can serve as insulators to prevent short circuits between the first gate lines GL1 and the conductive rail VL. Similarly, the first diffusion blocking structure 210 or the second diffusion blocking structure 220 may be located between a plurality of second gate lines GL2 spaced apart on the third direction D3, thereby preventing the conductive rail VL from contacting the plurality of second gate lines GL2. In other words, the first diffusion blocking structure 210 and the second diffusion blocking structure 220 can serve as insulators to prevent short circuits between the second gate lines GL2 and the conductive rail VL.

[0048] According to an example embodiment, the second diffusion blocking structure 220 may be disposed adjacent to the conductive rails VL in the second direction D2. Multiple conductive rails VL may be provided. The second diffusion blocking structure 220 may be disposed between adjacent pairs of conductive rails VL spaced apart along the second direction D2. A portion of the second diffusion blocking structure 220 may be embedded in the gate separator structure 150 in the second direction D2. A portion of the second diffusion blocking structure 220 may be embedded in the gate separator oxide film 154 and positioned to be spaced apart from the gate separator pad 152 in the first direction D1. According to an example embodiment, a portion of the second diffusion blocking structure 220 may overlap with the gate separator structure 150 in the second direction D2. That is, a sidewall of the second diffusion blocking structure 220 in the third direction D3 may be aligned with a sidewall of the gate separator pad 152 in the third direction D3.

[0049] According to the example embodiment, such as Figure 5 As shown, the second diffusion blocking structure 220 can contact the first gate line GL1 and the second gate line GL2. The second diffusion blocking structure 220 can serve as a gate cutout for the first gate line GL1 and the second gate line GL2 extending in the third direction D3. In other words, the second diffusion blocking structure 220 can be used to electrically insulate the first gate line GL1 and the second gate line GL2, which are spaced apart in the third direction D3, from each other. The second diffusion blocking structure 220 can have a tapered shape whose width narrows from an upper portion (i.e., the portion located at a high height in the first direction D1) to a lower portion (i.e., the portion located at a low height in the first direction D1). However, this is merely an example. In some example embodiments, the second diffusion blocking structure 220 can have a shape with a constant width in the first direction D1.

[0050] According to an example embodiment, the lower surface of the first lower nanosheet NS11, the lower surface of the first diffusion blocking structure 210, and the lower surface of the second diffusion blocking structure 220 may be located on the same plane. In some example embodiments, the lower surfaces of the first diffusion blocking structure 210 and the second diffusion blocking structure 220 may be located at a height lower than the lower surface of the first lower nanosheet NS11 in the first direction D1.

[0051] According to the example embodiment, the upper surface of the first diffusion blocking structure 210, the upper surface of the second diffusion blocking structure 220, and the upper surfaces of the plurality of conductive rails VL may be located on the same plane or may be coplanar with each other.

[0052] According to an example embodiment, the first diffusion blocking structure 210 and the second diffusion blocking structure 220 may include an insulating material. According to an example embodiment, the first diffusion blocking structure 210 and the second diffusion blocking structure 220 may include an insulating material such as a silicon oxide film or a silicon nitride film.

[0053] According to an example embodiment, the lower surface of the first diffusion blocking structure 210 may have a first height LV1 in the first direction D1. The lower surface of the second diffusion blocking structure 220 may have a second height LV2 in the first direction D1. The lower surface of the conductive rail VL may have a third height LV3 in the first direction D1. The first height LV1 of the lower surface of the first diffusion blocking structure 210 may be substantially equal to the second height LV2 of the lower surface of the second diffusion blocking structure 220. Furthermore, the third height LV3 of the conductive rail VL may be located at a height lower than the first height LV1 of the lower surface of the first diffusion blocking structure 210 and the second height LV2 of the lower surface of the second diffusion blocking structure 220.

[0054] As used herein, the expression “substantially equal to” can mean having the same value relative to one or more other values ​​to which it is compared, as will be understood by those skilled in the art, and allows for approximations, inaccuracies, and limits in the relevant context. In one or more respects, the terms “substantially,” “about,” and “approximately” can provide industry-accepted tolerances for the relativity between their corresponding terms and / or items, such as tolerances of ±1%, ±5%, or ±10% of the stated actual value, and other suitable tolerances.

[0055] According to an example embodiment, the integrated circuit device 10 may have a three-dimensional field-effect transistor structure, wherein a first transistor LTR and a second transistor UTR are spaced apart in a first direction D1, and a conductive rail VL may connect a back-side wiring structure BWS connected to the first transistor LTR and a front-side wiring structure FWS connected to the second transistor UTR.

[0056] According to an example embodiment, the upper surfaces of the first diffusion blocking structure 210, the second diffusion blocking structure 220, and the uppermost surface of the conductive rail VL can all be located on the same plane. As described below, the conductive rail VL can be formed between the first diffusion blocking structure 210 and the second diffusion blocking structure 220 in a self-aligned manner, and then a planarization process can be performed. According to the planarization process, the upper surfaces of the first diffusion blocking structure 210, the second diffusion blocking structure 220, and the uppermost surface of the conductive rail VL can all be located on the same plane.

[0057] According to an example embodiment, a first diffusion blocking structure 210 and a second diffusion blocking structure 220 with etch selectivity for the gate separator oxide film 154 can be provided, such that a conductive rail VL can be formed between the first diffusion blocking structure 210 and the second diffusion blocking structure 220 in a self-aligned manner. As described below, the first diffusion blocking structure 210 and the second diffusion blocking structure 220 can be formed to be spaced apart in the gate separator oxide film 154 in a second direction D2. The first diffusion blocking structure 210 and the second diffusion blocking structure 220 can have etch selectivity for the gate separator oxide film 154. After the first diffusion blocking structure 210 and the second diffusion blocking structure 220 are formed in the gate separator oxide film 154, an etching process can be performed on the gate separator oxide film 154 between the first diffusion blocking structure 210 and the second diffusion blocking structure 220, so that a via trench VH can be formed. At this point, since the first diffusion blocking structure 210 and the second diffusion blocking structure 220 have etch selectivity for the gate separator oxide film 154, the via trench VH can be formed as the gate separator oxide film 154 is etched, but the first diffusion blocking structure 210 and the second diffusion blocking structure 220 can remain essentially unetched. Then, an insulating pad VI and a conductor VC can be formed in the via trench VH, allowing the conductive rail VL to be completed. Using the process series described above, the conductive rail VL can be formed by etching without a photomask.

[0058] Figure 7 This is a cross-sectional view of an integrated circuit device 20 according to another exemplary embodiment of the present disclosure and... Figure 3 Corresponding example diagram.

[0059] Figure 7 The integrated circuit device 20 shown can be used with Figures 1 to 6 The integrated circuit device 10 shown is substantially the same or similar, except that the lower surface of the first diffusion blocking structure 210a and the lower surface of the second diffusion blocking structure 220a are at the same height in the first direction D1 as the lower surface of the conductive rail VLa. Therefore, the above references will be omitted or simplified below. Figures 1 to 6 Description of the components being described.

[0060] According to an example embodiment, the lower surface of the first diffusion blocking structure 210a may have a first height LV1a in the first direction D1. The lower surface of the second diffusion blocking structure 220a may have a second height LV2a in the first direction D1. The lower surface of the conductive rail VLa may have a third height LV3a in the first direction D1. The first height LV1a of the lower surface of the first diffusion blocking structure 210a may be substantially equal to the second height LV2a of the lower surface of the second diffusion blocking structure 220a. Furthermore, the third height LV3a of the lower surface of the conductive rail VLa may be substantially equal to the first height LV1a of the lower surface of the first diffusion blocking structure 210a and the second height LV2a of the lower surface of the second diffusion blocking structure 220a.

[0061] According to an example embodiment, a first diffusion blocking structure 210a and a second diffusion blocking structure 220a with etch selectivity for the gate separator oxide film 154 can be provided, such that conductive rails VLa can be formed between the first diffusion blocking structure 210a and the second diffusion blocking structure 220a in a self-aligned manner. After the first diffusion blocking structure 210a and the second diffusion blocking structure 220a are formed in the gate separator oxide film 154, an etching process can be performed on the gate separator oxide film 154 between the first diffusion blocking structure 210a and the second diffusion blocking structure 220a, so that a via trench VH can be formed. In the process of forming the via trench VH by etching the gate separator oxide film 154, the height of the lower surface of the via trench VH can be formed to be equal to a first height LV1a of the lower surface of the first diffusion blocking structure 210a and a second height LV2a of the lower surface of the second diffusion blocking structure 220a.

[0062] The lower surfaces of the first diffusion blocking structure 210a and the second diffusion blocking structure 220a can be located at the same height as the lower surface of the conductive rail VLa. (See also...) Figure 1 and Figure 7 The conductive rail VLa can completely overlap with both the first diffusion blocking structure 210a and the second diffusion blocking structure 220a in the second direction D2.

[0063] Figure 8 This is a cross-sectional view of an integrated circuit device 30 according to another exemplary embodiment of the present disclosure and... Figure 3 Corresponding example diagram.

[0064] Figure 8 The integrated circuit device 30 shown can be used with Figures 1 to 6The integrated circuit device 10 shown is substantially the same or similar, except that the lower surface of the first diffusion blocking structure 210b and the lower surface of the second diffusion blocking structure 220b are at a lower height in the first direction D1 than the lower surface of the conductive rail VLb is at a lower height in the first direction D1. Therefore, the above references will be omitted or simplified below. Figures 1 to 6 Description of the components being described.

[0065] According to an example embodiment, the lower surface of the first diffusion blocking structure 210b may have a first height LV1b in the first direction D1. The lower surface of the second diffusion blocking structure 220b may have a second height LV2b in the first direction D1. The lower surface of the conductive rail VLb may have a third height LV3b in the first direction D1. The first height LV1b of the lower surface of the first diffusion blocking structure 210b may be substantially equal to the second height LV2b of the lower surface of the second diffusion blocking structure 220b. Furthermore, the third height LV3b of the lower surface of the conductive rail VLb may be higher than the first height LV1b of the lower surface of the first diffusion blocking structure 210b and the second height LV2b of the lower surface of the second diffusion blocking structure 220b.

[0066] According to an example embodiment, a first diffusion blocking structure 210b and a second diffusion blocking structure 220b with etch selectivity for the gate separator oxide film 154 can be provided, such that conductive rails VLb can be formed between the first diffusion blocking structure 210b and the second diffusion blocking structure 220b in a self-aligned manner. After the first diffusion blocking structure 210b and the second diffusion blocking structure 220b are formed in the gate separator oxide film 154, an etching process can be performed on the gate separator oxide film 154 between the first diffusion blocking structure 210b and the second diffusion blocking structure 220b, so that a via trench VH can be formed. In the process of forming the via trench VH by etching the gate separator oxide film 154, the height of the lower surface of the via trench VH can be formed to be a first height LV1b higher than the lower surface of the first diffusion blocking structure 210b and a second height LV2b higher than the lower surface of the second diffusion blocking structure 220b.

[0067] The first height LV1b of the lower surface of the first diffusion blocking structure 210b and the second height LV2b of the lower surface of the second diffusion blocking structure 220b can be positioned below the third height LV3b of the lower surface of the conductive rail VLb. Thus, together with reference... Figure 1 and Figure 8 The conductive rail VLb can completely overlap with both the first diffusion blocking structure 210b and the second diffusion blocking structure 220b in the second direction D2.

[0068] Figure 9This is a schematic layout diagram illustrating an integrated circuit device 40 according to another exemplary embodiment of the present disclosure.

[0069] Figure 9 The integrated circuit device 40 shown can be used with Figures 1 to 6 The integrated circuit device 10 shown is substantially the same or similar, except that the length d1 of the gate separator structure 150 on the third direction D3 is shorter than the length d2 of the first diffusion blocking structure 210c on the third direction D3. Therefore, the above references will be omitted or simplified below. Figures 1 to 6 Description of the components being described.

[0070] refer to Figure 9 The integrated circuit device 40 may include a plurality of cells CRa. Each of the plurality of cells CRa may include a first diffusion blocking structure 210c and a second diffusion blocking structure 220c extending in a first direction D1 and a third direction D3. In addition, each of the plurality of cells CRa may include a plurality of conductive rails VL arranged to be spaced apart in a second direction D2.

[0071] According to the example embodiment, the length d2 of the first diffusion blocking structure 210c in the third direction D3 can be longer than the length d1 of the gate separator structure 150 in the third direction D3. In this case, the first diffusion blocking structure 210c can overlap with the gate separator structure 150 in the second direction D2. Specifically, when viewed from above in the first direction D1, the gate separator structure 150 can completely overlap with a portion of the first diffusion blocking structure 210c in the second direction D2.

[0072] According to an example embodiment, the first diffusion blocking structure 210c may overlap with the conductive rail VL in the second direction D2. Specifically, the conductive rail VL may completely overlap with a portion of the first diffusion blocking structure 210c in the second direction D2. When viewed from above in the first direction D1, the two sidewalls of the first diffusion blocking structure 210c facing each other in the third direction D3 may protrude from the two sidewalls of the gate spacer pad 152 facing each other in the third direction D3. Additionally, one sidewall of the second diffusion blocking structure 220c facing each other in the third direction D3 may protrude from one sidewall of the gate spacer pad 152 facing each other in the third direction D3.

[0073] According to an example embodiment, one of the two sidewalls of the first diffusion blocking structure 210c facing each other in the third direction D3 and one sidewall of the second diffusion blocking structure 220c in the third direction D3 may be located on the same plane. However, this is merely an example. In some example embodiments, the height of the sidewall of the first diffusion blocking structure 210c in the third direction D3 may be different from the height of the sidewall of the second diffusion blocking structure 220c in the third direction D3.

[0074] According to the example embodiment, with the first diffusion blocking structure 210c and the second diffusion blocking structure 220c as boundaries, the multiple conductive rails VL can be electrically insulated from each other.

[0075] Figure 10 This is a schematic layout diagram illustrating an integrated circuit device 50 according to another exemplary embodiment of the present disclosure.

[0076] Figure 10 The integrated circuit device 50 shown can be used with Figures 1 to 6 The integrated circuit device 10 shown is substantially the same or similar, except that the length d1 of the gate separator structure 150 on the third direction D3 is longer than the length d2_d of the first diffusion blocking structure 210d on the third direction D3. Therefore, the above references will be omitted or simplified below. Figures 1 to 6 Description of the components being described.

[0077] refer to Figure 10 The integrated circuit device 50 may include a plurality of cells CRb. Each of the plurality of cells CRb may include a first diffusion blocking structure 210d and a second diffusion blocking structure 220d extending in a first direction D1 and a third direction D3. In addition, each of the plurality of cells CRa may include a plurality of conductive rails VL arranged to be spaced apart in a second direction D2.

[0078] According to an example embodiment, the length d2_d of the first diffusion blocking structure 210d in the third direction D3 can be shorter than the length d1 of the gate separator structure 150 in the third direction D3. In this case, the first diffusion blocking structure 210d can overlap with a portion of the gate separator oxide film 154 in the second direction D2. However, the first diffusion blocking structure 210d may not overlap with the gate separator pad 152 in the second direction D2. According to an example embodiment, the first diffusion blocking structure 210d can overlap with the conductive rail VL in the second direction D2. Specifically, when viewed from above in the first direction D1, the conductive rail VL can completely overlap with a portion of the first diffusion blocking structure 210d in the second direction D2.

[0079] According to an example embodiment, one of the two sidewalls of the first diffusion blocking structure 210d facing each other in the third direction D3 and one sidewall of the second diffusion blocking structure 220d in the third direction D3 may be located on the same plane. However, this is merely an example. In some example embodiments, the height of the sidewall of the first diffusion blocking structure 210d in the third direction D3 may be different from the height of the sidewall of the second diffusion blocking structure 220d in the third direction D3.

[0080] According to the example embodiment, with the first diffusion blocking structure 210d and the second diffusion blocking structure 220d as boundaries, the multiple conductive rails VL can be electrically insulated from each other.

[0081] Figure 11 , Figure 12 , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 17E , Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 18E , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 21C , Figure 22A , Figure 22B , Figure 23 , Figure 24A , Figure 24B , Figure 25A and Figure 25B This is a cross-sectional view showing a method for manufacturing an integrated circuit device according to an exemplary embodiment of the present disclosure, arranged in process sequence. Figure 15A , Figure 16A , Figure 18A , Figure 20A and Figure 21A It's a layout diagram. Figure 11 , Figure 12 , Figure 13A , Figure 14A as well as Figure 15B , Figure 17B , Figure 18B , Figure 22A , Figure 23 , Figure 24A and Figure 25A Is along Figure 1 The diagram corresponding to the cross section intercepted by line A1-A1'. Figure 16B , Figure 17C , Figure 18C , Figure 19B , Figure 20B and Figure 21B Is along Figure 1 The diagram corresponding to the cross section intercepted by line A2-A2'. Figure 15C , Figure 17D and Figure 18D Is along Figure 1 The diagram corresponding to the cross section intercepted by line B1-B1'. Figure 17E and Figure 18E Is along Figure 1 The diagram corresponding to the cross section intercepted by line B2-B2', and Figure 13B , Figure 14B , Figure 16C , Figure 19C , Figure 21C , Figure 22B , Figure 24B and Figure 25B Is along Figure 1 The diagram corresponding to the cross-section intercepted by line B3-B3'. This will be described below. Figures 11 to 25B .

[0082] refer to Figure 11 An interlayer insulating layer IL can be formed over a substrate 110 including a first surface 110F and a second surface 110B (see [reference]). Figure 13B The first substrate insulating layer 142 and the lower channel stack ST1. The lower channel stack ST1 may include a plurality of lower nanosheets NS1 and a plurality of lower sacrificial layers NG1 arranged alternately.

[0083] According to example embodiments, the plurality of lower nanosheets NS1 may include: group IV semiconductors, such as silicon (Si) or germanium (Ge); group IV-IV compound semiconductors, such as silicon germanium (SiGe) or silicon carbide (SiC); or group III-V compound semiconductors, such as gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The plurality of lower sacrificial layers NG1 may include materials that are etch-selective for the plurality of lower nanosheets NS1. In some example embodiments, the plurality of lower nanosheets NS1 may include silicon (Si), and the plurality of lower sacrificial layers NG1 may include silicon germanium (SiGe). In some example embodiments, the plurality of lower nanosheets NS1 and the plurality of lower sacrificial layers NG1 may be formed by an epitaxial growth process. The epitaxial growth process may be a chemical vapor deposition (CVD) process such as vapor phase epitaxy (VPE) or ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy, or a combination thereof.

[0084] According to an example embodiment, an upper channel stack ST2 can be formed above the lower channel stack ST1. The upper channel stack ST2 may include a plurality of upper nanosheets NS2 and a plurality of upper sacrificial layers NG2 arranged alternately. In this case, according to the example embodiment, the thickness of the lowermost upper sacrificial layer NG2 may be greater than the thickness of the other upper sacrificial layers NG2. However, this is merely an example. In some example embodiments, the individual thicknesses of the plurality of upper sacrificial layers NG2 may be equal.

[0085] According to an example embodiment, the plurality of upper nanosheets NS2 may include: group IV semiconductors, such as silicon (Si) or germanium (Ge); group IV-IV compound semiconductors, such as silicon-germanium (SiGe) or silicon carbide (SiC); or group III-V compound semiconductors, such as gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The plurality of upper sacrificial layers NG2 may include materials that are etch-selective for the plurality of upper nanosheets NS2.

[0086] Then, multiple dummy gate lines 410 extending in the third direction D3 can be formed. The multiple dummy gate lines 410 can be configured to be spaced apart from each other at equal intervals in the second direction D2. In an example embodiment, the multiple dummy gate lines 410 can be formed using at least one of silicon oxide, silicon nitride, polysilicon, or a spin-coated hard mask. Each of the multiple dummy gate lines 410 can have a bilayer structure comprising different materials. Spacers 126 can be formed on the sidewalls of the multiple dummy gate lines 410.

[0087] refer to Figure 12The upper channel stack ST2 and the lower channel stack ST1 can be etched by using multiple dummy gate lines 410 and spacers 126 as etch masks, thereby forming a first opening portion HL1 extending on the third direction D3.

[0088] refer to Figure 13A and Figure 13B Semiconductor material can be epitaxially grown in the first opening portion HL1, thereby forming a first source / drain region SD1. The first source / drain region SD1 can cover the sidewalls of each of the plurality of lower nanosheets NS1 facing each other in the second direction D2. The upper surface of the first source / drain region SD1 can be located at a height lower than the lower surface of the lowest first upper nanosheet NS21 in the first direction D1.

[0089] refer to Figure 14A and Figure 14B A separator 130, a second source / drain region SD2, and a first insulating layer 162 can be formed in the first opening portion HL1. The separator 130 can be formed to cover the upper surface of the first source / drain region SD1 in the opening portion HL1. The separator 130 can contact the sidewall of the lowermost upper sacrificial layer NG2 among a plurality of upper sacrificial layers NG2. The upper surface of the separator 130 can be located at a height lower than the lower surface of the first upper nanosheet NS21 in the first direction D1. The separator 130 can be configured to electrically insulate the first source / drain region SD1 and the second source / drain region SD2, which will be formed later, from each other.

[0090] Then, in the first opening portion HL1 (see...) Figure 13A Semiconductor material is epitaxially grown in the nanosheet to form a second source / drain region SD2. The second source / drain region SD2 can cover the sidewalls of each of the plurality of upper nanosheets NS2 in the second direction D2. The upper surface of the second source / drain region SD2 can be located at a height higher than the upper surface of the uppermost third upper nanosheet NS23 in the first direction D1.

[0091] A first insulating layer 162 can then be formed covering the upper surface of the second source / drain region SD2. The insulating layer 162 can cover the outer sidewall of the spacer 126. In some example embodiments, a planarization process can be performed after the first insulating layer 162 has been formed. The planarization process can include, for example, a chemical mechanical polishing (CMP) process, but this is merely an example.

[0092] refer to Figure 15A , Figure 15B and Figure 15C It can remove Figure 14AThe dummy gate line 410 is shown, and the upper channel stack ST2 can be exposed. Then, multiple lower sacrificial layers NG1 can be removed (see below). Figure 14A ) and multiple upper sacrificial layers NG2 (see below) Figure 14A This allows the surface of each of the multiple lower nanosheets NS1 and multiple upper nanosheets NS2 to be exposed. The process for removing the multiple lower sacrificial layers NG1 and multiple upper sacrificial layers NG2 can be an etch-selective wet etching process.

[0093] Then, a lower gate insulating layer 122 and a first gate line GL1 can be formed in the space where multiple lower sacrificial layers NG1 have been removed, and an upper gate insulating layer 124 and a second gate line GL2 can be formed in the space where multiple upper sacrificial layers NG2 have been removed. At this time, both the first gate line GL1 and the second gate line GL2 can be spaced apart in the second direction D2 and extend in the third direction D3.

[0094] In an example embodiment, the first gate line GL1 and the second gate line GL2 may include a work function conductive layer and an embedded conductive layer. In an example embodiment, the work function conductive layer may include aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), titanium nitride (TiN), tungsten nitride (WN), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), or combinations thereof. The embedded conductive layer may include aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), titanium nitride (TiN), tungsten nitride (WN), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), or combinations thereof.

[0095] Then, a gate capping layer 128 can be formed on the second gate line GL2.

[0096] refer to Figure 16A , Figure 16B and Figure 16C A gate separator structure 150 can be formed, which traverses multiple second gate lines GL2 and multiple first gate lines GL1 extending in the third direction D3. The gate separator structure 150 can extend in the second direction D2 to cut the multiple second gate lines GL2 and multiple first gate lines GL1.

[0097] According to an example embodiment, a gate separator structure 150 can be formed by penetrating multiple first gate lines GL1, multiple second gate lines GL2, an interlayer insulating film IL, and a first substrate insulating layer 142. Portions of the multiple first gate lines GL1, multiple second gate lines GL2, an interlayer insulating film IL, and a first substrate insulating layer 142 can be etched on a first direction D1 and a third direction D3. The gate separator pad 152 can then be formed conformally within the etched space. An atomic layer deposition (ALD) method can be used to form the gate separator pad 152, but this is merely an example. After the gate separator pad 152 is formed, a gate separator oxide film 154 can be formed on the gate separator pad 152. According to an example embodiment, the gate separator oxide film 154 can have a tapered shape with a width narrowing in the direction toward the substrate 110.

[0098] refer to Figure 17A , Figure 17B , Figure 17C , Figure 17D and Figure 17E The gate separation structure 150 can be etched to form a plurality of second opening portions HL2 and a plurality of third opening portions HL3 extending in the first direction D1 and the third direction D3.

[0099] In the example embodiment, a plurality of second opening portions HL2 and a plurality of third opening portions HL3 can be arranged to be spaced apart in the second direction D2. When viewed from above in the first direction D1, only the gate separator structure 150 can be etched without etching the second gate line GL2, thereby forming the second opening portions HL2. The boundary of the second opening portion HL2 parallel to the second direction D2 and the outer wall of the gate separator pad 152 can be located in the same plane. The plurality of second opening portions HL2 can have a tapered shape with a width that narrows in the direction toward the substrate 110. The length of each of the plurality of second opening portions HL2 in the third direction D3 can be equal to the length of the gate separator structure 150 in the third direction D3.

[0100] According to an example embodiment, when viewed from above in the first direction D1, the gate separator structure 150, the interlayer insulating film IL, the second gate line GL2, and the first gate line GL1 can be etched to form a third opening portion HL3. The boundary of the third opening portion HL3 parallel to the second direction D2 and the outer wall of the gate separator pad 152 can be located in the same plane. A plurality of third opening portions HL3 can have a tapered shape with a width narrowing in the direction toward the substrate 110. The length of each of the plurality of third opening portions HL3 in the third direction D3 can be longer than the length of the gate separator structure 150 in the third direction D3 and the length of the second opening portion HL2 in the third direction D3.

[0101] According to the example embodiment, the depth of the second opening portion HL2 in the first direction D1 and the depth of the third opening portion HL3 in the third direction D1 can be equal to each other. Furthermore, the height of the lower surfaces of the second opening portion HL2 and the third opening portion HL3 in the first direction D1 can be positioned lower than the height of the lower surface of the first gate line GL1 in the first direction D1.

[0102] refer to Figure 18A , Figure 18B , Figure 18C , Figure 18D and Figure 18E A first diffusion-blocking structure 210 can be formed by filling multiple second opening portions HL2 with insulating material, and a second diffusion-blocking structure 220 can be formed by filling multiple third opening portions HL3 with insulating material. The shape of the first diffusion-blocking structure 210 can correspond to the second opening portions HL2, and the shape of the second diffusion-blocking structure 220 can correspond to the third opening portions HL3. Therefore, referring to... Figures 17A to 17E The description of the structural properties of the second opening portion HL2 and the third opening portion HL3 can be applied to the description of the structural properties of the first diffusion blocking structure 210 and the second diffusion blocking structure 220.

[0103] According to the example embodiment, both the first diffusion blocking structure 210 and the second diffusion blocking structure 220 can contact the sidewalls of the first gate line GL1 and the second gate line GL2 in a third-party direction. The statement "A can contact B in a third-party direction" means that A and B, forming the contact interface, are arranged along the third-party direction, and the contact interface is formed to intersect with or be inclined relative to the third-party direction. Furthermore, both the first diffusion blocking structure 210 and the second diffusion blocking structure 220 can contact the gate separator oxide film 154.

[0104] refer to Figure 19A , Figure 19B and Figure 19C A plurality of fourth opening portions HL4 are arranged in a direction intersecting with a plurality of first diffusion blocking structures 210 and a plurality of second diffusion blocking structures 220. The gate separator oxide film 154 can be etched on the first direction D1 to form the plurality of fourth opening portions HL4.

[0105] According to an example embodiment, the process of etching the gate separator oxide film 154 can be an etch-selective process. The first diffusion blocking structure 210 and the second diffusion blocking structure 220 can include materials that are etch-selective for the gate separator oxide film 154. Therefore, although the gate separator oxide film 154 is etched in the first direction D1 to form the fourth opening portion HL4, the etching of the first diffusion blocking structure 210 and the second diffusion blocking structure 220 can be performed very slowly compared to etching the gate separator oxide film 154. Therefore, although the fourth opening portion HL4 is formed as the etching process for the gate separator oxide film 154 is completed, the first diffusion blocking structure 210 and the second diffusion blocking structure 220 may be substantially unetched.

[0106] According to an example embodiment, a plurality of fourth opening portions HL4 can be formed to be spaced apart in the second direction D2. When viewed from above in the first direction D1, the boundaries of the fourth opening portions HL4 parallel to the third direction D3 can correspond to the outline of the first diffusion blocking structure 210 or the outline of the second diffusion blocking structure 220. The boundaries of the plurality of fourth opening portions HL4 parallel to the second direction D2 can lie on the same line.

[0107] According to an example embodiment, the lower surfaces of the plurality of fourth opening portions HL4 can be positioned at a height lower than the lower surfaces of the first diffusion blocking structure 210 and the second diffusion blocking structure 220 in the first direction D1. Additionally, in some example embodiments, the lower surfaces of the plurality of fourth opening portions HL4 can be positioned at a height lower than the upper surface of the first substrate insulating layer 142 in the first direction D1. However, this is merely an example.

[0108] refer to Figure 20A and Figure 20B Conductive material VCa and insulating material VIa can be formed in multiple fourth opening portions HL4. First, insulating material VIa can be formed to conformally cover the spaces in the multiple fourth opening portions HL4. Insulating material VIa of constant thickness can cover the spaces in the multiple fourth opening portions HL4, the upper surface of the first diffusion blocking structure 210, and the upper surface of the second diffusion blocking structure 220. Atomic layer deposition can be used in the process of forming insulating material VIa, but the method of forming insulating material VIa is not limited to this.

[0109] According to an example embodiment, after the insulating material VIa is formed, a conductive material VCa can be deposited on the insulating material VIa. The conductive material VCa can completely fill the spaces in the plurality of fourth opening portions HL4. Furthermore, the upper surface of the conductive material VCa can be formed above the upper surface of the first diffusion blocking structure 210 and the upper surface of the second diffusion blocking structure 220. The upper surface of the conductive material VCa can be formed above the upper surface of the insulating material VIa on the first diffusion blocking structure 210 and the second diffusion blocking structure 220.

[0110] refer to Figure 21A and Figure 21B It can remove conductive material VCa (see Figure 20B The upper part of the conductor VC can be formed by removing the insulating material VIa (see [link]). Figure 20B The upper part of the conductor VC and the insulating pad VI can be formed therein. The conductor VC and the insulating pad VI can be formed, and in this way, the conductive rail VL with the conductor VC and the insulating pad VI can be completed.

[0111] According to an example embodiment, the upper portions of the conductive material VCa and the upper portions of the insulating material VIa can be removed by a planarization process. After the planarization process, the upper surfaces of the first diffusion blocking structure 210, the second diffusion blocking structure 220, the upper surface of the conductor VC, and the uppermost surface of the insulating pad VI can all be located on the same plane. After the planarization process, when viewed in the first direction D1, the upper surfaces of the first diffusion blocking structure 210 and the second diffusion blocking structure 220 can both be exposed. Additionally, multiple conductive rails VL can be provided, and the multiple conductive rails VL can be arranged to be spaced apart in the second direction D2. The first diffusion blocking structure 210 or the second diffusion blocking structure 220 can be located between the multiple conductive rails VL. The planarization process can include, for example, a chemical mechanical polishing process, but this is merely an example.

[0112] According to the example embodiment, since the first diffusion blocking structure 210 and the second diffusion blocking structure 220 include materials that have etch selectivity for the gate separator oxide film 154, therefore... Figures 19A to 21B Among a series of processes, the conductive rail VL can be precisely completed using only etching, deposition and planarization processes without the need for a photomask.

[0113] refer to Figure 22A and Figure 22BA mask pattern (not shown) can be formed on the first insulating layer 162, and a portion of the first insulating layer 162 can be removed using the mask pattern to form a second contact hole (not shown). The second contact hole can be formed to the depth at which the upper portion of the second source / drain region SD2 is exposed. Additionally, a portion of the upper portion of the gate separator structure 150 and a portion of the upper portion of the conductive rail VL can be removed to form the second contact hole. The second contact hole can then be filled with a conductive material to form a second contact CA2.

[0114] According to an example embodiment, the second contact CA2 may include: an extension portion extending in a third direction D3, and a pass portion extending from the extension portion in a first direction D1. The extension portion may contact the upper surface of the conductor VC of the conductive rail VL to electrically connect to the conductive rail VL. The pass portion may contact the upper portion of the second source / drain region SD2 to electrically connect to the second source / drain region SD2. In other words, the second contact CA2 can electrically connect the conductive rail VL and the second source / drain region SD2.

[0115] refer to Figure 23 A second insulating layer 164 can be formed on the second contact CA2 and the first insulating layer 162, and a portion of the second insulating layer 164 can be removed to form a second via (not shown) and a gate contact via (not shown). The second via and the gate contact via can then be filled with a conductive material to form a second via VA2 and a gate contact CB. A front-side wiring structure FWS electrically connected to the second via VA2 and the gate contact CB can then be formed.

[0116] refer to Figure 24A and Figure 24B This allows the substrate 110 to be flipped, thereby allowing the substrate 110 (see...) Figure 23 The second surface 110B (see) Figure 23 The substrate 110 can be ground thin until the first substrate insulating layer 142 is exposed from the second surface 110B of the substrate 110.

[0117] Then, a wet etching process can be performed on the substrate 110 to remove the remaining portion of the substrate 110. During the wet etching process, the first substrate insulating layer 142 can be retained without being removed. After the substrate 110 is removed, the upper surface of the first substrate insulating layer 142 can be exposed.

[0118] Then, a mask pattern (not shown) can be formed on the first insulating layer 142, and a portion of the first insulating layer 142 can be removed by using the mask pattern to form a first contact hole (not shown). The first contact hole can be formed to a depth at which the first source / drain region SD1 is exposed. Additionally, a portion of the lower end portion of the gate separator structure 150 (which is a narrow region in the tapered structure) and a portion of the lower end portion of the conductive rail VL (which is a narrow region in the tapered structure) can be removed to form the first contact hole. The first contact hole can then be filled with a conductive material to form the first contact CA1.

[0119] According to an example embodiment, the first contact CA1 may include an extension portion extending in a third direction D3, and a pass portion extending from the extension portion in a first direction D1. The extension portion may contact the lower surface of the conductor VC of the conductive rail VL (which is the surface with the narrowest vertical cross-section in the tapered structure) to be electrically connected to the conductive rail VL. The pass portion may contact the first source / drain region SD1 to be electrically connected to the first source / drain region SD1. In other words, the first contact CA1 can electrically connect the conductive rail VL and the first source / drain region SD1.

[0120] refer to Figure 25A and Figure 25B A second substrate insulating layer 144 can be formed on the first contact CA1 and the first substrate insulating layer 142, and a portion of the second substrate insulating layer 144 can be removed to form a first via (not shown). The first via can then be filled with a conductive material to form a first via VA1. A back-side wiring structure BWS electrically connected to the first via VA1 can then be formed.

[0121] As described above, exemplary embodiments have been disclosed in the accompanying drawings and this disclosure. Specific terminology has been used to describe the technical spirit of this disclosure, but the terminology is merely for descriptive purposes and not for limiting the meaning or scope of the disclosure as described in the appended claims. Therefore, those skilled in the art will understand that various modifications or other equivalent exemplary embodiments are thus possible.

Claims

1. An integrated circuit device, the integrated circuit device comprising: Multiple first source / drain regions; A plurality of second source / drain regions, the plurality of second source / drain regions being spaced apart from the plurality of first source / drain regions in a first direction and stacked above the plurality of first source / drain regions in the first direction; A first contact is disposed on the lower surface of each of the plurality of first source / drain regions in the first direction; A second contact is disposed on the upper surface of each of the plurality of second source / drain regions in the first direction; A conductive rail, which is electrically connected to the first contact or the second contact and extends in the first direction; A first diffusion blocking structure is disposed next to the conductive rail in a second direction intersecting the first direction; as well as A second diffusion blocking structure is spaced apart from the first diffusion blocking structure in the second direction, and the conductive rail is located between the second diffusion blocking structure and the first diffusion blocking structure. The conductive rail overlaps with the first diffusion blocking structure and the second diffusion blocking structure in the second direction.

2. The integrated circuit device according to claim 1, wherein, The second diffusion blocking structure is longer in the third direction than the first diffusion blocking structure in the third direction, and the third direction intersects with the first direction and the second direction.

3. The integrated circuit device according to claim 1, wherein, The lower surface of the conductive rail is at a lower height in the first direction than the lower surface of the first diffusion blocking structure and the lower surface of the second diffusion blocking structure in the first direction.

4. The integrated circuit device according to claim 1, wherein, The height of the lower surface of the conductive rail in the first direction is equal to the height of the lower surface of the first diffusion blocking structure in the first direction and the height of the lower surface of the second diffusion blocking structure in the first direction.

5. The integrated circuit device according to claim 1, wherein, The lower surface of the conductive rail is at a height higher than the lower surface of the first diffusion blocking structure and the lower surface of the second diffusion blocking structure in the first direction.

6. The integrated circuit device according to claim 1, wherein, The upper surfaces of the first diffusion blocking structure, the second diffusion blocking structure, and the uppermost surface of the conductive rail are coplanar.

7. The integrated circuit device of claim 1, further comprising a first gate line located between pairs of first source / drain regions adjacent to each other in the second direction among the plurality of first source / drain regions. in, The first diffusion blocking structure contacts the side surface of the first gate line in a third direction, the third direction intersecting the first direction and the second direction.

8. The integrated circuit device of claim 1, further comprising a second gate line located between pairs of adjacent second source / drain regions in the second direction among the plurality of second source / drain regions. in, The first diffusion blocking structure contacts the side surface of the second gate line in a third direction, the third direction intersecting the first direction and the second direction.

9. The integrated circuit device according to claim 1, wherein, The first diffusion blocking structure and the second diffusion blocking structure include insulating materials.

10. An integrated circuit device, the integrated circuit device comprising: A plurality of first transistors, the plurality of first transistors including a plurality of first source / drain regions, a plurality of lower nanosheets connected to the plurality of first source / drain regions and spaced apart from each other in a first direction, a first gate line surrounding the plurality of lower nanosheets, and a first contact disposed on the lower surface of each of the plurality of first source / drain regions in the first direction. A plurality of second transistors, the plurality of second transistors including a plurality of second source / drain regions, a plurality of upper nanosheets connected to the plurality of second source / drain regions and spaced apart from each other in a first direction, a second gate line surrounding the plurality of upper nanosheets, and a second contact disposed on the upper surface of each of the plurality of second source / drain regions in the first direction; Multiple conductive rails, each of which extends in the first direction to connect one of the multiple first transistors and one of the multiple second transistors; A first diffusion blocking structure is disposed next to one of the plurality of conductive rails in a second direction intersecting the first direction; A second diffusion blocking structure is spaced apart from the first diffusion blocking structure in the second direction, and one of the plurality of conductive rails is located between the second diffusion blocking structure and the first diffusion blocking structure; as well as A gate separation structure is provided, located between pairs of adjacent second transistors in a third direction, the third direction intersecting the first direction and the second direction. The plurality of conductive rails overlap with the first diffusion blocking structure and the second diffusion blocking structure in the second direction.

11. The integrated circuit device according to claim 10, wherein, The first diffusion blocking structure and the second diffusion blocking structure have etch selectivity for the gate separation structure.

12. The integrated circuit device according to claim 10, wherein, The first diffusion blocking structure or the second diffusion blocking structure is located between pairs of conductive rails that are adjacent to each other in the second direction among the plurality of conductive rails.

13. The integrated circuit device according to claim 10, wherein, At least a portion of the first diffusion blocking structure and at least a portion of the second diffusion blocking structure are embedded in the gate separation structure.

14. The integrated circuit device according to claim 10, wherein, The plurality of conductive rails are embedded in the gate separation structure.

15. The integrated circuit device of claim 14, further comprising: A gate-separating oxide film surrounds the plurality of conductive rails; as well as A gate separator pad surrounds the gate separator oxide film.

16. The integrated circuit device according to claim 10, wherein, The length of the first diffusion blocking structure in the third direction is greater than the length of the gate separator structure in the third direction.

17. The integrated circuit device according to claim 10, wherein, The length of the first diffusion blocking structure in the third direction is less than the length of the gate separator structure in the third direction.

18. The integrated circuit device according to claim 10, wherein, The first diffusion blocking structure is located between the pairs of second transistors that are adjacent to each other in the third direction among the plurality of second transistors.

19. An integrated circuit device, the integrated circuit device comprising: Multiple first source / drain regions; A first contact is disposed on the lower surface of each of the plurality of first source / drain regions in a first direction; Multiple lower nanosheets are connected to the multiple first source / drain regions and spaced apart from each other in the first direction; A first gate line surrounds the plurality of lower nanosheets and extends in a second direction intersecting the first direction; A plurality of second source / drain regions, the plurality of second source / drain regions being spaced apart from the plurality of first source / drain regions in the first direction and stacked above the plurality of first source / drain regions in the first direction; A second contact is disposed on the lower surface of each of the plurality of second source / drain regions in the first direction; Multiple upper nanosheets are connected to the multiple second source / drain regions and spaced apart from each other in the first direction; A second gate line, the second gate line surrounding the plurality of upper nanosheets and extending in the second direction; A conductive rail, which is electrically connected to the first contact and the second contact and extends in the first direction; A first diffusion blocking structure is disposed next to the conductive rail in a third direction and in contact with the side surfaces of the first gate line and the second gate line in a second direction, wherein the third direction intersects the first direction and the second direction; as well as A second diffusion blocking structure is spaced apart from the first diffusion blocking structure in the third direction, and the conductive rail is located between the second diffusion blocking structure and the first diffusion blocking structure. Wherein, the conductive rail overlaps with the first diffusion blocking structure and the second diffusion blocking structure in the third direction.

20. The integrated circuit device according to claim 19, wherein, The second diffusion-blocking structure is positioned as follows: Located between pairs of first source / drain regions that are adjacent to each other in the direction of the third party, among the plurality of first source / drain regions; and Located between pairs of second source / drain regions that are adjacent to each other in the third direction among the plurality of second source / drain regions.

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