A silicon carbide CMOS integrated circuit structure
By introducing a control structure and dynamic bias compensation into SiC MOS devices, the problem of threshold voltage drift in SiC CMOS integrated circuits at high temperatures was solved, achieving stable operation in high-temperature environments and expanding application scenarios.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FUDAN UNIV NINGBO RES INST
- Filing Date
- 2026-06-10
- Publication Date
- 2026-07-14
AI Technical Summary
SiC CMOS integrated circuits suffer from severe threshold voltage drift under high temperature conditions, leading to circuit failure and increased leakage current. Existing technology improvement methods suffer from reduced integration density and increased process complexity.
Introducing a control structure into SiC MOS devices forms a synergistic control system. By defining the depletion region of the channel area through electric field and physical boundary, the threshold voltage is stabilized. This includes a three-sided trench gate structure and dynamic bias compensation.
It significantly improves the threshold voltage stability of SiC CMOS integrated circuits at high temperatures, ensuring reliable operation of the circuit in extreme environments and expanding application scenarios.
Smart Images
Figure CN122396041A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a silicon carbide CMOS integrated circuit structure. Background Technology
[0002] As a wide-bandgap semiconductor material, SiC possesses inherent advantages such as a large bandgap, high breakdown electric field, high thermal conductivity, and good high-temperature stability, making it a core material for fabricating integrated circuits used in high-temperature, high-pressure, and extreme environments. SiC complementary metal-oxide-semiconductor (CMOS) integrated circuits, due to their combination of high integration density and digital / analog logic processing capabilities, have the potential to become core devices in aerospace, oil drilling, and industrial high-temperature control applications.
[0003] Currently, SiC CMOS integrated circuits have significant shortcomings in high-temperature performance. The large drift of the threshold voltage with increasing temperature has become the core problem restricting its high-temperature applications. Specifically, the threshold voltage of SiC MOS devices has a significant negative temperature coefficient. The threshold voltage of N-type metal-oxide-semiconductor (NMOS) decreases with temperature at a rate of -4mV / ℃ to -6mV / ℃. The threshold voltage drift of P-type metal-oxide-semiconductor (PMOS) is not synchronized with that of NMOS. When the temperature rises to 300℃, the threshold voltage of NMOS is prone to drop below 0.5V or even enter the normally open state, directly destroying the core logic of CMOS "complementary cutoff-conduction", leading to circuit switching failure and a surge in leakage current.
[0004] Currently, there are virtually no methods to improve the threshold voltage drift of SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). If improvement techniques for Si devices are used, they all suffer from problems such as sacrificing integration density, complex manufacturing processes, and poor compatibility with layout design. Therefore, how to suppress high-temperature drift of the threshold voltage has become a pressing technical problem to be solved in this field. Summary of the Invention
[0005] To address the aforementioned issues, this application provides a silicon carbide CMOS integrated circuit structure that can suppress the threshold voltage drift of SiC MOS devices at high temperatures and improve the high-temperature operating limit of SiC CMOS integrated circuits.
[0006] The embodiments of this application disclose the following technical solutions: This application provides a silicon carbide CMOS integrated circuit structure, including: A substrate, first-type transistors and second-type transistors alternately arranged on the surface of the substrate along a first direction, and an isolation structure; the isolation structure is located between the first-type transistors and the second-type transistors. The first type of transistor includes a first well region located on the surface of a substrate, a second source / drain region located on the side of the first well region away from the substrate, a first gate structure embedded in the side of the first well region away from the substrate, at least two control structures, and a first source / drain region located on the side of the first gate structure close to the substrate. The first gate structure and at least two control structures are arranged at intervals along the first direction, with the at least two control structures respectively disposed on both sides of the first gate structure; the second source / drain region is located between the first gate structure and the control structure. The second type of transistor includes a second well region located on the surface of a substrate, a fourth source / drain region located on the side of the second well region away from the substrate, a second gate structure embedded in the side of the second well region away from the substrate, at least two control structures, and a third source / drain region located on the side of the second gate structure close to the substrate. The second gate structure and at least two control structures are arranged at intervals along the first direction, with the at least two control structures respectively disposed on both sides of the second gate structure; the fourth source / drain region is located between the second gate structure and the control structure.
[0007] The substrate, the first well region, the fourth source / drain region, and the third source / drain region are configured as the second conductivity type; the second well region, the second source / drain region, and the first source / drain region are configured as the first conductivity type.
[0008] In some embodiments, the control structure is a control gate structure, and the voltage of the control gate structure is the same as the voltage of the first gate structure.
[0009] In some embodiments, the first source / drain region is in contact with the first gate structure and the control gate structure on the side away from the substrate, and / or the third source / drain region is in contact with the second gate structure and the control gate structure on the side away from the substrate.
[0010] In some embodiments, the width of the first source / drain region and / or the third source / drain region decreases along a second direction in the first direction, the second direction being the direction from the substrate to the first well region.
[0011] In some embodiments, the doping concentration of the first source / drain region and / or the third source / drain region increases along a second direction, which is the direction from the substrate to the first well region.
[0012] In some embodiments, the control structure is an isolation oxide layer structure.
[0013] In some embodiments, the control structure is a third gate structure, and the gate voltage of the third gate structure is a dynamic bias voltage that varies with temperature.
[0014] In some embodiments, the control structure is a control gate structure and / or a third gate structure, and the control structure is discontinuously arranged along the third direction.
[0015] In some embodiments, the third gate structure is a dotted or short-line localized layout.
[0016] In some embodiments, the isolation structure includes an insulating material that extends through the first well region and the second well region and is embedded in the substrate.
[0017] This application establishes a synergistic control system by incorporating a first gate structure, a second gate structure, and at least two control structures within a transistor. This system enables control over the transistor's on and off states during normal operation. Simultaneously, the control structures, through electric field coordination and physical boundary definition, stabilize the depletion region of the channel, suppressing the effects of Fermi level drift at high temperatures. This significantly improves the threshold voltage stability of the device under high-temperature conditions, ensuring reliable operation even in high-temperature environments and expanding the application scenarios of integrated circuits in extreme environments. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 A schematic diagram of a silicon carbide CMOS integrated circuit structure provided in this application embodiment; Figure 2 A schematic diagram of a silicon carbide CMOS integrated circuit structure in which the width of the first source / drain region and / or the second source / drain region increases along the second direction in the first direction, as provided in the embodiments of this application. Figure 3 This is a schematic diagram of a silicon carbide CMOS integrated circuit structure with an isolation oxide layer structure, provided in an embodiment of this application. Figure 4 A schematic diagram of a silicon carbide CMOS integrated circuit structure with a third gate structure provided in an embodiment of this application; Figure 5 A schematic diagram of a silicon carbide CMOS integrated circuit structure with a gate control structure provided in this application embodiment; Figure 6 A schematic diagram of a silicon carbide CMOS integrated circuit structure with a third gate structure provided in an embodiment of this application; Figure 7 The schematic diagram of a silicon carbide CMOS integrated circuit structure provided in the embodiments of this application is a combination of a control gate structure and a third gate structure.
[0020] Explanation of reference numerals in the attached figures: 10-Silicon carbide CMOS integrated circuit structure; 11-First type transistor; 12-Second type transistor; 13-First well region; 14-Second source / drain region; 15-First gate structure; 16-Control structure; 17-First source / drain region; 18-Control gate structure; 19-Isolation oxide layer structure; 20-Third gate structure; 21-Second well region; 22-Fourth source / drain region; 23-Second gate structure; 24-Third source / drain region; 101-Substrate; 102-Isolation structure; 103-Gate metal layer; X-First direction; Y-Second direction; Z-Third direction. Detailed Implementation
[0021] The silicon carbide CMOS integrated circuit structure provided in this application can be used in the field of semiconductor technology. The above is only an example and does not limit the application field of the silicon carbide CMOS integrated circuit structure provided in this application.
[0022] In this application, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.
[0023] In the embodiments of this application, the terms "as an example" or "for example" are used to indicate that they are examples, illustrations, or explanations. Any embodiment or design that is described as "as an example" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design options. Specifically, the use of terms such as "as an example" or "for example" is intended to present the relevant concepts in a specific manner.
[0024] The terminology used in the implementation section of this application is for the purpose of explaining specific embodiments of this application only, and is not intended to limit this application.
[0025] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.
[0026] At high temperatures, the depletion regions of the P-type and N-type well regions in SiC MOS devices vary depending on the specific doping conditions. The channel surface potential drifts with changes in the depletion region. Furthermore, the higher the temperature, the greater the temperature sensitivity of the Fermi level, resulting in more significant temperature-dependent fluctuations. Existing static doping control schemes can only optimize the threshold voltage at room temperature or relatively low temperatures, and their control effectiveness diminishes considerably at ultra-high temperatures.
[0027] This application provides a silicon carbide CMOS integrated circuit structure, including: A substrate, first-type transistors and second-type transistors alternately arranged on the surface of the substrate along a first direction, and an isolation structure; the isolation structure is located between the first-type transistors and the second-type transistors. The first type of transistor includes a first well region located on the surface of a substrate, a second source / drain region located on the side of the first well region away from the substrate, a first gate structure embedded in the side of the first well region away from the substrate, at least two control structures, and a first source / drain region located on the side of the first gate structure close to the substrate. The first gate structure and at least two control structures are arranged at intervals along the first direction, with the at least two control structures respectively disposed on both sides of the first gate structure; the second source / drain region is located between the first gate structure and the control structure. The second type of transistor includes a second well region located on the surface of a substrate, a fourth source / drain region located on the side of the second well region away from the substrate, a second gate structure embedded in the side of the second well region away from the substrate, at least two control structures, and a third source / drain region located on the side of the second gate structure close to the substrate. The second gate structure and at least two control structures are arranged at intervals along the first direction, with the at least two control structures respectively disposed on both sides of the second gate structure; the fourth source / drain region is located between the second gate structure and the control structure. The substrate, the first well region, the fourth source / drain region, and the third source / drain region are configured as the second conductivity type; the second well region, the second source / drain region, and the first source / drain region are configured as the first conductivity type.
[0028] This application improves the high-temperature operating limit of SiC CMOS integrated circuits by setting a control structure in the device to suppress the threshold voltage drift of the device at high temperatures.
[0029] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0030] This application provides a silicon carbide CMOS integrated circuit structure 10, such as... Figure 1 As shown, Figure 1 This is a schematic diagram of a silicon carbide CMOS integrated circuit structure provided in an embodiment of this application.
[0031] like Figure 1 As shown, the silicon carbide CMOS integrated circuit structure 10 includes: a substrate 101, a first type transistor 11 and a second type transistor 12 alternately arranged along a first direction X on the surface of the substrate 101, and an isolation structure 102.
[0032] Specifically, in this embodiment, the substrate 101 of the silicon carbide CMOS integrated circuit structure 10 is made of SiC, with a first conductivity type of P-type and a second conductivity type of N-type. The first type transistor 11 is a PMOS transistor, and the second type transistor 12 is an NMOS transistor.
[0033] The isolation structure 102 is located between the first type transistor 11 and the second type transistor 12.
[0034] In this structure, first-type transistors 11 and second-type transistors 12 are alternately arranged on the surface of substrate 101 along the first direction X to form a CMOS complementary structure. An isolation structure 102 is disposed between adjacent first-type transistors 11 and second-type transistors 12 to achieve electrical isolation between them, avoid cross-interference between different types of transistors, and ensure the independent operation of each transistor and the logic stability of the overall circuit.
[0035] The first type of transistor 11 includes a first well region 13 located on the surface of a substrate 101, a second source / drain region 14 located on the side of the first well region 13 away from the substrate 101, a first gate structure 15 and at least two control structures 16 embedded in the side of the first well region 13 away from the substrate 101, and a first source / drain region 17 located on the side of the first gate structure 15 close to the substrate 101. The first gate structure 15 and the at least two control structures 16 are arranged at intervals along a first direction X, and the at least two control structures 16 are respectively disposed on both sides of the first gate structure 15; the second source / drain region 14 is located between the first gate structure 15 and the control structures 16.
[0036] Specifically, the first well region 13 is located on the surface of the substrate 101 and serves as the core functional region carrier of the first type transistor 11, providing basic structural support for carrier transport and gate electric field modulation within the transistor. The second source / drain region 14 serves as the carrier collection terminal of the first type transistor 11, i.e., the drain region. The first source / drain region 17 serves as the carrier injection terminal of the first type transistor 11, i.e., the source region, continuously providing carriers to the channel.
[0037] The first gate structure 15 can generate an electric field by applying a bias voltage, thereby regulating the conduction and cutoff states of the carriers in the channel within the first well region 13, and thus achieving switching control of the transistor. At least two regulation structures 16 form a synergistic regulation system with the first gate structure 15, which can fix the depletion region range of the channel within the first well region 13 through electric field coordination or physical boundary limitation, and suppress the drift of the Fermi level at high temperatures.
[0038] The second type transistor 12 includes a second well region 21 located on the surface of a substrate 101, a fourth source / drain region 22 located on the side of the second well region 21 away from the substrate 101, a second gate structure 23 embedded on the side of the second well region 21 away from the substrate 101, at least two control structures 16, and a third source / drain region 24 located on the side of the second gate structure 23 close to the substrate 101. The second gate structure 23 and the at least two control structures 16 are arranged at intervals along a first direction X, and the at least two control structures 16 are respectively disposed on both sides of the second gate structure 23; the fourth source / drain region 22 is located between the second gate structure 23 and the control structures 16.
[0039] Specifically, the second well region 21 is located on the surface of the substrate 101, serving as the core functional region carrier of the second type transistor 12. The fourth source-drain region 22 serves as the carrier collection terminal of the second type transistor 12, i.e., the drain region, used to collect carriers that have passed through the channel after being synergistically regulated by the second gate structure 23 and the control structure 16. The third source-drain region 24 serves as the carrier injection terminal of the second type transistor 12, i.e., the source region, providing a carrier source for the channel. The second gate structure 23 is the core control terminal of the second type transistor 12, and its structure and working principle are consistent with the first gate structure 15. It can generate an electric field by applying a bias voltage to regulate the conduction and cutoff states of the carriers in the channel within the second well region 21, and synergize with the first gate structure 15 to realize the logic control of the entire CMOS integrated circuit. The layout of the control structure 16 of the second type transistor 12 matches the control structure 16 of the first type transistor 11, and can work synergistically with the second gate structure 23 to fix the depletion region range of the channel within the second well region 21, achieving stability of the threshold voltage at high temperatures.
[0040] The substrate 101, the first well region 13, the fourth source / drain region 22, and the third source / drain region 24 are configured as the second conductivity type, i.e., N-type; the second well region 21, the second source / drain region 14, and the first source / drain region 17 are configured as the first conductivity type, i.e., P-type.
[0041] This application establishes a synergistic control system by incorporating a first gate structure 15, a second gate structure 23, and at least two control structures 16 within a transistor. This system enables control over the transistor's on and off states during normal operation. Simultaneously, the control structures 16, through electric field coordination and physical boundary definition, stabilize the depletion region of the channel, suppressing the effects of Fermi level drift at high temperatures. This significantly improves the threshold voltage stability of the device under high-temperature conditions, ensuring reliable operation even in high-temperature environments and expanding the application scenarios of integrated circuits in extreme environments.
[0042] It should be noted that the first gate structure 15, the second gate structure 23, and the control gate structure 18 are trench gate structures, which include a gate oxide layer and a gate polysilicon layer. The side of the first gate structure 15, the second gate structure 23, and the control gate structure 18 away from the substrate 101 is covered with a gate metal layer 103.
[0043] In some embodiments, such as Figure 1 As shown, the control structure 16 is a control gate structure 18, and the voltage of the control gate structure 18 is the same as the voltage of the first gate structure 15.
[0044] Specifically, control gate structures 18 are added on both sides of the channel of the first type transistor 11 and the second type transistor 12, forming a trench gate layout with the first gate structure 15 and the second gate structure 23 on three sides. The first gate structure 15, the second gate structure 23, and the control gate structure 18 are simultaneously biased. Through the synergistic effect of the electric fields of the multiple gates, the semiconductor material of the first well region 13 and the second well region 21 within the enclosed area is completely depleted, achieving a near-complete depletion state in the well regions. The spacing between the control gate structure 18 and the first gate structure 15 and the second gate structure 23 is 1μm to 2μm.
[0045] In the layout design of the corresponding integrated circuit structure, a new control gate structure 18 pattern is added, forming a trench-like enclosed structure with the first gate structure 15 pattern and the second gate structure 23 pattern, respectively. The first type of transistor structure and the second type of transistor structure are symmetrically arranged. The isolation structure 102 pattern cooperates with the enclosed gate pattern to further limit the horizontal expansion range of the depletion region, making its boundary clearer and more stable. The metal wiring layer has a separately designed wiring pattern for the control gate structure 18, which is separate from the wiring of the first gate structure 15 and the second gate structure 23 and does not interfere with each other. The distributed layout controls the spacing between the control gate structure 18 pattern and the active region boundary cell pattern to a few micrometers to tens of micrometers, ensuring that the temperature of each region can change synchronously and be uniformly transmitted, thereby improving the operating stability of the device at high temperatures.
[0046] The three-sided enclosed gate layout can form a synergistic electric field from multiple directions, providing a more comprehensive control range and stronger electric field than a single gate, and more reliably achieving complete depletion of the semiconductor within the enclosed area. Applying the same voltage to gate structure 18, the first gate structure 15, and the second gate structure 23 eliminates the need for complex additional voltage control circuitry, simplifying the design and ensuring consistent electric field coordination, preventing control confusion caused by voltage differences. The fully depleted channel state effectively suppresses the disordered movement of carriers and Fermi level drift at high temperatures, keeping the transistor's threshold voltage stable and preventing performance fluctuations due to temperature increases, ensuring stable operation of the circuit even in high-temperature environments. This three-sided enclosed trench gate structure does not require significant modifications to the original transistor's core layout, is relatively easy to implement, and is compatible with existing processes, balancing performance improvement and fabrication feasibility.
[0047] In some embodiments, such as Figure 2 As shown, Figure 2 This is a schematic diagram of a silicon carbide CMOS integrated circuit structure provided in an embodiment of this application, where the width of the first source / drain region and / or the second source / drain region increases along the second direction from the first direction. The first source / drain region 17, on the side facing away from the substrate 101, contacts the first gate structure 15 and the control gate structure 18, and / or the third source / drain region 24, on the side facing away from the substrate 101, contacts the second gate structure 23 and the control gate structure 18. This structural design increases the contact area between the first source / drain region 17 and the third source / drain region 24 and the channel, reduces the contact resistance of the first source / drain region 17 and the third source / drain region 24, makes the interface between the source region and the channel smoother, reduces the occurrence of inconsistent control effects in some areas, and thus reduces unstable fluctuations in the threshold voltage of the device.
[0048] In some embodiments, such as Figure 2 As shown, the width of the first source / drain region 17 and / or the third source / drain region 24 decreases along the second direction Y in the first direction X, where the second direction Y is the direction from the substrate 101 to the first well region 13.
[0049] For details, please refer to Figure 2 The first source / drain region 17 and the third source / drain region 24 have a wide-width structure on the side closest to the substrate 101, which directly increases the effective contact area between the source region and the metal electrode. According to the physical characteristics of contact resistance, the contact area is inversely proportional to the contact resistance. Wide-width contact can significantly reduce the ohmic contact resistance between the metal electrode and the source region, reduce power loss and voltage drop during electrical signal transmission, and improve the conversion efficiency of device power to carrier transport.
[0050] The first source / drain region 17 and the third source / drain region 24 have a narrow structure on the side near the channel, with their width in the first direction X corresponding to the channel width. This ensures that source carriers can only be injected into the channel along a fixed direction, preventing diffusion to both sides and thus improving the effective utilization of current. Simultaneously, this directional injection makes the current distribution within the channel more uniform, reducing situations where the local electric field is too strong or too weak, fundamentally reducing unstable fluctuations in the device's threshold voltage. It also reduces the carrier edge scattering problem caused by lateral width redundancy in traditional equal-width source regions, significantly improving the effective injection efficiency of carriers from the source region to the channel.
[0051] In some embodiments, the doping concentration of the first source / drain region 17 and / or the third source / drain region 24 increases along a second direction Y, where the second direction Y is the direction from the substrate 101 to the first well region 13.
[0052] Specifically, the doping concentration in the source region gradually increases along the second direction Y from the side closer to the substrate 101 to the side closer to the channel. This complements the structure described in the above embodiment, where the source region is wider on the side closer to the substrate 101 and narrower on the side closer to the channel. That is, the wider side has a lower doping concentration, while the narrower part has a higher doping concentration. This gradient design guides the carriers in the source region to naturally gather towards the channel side along the direction of increasing concentration, forming a regular and orderly transport path. This allows the carriers in the source region to achieve rapid and efficient transport during the directional injection into the channel by means of the concentration gradient, further improving the effective injection efficiency of carriers from the source region to the channel.
[0053] On the other hand, the connection between the narrower source region and the channel results in a more uniform current distribution across the entire source region, reducing the likelihood of excessive heat generation due to localized current concentration. This significantly reduces the thermal load on the device during high-temperature operation, effectively minimizing issues such as dopant malfunctions and internal device defects caused by localized overheating. It also reduces irregular changes in the depletion state of localized channel regions, thus ensuring a stable threshold voltage for the device at high temperatures without significant fluctuations.
[0054] In the corresponding layout design structure, the conventional source region pattern is designed as a stepped gradient pattern, with the pattern being narrower on the side closer to the channel and wider on the side farther from the channel. This achieves a correspondence between doping concentration and pattern shape, and no additional layout layers are added. It can be achieved by making local adjustments to the patterns of the original source and drain regions. This allows the depletion region of the device to achieve an ideal uniform state while maintaining the simplicity of the layout design and not increasing the complexity of design and manufacturing.
[0055] In some embodiments, such as Figure 3 As shown, Figure 3 This is a schematic diagram of a silicon carbide CMOS integrated circuit structure with an isolation oxide layer structure, provided as an embodiment of this application.
[0056] For details, please refer to Figure 3 The isolation oxide layer structure 19 can be an insulating silicon oxide-based thin film structure, respectively disposed on both sides of the first gate structure 15 of the first type transistor 11 and the second gate structure 23 of the second type transistor 12. It is arranged at intervals along the first direction X with the corresponding first gate structure 15 and second gate structure 23, forming a physically insulating boundary definition structure. Utilizing the insulating properties and structural stability of the oxide layer, it reduces the excessive expansion of the depletion region to both sides of the channel at high temperatures. The spacing between the isolation oxide layer structure 19 and the first gate structure 15 and second gate structure 23 is 0.3 μm to 0.5 μm.
[0057] The layout design of the corresponding integrated circuit structure does not require the addition of a new gate structure pattern. The metal wiring layer maintains the basic structure design. Compared with the integrated circuit structure with the control gate structure 18, the layout layer has fewer layers, the wiring is simpler, and the difficulty of photolithography and layout production is reduced.
[0058] In some embodiments, such as Figure 4 As shown, Figure 4 The diagram below shows a silicon carbide CMOS integrated circuit with a third gate structure, provided as an embodiment of this application. The gate voltage of the third gate structure 20 is a dynamic bias voltage that varies with temperature.
[0059] Specifically, refer to Figure 4 A third gate structure 20 is provided on both sides of the first gate structure 15 of the first type transistor 11 and on both sides of the second gate structure 23 of the second type transistor 12. The third gate structure 20 is independent of the first gate structure 15 and the second gate structure 23. The gate voltage of the third gate structure 20 is a dynamic bias voltage that varies with the operating temperature. The dynamic bias voltage can be applied according to the operating temperature. At room temperature, the third gate structure 20 has no bias voltage, and the device is normally controlled by the first gate structure 15 and the second gate structure 23. At high temperature, a compensation bias voltage is applied through the third gate structure 20 to reduce the channel surface potential and thus compensate for the drift of the threshold voltage.
[0060] In the layout design of the corresponding integrated circuit structure, a third gate structure 20 pattern is added to the gate layer, separate from the first gate structure 15 and the second gate structure 23 patterns. The spacing between the third gate structure 20 and the first gate structure 15 and the second gate structure 23 is designed to be 0.5μm~1μm, which ensures the synergistic effect of the electric field energy without occupying too much layout space and affecting the integration density of the circuit. The metal wiring layer is designed with an independent power supply line for the third gate structure 20, which does not intersect with the electrode wiring of the first gate structure 15, the second gate structure 23, the source region and the drain region. The bias voltage is led out through vias. The power supply interface of the third gate structure 20 is reserved on the layout to facilitate the subsequent integration of temperature detection circuit and bias voltage control circuit.
[0061] In some embodiments, such as Figures 5-7 As shown, Figure 5 A schematic diagram of a silicon carbide CMOS integrated circuit structure with a gate control structure provided in this application embodiment; Figure 6 A schematic diagram of a silicon carbide CMOS integrated circuit structure with a third gate structure provided in an embodiment of this application; Figure 7 The schematic diagram of a silicon carbide CMOS integrated circuit structure provided in the embodiments of this application is a combination of a control gate structure and a third gate structure. The control structure 16 can be a single control gate structure 18, a single third gate structure 20, or a combination of control gate structure 18 and third gate structure 20, and these control structures 16 are discontinuously arranged along the third direction Z.
[0062] This embodiment combines the static depletion fixing method of the above embodiments with the dynamic bias compensation method, achieving device control in high-temperature environments without requiring complex source region structure design. Specifically, on the one hand, the control gate structure 18 is retained to achieve basic, stable, and comprehensive depletion in the channel region; on the other hand, a local third gate structure 20 is added at a critical location in the channel. This third gate structure 20 is only arranged in the important region, rather than covering the entire channel. Through the combination of static fixing and local dynamic compensation, the threshold voltage drift can be adjusted, reducing the problem of insufficient compensation capability under extreme high temperatures when relying solely on static control.
[0063] In terms of the corresponding layout design, the original pattern of the control gate structure 18 is retained in the gate layer, while dot-like or short-line local patterns of the third gate structure 20 are set at key positions such as the channel center, without full-area coverage. In the metal wiring layer, simple independent power supply lines are set for the local third gate structure 20, and are arranged in layers with the lines of the control gate structure 18, the first gate structure 15, and the second gate structure 23, without interference. Compared with the scheme of setting the third gate structure 20 over the entire area in the previous embodiment, the wiring in this embodiment is simpler, the density is significantly reduced, and the process complexity is basically the same as that of the previous embodiment, which can well adapt to the extreme high-temperature working environment of 350°C to 400°C. In some embodiments, the isolation structure 102 includes an insulating material that penetrates the first well region 13 and the second well region 21 and is embedded in the substrate 101.
[0064] This deep trench isolation structure 102, which penetrates the well region and is embedded in the substrate, effectively blocks carrier diffusion paths and parasitic channel conduction paths between different types of transistors, preventing leakage, crosstalk, and latch-up effects between adjacent devices. Simultaneously, under high-temperature operating conditions, this isolation structure 102 can suppress problems such as increased carrier mobility and intensified dopant diffusion caused by temperature rise, ensuring independent and stable operation of each transistor and improving the electrical stability and logic reliability of the entire CMOS integrated circuit under high-temperature conditions. The insulating material can be silicon dioxide.
[0065] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. The method embodiments described above are merely illustrative, and some or all of the steps can be selected to achieve the purpose of this embodiment solution according to actual needs. Those skilled in the art can understand and implement this without creative effort.
[0066] The above description is only one specific embodiment of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application.
Claims
1. A silicon carbide CMOS integrated circuit structure, characterized in that, include: A substrate, first-type transistors and second-type transistors alternately arranged on the surface of the substrate along a first direction, and an isolation structure; The isolation structure is located between the first type of transistor and the second type of transistor; The first type of transistor includes a first well region located on the surface of the substrate, a second source / drain region located on the side of the first well region away from the substrate, a first gate structure and at least two control structures embedded in the side of the first well region away from the substrate, and a first source / drain region located on the side of the first gate structure close to the substrate. The first gate structure and at least two control structures are arranged at intervals along a first direction, and the at least two control structures are respectively disposed on both sides of the first gate structure; the second source / drain region is located between the first gate structure and the control structures. The second type of transistor includes a second well region located on the surface of the substrate, a fourth source / drain region located on the side of the second well region away from the substrate, a second gate structure embedded in the side of the second well region away from the substrate, at least two of the control structures, and a third source / drain region located on the side of the second gate structure close to the substrate. The second gate structure and at least two of the control structures are arranged at intervals along a first direction, and the at least two control structures are respectively disposed on both sides of the second gate structure; the fourth source / drain region is located between the second gate structure and the control structure. Wherein, the substrate, the first well region, the fourth source / drain region, and the third source / drain region are configured as a second conductivity type; the second well region, the second source / drain region, and the first source / drain region are configured as a first conductivity type.
2. The silicon carbide CMOS integrated circuit structure according to claim 1, characterized in that, The control structure is a control gate structure, and the voltage of the control gate structure is the same as the voltage of the first gate structure.
3. The silicon carbide CMOS integrated circuit structure according to claim 2, characterized in that, The first source / drain region is in contact with the first gate structure and the control gate structure on the side away from the substrate, and / or the third source / drain region is in contact with the second gate structure and the control gate structure on the side away from the substrate.
4. The silicon carbide CMOS integrated circuit structure according to claim 3, characterized in that, The width of the first source / drain region and / or the third source / drain region decreases along a second direction in a first direction, the second direction being the direction from the substrate to the first well region.
5. The silicon carbide CMOS integrated circuit structure according to claim 3, characterized in that, The doping concentration of the first source / drain region and / or the third source / drain region increases along a second direction, which is the direction from the substrate to the first well region.
6. The silicon carbide CMOS integrated circuit structure according to claim 1, characterized in that, The control structure is an isolation oxide layer structure.
7. The silicon carbide CMOS integrated circuit structure according to claim 1, characterized in that, The control structure is a third gate structure, and the gate voltage of the third gate structure is a dynamic bias voltage that varies with temperature.
8. The silicon carbide CMOS integrated circuit structure according to claim 1, characterized in that, The control structure is a control gate structure and / or a third gate structure, and the control structure is intermittently arranged along the third direction.
9. The silicon carbide CMOS integrated circuit structure according to claim 8, characterized in that, The third gate structure is a dotted or short-line local layout.
10. The silicon carbide CMOS integrated circuit structure according to claim 1, characterized in that, The isolation structure includes an insulating material that penetrates the first well region and the second well region and is embedded in the substrate.