Array substrate, preparation method thereof and display panel

Abstract

The application provides an array substrate, a preparation method thereof and a display panel. The array substrate comprises a first capacitor. The dielectric coefficient of the first dielectric layer of the first capacitor is greater than or equal to 5.0 and less than or equal to 6.5. The first dielectric layer has a high dielectric coefficient, which improves the capacitance value of the first capacitor, avoids characteristic drift and improves the display uniformity of the display panel. In addition, the first dielectric layer can be thinned, and the capacitance value of the first capacitor can be controlled by adjusting the thickness of the first dielectric layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, specifically to an array substrate and its fabrication method, and a display panel. Background Technology

[0002] With the booming development of emerging fields such as smartphones, wearable devices, automotive electronics, and artificial intelligence, integrated circuits are moving towards diversified applications. However, array substrates still face challenges such as complex fabrication processes and large thicknesses. Summary of the Invention

[0003] To address the aforementioned issues, embodiments of this application provide an array substrate, a method for fabricating the same, and a display panel.

[0004] In a first aspect, embodiments of this application provide an array substrate, comprising: a substrate, a first insulating layer, and a first capacitor; the first insulating layer is located on one side of the substrate; the first capacitor includes a first dielectric layer, the first dielectric layer being located on the first insulating layer; wherein the dielectric constant of the first dielectric layer is greater than or equal to 5.0 and less than or equal to 6.5.

[0005] In conjunction with the first aspect, along the direction perpendicular to the substrate, the thickness of the first dielectric layer is greater than or equal to 1000 Å and less than or equal to 2000 Å.

[0006] In conjunction with the first aspect, the first dielectric layer includes a silicon nitride layer and a silicon oxide layer stacked thereon; preferably, the thickness of the silicon nitride layer is greater than or equal to 500 Å and less than or equal to 1000 Å in a direction perpendicular to the substrate; preferably, the thickness of the silicon oxide layer is greater than or equal to 500 Å and less than or equal to 1000 Å in a direction perpendicular to the substrate.

[0007] In conjunction with the first aspect, the array substrate further includes a first conductive layer, a second conductive layer, a second insulating layer, and a third conductive layer. The first conductive layer is located between the substrate and the first insulating layer. The second conductive layer, the second insulating layer, and the third conductive layer are sequentially disposed on the side of the first insulating layer facing away from the substrate. The array substrate also includes a transistor, which includes a first gate, a first gate insulating layer, an active layer, a second gate insulating layer, and a second gate, sequentially stacked along a direction away from the substrate. The first gate is located on the first conductive layer, the first gate insulating layer is located on the first insulating layer, the active layer is located on the second conductive layer, the second gate insulating layer is located on the second insulating layer, and the second gate is located on the third conductive layer. The carrier concentration of the active layer is less than or equal to 12 cm⁻¹. 2 / Vs.

[0008] In conjunction with the first aspect, the array substrate further includes: a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer is located between the substrate and the first insulating layer. The second and third conductive layers are sequentially located on the side of the first insulating layer away from the substrate. The material of the second conductive layer includes indium gallium zinc oxide, and the third conductive layer includes a titanium nitride layer and a molybdenum layer. The first capacitor further includes a first electrode and a second electrode located on the side of the first dielectric layer away from the substrate. The first electrode is located on the first conductive layer, and the second electrode is located on either the second or third conductive layer. Preferably, along the direction perpendicular to the substrate, the thickness of the titanium nitride layer is greater than or equal to 300 Å and less than or equal to 500 Å. Preferably, along the direction perpendicular to the substrate, the thickness of the molybdenum layer is greater than or equal to 2500 Å and less than or equal to 3500 Å.

[0009] Secondly, embodiments of this application provide a method for fabricating an array substrate, comprising: providing a substrate; fabricating a first conductive material layer on one side of the substrate and patterning the first conductive material layer to form a first conductive layer; sequentially forming a first insulating material layer and a second conductive material layer on the side of the first conductive layer away from the substrate; forming a patterned photoresist layer on the side of the second conductive material layer away from the substrate and patterning the second conductive material layer to form a second conductive layer; etching the first insulating material layer to form a first insulating layer, wherein the photoresist layer is partially etched to expose a portion of the second conductive layer, thereby making the exposed portion of the second conductive layer conductive; and removing the conductive portion of the second conductive layer.

[0010] In conjunction with the second aspect, patterning the second conductive material layer to form the second conductive layer includes: etching the second conductive material layer using a wet etching process to form the second conductive layer and exposing a portion of the first insulating material layer. The orthographic projection of the photoresist layer on the substrate is located within the orthographic projection of the second conductive layer on the substrate. The distance between the orthographic projection of the edge of the second conductive layer on the substrate and the orthographic projection of the edge of the photoresist layer corresponding to the edge of the second conductive layer on the substrate is greater than or equal to 3 micrometers and less than or equal to 5 micrometers.

[0011] In conjunction with the second aspect, removing the conductive portion of the second conductive layer includes: removing the conductive portion of the second conductive layer using a wet etching process; preferably, after removing the conductive portion of the second conductive layer, it further includes: removing the photoresist layer.

[0012] In conjunction with the second aspect, the method for fabricating the array substrate further includes: fabricating a second insulating layer on the side of the second conductive layer away from the substrate; fabricating a third conductive material layer on the side of the second insulating layer away from the substrate, and patterning the third conductive material layer to form the third conductive layer; the array substrate further includes a transistor, the transistor including a first gate, a first gate insulating layer, an active layer, a second gate insulating layer, and a second gate; the first gate is located on the first conductive layer, the first gate insulating layer is located on the first insulating layer, the active layer is located on the second conductive layer; the second gate insulating layer is located on the second insulating layer, and the second gate is located on the third conductive layer.

[0013] Thirdly, embodiments of this application provide a display panel, including any of the array substrates mentioned above or an array substrate formed by any of the methods for preparing the array substrates mentioned above.

[0014] This application provides an array substrate and its fabrication method, as well as a display panel. The array substrate includes a first capacitor, which includes a first dielectric layer located within a first insulating layer. The dielectric constant of the first dielectric layer is greater than or equal to 5.0 and less than or equal to 6.5. The first dielectric layer of the first capacitor in this application has a high dielectric constant, which increases the capacitance value of the first capacitor, prevents characteristic drift, and improves the display uniformity of the display panel. Furthermore, this application allows for thinning of the first dielectric layer; by adjusting the thickness of the first dielectric layer, the capacitance value of the first capacitor can be controlled. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of an array substrate in related technologies.

[0016] Figure 2 This is a schematic diagram of the structure of an array substrate in related technologies.

[0017] Figure 3 This is a schematic diagram of the structure of an array substrate provided in an embodiment of this application.

[0018] Figure 4 This is a schematic diagram of the structure of an array substrate provided in another embodiment of this application.

[0019] Figure 5 This is a schematic diagram of the structure of an array substrate provided in another embodiment of this application.

[0020] Figure 6 This is a schematic flowchart of a method for fabricating an array substrate according to an embodiment of this application.

[0021] Figure 7 This is a schematic flowchart of a method for fabricating an array substrate according to another embodiment of this application.

[0022] Figures 8-19 This is a schematic diagram of the array substrate fabrication process provided in another embodiment of this application.

[0023] Figure 20 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application.

[0024] Explanation of reference numerals in the attached figures 100 Array substrate; 10 Substrate; 20 First conductive layer; 201 First conductive material layer; 30 First insulating layer; 301 First insulating material layer; 40 Second conductive layer; 401 Second conductive material layer; 50 Second insulating layer; 60 Third conductive layer; 601 Third conductive material layer; 70 Photoresist layer; C1 First capacitor; 21 First electrode; 31 First dielectric layer; 311 Silicon nitride layer; 312 Silicon oxide layer; C11 Second electrode; T transistor; 22 First gate; 32 First gate insulating layer; 41 Active layer; 51 Second gate insulating layer; 61 Second gate; 62 Titanium nitride layer; 63 Molybdenum layer; C2 Second capacitor; L1 Sub-1 conductive layer; L2 Sub-1 insulating layer; L3 Sub-2 conductive layer; L4 Sub-2 insulating layer; L5 Sub-3 conductive layer; L6 Sub-3 insulating layer; L7 Sub-4 conductive layer; C21 Third electrode; C22 Second dielectric layer; C23 Fourth electrode; C3 Third capacitor; C31 Fifth electrode; C32 Third dielectric layer; C33 Sixth electrode; 3011 Silicon nitride material layer; 3012 Silicon oxide material layer; 621 Titanium nitride material layer; 631 Molybdenum material layer; 200 Display panel; 300 Display layer. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] In the accompanying drawings, the dimensions of layers and regions may be exaggerated for clarity. It is understood that when a structure is referred to as being "on" or "below" another structure, the structure may be directly on or below the other structure, or there may be intermediate structures. The same reference numerals always indicate the same structure. Structures referred to herein include any of the following: membrane, element, device, component, assembly.

[0027] When a structure is referred to as being “connected” to another structure, it can be directly connected to the other structure or indirectly connected to the other structure by means of one or more intermediate structures placed between them.

[0028] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0029] In this specification, the term "same-layer setup" refers to a structure formed by two (or more) structures through the same patterning process, and their materials may be the same or different.

[0030] In related technologies, the array substrate includes a second capacitor and a transistor. Figure 1 This is a schematic diagram of the structure of an array substrate in related technologies. For example... Figure 1 As shown, along a direction perpendicular to the array substrate 100, the second capacitor C2 is stacked with the transistor T. Exemplarily, the array substrate 100 includes a substrate 10 and, sequentially disposed on one side of the substrate 10, a first conductive layer L1, a first insulating layer L2, a second conductive layer L3, a second insulating layer L4, a third conductive layer L5, a third insulating layer L6, and a fourth conductive layer L7. The second capacitor C2 includes a third electrode C21 and a fourth electrode C23 disposed opposite to each other, and a second dielectric layer C22 located between the third electrode C21 and the fourth electrode C23, wherein the third electrode C21 is located in the first conductive layer L1, the second dielectric layer C22 is located in the first insulating layer L2, and the fourth electrode C23 is located in the second conductive layer L3. Transistor T includes a first gate 22, a first gate insulating layer 32, an active layer 41, a second gate insulating layer 51, and a second gate 61. The first gate 22 is located in sub-second conductive layer L3, the first gate insulating layer 32 is located in sub-second insulating layer L4, the active layer 41 is located in sub-third conductive layer L5, the second gate insulating layer 51 is located in sub-third insulating layer L6, and the second gate 61 is located in sub-fourth conductive layer L7. The second dielectric is made of silicon nitride, which has a high dielectric constant. Therefore, the second capacitor C2 has a high capacitance value. However, the stacked arrangement of the second capacitor C2 and transistor T results in a large thickness of the array substrate 100, which is detrimental to the development of thinner and lighter display panels.

[0031] Figure 2 This is a schematic diagram of another array substrate structure in related technologies. For example... Figure 2As shown, the array substrate 100 includes a third capacitor C3 and a transistor T. Along a direction parallel to the substrate 10, the third capacitor C3 and the transistor T are arranged side-by-side, avoiding thickness issues caused by stacked configurations. Specifically, the array substrate 100 includes a substrate 10 and a first conductive layer 20, a first insulating layer 30, a second conductive layer 40, a second insulating layer 50, and a third conductive layer 60 sequentially disposed on one side of the substrate 10. The third capacitor C3 includes a fifth electrode C31 and a sixth electrode C33 disposed opposite to each other, and a third dielectric layer C32 located between the fifth electrode C31 and the sixth electrode C33. The fifth electrode C31 is located on the first conductive layer 20, the third dielectric layer C32 is located on the second insulating layer 50, and the sixth electrode C33 is located on the third conductive layer 60. Transistor T includes a first gate 22, a first gate insulating layer 32, an active layer 41, a second gate insulating layer 51, and a second gate 61. The first gate 22 is located on the first conductive layer 20, the first gate insulating layer 32 is located on the first insulating layer 30, the active layer 41 is located on the second conductive layer 40, the second gate insulating layer 51 is located on the second insulating layer 50, and the second gate 61 is located on the third conductive layer 60. It is understood that the fifth electrode C31 is disposed on the same layer as the first gate 22, the third dielectric layer C32 is disposed on the same layer as the second gate insulating layer 51, and the sixth electrode C33 is disposed on the same layer as the second gate 61. However, the second insulating layer 50 is made of silicon oxide, which has a low dielectric constant. In transistor T, the thickness of the second insulating layer 50 needs to be increased to prevent the second gate 61 from conducting with the active layer 41. However, the second insulating layer 50 also serves as the third dielectric layer C32 of the third capacitor C3. Since the capacitance value is inversely proportional to the thickness of the dielectric layer, a thicker second insulating layer 50 reduces the capacitance value of the third capacitor C3, thereby reducing the uniformity of the display panel and affecting the display effect. Furthermore, a thinner second insulating layer 50 causes irreversible and unexpected changes in the key electrical parameters of transistor T during positive bias temperature stress (PBTS) testing, resulting in characteristic drift, such as threshold voltage drift, which also affects the display panel's uniformity.

[0032] To balance the insulation of the second gate insulating layer 51 in transistor T with the capacitance of the third capacitor C3, the thickness of the second insulating layer 50 along the direction perpendicular to the substrate 10 is greater than or equal to 1200 Å and less than or equal to 2000 Å.

[0033] To address the aforementioned problems in related technologies, this application provides an array substrate. The array substrate includes: a substrate, a first insulating layer, and a first capacitor; the first insulating layer is located on one side of the substrate; the first capacitor includes a first dielectric layer, which is located within the first insulating layer; wherein the dielectric constant of the first dielectric layer is greater than or equal to 5.0 and less than or equal to 6.5. For example, the dielectric constant of the first dielectric layer can be 5.0, 5.3, 5.6, 5.9, 6.0, 6.3, 6.5, etc.

[0034] In this embodiment, the first dielectric layer of the first capacitor has a high dielectric constant, which increases the capacitance value of the first capacitor, avoids characteristic drift, and improves the display uniformity of the display panel. In addition, this application can also thin the first dielectric layer; by adjusting the thickness of the first dielectric layer, the capacitance value of the first capacitor can be controlled.

[0035] Figure 3 This is a schematic diagram of the structure of an array substrate provided in one embodiment of this application. Figure 3 As shown, the array substrate 100 includes a substrate 10 and a first insulating layer 30, with the first insulating layer 30 located on one side of the substrate 10. The array substrate 100 also includes a first capacitor C1, which includes a first dielectric layer 31 located on the first insulating layer 30. The first dielectric layer 31 includes a silicon nitride layer 311 and a silicon oxide layer 312 stacked together.

[0036] It is worth noting that the dielectric constant of the silicon nitride layer 311 is greater than or equal to 6.0 and less than or equal to 8.0. For example, the dielectric constant of the silicon nitride layer 311 can be 6.0, 6.5, 7.0, 7.5, 8.0, etc. The dielectric constant of the silicon oxide layer 312 is relatively large, greater than or equal to 3.7 and less than or equal to 4.3. For example, the dielectric constant of the silicon oxide layer 312 can be 3.7, 3.8, 3.9, 4.0, 4.1, 4.2, 4.3, etc. It is understood that because the silicon nitride layer 311 has a high dielectric constant, the first dielectric layer 31 can have a high capacitance value with a limited thickness.

[0037] In this embodiment, by configuring the first dielectric layer 31 as a stacked silicon nitride layer 311 and a silicon oxide layer 312 with a high dielectric constant, the overall dielectric constant of the first dielectric layer 31 is increased, thereby improving the capacitance value of the first capacitor C1, preventing characteristic drift, and improving the display uniformity of the display panel. Furthermore, since the first dielectric layer 31 has a high dielectric constant, this embodiment can also thin the first dielectric layer 31. By adjusting the thickness of the first dielectric layer 31, the capacitance value of the first capacitor C1 can be controlled.

[0038] In some embodiments, the thickness of the first dielectric layer 31, along a direction perpendicular to the substrate 10, is greater than or equal to 1000 Å and less than or equal to 2000 Å. Exemplarily, the thickness of the first dielectric layer 31 can be 1000 Å, 1200 Å, 1400 Å, 1600 Å, 1800 Å, 2000 Å, etc. Compared to Figure 2 In the array substrate 100 shown, the thickness of the first dielectric layer 31 of the first capacitor C1 is significantly reduced, thereby reducing the overall thickness of the array substrate 100 and making it more conducive to the thinner and lighter design of the display panel. In addition, since the capacitance value of a capacitor is inversely proportional to the thickness of the dielectric layer, the thinner first dielectric layer 31 can further increase the capacitance value of the first capacitor C1, that is, increase the capacitance of the first capacitor C1, and further improve the uniformity of the display panel.

[0039] Optionally, the thickness of the silicon nitride layer 311 along the direction perpendicular to the substrate 10 is greater than or equal to 500 Å and less than or equal to 1000 Å. For example, the thickness of the silicon nitride layer 311 can be 500 Å, 600 Å, 700 Å, 800 Å, 900 Å, 1000 Å, etc.

[0040] Optionally, the thickness of the silicon oxide layer 312 along the direction perpendicular to the substrate 10 is greater than or equal to 500 Å and less than or equal to 1000 Å. For example, the thickness of the silicon oxide layer 312 can be 500 Å, 600 Å, 700 Å, 800 Å, 900 Å, 1000 Å, etc.

[0041] Figure 4 This is a schematic diagram of the structure of an array substrate 100 provided in another embodiment of this application. For example... Figure 4 As shown, the array substrate 100 includes a substrate 10, a first conductive layer 20, a first insulating layer 30, a second conductive layer 40, a second insulating layer 50, and a third conductive layer 60. The first conductive layer 20 is located between the substrate 10 and the first insulating layer 30. The second conductive layer 40, the second insulating layer 50, and the third conductive layer 60 are sequentially disposed on the side of the first insulating layer 30 facing away from the substrate 10. The first insulating layer 30 includes a silicon nitride layer 311 and a silicon oxide layer 312 stacked together. The second conductive layer 40 is made of indium gallium zinc oxide, and the third conductive layer 60 includes a titanium nitride layer 62 and a molybdenum layer 63.

[0042] In some embodiments, along a direction perpendicular to the substrate 10, the thickness of the titanium nitride layer 62 is greater than or equal to 300 Å and less than or equal to 500 Å, and the thickness of the molybdenum layer 63 is greater than or equal to 2500 Å and less than or equal to 3500 Å. Exemplarily, along a direction perpendicular to the substrate 10, the thickness of the titanium nitride layer 62 can be 300 Å, 350 Å, 400 Å, 450 Å, 500 Å, etc., and the thickness of the molybdenum layer 63 can be 2500 Å, 2700 Å, 2900 Å, 3000 Å, 3100 Å, 3300 Å, 3500 Å, etc.

[0043] The first capacitor C1 includes a first electrode 21 and a second electrode C11 disposed opposite to each other, and a first dielectric layer 31 located between the first electrode 21 and the second electrode C11. The second electrode C11 is located on the side of the first dielectric layer 31 facing away from the substrate 10. The first electrode 21 is located in the first conductive layer 20, and the first dielectric layer 31 is located in the first insulating layer 30. That is, the first dielectric layer 31 includes a silicon nitride layer 311 and a silicon oxide layer 312 stacked together. The second electrode C11 is located in the second conductive layer 40. The array substrate 100 also includes a transistor T, which includes a first gate 22, a first gate insulating layer 32, an active layer 41, a second gate insulating layer 51, and a second gate 61 stacked sequentially along the direction away from the substrate 10. The first gate 22 is located in the first conductive layer 20, and the first gate insulating layer 32 is located in the first insulating layer 30. That is, the first gate insulating layer 32 includes a silicon nitride layer 311 and a silicon oxide layer 312 stacked together. The active layer 41 is located in the second conductive layer 40, the second gate insulating layer 51 is located in the second insulating layer 50, and the second gate 61 is located in the third conductive layer 60. That is, the second gate 61 includes a titanium nitride layer 62 and a molybdenum layer 63.

[0044] Understandably, the first electrode 21 of the first capacitor C1 and the first gate 22 of the transistor T are disposed on the same layer, both located in the first conductive layer 20; the first dielectric layer 31 of the first capacitor C1 and the first gate insulating layer 32 of the transistor T are disposed on the same layer, both located in the first insulating layer 30; the second electrode C11 of the first capacitor C1 and the active layer 41 of the transistor T are disposed on the same layer, both located in the second conductive layer 40.

[0045] In this embodiment, the first capacitor C1 and the transistor T are arranged side-by-side along a direction parallel to the substrate 10, rather than being stacked, effectively reducing the thickness of the entire array substrate 100 and facilitating the thinning of the display panel. Furthermore, since the first dielectric layer 31 includes stacked silicon nitride layers 311 and silicon oxide layers 312, i.e., the first insulating layer 30 includes stacked silicon nitride layers 311 and silicon oxide layers 312, the first insulating layer 30 has a high dielectric constant, giving it strong insulating properties. Therefore, even if the first insulating layer 30 is thin, it can prevent current conduction between the conductive layers on both sides of the first insulating layer 30. In other words, the thinner first gate insulating layer 32 can also prevent the active layer 41 from conducting with the first gate 22, while increasing the current through the transistor T and preventing characteristic drift. Therefore, in this embodiment, the thickness of the first insulating layer 30 can be significantly reduced, improving the current transmission performance of the transistor T and preventing characteristic drift, while also increasing the capacitance of the first capacitor C1 and improving the uniformity of the display panel. In addition, since the first insulating layer 30 has strong insulating properties, this embodiment can also adjust the capacitance value of the first capacitor C1 by adjusting the thickness of the first insulating layer 30, that is, by adjusting the thickness of the first dielectric layer 31.

[0046] It is worth noting that in this embodiment, the carrier concentration of the active layer 41 is equal everywhere and less than or equal to 12 cm⁻¹. 2 / Vs. For example, the carrier concentration of the active layer 41 is 2 cm⁻¹. 2 / Vs、4 cm 2 / Vs、6 cm 2 / Vs、8 cm 2 / Vs、10cm 2 / Vs、12 cm 2 / Vs etc. Understandably, the carrier concentration is uniform everywhere and less than or equal to 12 cm⁻¹. 2 The active layer 41 with a voltage of / Vs exhibits superior electrical stability, thereby improving the uniformity of the display panel. Furthermore, the active layer 41 in this embodiment can reduce transistor T threshold voltage drift caused by uneven carrier concentration distribution, thus improving the display stability and lifespan of the display panel.

[0047] Figure 5 This is a schematic diagram of the structure of an array substrate provided in another embodiment of this application. For example... Figure 5 As shown, the structure of the array substrate 100 is similar to... Figure 4The array substrate 100 shown is similar, except that the second electrode C11 is located on the third conductive layer 60. It is understandable that because the first insulating layer 30 has a large dielectric constant, it possesses strong insulating properties. Therefore, even if the thickness of the first insulating layer 30 is thin, it can prevent current conduction between the conductive layers on both sides of the first insulating layer 30. Thus, this embodiment can significantly reduce the thickness of the first insulating layer 30, effectively reducing the overall thickness of the array substrate 100, which is beneficial for achieving a thinner and lighter display panel. The thinner first insulating layer 30 can, on the one hand, improve the current transmission performance of the transistor T, avoiding characteristic drift, and on the other hand, increase the capacitance of the first capacitor C1, improving the uniformity of the display panel. In addition, in this embodiment, the carrier concentration of the active layer 41 is equal everywhere and less than or equal to 12 cm⁻¹. 2 / Vs further enhances the uniformity of the display panel, as well as the display stability and lifespan of the display panel.

[0048] Figure 6 This is a schematic flowchart illustrating a method for fabricating an array substrate according to an embodiment of this application. Figure 6 As shown, the method for fabricating the array substrate includes: Step S110: Provide a substrate.

[0049] Step S120: Form a first insulating layer on one side of the substrate.

[0050] The first insulating layer 30 includes a first dielectric layer 31.

[0051] The first dielectric layer 31 includes a silicon nitride layer 311 and a silicon oxide layer 312 stacked together.

[0052] In this embodiment, by setting the first dielectric layer 31 as a stacked silicon nitride layer 311 and a silicon oxide layer 312 with a large dielectric constant, the overall dielectric constant of the first dielectric layer 31 is increased, the capacitance value of the first capacitor C1 is increased, and the display uniformity of the display panel is improved.

[0053] In some embodiments, a first insulating layer is formed on the side of the first conductive layer away from the substrate. Specifically, this includes forming a first insulating material layer on the side of the first conductive layer away from the substrate and activating the first insulating material layer. Specifically, this involves heating the first insulating material layer for a preset time to reduce porosity and defects within the first insulating material layer, improve the interfacial characteristics between the first insulating material layer and subsequently deposited films, and enhance the stability of the insulation performance. The preset time is greater than or equal to 15 minutes and less than or equal to 60 minutes, and the heating temperature is greater than or equal to 400 °C and less than or equal to 480 °C. For example, the preset time can be 15 minutes, 20 minutes, 30 minutes, 40 minutes, 50 minutes, 60 minutes, etc.; the heating temperature can be 400 °C, 420 °C, 440 °C, 460 °C, 480 °C, etc., preferably 450 °C.

[0054] In some embodiments, the first capacitor C1 further includes a first electrode 21 and a second electrode C11 located on both sides of the first dielectric layer 31, the first electrode 21 being located on the side of the first dielectric layer 31 closer to the substrate 10, and the second electrode C11 being located on the side of the first dielectric layer 31 away from the substrate 10. Before forming the first insulating layer on one side of the substrate in step S120, the method for fabricating the array substrate further includes: fabricating a first conductive material layer on one side of the substrate and patterning the first conductive material layer to form a first conductive layer. The first conductive layer includes a first electrode plate.

[0055] After forming a first insulating layer on one side of the substrate in step S120, the method further includes: forming a second conductive material layer on the side of the first insulating layer away from the substrate, and patterning the second conductive material layer to form a second conductive layer. Specifically, the second conductive material layer is formed on the side of the first insulating layer away from the substrate using a sputtering deposition process. During the sputtering deposition process, the oxygen partial pressure is greater than or equal to 50% and less than or equal to 70%. For example, the oxygen partial pressure can be 50%, 55%, 60%, 65%, 70%, etc. When the oxygen partial pressure is greater than or equal to 50% and less than or equal to 70%, the second conductive material layer 401 is a semiconductor. Along the direction perpendicular to the substrate 10, the thickness of the second conductive material layer is greater than or equal to 250 Å and less than or equal to 400 Å. For example, the thickness of the second conductive material layer can be 250 Å, 300 Å, 350 Å, 400 Å, etc.

[0056] In some embodiments, the material of the second conductive material layer includes indium tin oxide.

[0057] In some embodiments, a second insulating layer is formed on the side of the second conductive layer away from the substrate using chemical deposition. The material of the second insulating layer includes silicon oxide, and the thickness of the second insulating layer along a direction perpendicular to the substrate is greater than or equal to 1000 Å and less than or equal to 2000 Å. For example, the thickness of the second insulating layer can be 1000 Å, 1200 Å, 1400 Å, 1600 Å, 1800 Å, 2000 Å, etc.

[0058] In some embodiments, a third conductive material layer is prepared on the side of the second insulating layer away from the substrate using a construction deposition method, and the third conductive material layer is patterned to form the third conductive layer. The third conductive material layer includes a titanium nitride layer and a molybdenum layer. Along the direction perpendicular to the substrate, the thickness of the titanium nitride layer is greater than or equal to 300 Å and less than or equal to 500 Å, and the thickness of the molybdenum layer is greater than or equal to 2500 Å and less than or equal to 3500 Å. Exemplarily, along the direction perpendicular to the substrate, the thickness of the titanium nitride layer can be 300 Å, 350 Å, 400 Å, 450 Å, 500 Å, etc., and the thickness of the molybdenum layer can be 2500 Å, 2700 Å, 2900 Å, 3000 Å, 3100 Å, 3300 Å, 3500 Å, etc. The third conductive material layer is patterned using a dry etching process to form the third conductive layer. For example, gases such as chlorine, boron trichloride, or sulfur hexafluoride are used to etch the third conductive material layer.

[0059] The second electrode plate is located in the second conductive layer or the third conductive layer.

[0060] Understandably, in embodiments where the second electrode is located in the second conductive layer, after the third conductive layer is formed, a conductive gas is used to conduct a portion of the second conductive layer. Since the conductive gas has difficulty penetrating the third conductive layer, it can increase the conductivity of the portion of the second conductive layer not covered by the third conductive layer, enabling this conductivity to form the second electrode of the first capacitor. The conductive gas includes boron trichloride.

[0061] It is worth noting that the array substrate also includes transistors. The transistors include a first gate, a first gate insulating layer, an active layer, a second gate insulating layer, and a second gate, which are sequentially stacked along the direction away from the substrate. The first gate is disposed on a first conductive layer, the first gate insulating layer is disposed on a first insulating layer, the active layer is disposed on a second conductive layer, the second gate insulating layer is disposed on a second insulating layer, and the second gate is disposed on a third conductive layer.

[0062] Understandably, in this embodiment, the first gate and the first electrode are disposed in the same layer, therefore the first gate and the first electrode can be fabricated using the same mask; the second electrode is disposed in the same layer as the active layer or the second gate, therefore the second electrode can be fabricated using the same mask as the active layer or the second gate. Compared to Figure 1 The related technologies shown in this embodiment reduce two masking processes, thereby lowering production costs.

[0063] Figure 7 This is a schematic flowchart of a method for fabricating an array substrate according to another embodiment of this application.

[0064] like Figure 7 As shown, the method for fabricating the array substrate includes: Step S210: Provide a substrate.

[0065] Step S220: Prepare a first conductive material layer on one side of the substrate and pattern the first conductive material layer to form a first conductive layer.

[0066] Step S230: A first insulating material layer and a second conductive material layer are sequentially formed on the side of the first conductive layer away from the substrate.

[0067] Step S240: A patterned photoresist layer is formed on the side of the second conductive material layer away from the substrate, and the second conductive material layer is patterned to form the second conductive layer.

[0068] For example, the material of the second conductive layer is indium tin oxide.

[0069] Step S250: Etch the first insulating material layer to form the first insulating layer.

[0070] Specifically, a dry etching process is used to etch the first insulating material layer to form the first insulating layer. For example, the etching gas includes gases such as carbon tetrafluoride and sulfur hexafluoride.

[0071] It is worth noting that the etching gas etches the photoresist layer while simultaneously etching the first insulating material layer. Therefore, the photoresist layer is partially etched, specifically the edge region, exposing a portion of the second conductive layer. In this case, the distance between the orthographic projection of the edge of the second conductive layer onto the substrate and the orthographic projection of the corresponding etched photoresist layer edge onto the substrate is greater than or equal to 3 micrometers and less than or equal to 5 micrometers. The portion of the second conductive layer in contact with the etching gas becomes conductive. For example, the distance between the orthographic projection of the edge of the second conductive layer onto the substrate and the corresponding etched photoresist layer edge onto the substrate can be 3.0 micrometers, 3.5 micrometers, 4.0 micrometers, 4.5 micrometers, 5.0 micrometers, etc.

[0072] Step S260: Remove the conductive portion of the second conductive layer.

[0073] In this embodiment, the second conductive material layer and the first insulating layer are sequentially patterned using the same photoresist layer to form the second conductive layer and the first insulating layer. This reduces the number of photomask uses and masking processes, significantly lowering the fabrication cost and production cycle of the array substrate. However, during the patterning of the second conductive material layer, part of the photoresist layer is etched away, exposing part of the second conductive layer. During the patterning of the first insulating material layer, the etching gas makes the exposed part of the second conductive layer conductive. At this time, the carrier concentration of the exposed part of the second conductive layer is greater than that of the part of the second conductive layer covered by the photoresist layer. The second conductive layer with uneven carrier concentration has poor electrical stability, reducing the uniformity of the display panel. This embodiment effectively solves the problem of uneven carrier concentration in the second conductive layer by removing the conductive part of the second conductive layer, making the carrier concentration of the remaining second conductive layer equal everywhere. This ensures that the second conductive layer has excellent electrical stability, further improving the uniformity, stability, and lifespan of the display panel.

[0074] Figures 8-17 This is a schematic diagram of the array substrate fabrication process provided in another embodiment of this application. Specifically, as shown... Figure 8 and Figure 9 As shown, a first conductive material layer 201 is prepared on one side of the substrate 10, and the first conductive material layer 201 is patterned to form a first conductive layer 20. Figure 10 As shown, a first insulating material layer 301 is prepared on the first conductive layer 20 by chemical vapor deposition. Specifically, the first insulating material layer 301 includes a silicon nitride material layer 3011 and a silicon oxide material layer 3012 sequentially disposed along the direction away from the substrate 10.

[0075] The first insulating material layer 301 is activated by heating for a preset time to reduce porosity and defects within the first insulating material layer 301, improve the interfacial characteristics between the first insulating material layer 301 and the subsequently deposited film, and enhance the stability of the insulation performance. The preset time is greater than or equal to 15 minutes and less than or equal to 60 minutes, and the heating temperature is greater than or equal to 400 ℃ and less than or equal to 480 ℃. For example, the preset time can be 15 minutes, 20 minutes, 30 minutes, 40 minutes, 50 minutes, 60 minutes, etc.; the heating temperature can be 400 ℃, 420 ℃, 440 ℃, 460 ℃, 480 ℃, etc., preferably 450 ℃.

[0076] like Figure 11As shown, a second conductive material layer 401 is prepared on the first insulating material layer 301 using sputtering deposition. The oxygen partial pressure is greater than or equal to 50% and less than or equal to 70%. For example, the oxygen partial pressure can be 50%, 55%, 60%, 65%, 70%, etc. It is understood that when the oxygen partial pressure is greater than or equal to 50% and less than or equal to 70%, the second conductive material layer 401 is a semiconductor. Along the direction perpendicular to the substrate 10, the thickness of the second conductive material layer 401 is greater than or equal to 250 Å and less than or equal to 400 Å. For example, the thickness of the second conductive material layer 401 can be 250 Å, 300 Å, 350 Å, 400 Å, etc.

[0077] like Figure 12 and Figure 13 As shown, a patterned photoresist layer 70 is formed on the second conductive material layer 401. A wet etching process is used to etch the second conductive material layer 401 to form the second conductive layer 40, exposing a portion of the first insulating material layer 301. It is worth noting that the etching time is controlled so that only the exposed portion of the second conductive material layer 401 of the photoresist layer 70 is etched; that is, the orthographic projection of the photoresist layer 70 on the substrate 10 lies within the orthographic projection of the second conductive layer 40 on the substrate 10. Specifically, the distance l1 between the orthographic projection of the edge of the second conductive layer 40 on the substrate 10 and the orthographic projection of the edge of the corresponding photoresist layer 70 on the substrate 10 is greater than or equal to 3 micrometers and less than or equal to 5 micrometers. For example, the distance l1 can be 3.0 micrometers, 3.5 micrometers, 4.0 micrometers, 4.5 micrometers, 5.0 micrometers, etc. It can be understood that this embodiment saves time in etching the second conductive material layer 401, improving production efficiency. Specifically, compared to the fact that the orthographic projection of the second conductive layer 40 formed by etching on the substrate 10 coincides with the orthographic projection of the photoresist layer 70 on the substrate 10, this embodiment can shorten the time by 2 to 4 seconds. For example, this embodiment can shorten the time by 2.0 seconds, 2.5 seconds, 3.0 seconds, 3.5 seconds, 4.0 seconds, etc.

[0078] like Figure 14As shown, gases such as carbon tetrafluoride and sulfur hexafluoride are used to etch the first insulating material layer not covered by the photoresist layer 70 and the second conductive layer 40 to form a first insulating layer 30, wherein the first insulating layer 30 includes a silicon nitride layer 311 and a silicon oxide layer 312. As described above, when etching the first insulating material layer 301, gases such as carbon tetrafluoride and sulfur hexafluoride also etch the edge region of the photoresist layer 70 to expose more of the second conductive layer 40. In addition, the second conductive layer 40 in contact with the gases such as carbon tetrafluoride and sulfur hexafluoride becomes conductive. At this time, the distance l2 between the orthographic projection of the edge of the second conductive layer 40 on the substrate 10 and the orthographic projection of the edge of the etched photoresist layer 70 corresponding to the edge of the second conductive layer 40 on the substrate 10 is greater than or equal to 3 micrometers and less than or equal to 5 micrometers. For example, the distance l2 can be 3.0 micrometers, 3.5 micrometers, 4.0 micrometers, 4.5 micrometers, 5.0 micrometers, etc.

[0079] like Figure 15 As shown, the second conductive layer 40 exposed by the photoresist layer 70 is etched again using a wet etching process, that is, the conductive portion of the second conductive layer 40 is removed.

[0080] like Figure 16 and Figure 17 As shown, the photoresist layer 70 is removed; a second insulating layer 50 is formed on the side of the second conductive layer 40 facing away from the substrate 10 using chemical vapor deposition. For example, the material of the second insulating layer 50 includes silicon oxide, and the thickness of the second insulating layer 50 along a direction perpendicular to the substrate 10 is greater than or equal to 1000 Å and less than or equal to 2000 Å. For example, the thickness of the second insulating layer 50 can be 1000 Å, 1200 Å, 1400 Å, 1600 Å, 1800 Å, 2000 Å, etc.

[0081] like Figure 18 As shown, a third conductive material layer 601 is prepared on the side of the second insulating layer 50 facing away from the substrate 10 using a sputtering deposition process. The third conductive material layer 601 includes a titanium nitride material layer 621 and a molybdenum material layer 631. Along the direction perpendicular to the substrate 10, the thickness of the titanium nitride material layer 621 is greater than or equal to 300 Å and less than or equal to 500 Å, and the thickness of the molybdenum material layer 631 is greater than or equal to 2500 Å and less than or equal to 3500 Å. For example, along the direction perpendicular to the substrate 10, the thickness of the titanium nitride material layer 621 can be 300 Å, 350 Å, 400 Å, 450 Å, 500 Å, etc., and the thickness of the molybdenum material layer 631 can be 2500 Å, 2700 Å, 2900 Å, 3000 Å, 3100 Å, 3300 Å, 3500 Å, etc.

[0082] like Figure 19As shown, a dry etching process is used to pattern the third conductive material layer to form a third conductive layer 60, which includes a titanium nitride layer 62 and a molybdenum layer 63. The third conductive material layer 601 can be etched using gases such as chlorine, boron trichloride, or sulfur hexafluoride.

[0083] It is worth noting that the array substrate 100 also includes a transistor T, which includes a first gate 22, a first gate insulating layer 32, an active layer 41, a second gate insulating layer 51, and a second gate 61; the first gate 22 is located in the first conductive layer 20, the first gate insulating layer 32 is located in the first insulating layer 30, the active layer 41 is located in the second conductive layer 40, the second gate insulating layer 51 is located in the second insulating layer 50, and the second gate 61 is located in the third conductive layer 60.

[0084] In this embodiment, the second conductive material layer and the second conductive layer are patterned sequentially using the same photoresist layer to form the second conductive layer and the first insulating layer. This reduces the number of photomask uses, reduces masking processes, and lowers the fabrication cost and production cycle of the array substrate. By removing the conductive portion of the second conductive layer, the problem of uneven carrier concentration in the second conductive layer can be effectively solved, ensuring that the carrier concentration in the remaining second conductive layer is equal everywhere. This guarantees that the second conductive layer has excellent electrical stability, further improving the uniformity, stability, and lifespan of the display panel.

[0085] Figure 20 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application. Figure 20 As shown, this application embodiment also provides a display panel 200, which includes the array substrate 100 of any of the above embodiments, or the array substrate 100 formed according to the array substrate preparation method of any of the above embodiments.

[0086] In some embodiments, the display panel 200 further includes a display layer 300 located on one side of the array substrate 100.

[0087] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0088] The block diagrams of devices, apparatuses, devices, and systems involved in this application are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0089] It should also be noted that in the apparatus, equipment, and methods of this application, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions of this application.

[0090] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this application. Therefore, this application is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0091] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

[0092] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. An array substrate, characterized in that, include: Substrate; A first insulating layer is located on one side of the substrate; A first capacitor, the first capacitor including a first dielectric layer, the first dielectric layer being located on the first insulating layer; Wherein, the dielectric constant of the first dielectric layer is greater than or equal to 5.0 and less than or equal to 6.

5.

2. The array substrate according to claim 1, characterized in that, Along a direction perpendicular to the substrate, the thickness of the first dielectric layer is greater than or equal to 1000 Å and less than or equal to 2000 Å.

3. The array substrate according to claim 1, characterized in that, The first dielectric layer includes a silicon nitride layer and a silicon oxide layer stacked together; Preferably, the thickness of the silicon nitride layer is greater than or equal to 500 Å and less than or equal to 1000 Å in a direction perpendicular to the substrate; Preferably, the thickness of the silicon oxide layer is greater than or equal to 500 Å and less than or equal to 1000 Å in a direction perpendicular to the substrate.

4. The array substrate according to claim 1, characterized in that, The array substrate further includes a first conductive layer, a second conductive layer, a second insulating layer, and a third conductive layer. The first conductive layer is located between the substrate and the first insulating layer, and the second conductive layer, the second insulating layer, and the third conductive layer are sequentially disposed on the side of the first insulating layer away from the substrate. The array substrate further includes a transistor, the transistor comprising a first gate, a first gate insulating layer, an active layer, a second gate insulating layer and a second gate, which are sequentially stacked along a direction away from the substrate. The first gate is located in the first conductive layer, the first gate insulating layer is located in the first insulating layer, the active layer is located in the second conductive layer, the second gate insulating layer is located in the second insulating layer, and the second gate is located in the third conductive layer. Wherein, the carrier concentration of the active layer is less than or equal to 12 cm⁻¹ 2 / Vs.

5. The array substrate according to claim 1, characterized in that, The array substrate further includes: a first conductive layer, a second conductive layer, and a third conductive layer, wherein the first conductive layer is located between the substrate and the first insulating layer, and the second conductive layer and the third conductive layer are sequentially located on the side of the first insulating layer facing away from the substrate. The second conductive layer is made of indium gallium zinc oxide, and the third conductive layer includes a titanium nitride layer and a molybdenum layer; The first capacitor further includes a first electrode plate and a second electrode plate located on both sides of the first dielectric layer, the first electrode plate being located in the first conductive layer, and the second electrode plate being located in the second conductive layer or the third conductive layer. Preferably, the thickness of the titanium nitride layer along the direction perpendicular to the substrate is greater than or equal to 300 Å and less than or equal to 500 Å; Preferably, the thickness of the molybdenum layer is greater than or equal to 2500 Å and less than or equal to 3500 Å along the direction perpendicular to the substrate.

6. A method for fabricating an array substrate, characterized in that, include: Provide substrate; A first conductive material layer is prepared on one side of the substrate, and the first conductive material layer is patterned to form a first conductive layer; A first insulating material layer and a second conductive material layer are sequentially formed on the side of the first conductive layer that is away from the substrate; A patterned photoresist layer is formed on the side of the second conductive material layer away from the substrate, and the second conductive material layer is patterned to form the second conductive layer; The first insulating material layer is etched to form a first insulating layer. The photoresist layer is partially etched to expose a portion of the second conductive layer, thereby making the exposed portion of the second conductive layer conductive. Remove the conductive portion of the second conductive layer.

7. The method for fabricating an array substrate according to claim 6, characterized in that, The step of patterning the second conductive material layer to form the second conductive layer includes: The second conductive material layer is etched using a wet etching process to form a second conductive layer and expose a portion of the first insulating material layer. The orthographic projection of the photoresist layer on the substrate lies within the orthographic projection of the second conductive layer on the substrate. The distance between the orthographic projection of the edge of the second conductive layer on the substrate and the orthographic projection of the edge of the photoresist layer corresponding to the edge of the second conductive layer on the substrate is greater than or equal to 3 micrometers and less than or equal to 5 micrometers.

8. The method for fabricating an array substrate according to claim 6, characterized in that, The removal of the conductive portion of the second conductive layer includes: The conductive portion of the second conductive layer is removed using a wet etching process; Preferably, after removing the conductive portion of the second conductive layer, the method further includes removing the photoresist layer.

9. The method for fabricating an array substrate according to claim 6, characterized in that, The method for fabricating the array substrate further includes: A second insulating layer is prepared on the side of the second conductive layer that is opposite to the substrate; A third conductive material layer is prepared on the side of the second insulating layer away from the substrate, and the third conductive material layer is patterned to form a third conductive layer; The array substrate further includes transistors, each transistor comprising a first gate, a first gate insulating layer, an active layer, a second gate insulating layer, and a second gate; the first gate is located on the first conductive layer, the first gate insulating layer is located on the first insulating layer, and the active layer is located on the second conductive layer; the second gate insulating layer is located on the second insulating layer, and the second gate is located on the third conductive layer.

10. A display panel, characterized in that, The array substrate includes the array substrate according to any one of claims 1 to 5 or the array substrate prepared by the method according to any one of claims 6 to 9.

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