Integrated circuit comprising integrated standard cell structures

Abstract

An integrated circuit includes a first standard cell, a second standard cell, a fill cell, and a cell separation film. The fill cell is between the first standard cell and the second standard cell and includes a first dummy gate stack and a second dummy gate stack. The cell separation film extends along a boundary of the first standard cell, a boundary of the fill cell, and a boundary of the second standard cell. The fill cell has a pitch dimension. The first dummy gate stack and the second dummy gate stack are spaced apart from each other by the pitch dimension. The first dummy gate stack of the fill cell is disposed at the boundary between the first standard cell and the fill cell. The first dummy gate stack of the fill cell is disposed at the boundary between the second standard cell and the fill cell. The fill cell includes a first fill contact connected to the first dummy gate stack and a second fill contact connected to the second dummy gate stack. The first fill contact and the second fill contact overlap the cell separation film.

Description

[0001] This application is a divisional application of the patent application filed on September 9, 2020, with application number 202010940222.7 and entitled "Integrated Circuit Including Integrated Standard Unit Structure". Technical Field

[0002] The present invention relates to integrated circuits including integrated standard cell structures. Background Technology

[0003] Standard cells can be used to design integrated circuits. Specifically, the layout of an integrated circuit can be generated by arranging standard cells according to the data defining the integrated circuit and by wiring the arranged standard cells. Such standard cells are pre-designed and stored in a cell library.

[0004] As semiconductor manufacturing processes become miniaturized, the size of patterns in standard cells can be reduced, and the size of standard cells can also be reduced. Summary of the Invention

[0005] Embodiments of this invention provide an integrated circuit that can use fill cells to improve the integration density of the layout and enhance the performance and reliability of the designed semiconductor device.

[0006] However, the embodiments of the present invention are not limited to those described herein. The above and other embodiments of the present invention will become more apparent to those skilled in the art upon which the present invention pertains from the following detailed description of the present invention.

[0007] According to an exemplary embodiment of the present invention, an integrated circuit includes: a first active region extending in a first direction; a second active region extending in the first direction and spaced apart from the first active region in a second direction different from the first direction; a first standard cell disposed on the first and second active regions, the first standard cell including a first p-type transistor on the first active region and a first n-type transistor on the second active region; a second standard cell disposed on the first and second active regions, the second standard cell including a second p-type transistor on the first active region and a second n-type transistor on the second active region; and a fill cell disposed between the first and second standard cells and including a first insulating spacer and a second insulating spacer, each of the first and second insulating spacers extending in the second direction. The fill cell has a pitch dimension. The first and second insulating spacers are spaced apart from each other by the pitch dimension in the first direction. The first insulating spacer of the fill cell is disposed at a first boundary between the first standard cell and the fill cell. The second insulating spacer of the fill cell is disposed at a second boundary between the second standard cell and the fill cell. The first insulating barrier and the second insulating barrier separate at least a portion of the first active region and at least a portion of the second active region.

[0008] According to an exemplary embodiment of the present invention, an integrated circuit includes: a first standard cell including a first p-type transistor and a first n-type transistor; a second standard cell including a second p-type transistor and a second n-type transistor and spaced apart from the first standard cell in a first direction; a fill cell disposed between the first standard cell and the second standard cell and including a first insulating spacer and a second insulating spacer; and a third standard cell spaced apart from the first standard cell and the fill cell in a second direction different from the first direction and including a third p-type transistor and a third n-type transistor. The fill cell has a pitch dimension. The first insulating spacer and the second insulating spacer are spaced apart from each other by the pitch dimension in the first direction. The first insulating spacer of the fill cell is disposed at the boundary between the first standard cell and the fill cell. The second insulating spacer of the fill cell is disposed at the boundary between the second standard cell and the fill cell. The first p-type transistor and the second p-type transistor are formed on a first active region. The first n-type transistor and the second n-type transistor are formed on a second active region. The third standard cell includes a third insulating spacer disposed at a first boundary of the third standard cell. The first insulating spacer and the second insulating spacer separate at least a portion of the first active region. The first and second insulating barriers separate at least a portion of the second active region. The third insulating barrier is aligned with the second insulating barrier in a second direction.

[0009] According to an exemplary embodiment of the present invention, an integrated circuit includes: a first standard cell including a first p-type transistor and a first n-type transistor; a second standard cell including a second p-type transistor and a second n-type transistor and spaced apart from the first standard cell in a first direction; a fill cell disposed between the first standard cell and the second standard cell and including a first insulating spacer and a second insulating spacer; and a third standard cell spaced apart from the first standard cell and the fill cell in a second direction different from the first direction and including a third p-type transistor and a third n-type transistor. The fill cell has a pitch dimension. The first insulating spacer and the second insulating spacer are spaced apart from each other by the pitch dimension in the first direction. The first insulating spacer of the fill cell is disposed at the boundary between the first standard cell and the fill cell. The second insulating spacer of the fill cell is disposed at the boundary between the second standard cell and the fill cell. The third standard cell includes a first gate stack and a second gate stack spaced apart from each other by the pitch dimension. The first gate stack is aligned with the first insulating gate of the fill cell in the second direction. The second gate stack is aligned with the second insulating gate of the fill cell in the second direction.

[0010] According to an exemplary embodiment of the present invention, an integrated circuit includes: a first standard cell including a first p-type transistor and a first n-type transistor; a second standard cell including a second p-type transistor and a second n-type transistor and spaced apart from the first standard cell in a first direction; a fill cell including a first dummy gate stack and a second dummy gate stack, the fill cell being disposed between the first standard cell and the second standard cell, wherein each of the first dummy gate stack and the second dummy gate stack extends in a second direction different from the first direction; a power rail extending in the first direction and connected to the first dummy gate stack and the second dummy gate stack; and a cell separator extending along the boundary of the first standard cell, the boundary of the fill cell, and the boundary of the second standard cell in the first direction and overlapping with the power rail. The fill cell has a pitch dimension. The first dummy gate stack and the second dummy gate stack are spaced apart from each other by the pitch dimension in the first direction. The first dummy gate stack of the fill cell is disposed at the boundary between the first standard cell and the fill cell. The second dummy gate stack of the fill cell is disposed at the boundary between the second standard cell and the fill cell. The fill cell includes a first fill contact connected to the first dummy gate stack and a second fill contact connected to the second dummy gate stack. The first and second filling contacts overlap with the separator membrane.

[0011] According to an exemplary embodiment of the present invention, an integrated circuit includes: a first standard cell including a first p-type transistor and a first n-type transistor; a second standard cell including a second p-type transistor and a second n-type transistor and configured to be adjacent to each other in a first direction; a fill cell including a first dummy gate stack and a second dummy gate stack disposed between the first standard cell and the second standard cell, the first dummy gate stack and the second dummy gate stack extending in a second direction different from the first direction; and a power rail extending in the first direction and connected to the first dummy gate stack and the second dummy gate stack. The fill cell has a pitch dimension. The first dummy gate stack and the second dummy gate stack are spaced apart from each other in the first direction by the pitch dimension. The first dummy gate stack of the fill cell is disposed at the boundary between the first standard cell and the fill cell. The second dummy gate stack of the fill cell is disposed at the boundary between the second standard cell and the fill cell. The first standard cell includes a first gate stack extending in the second direction. The second standard cell includes a second gate stack extending in the second direction. The length of each of the first dummy gate stack and the second dummy gate stack is greater than the length of each of the first gate stack and the second gate stack.

[0012] According to an exemplary embodiment of the present invention, an integrated circuit includes: a first standard cell including a first p-type transistor and a first n-type transistor; a second standard cell including a second p-type transistor and a second n-type transistor and spaced apart from the first standard cell in a first direction; a fill cell including a first dummy gate stack and a second dummy gate stack disposed between the first standard cell and the second standard cell, a first fill contact connected to the first dummy gate stack, and a second fill contact connected to the second dummy gate stack, the first dummy gate stack and the second dummy gate stack extending in a second direction different from the first direction; and a power rail extending in the first direction and connected to the first dummy gate stack via the first fill contact and connected to the second dummy gate stack via the second fill contact. The fill cell has a pitch dimension. The first dummy gate stack and the second dummy gate stack are spaced apart from each other by the pitch dimension in the first direction. The first dummy gate stack of the fill cell is disposed at the boundary between the first standard cell and the fill cell. The second dummy gate stack of the fill cell is disposed at the boundary between the second standard cell and the fill cell. The first p-type transistor and the second p-type transistor are formed on a first active region. The first n-type transistor and the second n-type transistor are formed on a second active region. The filling cell also includes a dummy gate dicing pattern on an active region partition film, the active region partition film extending in a first direction and interposed between a first active region and a second active region. A first dummy gate stack includes a first portion and a second portion separated by the dummy gate dicing pattern. A second dummy gate stack includes a first portion and a second portion separated by the dummy gate dicing pattern. A first filling contact includes a first upper filling contact connected to the first portion of the first dummy gate stack and a first lower filling contact connected to the second portion of the first dummy gate stack. A second filling contact includes a second upper dummy contact connected to the first portion of the second dummy gate stack and a second lower filling contact connected to the second portion of the second dummy gate stack. The first upper filling contact, the first lower filling contact, the second upper filling contact, and the second lower filling contact overlap with a cell partition film extending in a first direction along the boundary of the first standard cell, the boundary of the filling cell, and the boundary of the second standard cell.

[0013] Other features and implementations will become apparent from the following detailed description and accompanying drawings. Attached Figure Description

[0014] The above and other aspects and features of the present invention will become more apparent from the exemplary embodiments described in detail with reference to the accompanying drawings, in which:

[0015] Figures 1 to 3 , Figure 4A and Figure 4B , Figure 5A and Figure 5B , Figures 6A to 6C , Figure 7A and Figure 7B , Figure 8 , Figure 9 as well as Figure 10A and Figure 10B It is a diagram used to illustrate an integrated circuit according to some embodiments;

[0016] Figure 11 This is a top view used to illustrate an integrated circuit according to some embodiments;

[0017] Figure 12 This is a top view used to illustrate an integrated circuit according to some embodiments;

[0018] Figure 13 This is a top view used to illustrate an integrated circuit according to some embodiments;

[0019] Figure 14 This is a top view used to illustrate an integrated circuit according to some embodiments;

[0020] Figures 15 to 18 as well as Figure 19A and Figure 19B It is a diagram used to illustrate an integrated circuit according to some embodiments;

[0021] Figures 20 to 24 These are diagrams illustrating integrated circuits according to some implementation methods;

[0022] Figure 25 and Figure 26 These are top views illustrating an integrated circuit according to some embodiments;

[0023] Figure 27 and Figure 28 These are, respectively, top views illustrating an integrated circuit according to some embodiments; and

[0024] Figure 29 and Figure 30 It is a diagram related to a method for designing the layout of an integrated circuit according to some implementations. Detailed Implementation

[0025] In the following description, a substrate ( Figure 2 Integrated circuits in various embodiments on a semiconductor substrate (e.g., a semiconductor substrate). The integrated circuit has a layout including various standard cells. Standard cells are integrated circuit structures pre-designed for repeated use in the design of various integrated circuits. An efficient integrated circuit design layout includes predetermined rules relating to the arrangement of standard cells to enhance the performance of the pre-designed various standard cells and circuits and reduce circuit area.

[0026] An integrated circuit according to some embodiments includes one or more standard cells arranged in an integrated circuit layout according to predetermined rules. Such standard cells are repeatedly used in integrated circuit design. Therefore, standard cells are pre-designed and stored in a standard cell library according to manufacturing techniques. Integrated circuit designers can search for such standard cells and include them in the integrated circuit design, and can arrange them in the integrated circuit layout according to predetermined placement rules.

[0027] Standard cells can include various basic circuit devices, such as inverters, AND, NAND, OR, XOR, and NOR, which are frequently used in digital circuit design for electronic devices such as central processing units (CPUs), graphics processing units (GPUs), and systems-on-a-chip (SoCs). Standard cells can also include other cells that are frequently used in circuit blocks, such as flip-flops and latches.

[0028] A fill cell can be a design block of an integrated circuit inserted between two adjacent standard cells to comply with integrated circuit design and manufacturing rules. Proper design and arrangement of standard cells and fill cells can improve package density and circuit performance.

[0029] Figures 1 to 10B This is a diagram used to illustrate an integrated circuit according to some implementation methods.

[0030] Figure 1 This is a top view of the FEOL (front-end process) of an integrated circuit according to some implementation methods. Figure 2 It is along Figure 1 The cross-sectional view taken from line AA. Figure 3 It is along Figure 1 The cross-sectional view of line BB. Figure 4A and Figure 4B They are along Figure 1 The cross-sectional view taken from line CC. Figure 5A and Figure 5B This is a top view of an integrated circuit according to some implementations, showing up to MOL (intermediate process). Figure 6A and Figure 6B They are along Figure 5A The cross-sectional view taken from line D1-D1. Figure 6C It is along Figure 5B The cross-sectional view taken from line D2-D2. Figure 7A and Figure 7B By cutting in the second direction Y Figure 5A and Figure 5B Various views are visible from the source / drain contacts 170 and 170_1. Figure 8 This is a top view of an integrated circuit according to some implementations, showing up to BEOL (back-end process). Figure 9 It is along Figure 8 The cross-sectional view of lines EE and FF. Figure 10A and Figure 10B It is along Figure 8 Other exemplary cross-sectional views of the lines EE and FF.

[0031] For reference, Figure 4A and Figure 4B In the diagram, XX and YY represent the cutting direction. Figure 8 It can be that the wiring layer is formed in Figure 5A The diagram shown is a top view. Furthermore... Figure 8 Only the vias connecting to the gate contact and the source / drain contact are shown, along with the M1 metal layer on the vias.

[0032] Reference Figures 1 to 10B According to some embodiments, the integrated circuit includes a first standard cell 20, a second standard cell 22, a first insulating filler cell 10, and a cell gate dicing pattern 160.

[0033] exist Figure 1 As shown in Figure 4, the first standard unit 20, the second standard unit 22, and the first insulating filler unit 10 can be formed on the substrate 100.

[0034] The substrate 100 may be a silicon substrate or SOI (silicon-on-insulator). Optionally, the substrate 100 may include, but is not limited to, silicon germanium, SGOI (silicon-on-insulator), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0035] The first active region 112 may be defined in a first direction X. The first active region 112 may be defined by a deep trench DT. The first active region 112 may be a region in which a p-type transistor (e.g., a pFET) is formed. The first active region 112 may include, for example, a well region doped with an n-type impurity.

[0036] The first active region 112 may include a first lower active region 112B, a first upper active region 112U, and a first nanosheet 112NS. The first lower active region 112B may have sidewalls defined by a deep trench DT. The first upper active region 112U may have fins protruding from the first lower active region 112B. The first upper active region 112U may have sidewalls defined by trenches shallower than the deep trench DT. The first nanosheet 112NS may be configured to be spaced apart from the first upper active region 112U. Although two first nanosheets 112NS are shown, this is only for illustrative purposes, and their number is not limited thereto.

[0037] The second active region 114 may be defined in the first direction X. The second active region 114 may be defined in the second direction Y, spaced apart from the first active region 112. The first active region 112 and the second active region 114 may be separated by a deep trench DT. The second active region 114 may be a region in which an n-type transistor (e.g., an nFET) is formed. The second active region 114 may include, for example, a well region doped with p-type impurities.

[0038] exist Figure 1 and Figure 8 In this embodiment, the second active region 114 may include a second lower active region 114B, a second upper active region 114U, and a second nanosheet 114NS. The second lower active region 114B may have sidewalls defined by a deep trench DT. The second upper active region 114U may have fins protruding from the second lower active region 114B. The second upper active region 114U may have sidewalls defined by a trench shallower than the deep trench DT. This trench may be connected to the deep trench DT. The second nanosheet 114NS may be configured to be spaced apart from the second upper active region 114U. Although two second nanosheets 114NS are shown, this is for illustrative purposes only, and their number is not limited thereto.

[0039] Each of the first standard unit 20, the second standard unit 22, and the first insulation filling unit 10 may include a first active region 112 and a second active region 114.

[0040] An active region separation film 105 may be formed on the substrate 100. The active region separation film 105 may be interposed between the first active region 112 and the second active region 114. The active region separation film 105 may extend in a first direction X between the first active region 112 and the second active region 114. The active region separation film 105 may fill the deep trench DT that separates the first active region 112 and the second active region 114.

[0041] A cell separator 106 may be formed on a substrate 100. The cell separator 106 may fill a deep trench DT that separates the first active region 112 and the second active region 114. The cell separator 106 may extend in a first direction X along the boundary of the first standard cell 20, the boundary of the second standard cell 22, and the boundary of the first insulating filler cell 10. Each of the active region separator 105 and the cell separator 106 may include an insulating material.

[0042] The active zone separator 105 and the cell separator 106 may include an insulating material filling the deep trench DT defining the first active zone 112 and the second active zone 114. In the following description, the active zone separator 105 may be an insulating material film disposed between the first active zone 112 and the second active zone 114 included in a single standard cell. For example, the active zone separator 105 will be described as an insulating material film disposed inside the cell. The cell separator 106 may be an insulating material film not disposed inside the cell, but extending along a cell boundary in a first direction X among the cell boundaries. For example, the cell separator 106 will be described as an insulating material film disposed along a cell boundary.

[0043] An integrated circuit according to some embodiments may include a plurality of gate stacks 120 and a plurality of insulating gates 150. The gate stacks 120 and insulating gates 150 may extend in a second direction Y. The gate stacks 120 and insulating gates 150 may be configured to be adjacent to each other in a first direction X. The plurality of insulating gates 150 may also be referred to as a plurality of insulating isolators.

[0044] The gate stacks 120 and insulating gates 150 adjacent in the first direction X are configured to be spaced apart by 1 CPP (contacted poly pitch). As one example, two adjacent gate stacks 120 can be separated by 1 CPP. As another example, adjacent gate stacks 120 and insulating gates 150 can be spaced apart by 1 CPP. As yet another example, two adjacent insulating gates 150 can be spaced apart by 1 CPP.

[0045] For example, suppose there are first gate stacks and second gate stacks that are adjacent to each other. If the distance between the center line of the first gate stack extending in the second direction Y and the center line of the second gate stack extending in the second direction Y is 1 CPP, this means that there are no other gate stacks or insulating gates disposed between the first gate stack and the second gate stack.

[0046] Gate stack 120 and insulating gate 150 may be disposed above the first active region 112 and the second active region 114. Gate stack 120 and insulating gate 150 may extend from the first active region 112 to the second active region 114. Gate stack 120 and insulating gate 150 may intersect with the active region separator film 105. A portion of gate stack 120 and a portion of insulating gate 150 may extend to the top of cell separator film 106. Figure 3 As shown, the bottom surface of the insulating gate 150 is lower than the upper surface of the cell separator 106, and the upper surface of the cell separator 106 is higher than the upper surface of the active region separator 105.

[0047] Gate stack 120 may include gate electrode 122, gate insulating film 124, gate spacer 126, and gate capping film 128. The invention is not limited thereto. In one example embodiment, gate stack 120 may not include gate capping film 128. Gate spacer 126 may define gate trenches in which gate insulating film 124 and gate electrode 122 may be formed. Gate spacer 126 may include, for example, an insulating material. Gate insulating film 124 may be formed along the periphery of first nanosheet 112NS. Although not shown, gate insulating film 124 may be formed along the periphery of second nanosheet (…). Figure 9 The gate insulating film 124 may be formed around the first nanosheet 112NS. The gate insulating film 124 may include at least one of, for example, silicon oxide or a high dielectric constant material. The high dielectric constant material may be, for example, a material having a dielectric constant greater than that of silicon oxide. A gate electrode 122 may be formed on the gate insulating film 124. The gate electrode 122 may surround the first nanosheet 112NS. Although not shown, the gate electrode 122 may surround a second nanosheet (…). Figure 9 The gate electrode 122 may include, for example, at least one of a metal (representing a metal alloy comprising two or more metals), a metal nitride, a metal carbide, a metal silicide, and a semiconductor material. A gate capping film 128 may be disposed on the gate electrode 122. The gate capping film 128 may include, for example, an insulating material.

[0048] An insulating gate 150 can separate at least a portion of the first active region 112 and at least a portion of the second active region 114. The insulating gate 150 can also separate a first upper active region 112U of the first active region 112. Although the insulating gate 150 is shown as separating a portion of the first lower active region 112B in the first active region 112, the implementation is not limited thereto. The insulating gate 150 can completely separate the first lower active region 112B for electrical isolation of adjacent elements. Although not shown, the insulating gate 150 can separate a second upper active region 114U in the second active region 114 and a portion of the second lower active region 114B. Considering the manufacturing process used to form the insulating gate 150, after removing at least a portion of the first active region 112 and at least a portion of the second active region 114, an insulating material is filled in the portions from which the first active region 112 and the second active region 114 are removed. Therefore, an insulating gate 150 can be formed. Therefore, a portion of the sidewall of the insulating gate 150 may contact the first active region 112 and the second active region 114. A portion of the sidewall of the insulating gate 150 may also contact the semiconductor material film included in the first active region 112 and the second active region 114. Unless the context otherwise indicates, the term "contact" as used herein refers to direct connection (i.e., touching).

[0049] An insulating gate 150 may intersect with an active region separator 105. The insulating gate 150 may be disposed on the active region separator 105. A portion of the insulating gate 150 may extend into the active region separator 105. During the process of forming the insulating gate 150, a portion of the active region separator 105 may be removed. Therefore, a portion of the insulating gate 150 may extend into the active region separator 105. Gate spacers 126 may be disposed on the sidewalls of the insulating gate 150. The insulating gate 150 may include, for example, an insulating material. Although the insulating gate 150 is shown as a single film, the implementation is not limited thereto.

[0050] In an integrated circuit according to some embodiments, at least a portion of an insulating gate 150 extending in the second direction Y may be disposed at the boundary between two adjacent standard cells and separate the two adjacent standard cells. The insulating gate 150 may be disposed not only in the boundary of the standard cell but also inside the standard cell. However, in the following, the insulating gate 150 will be described as being disposed at the boundary of the standard cell extending in the second direction Y.

[0051] Semiconductor pattern 130 can be formed between adjacent gate stacks 120 and insulating gates 150. Semiconductor pattern 130 can be formed by removing some of the active regions 112 and 114 to form a recess, and then filling the recess by an epitaxial growth process. Semiconductor pattern 130 can be formed on the first active region 112. Figure 6A and Figure 6B In this transistor, a semiconductor pattern 130 may be formed on a first active region 112 and a second active region 114. At least a portion of the semiconductor pattern 130 may be included in the source / drain region of the transistor. The semiconductor pattern 130 formed on the first active region 112 may be doped with impurities of a different conductivity type than the semiconductor pattern 130 formed on the second active region 114. The semiconductor pattern 130 may also be formed between adjacent insulating gates 150.

[0052] A cell gate dicing pattern 160 may be disposed on the cell separator film 106. The cell gate dicing pattern 160 may extend in a first direction X. The cell gate dicing pattern 160 may extend in the first direction X along the boundary of the first standard cell 20, the boundary of the first insulating filler cell 10, and the boundary of the second standard cell 22. A gate stack 120 and an insulating gate 150 may be disposed between the cell gate dicing patterns 160 spaced apart from each other in a second direction Y. The cell gate dicing pattern 160 may include, for example, an insulating material.

[0053] The cell gate dicing pattern 160 can dice the gate stack 120 or the insulating gate 150 at the boundary of the cell. The cell gate dicing pattern 160 can contact the gate stack 120 and the insulating gate 150. The cell gate dicing pattern 160 can contact the short side of the gate stack 120 extending in the first direction X and the short side of the insulating gate 150 extending in the first direction X. The first standard cell 20, the first insulating fill cell 10 and the second standard cell 22 may also include the cell gate dicing pattern 160 formed along the boundary extending in the first direction X.

[0054] exist Figure 4A In this embodiment, the gate insulating film 124 may not be formed on the sidewall of the cell gate dicing pattern 160. The invention is not limited thereto. In cases such as... Figure 4B In the example embodiment shown, the gate insulating film 124 may extend along the sidewalls of the cell gate dicing pattern 160. This difference can vary depending on at which stage the cell gate dicing pattern 160 is formed. When the cell gate dicing pattern 160 is formed after the gate electrode 122 is formed, as... Figure 4A As shown, the gate insulating film 124 may not be formed on the sidewalls of the cell gate dicing pattern 160. On the other hand, when the cell gate dicing pattern 160 is formed before fabricating the gate electrode 122 (the molding gate stage for forming the gate electrode 122), as... Figure 4B As shown, the gate insulating film 124 can extend along the sidewall of the cell gate dicing pattern 160.

[0055] The first insulating filler unit 10 may be disposed between the first standard unit 20 and the second standard unit 22. The first standard unit 20 and the second standard unit 22 may be arranged to be adjacent to each other in the first direction X, and the first insulating filler unit 10 may be inserted between them. The boundary between the first insulating filler unit 10 and the first standard unit 20 extends in the second direction Y, and the boundary between the first insulating filler unit 10 and the second standard unit 22 also extends in the second direction Y.

[0056] The first insulating filling unit 10 may include two insulating gates 150 that intersect with the first active region 112 and the second active region 114 and are adjacent to each other in the first direction X. Each insulating gate 150 may be located at the boundary of the first insulating filling unit 10 extending in the second direction Y.

[0057] The first insulating filler unit 10 may have a pitch dimension in the first direction X. The pitch dimension may be 1 CPP (contact polysilicon pitch). For example, when the first insulating filler unit 10 has a first filler unit boundary and a second filler unit boundary extending in the second direction Y, the first insulating filler unit 10 may extend the pitch dimension from the first filler unit boundary to the second filler unit boundary in the first direction X.

[0058] For ease of description, the first standard cell 20 may have a width of 5 CPP in the first direction X. The first standard cell 20 may be defined by two insulating gates 150 spaced 5 CPP apart from each other. Four gate stacks 120 may be disposed in the first standard cell 20. For example, four gate stacks 120 may be disposed between the two insulating gates 150 defining the first standard cell 20 in the first direction X. The first standard cell 20 may form a boundary with the first insulating fill cell 10. The first insulating fill cell 10 may form a boundary with the first standard cell 20 in one of the two insulating gates 150 of the first insulating fill cell 10. Adjacent first standard cells 20 and first insulating fill cells 10 may share an insulating gate 150 at a common boundary. The first standard cell 20 may also include an insulating gate 150 spaced 5 CPP apart from said one of the two insulating gates 150 and located at a different boundary from the first insulating fill cell 10. The first standard cell 20 may include one or more (e.g., four) gate stacks 120 disposed between the insulating gates 150 located at the boundary of the first standard cell 20. Figure 1 In this context, the first standard unit 20 can have a width of 5 CPP.

[0059] The second standard cell 22 may form a boundary with the first insulating fill cell 10. The first insulating fill cell 10 may form a boundary with the second standard cell 22 in the other of the two insulating gates 150 of the first insulating fill cell 10. Adjacent second standard cells 22 and first insulating fill cells 10 may share an insulating gate 150 at a common boundary. The second standard cell 22 may also include an insulating gate 150 spaced 5 CPP from the other of the two insulating gates 150 and located at a different boundary from the first insulating fill cell 10. The second standard cell 22 may include one or more (e.g., four) gate stacks 120 disposed between the insulating gates 150 located at the boundary of the second standard cell 22. Figure 1 In this context, the second standard unit 22 can have a width of 5 CPP.

[0060] The first standard cell 20 may further include a first portion of a first active region 112 and a first portion of a second active region 114. The gate stack 120 included in the first standard cell 20 may intersect with the first portion of the first active region 112 and the first portion of the second active region 114. The first standard cell 20 may include an integrated first p-type transistor 132 and a first n-type transistor 134. In an example embodiment, the first p-type transistor 132 and the first n-type transistor 134 may be interconnected to achieve the intended function of the first standard cell 20. The first p-type transistor 132 may be formed at the location where the gate stack 120 intersects with the first portion of the first active region 112, and the first n-type transistor 134 may be formed at the location where the gate stack 120 intersects with the first portion of the second active region 114. For example, each first p-type transistor 132 may include a gate electrode 122, a first nanosheet 112NS as a channel region, and a semiconductor pattern 130 as a source / drain region.

[0061] The second standard unit 22 may further include a second portion of the first active region 112 and a second portion of the second active region 114. The gate stack 120 included in the second standard unit 22 may intersect with the second portion of the first active region 112 and the second portion of the second active region 114. The second standard unit 22 may include an integrated second p-type transistor 136 and a second n-type transistor 138. The second p-type transistor 136 may be formed at the location where the gate stack 120 intersects with the second portion of the first active region 112, and the second n-type transistor 138 may be formed at the location where the gate stack 120 intersects with the second portion of the second active region 114. For example, each second p-type transistor 136 may include a gate electrode 122, a first nanosheet 112NS as a channel region, and a semiconductor pattern 130 as a source / drain region.

[0062] The first p-type transistor 132 and the second p-type transistor 136 are respectively formed on the first part and the second part of the first active region 112, and the first n-type transistor 134 and the second n-type transistor 138 are respectively formed on the first part and the second part of the second active region 114.

[0063] The first insulating filler unit 10, disposed between the first standard unit 20 and the second standard unit 22, includes two insulating gates 150 spaced apart from each other, for example, by 1 CPP. Since each insulating gate 150 separates at least some of the first active regions 112 and the second active regions 114, the first active regions 112 and 114 can each be divided into at least three portions in the first direction X. For example, in addition to the first and second portions of the first active region 112, at least three portions of the first active region 112 may also include a third portion disposed in the first insulating filler unit 10. Similarly, in addition to the first and second portions of the second active region 114, at least three portions of the second active region 114 may also include a third portion disposed in the first insulating filler unit 10. A semiconductor pattern 130 may be disposed between the two insulating gates 150 included in the first insulating filler unit 10. In the first insulating filler unit 10, the semiconductor pattern 130 may be disposed in the first active regions 112 and 114 and between the two insulating gates 150 of the first insulating filler unit 10.

[0064] The first standard cell 20, the second standard cell 22, and the first insulating filler cell 10 may further include a cell gate dicing pattern 160. The cell gate dicing pattern 160 may extend along the boundary of the first standard cell 20 extending in the first direction X, the boundary of the first insulating filler cell 10 extending in the first direction X, and the boundary of the second standard cell 22 extending in the first direction X. The cell gate dicing pattern 160 may contact the gate stack 120 included in the first standard cell 20, the gate stack 120 included in the second standard cell 22, and the insulating gate 150 included in the first insulating filler cell 10. In an example embodiment, the cell gate dicing pattern 160 may include an upper cell gate dicing pattern and a lower cell gate dicing pattern spaced apart from each other in the second direction Y. The upper cell gate dicing pattern may contact a first side of the first standard cell 20, and the lower cell gate dicing pattern may contact a second side of the first standard cell 20 opposite to the first side in the second direction Y. The upper cell gate dicing pattern can contact the first side of the second standard cell 22, and the lower cell gate dicing pattern can contact the second side of the second standard cell 22 opposite to the first side in the second direction Y. The upper cell gate dicing pattern can contact the first side of the first insulating filler cell 10, and the lower cell gate dicing pattern can contact the second side of the first insulating filler cell 10 opposite to the first side in the second direction Y.

[0065] exist Figures 5A to 7B In some embodiments, an integrated circuit may include source / drain contacts 170, 170_1 and 170_2 and a gate contact 175.

[0066] Source / drain contacts 170, 170_1, and 170_2 may be disposed on the first active region 112 and the second active region 114. Source / drain contacts 170, 170_1, and 170_2 may be connected to a semiconductor pattern 130 formed on the first active region 112 and the second active region 114. Source / drain contacts 170, 170_1, and 170_2 may include a normal source / drain contact 170, an extended source / drain contact 170_1, and a filled source / drain contact 170_2. The normal source / drain contact 170 may generally overlap with the first active region 112 or the second active region 114. For example, the normal source / drain contact 170 may refer to a source / drain contact in the first active region 112 or a source / drain contact in the second active region 114. A portion of the extended source / drain contact 170_1 may extend to the top of the cell separator 106 and the cell gate dicing pattern 160. The extended source / drain contact 170_1 may be connected to a power rail, which will be described later. Figure 8 (195_1 and 195_2). The fill source / drain contact 170_2 may be disposed between the insulating gates 150 of the first insulating fill cell 10. The fill source / drain contact 170_2 may not be electrically connected to a wiring layer formed at a level higher than the fill source / drain contact 170_2.

[0067] Gate contact 175 is formed on gate stack 120, but not on insulated gate 150. Gate contact 175 may be connected to gate stack 120. For example, gate contact 175 may be electrically connected to gate electrode 122 of gate stack 120.

[0068] Gate contacts 175 may be disposed on the first active region 112, the second active region 114, or the active region separation film 105. In an integrated circuit according to some embodiments, some gate contacts 175 may be disposed on the first active region 112, and some gate contacts 175 may be disposed on the second active region 114.

[0069] Each of the first standard unit 20 and the second standard unit 22 may include a normal source / drain contact 170, an extended source / drain contact 170_1, and a gate contact 175.

[0070] exist Figure 5A , Figure 6A and Figure 6B In this context, the first insulating filling unit 10 may include a filled source / drain contact 170_2. Figure 5B and Figure 6C In the first insulating filling unit 10, the filling source / drain contact 170_2 is not included.

[0071] exist Figure 6AIn the process, the source / drain contact 170_2 may include a contact barrier film 170a and a contact fill film 170b. The contact fill film 170b may fill the trench defined by the contact barrier film 170a. On the other hand, in Figure 6B In this configuration, the contact barrier film 170a may be formed only between the semiconductor pattern 130 and the contact fill film 170b, and may not be formed between the interlayer insulating film 190 and the contact fill film 170b. The normal source / drain contact 170 and the extended source / drain contact 170_1 may also have the following characteristics: Figure 6A or Figure 6B The shape is shown. In the following figures, the contact barrier film 170a and the contact filler film 170b are shown as a single film without distinction.

[0072] Figure 7A and Figure 7B Exemplary cross-sections of source / drain contacts 170 and 170_1 are shown. Figure 7A and Figure 7B This can be a cross-sectional view taken in the second direction Y. Since the gate contact 175 is disposed in the first active region 112 or the second active region 114, a tight margin between the gate contact 175 and the source / drain contacts 170 and 170_1 should be taken into account. For example, depending on whether the gate contact 175 is located around the source / drain contacts 170 and 170_1, the cross-section of the source / drain contacts 170 and 170_1 can have an L-shape ( Figure 7A ) or may have an inverted T-shape ( Figure 7B If the gate contact 175 is not disposed around the source / drain contacts 170 and 170_1, then the source / drain contacts 170 and 170_1 may have the following characteristics: Figure 6A and Figure 6B The cross-section shown.

[0073] exist Figures 8 to 10B In some embodiments, the integrated circuit may include source / drain paths 180 and 180_1, gate path 185, wiring pattern 195, and power rails 195_1 and 195_2. Each of the first standard unit 20 and the second standard unit 22 may include source / drain paths 180 and 180_1, gate path 185, wiring pattern 195, and power rails 195_1 and 195_2.

[0074] A gate path 185 may be formed on a gate contact 175. The gate path 185 may connect the gate contact 175 and the wiring pattern 195. Source / drain paths 180 and 180_1 may be formed on source / drain contacts 170 and 170_1. Source / drain paths 180 and 180_1 may connect to at least some of the source / drain contacts 170 and 170_1. Source / drain paths 180 and 180_1 may include: a normal path 180, connecting the normal source / drain contact 170 and the wiring pattern 195; and a power rail path 180_1, connecting the extended source / drain contact 170_1 and power rails 195_1 and 195_2. The power rail path 180_1 may overlap with a portion of the extended source / drain contact 170_1, and extend further from the extended source / drain contact 170_1 to the power rails 195_1 and 195_2 in the second direction Y.

[0075] Wiring pattern 195 and power rails 195_1 and 195_2 may extend in a first direction X. Power rails 195_1 and 195_2 may include an upper power rail 195_1 to which a first voltage is supplied and a lower power rail 195_2 to which a second voltage is supplied. The upper power rail 195_1 may supply power to a p-type transistor, and the lower power rail 195_2 may supply power to an n-type transistor.

[0076] The structure connecting the gate contact 175 and the wiring pattern 195, and the structure connecting the source / drain contacts 170 and 170_1 with the wiring pattern 195 and the power rails 195_1 and 195_2, may not have the following characteristics: Figure 9 The structure shown.

[0077] exist Figure 10A In this configuration, intermediate contact 176 can be inserted between source / drain paths 180 and 180_1 and source / drain contacts 170 and 170_1. Intermediate contact 176 can also be inserted between gate path 185 and gate contact 175. Although wiring pattern 195 and gate path 185 are shown as having an integrated structure, the invention is not limited thereto. Wiring pattern 195 and gate path 185 can be separated by a barrier film.

[0078] exist Figure 10B In this configuration, source / drain contacts 170 and 170_1 can be connected to wiring pattern 195 and power rails 195_1 and 195_2 without source / drain paths 180 and 180_1. Gate contact 175 can be connected to wiring pattern 195 without gate path 185.

[0079] Figure 11This is a top view used to illustrate an integrated circuit according to some embodiments. In the following description and drawings, only the gate stack 120, the insulating gate 150, the first active region 112, the second active region 114, and the cell gate dicing pattern 160 will be described. Furthermore, the use of [specific details] will be simplified or omitted. Figures 1 to 10B The description contains repeated content.

[0080] Reference Figure 11 According to some embodiments, the integrated circuit may include a first insulating filler unit 10, a second insulating filler unit 12, a third standard unit 24, a fourth standard unit 26, a fifth standard unit 28, and a sixth standard unit 30.

[0081] The first insulating filler unit 10 and the second insulating filler unit 12 may have a width of 1 CPP in the first direction X. The third standard unit 24, the fourth standard unit 26, and the fifth standard unit 28 may have a width of 3 CPP in the first direction X. The sixth standard unit 30 may have a width of 2 CPP in the first direction X. When the first insulating filler unit 10, the second insulating filler unit 12, the third standard unit 24, the fifth standard unit 28, and the sixth standard unit 30 have a height B in the second direction Y, the fourth standard unit 26 may have a height 2B.

[0082] Each of the first insulating filler unit 10, the second insulating filler unit 12, the third standard unit 24, the fourth standard unit 26, the fifth standard unit 28, and the sixth standard unit 30 may include an insulating gate 150 located on the boundary.

[0083] Each of the first insulating fill unit 10 and the second insulating fill unit 12 includes two insulating gates 150. A third standard unit 24 may be disposed between the first insulating fill unit 10 and the second insulating fill unit 12. The third standard unit 24 may be adjacent to the first insulating fill unit 10 and the second insulating fill unit 12 in a first direction X. The third standard unit 24 may form a first boundary with the first insulating fill unit 10 in one insulating gate 150, and may form a second boundary with the second insulating fill unit 12 in one insulating gate 150, the second boundary being opposite to the first boundary in the first direction X.

[0084] The sixth standard cell 30 may be adjacent to the first insulating filler cell 10 in the second direction Y. The fifth standard cell 28 may be adjacent to the sixth standard cell 30 in the first direction X. The fifth standard cell 28 may be adjacent to the second insulating filler cell 12 in the second direction Y. The fifth standard cell 28 may form a boundary with the sixth standard cell 30. The insulating gate 150 may be located at the boundary between the fifth standard cell 28 and the sixth standard cell 30. For example, the fifth standard cell 28 and the sixth standard cell 30 may share the insulating gate 150 at a common boundary.

[0085] The gate stack 120 included in the sixth standard cell 30 can be aligned in the second direction Y with one of the two insulating gates 150 of the first insulating fill cell 10 that forms a boundary with the third standard cell 24. One of the two gate stacks 120 of the fifth standard cell 28 can be aligned in the second direction Y with one of the two insulating gates 150 of the second insulating fill cell 12 that forms a boundary with the third standard cell 24.

[0086] The cell gate dicing pattern 160 can be disposed between the third standard cell 24 and the fifth standard cell 28, and between the third standard cell 24 and the sixth standard cell 30. The cell gate dicing pattern 160 can contact the insulating gate 150 and / or gate stack 120 included in the first insulating fill cell 10, the second insulating fill cell 12, the third standard cell 24, the fifth standard cell 28, and the sixth standard cell 30. For example, the first insulating fill cell 10 can be formed in the cell gate dicing pattern 160 to form a boundary with the sixth standard cell 30.

[0087] The fourth standard cell 26 may form a boundary with the first insulating filler cell 10 within the insulating gate 150 of the first insulating filler cell 10. Furthermore, the fourth standard cell 26 may form a boundary with the sixth standard cell 30. The insulating gate 150 included in the fourth standard cell 26 may be located at the boundary between the fourth standard cell 26 and the sixth standard cell 30. The insulating gate 150 located at the boundary between the first insulating filler cell 10 and the fourth standard cell 26 may be spaced apart in the second direction Y from the insulating gate 150 located at the boundary between the fourth standard cell 26 and the sixth standard cell 30. The insulating gate 150 located at the boundary between the first insulating filler cell 10 and the fourth standard cell 26 may be aligned in the second direction Y with the insulating gate 150 located at the boundary between the fourth standard cell 26 and the sixth standard cell 30. The insulating gate 150 located at the boundary between the first insulating filler cell 10 and the fourth standard cell 26 may be separated from the insulating gate 150 located at the boundary between the fourth standard cell 26 and the sixth standard cell 30 by a cell gate cutting pattern 160.

[0088] Since the fourth standard unit 26 forms the boundary with the first insulating filler unit 10 and the sixth standard unit 30, the height of the fourth standard unit 26 in the second direction Y can be the sum of the height of the first insulating filler unit 10 in the second direction Y and the height of the sixth standard unit 30 in the second direction Y.

[0089] Furthermore, the sum of the widths of the first insulating filler unit 10, the third standard unit 24, and the second insulating filler unit 12 in the first direction X can be the same as the sum of the widths of the fifth standard unit 28 and the sixth standard unit 30 in the first direction X. For example, the density of the integrated circuit layout can be increased by appropriately using insulating filler units 10 and 12 with a width of 1 CPP.

[0090] The cell gate cutting pattern 160 disposed between the third standard cell 24 and the fifth standard cell 28 and between the third standard cell 24 and the sixth standard cell 30 may not extend into the interior of the fourth standard cell 26.

[0091] The third standard unit 24, the fourth standard unit 26, the fifth standard unit 28, and the sixth standard unit 30 may include p-type transistors and n-type transistors formed on the first active region 112 and the second active region 114, respectively.

[0092] The widths of the third standard unit 24, the fourth standard unit 26, the fifth standard unit 28, and the sixth standard unit 30 described above in the first direction X and the height in the second direction Y are exemplary and therefore not limited thereto. In one example embodiment, standard units and insulating fill units having widths in the first direction X and heights in the second direction Y that differ from those described above are combined to allow the integrated circuit layout to have a square or rectangular shape.

[0093] Figure 12 This is a top view used to illustrate an integrated circuit according to some embodiments. Figure 13 This is a top view used to illustrate an integrated circuit according to some embodiments. Figure 14 This is a top view used to illustrate an integrated circuit according to some embodiments. In the following description and drawings, it will be described only by means of the gate stack 120, the insulating gate 150, the first active region 112, the second active region 114, and the cell gate dicing pattern 160. Furthermore, simplified or omitted usage will be used. Figures 1 to 11 The description repeats the content of the component.

[0094] Reference Figures 12 to 14 According to some embodiments, an integrated circuit may include a first insulating filler unit 10, a third standard unit 24, a seventh standard unit 32, an eighth standard unit 34, and a ninth standard unit 36.

[0095] The third standard unit 24, the seventh standard unit 32, the eighth standard unit 34, and the ninth standard unit 36 ​​may have a width of 3 CPP in the first direction X. The third standard unit 24, the seventh standard unit 32, the eighth standard unit 34, and the ninth standard unit 36 ​​may have an insulated gate 150 located at the boundary. Furthermore, each of the third standard unit 24, the seventh standard unit 32, the eighth standard unit 34, and the ninth standard unit 36 ​​may include two gate stacks 120.

[0096] The first insulating fill cell 10 may form a boundary with the third standard cell 24 and the seventh standard cell 32 that are adjacent to each other in the first direction X. Each of the third standard cell 24 and the seventh standard cell 32 may form a boundary with the first insulating fill cell 10 in the insulating gate 150 included in the first insulating fill cell 10.

[0097] The eighth standard unit 34 can be configured to be adjacent to the first insulating filler unit 10 in the second direction Y. The ninth standard unit 36 ​​can be configured to be adjacent to the first insulating filler unit 10 in the second direction Y. The first insulating filler unit 10 can be disposed between the eighth standard unit 34 and the ninth standard unit 36.

[0098] exist Figure 12 In the first insulating filling unit 10, the insulating gate 150 can be aligned with the gate stack 120 included in the eighth standard unit 34 in the second direction Y. The insulating gate 150 of the first insulating filling unit 10 can be aligned with the gate stack 120 included in the ninth standard unit 36 ​​in the second direction Y.

[0099] exist Figure 13 In this configuration, one of the two insulating gates 150 of the first insulating fill unit 10 located on the boundary with the third standard unit 24 can be aligned in the second direction Y with the gate stack 120 of the eighth standard unit 34. The other of the two insulating gates 150 of the first insulating fill unit 10 located on the boundary with the seventh standard unit 32 can be aligned in the second direction Y with the insulating gate 150 located on the boundary of the eighth standard unit 34. However, the other of the two insulating gates 150 of the first insulating fill unit 10 can be aligned in the second direction Y with the gate stack 120 included in the ninth standard unit 36.

[0100] exist Figure 14In this configuration, one of the two insulating gates 150 of the first insulating fill unit 10 located on the boundary with the third standard unit 24 can be aligned with the gate stack 120 of the eighth standard unit 34 in the second direction Y. The other of the two insulating gates 150 of the first insulating fill unit 10 located on the boundary with the seventh standard unit 32 can be aligned with the insulating gate 150 located on the boundary of the eighth standard unit 34 in the second direction Y. The one of the two insulating gates 150 of the first insulating fill unit 10 located on the boundary with the third standard unit 24 can be aligned with the insulating gate 150 located on the boundary of the ninth standard unit 36 ​​in the second direction Y. The other of the two insulating gates 150 of the first insulating fill unit 10 located on the boundary with the seventh standard unit 32 can be aligned with the gate stack 120 of the ninth standard unit 36 ​​in the second direction Y.

[0101] Each of the third standard unit 24, the seventh standard unit 32, the eighth standard unit 34, and the ninth standard unit 36 ​​may include a p-type transistor and an n-type transistor formed on the first active region 112 and the second active region 114, respectively.

[0102] The widths of the third standard unit 24, the seventh standard unit 32, the eighth standard unit 34 and the ninth standard unit 36 ​​in the first direction X are exemplary and therefore not limited thereto.

[0103] Figures 15 to 19A and Figure 19B This is a diagram used to illustrate an integrated circuit according to some implementation methods.

[0104] Figure 15 This is a top view of an integrated circuit, used to illustrate an integrated circuit according to some implementation methods. Figure 16 It is along Figure 15 The cross-sectional view of line GG. Figure 17 It is along Figure 15 The cross-sectional view taken from line HH. Figure 18 It is along Figure 15 The cross-sectional view taken from line II. Figure 19A and Figure 19B This is an exemplary plan view showing the gate electrode in a floating (or dummy) gate dicing pattern. The repetition of the components described above will be simplified or omitted in the following description.

[0105] Reference Figures 15 to 19A and Figure 19B According to some embodiments, the integrated circuit may include a tenth standard unit 42, an eleventh standard unit 44, and a conductive fill unit 40.

[0106] The integrated circuit may include multiple gate stacks 120 and multiple floating gate stacks 125, 125_1, and 125_2. The gate stacks 120 and the floating gate stacks 125, 125_1, and 125_2 may extend along a second direction Y. The gate stacks 120 and the floating gate stacks 125, 125_1, and 125_2 may be arranged adjacent to each other in a first direction X. The gate stacks 120 and the floating gate stacks 125, 125_1, and 125_2 may be spaced apart from each other by 1 CPP in the first direction. The multiple floating gate stacks 125, 125_1, and 125_2 may also be referred to as multiple dummy gate stacks. As used herein, the term "dummy" is used to refer to a component that has the same or similar structure and shape as other components but does not have a substantial function and exists only as a pattern in the device.

[0107] Each of the floating gate stacks 125, 125_1, and 125_2 may have the same stack structure as the gate stack 120. Each of the floating gate stacks 125, 125_1, and 125_2 may include a gate electrode ( Figure 2 122), gate insulating film ( Figure 2 124), gate spacer ( Figure 2 126) and gate cover film 128.

[0108] Floating gate stacks 125, 125_1, and 125_2 may be disposed above the first active region 112 and the second active region 114. The floating gate stacks 125, 125_1, and 125_2 may extend from the first active region 112 to the second active region 114 and may intersect with the active region separator film 105. Some of the floating gate stacks 125, 125_1, and 125_2 may extend to the top of the cell separator film 106. In integrated circuits according to some embodiments, at least some of the floating gate stacks 125, 125_1, and 125_2 may be disposed at the boundary of a standard cell extending in the second direction Y to electrically separate the standard cell from other adjacent standard cells. The floating gate stacks 125, 125_1, and 125_2 can electrically separate adjacent standard cells rather than physically separating the standard cells. Although the floating gate stacks 125, 125_1, and 125_2 have the same structure as the gate stack 120, they are not used as gates for transistors because they are connected to power rails 195_1 and 195_2. The floating gate stacks 125, 125_1, and 125_2 can be disposed not only at the boundary of a standard cell but also inside the standard cell. However, in the following description, the floating gate stacks 125, 125_1, and 125_2 will be described as being disposed at the boundary of the standard cell extending in the second direction Y.

[0109] A cell gate dicing pattern 160 can be disposed on the cell separator film 106. The cell gate dicing pattern 160 can extend along the boundary of the tenth standard cell 42, the boundary of the conductive fill cell 40, and the boundary of the eleventh standard cell 44 in a first direction X. Gate stacks 120 and floating gate stacks 125, 125_1, and 125_2 can be disposed between the cell gate dicing patterns 160 spaced apart from each other in a second direction Y. The cell gate dicing pattern 160 can cut into the gate stacks 120 or the floating gate stacks 125, 125_1, and 125_2 at the cell boundaries. The cell gate dicing pattern 160 can contact the gate stacks 120 and the floating gate stacks 125, 125_1, and 125_2.

[0110] A floating (or dummy) gate dicing pattern 165 may be disposed on the active partition film 105. The floating gate dicing pattern 165 can divide the floating gate stacks 125, 125_1, and 125_2 into two parts. The two parts of the floating gate stacks 125, 125_1, and 125_2 separated by the floating gate dicing pattern 165 are electrically insulated from each other. The floating gate dicing pattern 165 is in contact with the two parts of the floating gate stacks 125, 125_1, and 125_2. The floating gate dicing pattern 165 may include, for example, an insulating material. During manufacturing, the floating gate dicing pattern 165 may be formed in the same manufacturing process as the cell gate dicing pattern 160, but is not limited thereto.

[0111] The conductive filling unit 40 can be disposed between the tenth standard unit 42 and the eleventh standard unit 44. The tenth standard unit 42 and the eleventh standard unit 44 can be arranged to be adjacent to each other in the first direction X, with the conductive filling unit 40 inserted between them. The boundary between the conductive filling unit 40 and the tenth standard unit 42 extends in the second direction Y, and the boundary between the conductive filling unit 40 and the eleventh standard unit 44 also extends in the second direction Y.

[0112] The conductive fill cell 40 may include a first floating gate stack 125_1 and a second floating gate stack 125_2 that intersect with the first active region 112 and the second active region 114 and are adjacent to each other in the first direction X. The first floating gate stack 125_1 and the second floating gate stack 125_2 may be located at opposite boundaries of the conductive fill cell 40 extending in the second direction Y. The conductive fill cell 40 may have a pitch dimension in the first direction X.

[0113] The conductive filling unit 40 may further include a floating gate dicing pattern 165 disposed on the active partition film 105. The first floating gate stack 125_1 includes a first upper floating gate stack 125_1U and a first lower floating gate stack 125_1L separated by the floating gate dicing pattern 165. The second floating gate stack 125_2 includes a second upper floating gate stack 125_2U and a second lower floating gate stack 125_2L separated by the floating gate dicing pattern 165.

[0114] The conductive filler unit 40 may further include first floating (or fill) contacts 201 and 202 and second floating (or fill) contacts 203 and 204. The first fill contacts 201 and 202 connect the first floating gate stack 125_1 to power rails 195_1 and 195_2. The second fill contacts 203 and 204 connect the second floating gate stack 125_2 to power rails 195_1 and 195_2. The first fill contacts 201 and 202 include a first upper fill contact 201 and a first lower fill contact 202. The second fill contacts 203 and 204 include a second upper fill contact 203 and a second lower fill contact 204. The first upper fill contact 201 connects the first upper floating gate stack 125_1U to the upper power rail 195_1. The first lower fill contact 202 connects the first lower floating gate stack 125_1L to the lower power rail 195_2. The second upper fill contact 203 connects the second upper floating gate stack 125_2U to the upper power rail 195_1. The second lower fill contact 204 connects the second lower floating gate stack 125_2L to the lower power rail 195_2.

[0115] In an integrated circuit according to some embodiments, the gate insulating film 124 included in each of the first floating gate stack 125_1 and the second floating gate stack 125_2 does not extend along the sidewall of the floating gate dicing pattern 165.

[0116] The first fill contacts 201 and 202 and the second fill contacts 203 and 204 can be disposed at the locations where the first floating gate stack 125_1 and the second floating gate stack 125_2 overlap with the cell separator film 106. The first fill contacts 201 and 202 and the second fill contacts 203 and 204 are not disposed inside the cell, but can be located at the cell boundary. Therefore, the wiring for connecting the power rails 195_1 and 195_2 to the floating gate stacks 125_1 and 125_2 can be simplified. For example, in some embodiments of the integrated circuit according to the present invention, the connection between the power rails 195_1 and 195_2 and the floating gate stacks 125_1 and 125_2 does not cross the source / drain contacts (170 and 170_1 in FIG. 5).

[0117] In an integrated circuit according to some embodiments, the first filled contacts 201 and 202 and the second filled contacts 203 and 204 may include contact portions 201_1, 202_1, 203_1 and 204_1 and through portions 201_2, 202_2, 203_2 and 204_2. Contact portions 201_1, 202_1, 203_1 and 204_1 may be similar to... Figure 5A or Figure 5B The gate contact 175. The pass portions 201_2, 202_2, 203_2, and 204_2 can be similar to... Figure 8 Gate path 185.

[0118] The tenth standard cell 42 may form a boundary with the conductive fill cell 40. The conductive fill cell 40 may form a boundary with the tenth standard cell 42 at the first floating gate stack 125_1. The tenth standard cell 42 may include a third floating gate stack 125 located at a different boundary from the conductive fill cell 40. The floating gate stacks 125 and 125_1 may be located at the boundary of the tenth standard cell 42. The tenth standard cell 42 may include one or more (e.g., two) gate stacks 120 disposed between the floating gate stacks 125 and 125_1 located at the boundary of the tenth standard cell 42.

[0119] The eleventh standard cell 44 may form a boundary with the conductive fill cell 40. The conductive fill cell 40 may form a boundary with the eleventh standard cell 44 at the second floating gate stack 125_2. The eleventh standard cell 44 may include a third floating gate stack 125 located at a different boundary from the conductive fill cell 40. The floating gate stacks 125 and 125_2 may be located at the boundary of the eleventh standard cell 44. The eleventh standard cell 44 may include one or more (e.g., two) gate stacks 120 disposed between the floating gate stacks 125 and 125_2 located at the boundary of the eleventh standard cell 44.

[0120] The third floating gate stack 125, located at the boundary between the tenth standard cell 42 and the eleventh standard cell 44, can be divided into two parts by a floating gate cut pattern 165. The third floating gate stack 125 can also be connected to power rails 195_1 and 195_2 by fill contacts similar to fill contacts 201 and 203 and 202 and 204.

[0121] The tenth standard unit 42 and the eleventh standard unit 44 may further include a first active region 112 and a second active region 114. The tenth standard unit 42 and the eleventh standard unit 44 may include a p-type transistor and an n-type transistor respectively formed on the first active region 112 and the second active region 114.

[0122] The tenth standard cell 42, the eleventh standard cell 44, and the conductive fill cell 40 may further include a cell gate dicing pattern 160. The cell gate dicing pattern 160 may extend along the boundary of the tenth standard cell 42 extending in the first direction X, the boundary of the conductive fill cell 40 extending in the first direction X, and the boundary of the eleventh standard cell 44 extending in the first direction X. The cell gate dicing pattern 160 may contact the gate stack 120 included in the tenth standard cell 42, the gate stack 120 included in the eleventh standard cell 44, and the first and second floating gate stacks 125_1 and 125_2.

[0123] In an integrated circuit according to some embodiments, the cell gate dicing pattern 160 may have an "I"-shaped linear shape.

[0124] exist Figure 19A In the plan view, the gate electrode 122 of the first upper floating gate stack 125_1U can be spaced apart from the gate electrode 122 of the first lower floating gate stack 125_1L, with a floating gate diced pattern 165 between them. The boundary between the gate electrode 122 of the first upper floating gate stack 125_1U and the floating gate diced pattern 165 can have a concave shape in the second direction Y. The boundary between the gate electrode 122 of the first lower floating gate stack 125_1L and the floating gate diced pattern 165 can have a concave shape in the direction opposite to the second direction Y. The same configuration can also be applied to the gate electrode 122 of the second upper floating gate stack 125_2U and the gate electrode 122 of the second lower floating gate stack 125_2L.

[0125] exist Figure 19B In the plan view, the gate electrode 122 of the first upper floating gate stack 125_1U can be spaced apart from the gate electrode 122 of the first lower floating gate stack 125_1L, with a floating gate diced pattern 165 between them. The boundary between the gate electrode 122 of the first upper floating gate stack 125_1U and the floating gate diced pattern 165 can have a flat shape. The boundary between the gate electrode 122 of the first lower floating gate stack 125_1L and the floating gate diced pattern 165 can also have a flat shape. The same configuration can also be applied to the gate electrode 122 of the second upper floating gate stack 125_2U and the gate electrode 122 of the second lower floating gate stack 125_2L.

[0126] Figures 20 to 24 These are diagrams illustrating integrated circuits according to some embodiments. For ease of explanation, the description and use will be discussed. Figures 15 to 19A and Figure 19B The differences in the content are explained below. For reference only. Figure 20 It is along Figure 15 The cross-sectional view taken from line HH. Figure 21 and Figure 22 This is a diagram used to illustrate the relationship between the first upper fill contact 201 and the second upper fill contact 203. Figure 23 and Figure 24 This is a diagram showing another structure of the first filling contacts 201 and 202.

[0127] Reference Figure 20 In an integrated circuit according to some embodiments, a gate insulating film 124 included in a first floating gate stack 125_1 may extend along the sidewall of a floating gate dicing pattern 165.

[0128] The gate insulating film 124 included in the second floating gate stack 125_2 can extend along the sidewalls of the floating gate dicing pattern, similar to Figure 20 As shown.

[0129] Reference Figure 21 In an integrated circuit according to some embodiments, the via portion 201_2 of the first overfilled contact 201 and the via portion 203_2 of the second overfilled contact 203 may be a single conductive pattern connected to each other.

[0130] Similarly, the passage portion 202_2 of the first underfill contact 202 and the passage portion 204_2 of the second underfill contact 204 can also be a single conductive pattern connected to each other.

[0131] Reference Figure 22 In an integrated circuit according to some embodiments, the contact portion 201_1 of the first overfilled contact and the contact portion 203_1 of the second overfilled contact may be a single conductive pattern connected to each other.

[0132] Similarly, the contact portion 202_1 of the first lower fill contact and the contact portion 204_1 of the second lower fill contact can also be a single conductive pattern connected to each other.

[0133] Reference Figure 23 In an integrated circuit according to some embodiments, the first upper fill contact 201 and the first lower fill contact 202 may also include connecting contact portions 201_3 and 202_3, respectively.

[0134] The connecting contact parts 201_3 and 202_3 can be similar to Figure 10A The intermediate contact 176. The second upper fill contact 203 and the second lower fill contact 204 may further include connecting contact portions.

[0135] Reference Figure 24In some embodiments of the integrated circuit, power rails 195_1 and 195_2 may be connected to contact portions 201_1 and 202_1, without as shown in the reference. Figure 23 The aforementioned pathway portions 201_2 and 202_2. Similarly, power rails 195_1 and 195_2 can be connected to contact portions 203_1 and 204_1, without pathway portions 203_2 and 204_2.

[0136] Figure 25 and Figure 26 These are top views illustrating integrated circuits according to some embodiments. For ease of explanation, the description and use will be... Figures 15 to 19B The differences in the content of the explanation.

[0137] Reference Figure 25 and Figure 26 In an integrated circuit according to some embodiments, the floating gate stacks 125, 125_1 and 125_2 may extend further beyond one end of the gate stack 120 in the second direction Y.

[0138] The floating gate stacks 125, 125_1 and 125_2 have a length in the second direction Y that is greater than the length of the gate stack 120.

[0139] exist Figure 25 In this configuration, the cell gate dicing pattern 160 may include a portion protruding toward the gate stack 120. The first sidewall of the cell gate dicing pattern 160 extending along the first direction X may be irregular.

[0140] However, the second sidewall of the cell gate cutting pattern 160, which is opposite to the first sidewall, can be flat and without irregularities.

[0141] exist Figure 26 In this process, the cell gate cutting pattern 160 may have a shape in which dumbbell shapes are repeated.

[0142] Figure 27 and Figure 28 These are top views illustrating integrated circuits according to some embodiments. For ease of explanation, the description and use will be... Figures 15 to 19B The differences in the content of the explanation.

[0143] Reference Figure 27 and Figure 28 According to some embodiments, the integrated circuit may also include a twelfth standard unit 46.

[0144] The twelfth standard cell 46 may be adjacent to the conductive fill cell 40 in the second direction Y. The twelfth standard cell 46 may include a third floating gate stack 125 and a gate stack 120.

[0145] The first bottom fill contact 202 can be connected to the gate stack 120 included in the twelfth standard cell 46. The second bottom fill contact 204 can be connected to the gate stack 120 included in the twelfth standard cell 46.

[0146] exist Figure 27 In this context, the gate stack 120, included in the twelfth standard cell 46, can contact the cell gate cut pattern 160.

[0147] exist Figure 28 In this configuration, the gate stack 120 included in the twelfth standard cell 46 does not contact the cell gate dicing pattern 160. The gate stack 120 included in the twelfth standard cell 46 may contact the first floating gate stack 125_1 and the second floating gate stack 125_2.

[0148] Figure 29 and Figure 30 It is a diagram related to methods for designing integrated circuit layouts according to some implementations.

[0149] Reference Figure 29 The first unit CELL1 and the second unit CELL2 are set apart from each other by 1 CPP in the first direction X.

[0150] Each of the first cell CELL1 and the second cell CELL2 includes a normal gate NG and a dummy gate DG spaced apart from each other in the first direction X. Each of the first cell CELL1 and the second cell CELL2 may include a first free active region ACT1 and a second free active region ACT2 spaced apart from each other in the second direction Y.

[0151] Each of the first cell CELL1 and the second cell CELL2 may include a gate removal mask GRM for removing the dummy gate DG. The gate removal mask GRM included in the first cell CELL1 is spaced 1 CPP apart from the gate removal mask GRM included in the second cell CELL2.

[0152] The first free active region ACT1, contained in each of the first cell CELL1 and the second cell CELL2, is not connected to each other. The second free active region ACT2, contained in each of the first cell CELL1 and the second cell CELL2, is not connected to each other.

[0153] Reference Figure 30 The first free active region ACT1 of the first cell CELL1 and the first free active region ACT1 of the second cell CELL2 can be connected to each other according to the design. The second free active region ACT2 of the first cell CELL1 and the second free active region ACT2 of the second cell CELL2 can be connected to each other according to the design.

[0154] Furthermore, the active region removal mask (ARM) can be used instead of the gate removal mask (GRM). Therefore, the separate SDB (single diffused interrupt) masks can be transformed into a single DDB (double diffused interrupt) mask.

[0155] In closing, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the inventive concept. Therefore, the preferred embodiments disclosed herein are used in a general and descriptive sense only and not for limiting purposes.

[0156] This application claims priority to Korean Patent Application No. 10-2019-0111302, filed on September 9, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An integrated circuit, comprising: The first standard unit includes a first p-type transistor and a first n-type transistor; The second standard cell includes a second p-type transistor and a second n-type transistor, and is spaced apart from the first standard cell in a first direction; A filling cell includes a first dummy gate stack and a second dummy gate stack, the filling cell being disposed between the first standard cell and the second standard cell, wherein each of the first dummy gate stack and the second dummy gate stack extends in a second direction different from the first direction; A power rail extends in the first direction and connects to the first dummy gate stack and the second dummy gate stack; as well as The cell separator extends in the first direction along the boundary of the first standard cell, the boundary of the filling cell, and the boundary of the second standard cell, and overlaps with the power rail. in: The filling unit has a pitch dimension. The first dummy gate stack and the second dummy gate stack are spaced apart from each other by the dimension of one pitch in the first direction. The first dummy gate stack of the filling cell is disposed at the boundary between the first standard cell and the filling cell. The second dummy gate stack of the filling cell is disposed at the boundary between the second standard cell and the filling cell. The filling unit includes a first filling contact connected to the first dummy gate stack and a second filling contact connected to the second dummy gate stack, and The first filling contact and the second filling contact overlap with the unit separator membrane.

2. The integrated circuit according to claim 1, in, The first dummy gate stack and the second dummy gate stack overlap with the cell separator film.

3. The integrated circuit according to claim 1, in, The first p-type transistor and the second p-type transistor are formed on a first active region extending in the first direction. Wherein, the first n-type transistor and the second n-type transistor are formed on a second active region extending in the first direction, and The first active region and the second active region are spaced apart from each other in the second direction.

4. The integrated circuit according to claim 3, further comprising: An active region separation membrane extends in the first direction and is inserted between the first active region and the second active region. in: The filling unit further includes a dummy gate dicing pattern on the active region separation film. The first dummy gate stack includes a first portion and a second portion separated by the dummy gate dicing pattern. The second dummy gate stack includes a first portion and a second portion separated by the dummy gate dicing pattern. The power rails include an upper power rail and a lower power rail spaced apart from each other in the second direction. The upper power rail is connected to the first portion of the first dummy gate stack and the first portion of the second dummy gate stack, and The lower power rail is connected to the second portion of the first dummy gate stack and the second portion of the second dummy gate stack.

5. The integrated circuit according to claim 4, in, The boundary between the first portion of the first dummy gate stack and the dummy gate dicing pattern, the boundary between the second portion of the first dummy gate stack and the dummy gate dicing pattern, the boundary between the first portion of the second dummy gate stack and the dummy gate dicing pattern, and the boundary between the second portion of the second dummy gate stack and the dummy gate dicing pattern have a concave shape in the plan view.

6. The integrated circuit according to claim 4, in, The boundary between the first portion of the first dummy gate stack and the dummy gate dicing pattern, the boundary between the second portion of the first dummy gate stack and the dummy gate dicing pattern, the boundary between the first portion of the second dummy gate stack and the dummy gate dicing pattern, and the boundary between the second portion of the second dummy gate stack and the dummy gate dicing pattern have a flat shape in the plan view.

7. The integrated circuit according to claim 4, in, The first portion of the first dummy gate stack, the second portion of the first dummy gate stack, the first portion of the second dummy gate stack, and the second portion of the second dummy gate stack are in contact with the sidewall of the dummy gate dicing pattern.

8. The integrated circuit according to claim 1, further comprising: The cell gate dicing pattern extends in the first direction on the cell separator film. The first standard cell includes a first gate stack extending in the second direction. The second standard cell includes a second gate stack extending in the second direction, and The first gate stack, the second gate stack, the first dummy gate stack, and the second dummy gate stack are in contact with the cell gate dicing pattern.

9. The integrated circuit according to claim 8, in, The cell gate dicing pattern has a linear shape, and Wherein, the longitudinal direction of the cell gate cutting pattern is parallel to the first direction.

10. The integrated circuit according to claim 8, in, The cell gate dicing pattern includes a first sidewall portion protruding toward the first gate stack and the second gate stack, and The first sidewall portion is in contact with the first gate stack and the second gate stack.

11. The integrated circuit according to claim 8, in, The cell gate dicing pattern further includes a second sidewall portion protruding away from the first gate stack and the second gate stack.

12. An integrated circuit, comprising: The first standard unit includes a first p-type transistor and a first n-type transistor; The second standard cell includes a second p-type transistor and a second n-type transistor, and is configured to be adjacent to the first standard cell in a first direction; The filling cell includes a first dummy gate stack and a second dummy gate stack disposed between the first standard cell and the second standard cell, wherein the first dummy gate stack and the second dummy gate stack extend in a second direction different from the first direction; as well as A power rail extends in the first direction and connects to the first dummy gate stack and the second dummy gate stack. in: The filling unit has a pitch dimension. The first dummy gate stack and the second dummy gate stack are spaced apart from each other by the dimension of one pitch in the first direction. The first dummy gate stack of the filling cell is disposed at the boundary between the first standard cell and the filling cell. The second dummy gate stack of the filling cell is disposed at the boundary between the second standard cell and the filling cell. The first standard cell includes a first gate stack extending in the second direction. The second standard cell includes a second gate stack extending in the second direction, and The length of each of the first dummy gate stack and the second dummy gate stack is greater than the length of each of the first gate stack and the second gate stack.

13. The integrated circuit of claim 12, further comprising: The cell separator membrane extends in the first direction along the boundary of the first standard cell, the boundary of the filling cell, and the boundary of the second standard cell. The filling unit includes a first filling contact connected to the first dummy gate stack and a second filling contact connected to the second dummy gate stack. The first filling contact and the second filling contact overlap with the unit separator membrane.

14. The integrated circuit of claim 12, further comprising: The cell gate dicing pattern extends in the first direction along the boundary of the first standard cell, the boundary of the filling cell, and the boundary of the second standard cell. The first gate stack, the second gate stack, the first dummy gate stack, and the second dummy gate stack are in contact with the cell gate dicing pattern.

15. The integrated circuit according to claim 14, in, The sidewalls of the cell gate dicing pattern include a first protruding portion protruding toward the first standard cell and a second protruding portion protruding toward the second standard cell, and Wherein, the first gate stack is in contact with the first protrusion, and The second gate stack is in contact with the second protrusion.

16. An integrated circuit, comprising: The first standard unit includes a first p-type transistor and a first n-type transistor; The second standard cell includes a second p-type transistor and a second n-type transistor, and is spaced apart from the first standard cell in a first direction; The filling cell includes a first dummy gate stack and a second dummy gate stack disposed between the first standard cell and the second standard cell, a first filling contact connected to the first dummy gate stack, and a second filling contact connected to the second dummy gate stack, wherein the first dummy gate stack and the second dummy gate stack extend in a second direction different from the first direction; as well as A power rail extends in the first direction and is connected to the first dummy gate stack via the first fill contact and to the second dummy gate stack via the second fill contact. in: The filling unit has a pitch dimension. The first dummy gate stack and the second dummy gate stack are spaced apart from each other by the dimension of one pitch in the first direction. The first dummy gate stack of the filling cell is disposed at the boundary between the first standard cell and the filling cell. The second dummy gate stack of the filling cell is disposed at the boundary between the second standard cell and the filling cell. The first p-type transistor and the second p-type transistor are formed on the first active region. The first n-type transistor and the second n-type transistor are formed on the second active region. The filling unit further includes a dummy gate dicing pattern on an active region separation film, the active region separation film extending in the first direction through the space between the first active region and the second active region. The first dummy gate stack includes a first portion and a second portion separated by the dummy gate dicing pattern. The second dummy gate stack includes a first portion and a second portion separated by the dummy gate dicing pattern. The first fill contact includes a first upper fill contact connected to the first portion of the first dummy gate stack and a first lower fill contact connected to the second portion of the first dummy gate stack. The second fill contact includes a second upper fill contact connected to the first portion of the second dummy gate stack and a second lower fill contact connected to the second portion of the second dummy gate stack. The first upper fill contact, the first lower fill contact, the second upper fill contact, and the second lower fill contact overlap with a cell separator membrane extending in the first direction along the boundary of the first standard cell, the boundary of the fill cell, and the boundary of the second standard cell.

17. The integrated circuit according to claim 16, in, The first upper fill contact includes a first upper contact portion and a first upper passage portion on the first upper contact portion, and The second upper fill contact includes a second upper contact portion and a second upper passage portion on the second upper contact portion.

18. The integrated circuit according to claim 17, in, The first upper contact portion comes into contact with the second upper contact portion.

19. The integrated circuit according to claim 17, in, The first upper passage portion is in contact with the second upper passage portion.

20. The integrated circuit according to claim 16, in, The power rails include an upper power rail and a lower power rail spaced apart from each other in the second direction. The upper power rail is connected to the first upper filler contact and the second upper filler contact, and The lower power rail is connected to the first lower filler contact and the second lower filler contact.

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