Double-sided velvet tunneling oxide passivated back contact solar cell and method of making same

Abstract

The disclosure discloses a double-sided-textured tunneling oxide passivated back contact solar cell and a preparation method thereof. The double-sided-textured tunneling oxide passivated back contact solar cell comprises a silicon wafer with a textured front surface and a textured back surface. The back surface of the silicon wafer has a P region, an N region and an isolation region. The front surface of the silicon wafer is sequentially provided with a passivation layer and an anti-reflection layer. The double-sided-textured tunneling oxide passivated back contact solar cell is adapted to a TBC structure without a front electrode through the front surface and the back surface. The double-sided-textured tunneling oxide passivated back contact solar cell can realize synchronous improvement of light absorption enhancement and carrier collection, and is beneficial to the improvement of the power of a photovoltaic module.

Description

Technical Field

[0001] This disclosure relates to the field of solar cell technology, and more specifically, to a double-textured tunneling oxide passivated back contact solar cell and a method for its fabrication. Background Technology

[0002] With the continuous advancement of photovoltaic technology, the conversion efficiency and manufacturing cost of solar cells have become key concerns in the industry. Tunneling oxide passivated back contact (TBC) solar cells, as a novel structure, reduce light obstruction due to their grid-free front design, thereby improving the utilization of incident light. Furthermore, the back tunneling passivation structure of TBC cells is highly compatible with the process route of tunneling oxide passivation (TOPCon) solar cells, allowing TBC cells to leverage the mature TOPCon process during manufacturing, thus reducing production costs and technological barriers.

[0003] TBC (Transient Carbon Base) cells avoid light reflection and absorption losses caused by the front-side grid lines of traditional solar cells by placing both positive and negative electrodes on the back side. Furthermore, the tunneling oxide layer and passivated contact structure on the back side effectively reduce carrier recombination, improving the open-circuit voltage and fill factor. These advantages enable TBC cells to exhibit high conversion efficiency potential in laboratory environments. However, TBC cells face the problem of low solar energy utilization efficiency in practical applications, especially after being fabricated into modules, where their power generation is significantly lower than theoretically expected. This bottleneck severely restricts the large-scale production and commercialization of TBC cells.

[0004] In view of this, this disclosure is hereby made. Summary of the Invention

[0005] The purpose of this disclosure is to provide a double-sided textured tunneling oxide passivated back contact solar cell and a method for its fabrication, which is beneficial to improving the power generation of the modules made therefrom.

[0006] This disclosure is implemented as follows: In a first aspect, this disclosure provides a double-textured tunneling oxide passivated back contact solar cell, comprising a silicon wafer with textured surfaces on both the front and back sides. The back side of the silicon wafer has a P-region, an N-region, and an isolation region, and the front side of the silicon wafer is provided with a passivation layer and an anti-reflection layer stacked sequentially.

[0007] In an optional embodiment, the passivation layer is an aluminum oxide layer.

[0008] In an optional embodiment, the antireflection layer is a silicon nitride layer or a silicon oxynitride layer.

[0009] In an optional embodiment, the P region includes a tunneling layer, a boron-doped polysilicon layer, a passivation layer, and an antireflection layer sequentially stacked on a silicon wafer, and a positive electrode is disposed on the antireflection layer of the P region.

[0010] In an optional embodiment, the N-region includes a tunneling layer, a phosphorus-doped polycrystalline silicon layer, a passivation layer, and an antireflection layer sequentially stacked on a silicon wafer, and a negative electrode is disposed on the antireflection layer of the N-region.

[0011] In an optional embodiment, the isolation region includes a passivation layer and an antireflection layer sequentially stacked on the silicon wafer.

[0012] In an optional embodiment, the thickness of the tunneling layer is 1.5 - 3 nm; In an optional embodiment, the tunneling layer is made of silicon oxide.

[0013] In an optional embodiment, the thickness of the boron-doped polycrystalline silicon layer is 100-200 nm; In an optional embodiment, the thickness of the phosphorus-doped polycrystalline silicon layer is 100-200 nm.

[0014] In an optional implementation, the thickness of the N-region silicon wafer is 2-4 μm greater than the thickness of the isolation region silicon wafer.

[0015] Secondly, this disclosure provides a method for fabricating a double-textured tunneling oxide passivated back contact solar cell according to any one of the foregoing embodiments, comprising: Step 1: Texturing the back of the n-type silicon wafer; Step 2: Sequentially form a tunneling layer and an amorphous silicon layer on the back side of the n-type silicon wafer; Step 3: Anneal and boron diffusion are performed sequentially on the n-type silicon wafer that forms the tunneling layer and amorphous silicon layer to form a boron-doped polycrystalline silicon layer; Step 4: Laser removal of the borosilicate glass layer at the corresponding positions in the N-region and the isolation region; Step 5: Wet etching removes all layers on the N-region and isolation region and texturing the corresponding n-type silicon wafer; Step 6: Sequentially form a tunneling layer and an amorphous silicon layer on the back side of the n-type silicon wafer; Step 7: Anneal and phosphorus diffusion are performed sequentially on the n-type silicon wafer that forms the tunneling layer and amorphous silicon layer to form a phosphorus-doped polycrystalline silicon layer; Step 8: Laser removal of the phosphosilicate glass layer in the P-region and the isolation region; Step 9: Wet etching of all layers on the front and side surfaces of the n-type silicon wafer; Step 10: Wet etching removes all layers on the boron-doped polysilicon layer in the P-region, all layers on the phosphorus-doped polysilicon layer in the N-region, and all layers on the silicon wafer in the isolation region. Texturing is then performed on the isolation region and the front side of the n-type silicon wafer. Step 11: Passivation layer and antireflection layer are sequentially prepared on the front and back sides of the silicon wafer, and then electrodes are printed on the back side of the silicon wafer.

[0016] Thirdly, this disclosure provides a method for preparing a double-sided textured tunneling oxide passivated back contact solar cell according to the foregoing embodiments, wherein the annealing step has a heating rate of 1-5°C / min, a temperature of 600-700°C, and a time of 10-20 min. In an optional implementation, the amorphous silicon layer is formed using plasma-enhanced chemical vapor deposition.

[0017] This disclosure has the following beneficial effects: The double-textured tunneling oxide passivated back contact solar cell disclosed herein has a front and back textured surface adapted to a TBC structure without a front electrode, which can achieve simultaneous improvement in light absorption enhancement and carrier collection, thus contributing to the increase in photovoltaic module power. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this disclosure and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of the double-sided textured tunneling oxide passivated back contact solar cell in this disclosure; Figure 2 A schematic diagram of a single-sided textured silicon wafer; Figure 3 This is a schematic diagram of the structure of a silicon wafer after the deposition of an amorphous silicon layer; Figure 4 This is a schematic diagram of the structure of a silicon wafer after boron diffusion; Figure 5 A schematic diagram of the silicon wafer structure after removing the back portion of the BSG; Figure 6 A schematic diagram of the silicon wafer after cleaning and texturing the N-region and isolation region; Figure 7 This is a schematic diagram of the structure after the amorphous silicon layer is deposited again; Figure 8 A schematic diagram of the silicon wafer structure after removing the PSG portion on the back side; Figure 9 This is a schematic diagram of the structure of the isolation area and the front-side textured silicon wafer. Figure 10 This is a schematic diagram of the silicon wafer structure after the nitride antireflection layer.

[0020] Illustration: 1-Tunneling layer; 2-Amorphous silicon layer; 3-Boron-doped polycrystalline silicon layer; 4-Borosilicate glass; 5-Phosphorus-doped polycrystalline silicon; 6-Phosphosilicate glass; 7-Passivation layer; 8-Antireflective layer; 9-Electrode. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the embodiments of this disclosure will be clearly and completely described below. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments whose manufacturers are not specified are all conventional products that can be purchased commercially.

[0022] While traditional TBC cells offer advantages such as no grid lines on the front and low optical loss, their structural design typically only texturizes the front side to enhance light absorption, while the back side remains a polished flat surface. This single-sided texturized configuration makes it difficult to effectively capture and utilize incident light from the back side, resulting in high reflectivity and a short optical path, significantly limiting the generation of photocurrent on the back side and leading to a low overall bifaciality. In practical applications, especially in scenarios with abundant ground-reflected light (such as snow, light-colored roofs, and sandy soil) or at moderate installation heights, the low bifaciality directly weakens the cell's response to environmental reflected irradiance, causing the power generation potential per unit area to be insufficiently released, thus affecting system-level energy output efficiency.

[0023] To overcome the above problems, this disclosure provides a double-sided textured tunneling oxide passivated back contact solar cell, such as... Figure 1 As shown, a silicon wafer 100 with a textured surface on both the front and back sides is included. The back side of the silicon wafer 100 has a P-region, an N-region, and an isolation region. The front side of the silicon wafer 100 is provided with a passivation layer 7 and an anti-reflection layer 8 stacked in sequence.

[0024] This disclosure describes a bifacial textured tunneling oxide passivated back-contact solar cell. By simultaneously constructing a textured structure on both the front and back sides of an n-type silicon substrate, as well as in the isolation region, the cell achieves highly efficient capture and utilization of incident light from both vertical and horizontal directions. This structure not only expands the photon absorption path but also enhances the internal scattering and reabsorption mechanisms of long-wavelength light, thereby systematically increasing the back-side photogenerated carrier yield. Consequently, the cell exhibits more balanced and stable bifacial power generation response characteristics at the module level, significantly enhancing its adaptability to diverse installation environments and its overall lifecycle power generation benefits, which is beneficial for improving the power output of photovoltaic modules.

[0025] It should be noted that the front and back textured surfaces in this disclosure can be made with different structures as needed, such as pyramid height (1μm~2μm) and slope angle (40°~60°).

[0026] In an optional embodiment, the passivation layer 7 is an aluminum oxide layer, and the thickness of the passivation layer 7 can be 3nm to 5nm. When combined with the double-sided textured structure, it can form a uniform coverage on the micro-undulating surface, ensuring the consistency of passivation quality throughout the entire area.

[0027] In an optional embodiment, the antireflection layer 8 is a silicon nitride layer or a silicon oxynitride layer, and the thickness of the antireflection layer 8 can be 70 nm to 120 nm. Both types of materials have good antireflection properties and passivation assistance, and have a wide adjustable refractive index range, which is convenient for matching the wide spectral response requirements of double-sided textured surfaces.

[0028] In an optional embodiment, the P region includes a tunneling layer 1, a boron-doped polysilicon layer 3, a passivation layer 7, and an antireflection layer 8 sequentially stacked on the silicon wafer 100, and a positive electrode 9 is disposed on the antireflection layer 8 of the P region.

[0029] In an optional embodiment, the N region includes a tunneling layer 1, a phosphorus-doped polycrystalline silicon layer 5, a passivation layer 7, and an antireflection layer 8 sequentially stacked on the silicon wafer 100, and a negative electrode 9 is disposed on the antireflection layer 8 of the N region.

[0030] In an optional embodiment, the isolation region includes a passivation layer 7 and an antireflection layer 8 sequentially stacked on the silicon wafer 100.

[0031] For the structure of the P-region, N-region, and isolation region, in this disclosure, the tunneling layer 1 in the P-region and N-region ensures selective carrier transport, the doped polysilicon layer provides a low-resistance conductive path, the passivation layer 7 suppresses interface recombination, and the anti-reflection layer 8 uniformly manages incident light loss. Both positive and negative electrodes 9 are located on the outermost anti-reflection layer 8, which not only shortens the lateral carrier transport distance and reduces series resistance, but also prevents the electrode paste from eroding and contaminating the underlying functional film, improving contact stability. The isolation region abandons the conductive layer, retaining only the passivation layer 7 and the anti-reflection layer 8. This thoroughly passivates the exposed silicon surface, eliminates leakage paths, and eliminates reflection losses caused by structural abrupt changes through optical continuity design, resulting in consistent optical response characteristics across the entire surface. The three layers work together: the P / N regions focus on efficient carrier extraction and output, the isolation region focuses on high-reliability insulation and optical integration, and the overall structure is highly adaptable to double-sided textured substrates, balancing photoelectric conversion efficiency, bi-sided response uniformity, and feasibility without increasing process complexity.

[0032] In an optional embodiment, the thickness of the tunneling layer is 1.5–3 nm, for example 1.5 nm, 1.67 nm, 1.83 nm, 2.0 nm, 2.17 nm, 2.33 nm, 2.5 nm, 2.67 nm, 2.83 nm, or 3 nm. The thickness of 1.5–3 nm ensures quantum tunneling efficiency while effectively blocking metal ion diffusion and hot carrier injection, thus balancing conductivity and blocking properties.

[0033] In an optional embodiment, the tunneling layer is made of silicon oxide. The tunneling layer 1 is made of silicon oxide, which has excellent interface compatibility and chemical stability with the silicon substrate, and provides a low defect density template for the subsequent growth of polycrystalline silicon layers.

[0034] In an optional embodiment, the thickness of the boron-doped polycrystalline silicon layer 3 is 100-200 nm, for example 100 nm, 111 nm, 122 nm, 133 nm, 144 nm, 156 nm, 167 nm, 178 nm, 189 nm, or 200 nm. In an optional embodiment, the thickness of the phosphorus-doped polycrystalline silicon 5-layer is 100-200 nm, for example 100 nm, 111 nm, 122 nm, 133 nm, 144 nm, 156 nm, 167 nm, 178 nm, 189 nm, or 200 nm.

[0035] The five layers of boron-doped and phosphorus-doped polycrystalline silicon are all controlled within the range of 100-200nm, which satisfies the carrier concentration and sheet resistance requirements for lateral conductivity, while avoiding problems such as internal stress accumulation, light absorption loss and uneven crystallization caused by excessive thickness.

[0036] In an optional embodiment, the thickness of the N-region silicon wafer 100 is 2-4 μm greater than the thickness of the isolation region silicon wafer 100, for example, 2.0 μm, 2.2 μm, 2.4 μm, 2.6 μm, 2.8 μm, 3.0 μm, 3.2 μm, 3.4 μm, 3.6 μm, 3.8 μm, or 4.0 μm. The slightly thicker N-region is beneficial for light absorption and carrier collection, while the thinner isolation region reduces optical loss and material consumption. The combination of the two is beneficial for enhancing bifacial power generation performance.

[0037] This disclosure discloses a method for fabricating a double-textured tunneling oxidation passivation back contact solar cell. An initial texturing surface is selectively formed on the back side using an alkaline texturing solution containing surfactants and corrosion inhibitors, such as a dilute sodium hydroxide system. Subsequently, a P-type tunneling passivation stack (SiO₂) is sequentially completed. xThe process involves depositing and boron-doped i-poly-Si, followed by localized removal of the BSG layer using laser ablation. A second etching process is then performed using a strongly alkaline etchant. Next, an N-type tunneling passivation stack is constructed and phosphorus doping is completed. Again, combining laser ablation and selective etching, the front and isolation areas are simultaneously textured. The entire process utilizes chemical cleaning and wet tank etching as core techniques, ultimately forming a double-textured tunneling oxide passivated back contact solar cell. Specifically: This disclosure also provides a method for fabricating a double-textured tunneling oxide passivated back contact solar cell as described in any of the foregoing embodiments, comprising: Step 1: Texturing the back side of the n-type silicon wafer 100; Step 2: Form a tunneling layer 1 and an amorphous silicon layer 2 sequentially on the back side of the n-type silicon wafer 100; Step 3: Annealing and boron diffusion are performed sequentially on the n-type silicon wafer 100 that forms the tunneling layer 1 and the amorphous silicon layer 2 to form the boron-doped polycrystalline silicon layer 3; Step 4: Laser removal of the four layers of borosilicate glass at corresponding positions in the N-region and the isolation region; Step 5: Wet etching removes all layers on the N-region and isolation region and texturing the n-type silicon wafer 100 at the corresponding location; Step 6: Form a tunneling layer 1 and an amorphous silicon layer 2 sequentially on the back side of the n-type silicon wafer 100; Step 7: Anneal and phosphorus diffusion are performed sequentially on the n-type silicon wafer 100 that forms the tunneling layer 1 and the amorphous silicon layer 2 to form a phosphorus-doped polycrystalline silicon layer 5. Step 8: Laser removal of 6 layers of phosphosilicate glass in the P-region and isolation region; Step 9: Wet etching of all layers on the front and side surfaces of the n-type silicon wafer 100; Step 10: Wet etching removes all layers on the boron-doped polysilicon layer 3 in the P-region, all layers on the phosphorus-doped polysilicon layer 5 in the N-region, and all layers on the silicon wafer 100 in the isolation region, and texturing is performed on the isolation region and the front side of the n-type silicon wafer 100. Step 11: Passivation layer 7 and antireflection layer 8 are sequentially prepared on the front and back sides of silicon wafer 100, and then electrode 9 is printed on the back side of silicon wafer 100.

[0038] In an optional embodiment, the heating rate of the annealing step is 1-5 °C / min, for example 1 °C / min, 1.4 °C / min, 1.9 °C / min, 2.3 °C / min, 2.8 °C / min, 3.2 °C / min, 3.7 °C / min, 4.1 °C / min, 4.6 °C / min, or 5 °C / min; the temperature is 600-700 °C, for example 600 °C, 611 °C, 622 °C, 633 °C, 644 °C, 656 °C, 667 °C, 678 °C, 689 °C, or 700 °C; and the time is 10-20 min, for example 10 min, 11 min, 12 min, 13 min, 14 min, 15 min, 16 min, 17 min, 18 min, 19 min, or 20 min.

[0039] In an optional embodiment, the amorphous silicon layer 2 is formed using plasma-enhanced chemical vapor deposition (PECVD).

[0040] In bifacial textured TBC cell structures, the microstructure characteristics of the textured silicon substrate (such as peaks, trenches, and high-curvature surfaces) significantly increase the complexity of the physical contact between the doped polycrystalline silicon layer and its interface. Traditional high-temperature one-step crystallization processes tend to lead to preferential nucleation of the amorphous silicon layer 2 at the textured protrusions, uneven coverage of the recessed areas, and induce localized stress concentration and increased interfacial dangling bond density, thereby degrading the passivation effect. To address this issue, this disclosure first uniformly deposits the intrinsic amorphous silicon layer 2 at a lower temperature using PECVD to ensure complete coverage of the textured surface; then, it is transferred to an LPCVD device, employing a gradient slow heating method to complete the phase transition from amorphous silicon to polycrystalline silicon. This slow heating process provides silicon atoms with sufficient time for surface migration and bond reconstruction, effectively mitigating the lattice strain caused by the geometric deformation of the textured surface and promoting SiO2 transformation. x The poly-Si interface exhibits atomically ordered matching. The doped polycrystalline silicon / textured silicon interface obtained by this two-step process demonstrates a high-quality passivation level comparable to that of conventional polished substrate interfaces in terms of recombination characteristics, band alignment, and charge transport continuity. This fundamentally overcomes the technical barrier that makes it difficult to achieve compatibility between textured structures and high-performance selective carrier contact.

[0041] It should be noted that the slow-heating annealing, in conjunction with the thickness of the doped polycrystalline silicon, can achieve continuous, dense, and appropriately grained polycrystalline silicon coverage on the double-sided textured morphology, ensuring efficient transport of charge carriers and low recombination loss at the undulating interface. This enables the TBC cell to maintain a high open-circuit voltage and fill factor while obtaining robust double-sided current output capability, significantly improving the conversion efficiency between structural innovation and performance implementation.

[0042] The features and performance of this disclosure will be further described in detail below with reference to embodiments.

[0043] Example 1 This embodiment provides a method for fabricating a double-sided textured tunneling oxide passivated back contact solar cell, specifically including the following steps: Step 1: Using texturing additives (Changzhou Shichuang Energy Co., Ltd.) and a 1% sodium hydroxide solution, the back surface of the n-type silicon wafer 100 is textured. The pyramid height of the textured surface is 1.5μm, and the bevel angle is 50°. The structure of silicon wafer 100 is as follows: Figure 2 As shown; Step 2: Using PECVD technology at 450℃, a 2nm thick SiO layer is sequentially formed on the back side of an n-type silicon wafer 100. x The structure of silicon wafer 100 is as follows: tunneling layer 1 and a 150 nm thick amorphous silicon layer 2 (i-Poly). Figure 3 As shown; Step 3: Transfer to the LPCVD equipment, heat to 650°C at a heating rate of 3°C / min, and hold at that temperature for 15 minutes to react the i-Poly and SiO2 formed in "Step 2". x Crystallization is then performed, followed by the introduction of boron trichloride (BCl3) and oxygen to complete boron diffusion, forming a boron-doped polycrystalline silicon layer 3 with a boron doping concentration of 2.5 × 10⁻⁶. 19 cm -3 The structure of a silicon wafer 100 is as follows: Figure 4 As shown; Step 4: Using laser delamination technology, based on the silicon wafer 100 fabricated in Step 3, the borosilicate glass 4 (BSG) at the corresponding positions of the N-region and the isolation region is removed. The structure of silicon wafer 100 is as follows: Figure 5 As shown; Step 5: Using a wet-tank process, all layers on the N-region and isolation region are removed using a strongly alkaline solution and additives, and the corresponding n-type silicon wafer 100 is texturized. The pyramid height of the texturized surface is 1.5 μm, and the slope angle is 50°. The structure of silicon wafer 100 is as follows: Figure 6 As shown; Step Six: Using PECVD technology, a 2 nm thick SiO layer is sequentially formed on the back side of the n-type silicon wafer 100. x The structure of silicon wafer 100 is as follows: tunneling layer 1 and a 150 nm thick amorphous silicon layer 2. Figure 7 As shown; Step 7: Transfer to the LPCVD equipment, heat to 650°C at a heating rate of 3°C / min, and hold at that temperature for 15 minutes to react the i-Poly and SiO2 formed in "Step 6". xCrystallization was then performed, followed by the introduction of phosphorus oxychloride (POCl3) and oxygen to complete phosphorus diffusion, forming a 5-layer phosphorus-doped polycrystalline silicon substrate with a phosphorus doping concentration of 2.5 × 10⁻⁶. 20 cm -3 ; Step 8: Using laser film-forming technology, the phosphorosilicate glass 6 with the P-region and isolation region removed from the back of the battery fabricated in Step 7, resulting in a silicon wafer 100 structure as shown below. Figure 8 As shown; Step Nine: Using a wet chain process, with the aid of additives (Changzhou Shichuang Energy Co., Ltd.), strong acids, and strong alkalis, all layers on the front and sides of the solar cell are removed, resulting in a 100mm silicon wafer structure. Figure 9 As shown; Step 10: Wet etching removes all layers on the boron-doped polysilicon layer 3 in the P-region, all layers on the phosphorus-doped polysilicon layer 5 in the N-region, and all layers on the silicon wafer 100 in the isolation region. The isolation region and the front side of the n-type silicon wafer 100 are texturized with a pyramid height of 1.5 μm and a slope angle of 50°. Step 11: Deposit a 3.5nm thick aluminum oxide passivation layer 7 on both sides of the cell using the ALD process, followed by a 950nm thick nitride antireflection layer 8 on both sides of the cell using the PECVD process. The silicon wafer 100 structure is as follows: Figure 10 As shown, electrodes 9 are then printed on the back side of the silicon wafer 100 to complete the process. Figure 1 The double-sided textured TBC cell shown is fabricated.

[0044] Example 2 The only difference between this embodiment and Embodiment 1 is that steps two and six are different: Step 2: Using PECVD technology at 600℃, a 2 nm thick SiO layer is sequentially formed on the back side of an n-type silicon wafer 100. x Tunneling layer 1 and a 150 nm thick amorphous silicon layer 2 (i-Poly); Step 6: Using PECVD technology, a 2nm thick SiO layer is sequentially formed on the back side of the n-type silicon wafer 100. x Tunneling layer 1 and amorphous silicon layer 2 with a thickness of 150 nm.

[0045] Example 3 The only difference between this embodiment and Embodiment 1 is that steps three and seven are different: Step 3: Transfer to the LPCVD equipment, heat to 650°C at a heating rate of 5°C / min, and hold at that temperature for 15 minutes to react the i-Poly and SiO2 formed in Step 2. x Crystallization is then performed, followed by the introduction of boron trichloride (BCl3) and oxygen to complete boron diffusion, forming a boron-doped polycrystalline silicon layer 3 with a boron doping concentration of 2.5 × 10⁻⁶.19 cm -3 ; Step 7: Transfer to the LPCVD equipment, heat to 650°C at a heating rate of 5°C / min, and hold at that temperature for 15 minutes to react the i-Poly and SiO2 formed in Step 6. x Crystallization is followed by the introduction of phosphorus oxychloride (POCl3) and oxygen to complete phosphorus diffusion, forming a 5-layer phosphorus-doped polycrystalline silicon substrate with a phosphorus doping concentration of 2 × 10⁻⁶. 20 cm -3 .

[0046] Example 4 The only difference between this embodiment and Embodiment 2 is that in step two, the deposition temperature is 400°C, while steps three and seven are the same as in Embodiment 3.

[0047] Comparative Example 1 The comparative example is a method for fabricating a single-sided textured tunneling oxide passivated back contact solar cell. The only difference between this method and Example 1 is that steps one and five are different: Step 1: Polish the n-type silicon wafer on both sides using polishing additives (Changzhou Shichuang Energy Co., Ltd.) and 1% sodium hydroxide solution; Step 5: Remove all layers on the N-zone and isolation zone using a wet tank process with a strongly alkaline solution and additives.

[0048] The performance of the double-textured tunneling oxide passivated back contact solar cells prepared in the above embodiments and comparative examples was tested, and the test results are shown in Table 1. For each group of test samples, 16 cells were selected from 160 cells for testing. The test method is as follows, and the test results are shown in Table 1.

[0049] Finished battery testing method: Flash Test (IV curve test). Standard test conditions (STC): Irradiance: 1000 W / m²; Battery temperature: 25°C; Spectrum: AM1.5. Test parameters: Open circuit voltage (Voc): Maximum voltage of the battery under no load. Short circuit current (Isc): Maximum current of the battery when short-circuited. Fill factor (FF): A key indicator of battery quality. Conversion efficiency: Photovoltaic conversion efficiency.

[0050] Table 1

[0051] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A double-sided textured tunneling oxide passivated back contact solar cell, characterized in that, The silicon wafer includes a textured surface on both the front and back sides. The back side of the silicon wafer has a P-region, an N-region, and an isolation region. The front side of the silicon wafer is provided with a passivation layer and an anti-reflection layer stacked in sequence.

2. The double-sided textured tunneling oxide passivated back contact solar cell according to claim 1, characterized in that, The passivation layer is an aluminum oxide layer; And / or, the antireflective layer is a silicon nitride layer or a silicon oxynitride layer.

3. The double-sided textured tunneling oxide passivated back contact solar cell according to claim 1, characterized in that, The P-region includes a tunneling layer, a boron-doped polysilicon layer, a passivation layer, and an antireflection layer stacked sequentially on a silicon wafer, and a positive electrode is disposed on the antireflection layer of the P-region.

4. The double-sided textured tunneling oxide passivated back contact solar cell according to claim 3, characterized in that, The N-region includes a tunneling layer, a phosphorus-doped polycrystalline silicon layer, a passivation layer, and an antireflection layer stacked sequentially on a silicon wafer, and a negative electrode is disposed on the antireflection layer of the N-region.

5. The double-sided textured tunneling oxide passivated back contact solar cell according to claim 1, characterized in that, The isolation region includes a passivation layer and an antireflection layer stacked sequentially on the silicon wafer.

6. The double-sided textured tunneling oxide passivated back contact solar cell according to claim 3, characterized in that, The thickness of the tunneling layer is 1.5 - 3 nm; And / or, the material of the tunneling layer is silicon oxide.

7. The double-sided textured tunneling oxide passivated back contact solar cell according to claim 4, characterized in that, The thickness of the boron-doped polycrystalline silicon layer is 100-200 nm; And / or, the thickness of the phosphorus-doped polycrystalline silicon layer is 100-200 nm.

8. The double-sided textured tunneling oxide passivated back contact solar cell according to claim 1, characterized in that, The thickness of the N-region silicon wafer is 2-4 μm greater than that of the isolation region silicon wafer.

9. A method for preparing a double-sided textured tunneling oxide passivated back contact solar cell according to any one of claims 1-8, characterized in that, include: Step 1: Texturing the back of the n-type silicon wafer; Step 2: Sequentially form a tunneling layer and an amorphous silicon layer on the back side of the n-type silicon wafer; Step 3: Anneal and boron diffusion are performed sequentially on the n-type silicon wafer that forms the tunneling layer and amorphous silicon layer to form a boron-doped polycrystalline silicon layer; Step 4: Laser removal of the borosilicate glass layer at the corresponding positions in the N-region and the isolation region; Step 5: Wet etching removes all layers on the N-region and isolation region and texturing the corresponding n-type silicon wafer; Step 6: Sequentially form a tunneling layer and an amorphous silicon layer on the back side of the n-type silicon wafer; Step 7: Anneal and phosphorus diffusion are performed sequentially on the n-type silicon wafer that forms the tunneling layer and amorphous silicon layer to form a phosphorus-doped polycrystalline silicon layer; Step 8: Laser removal of the phosphosilicate glass layer in the P-region and the isolation region; Step 9: Wet etching of all layers on the front and side surfaces of the n-type silicon wafer; Step 10: Wet etching removes all layers on the boron-doped polysilicon layer in the P-region, all layers on the phosphorus-doped polysilicon layer in the N-region, and all layers on the silicon wafer in the isolation region. Texturing is then performed on the isolation region and the front side of the n-type silicon wafer. Step 11: Passivation layer and antireflection layer are sequentially prepared on the front and back sides of the silicon wafer, and then electrodes are printed on the back side of the silicon wafer.

10. The method for fabricating a double-sided textured tunneling oxide passivated back contact solar cell according to claim 9, characterized in that, The annealing step has a heating rate of 1-5°C / min, a temperature of 600-700°C, and a time of 10-20 min; And / or, the amorphous silicon layer is formed using plasma-enhanced chemical vapor deposition.

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