Power module and string inverter

Abstract

The embodiment of the application relates to the power semiconductor technical field, and discloses a power module and a string type photovoltaic inverter, the power module comprises a substrate and two pieces of DBC with different heat transfer efficiencies arranged on the substrate, a plurality of first chips are arranged on a first DBC with strong heat transfer efficiency, a plurality of second chips are arranged on a second DBC with weak heat transfer efficiency, the first chips are high-heat chips, and the second chips are low-heat chips, the technical scheme of the application adopts a core design based on matching the heat transfer efficiency of the DBC according to the heat generation demand of the chips, the first DBC and the second DBC with different heat transfer efficiencies are designed, the high-heat chips are arranged on the first DBC with stronger heat transfer efficiency, heat coupling of the high-heat chips is avoided, and the low-heat chips are arranged on the second DBC with weak heat transfer efficiency, so that the low-heat chips are not affected by the high-heat chips.

Description

Technical Field

[0001] This application relates to the field of power semiconductor technology, and in particular to a power module and a string photovoltaic inverter. Background Technology

[0002] In the power modules of string photovoltaic inverters, traditional power modules use one or two DBCs of the same area to mix and arrange all the chips, and the chip arrangement is more based on the requirements of circuit topology, ignoring the differences in heat generation between chips. However, high-heat-generating chips are the main source of total power module losses and have extremely high requirements for heat dissipation efficiency; but the heat transfer efficiency of a single substrate is fixed. When high-heat and low-heat-generating chips are mixed, the heat generated by the high-heat-generating chips will be conducted to the surrounding low-heat-generating chips, causing the operating temperature of the low-heat-generating chips to rise, affecting their stability, and thus reducing the reliability of the entire power module. Summary of the Invention

[0003] The purpose of this application is to provide at least one power module and string photovoltaic inverter, which involves a DBC with differentiated heat transfer efficiency. The first DBC and the second DBC correspond to high-heat and low-heat chips respectively, forming a clear heat dissipation functional partition, avoiding thermal coupling between low-heat and high-heat chips, and improving the reliability of the entire power module.

[0004] To solve the above-mentioned technical problems, at least one embodiment of this application provides a power module, the power module including: a substrate and two DBCs with different heat transfer efficiencies disposed on the substrate, wherein a first DBC with stronger heat transfer efficiency is disposed on a plurality of first chips, and a second DBC with weaker heat transfer efficiency is disposed on a plurality of second chips, the first chips being high-heat-generating chips and the second chips being low-heat-generating chips.

[0005] In an optional embodiment, the physical area of ​​the first DBC is larger than the physical area of ​​the second DBC, and the heat loss of the plurality of first chips accounts for more than or equal to 50% of the total loss of the first DBC; the heat loss of the plurality of second chips accounts for less than 50% of the total loss of the second DBC.

[0006] In an optional embodiment, the first DBC and the second DBC are electrically interconnected via a low-inductance connector, which is at least one of the following: a silver-plated flat copper strip, an aluminum strip, or a bonding wire.

[0007] In an optional embodiment, the ratio of the total heat generation power of the plurality of first chips to the total single-chip layout area of ​​the plurality of first chips is greater than the ratio of the total heat generation power of the plurality of second chips to the total single-chip layout area of ​​the plurality of second chips.

[0008] In an optional embodiment, at least one of the first chips and / or at least one of the second chips are also slow-switching chips, wherein the switching time of the slow-switching chip is greater than 200 ns; the copper layer at the location of the slow-switching chip includes a power current copper layer and a drive signal copper layer separately disposed.

[0009] In an optional embodiment, the DBC on which the slow switching speed chip is disposed further includes: a Kelvin connection structure; The drive signal is connected to the surface of the slow-switching chip via the Kelvin connection structure and independent bonding wires to form a drive control loop.

[0010] In an optional embodiment, the copper layer thickness of the power current copper cladding is 300μm-500μm.

[0011] In an optional embodiment, the spacing between the power current copper layer and the drive signal copper layer is greater than or equal to 0.5 mm, and an insulating dielectric layer is disposed between them, wherein the breakdown voltage of the insulating dielectric layer is greater than or equal to 4000 V.

[0012] At least one embodiment of this application also provides a string photovoltaic inverter, including the power module as described in any of the preceding claims.

[0013] In an optional embodiment, it further includes: a heat sink, wherein a first DBC with high heat transfer efficiency is located in the orthographic projection area where the combined thermal resistance of the substrate and the heat sink is minimized, the combined thermal resistance being the sum of the conduction thermal resistance from the DBC to the substrate, the contact thermal resistance between the substrate and the heat sink, and the thermal resistance of the heat sink itself.

[0014] The power module and string photovoltaic inverter provided in the embodiments of this application adopt a core design based on matching the heat transfer efficiency of the DBC according to the heat dissipation requirements of the chips. It features a first DBC and a second DBC with different heat transfer efficiencies. The high-heat-generating chip is configured in the first DBC, which has a higher heat transfer efficiency. Higher heat transfer efficiency results in a better heat conduction path and faster heat diffusion, effectively absorbing and conducting the heat generated by the high-heat-generating chip, preventing the junction temperature of the high-heat-generating chip from exceeding the limit due to heat dissipation bottlenecks. The low-heat-generating chip is separately arranged in the second DBC, which has a lower heat transfer efficiency, avoiding thermal coupling with the high-heat-generating chip. The low-heat-generating chip is not affected by the heat radiation / conduction of the high-heat-generating area, resulting in a more stable operating temperature. This ensures stable operating temperature and minimal fluctuations for the low-heat-generating chip, reducing fatigue stress on the interconnect interface and guaranteeing long-term operational reliability and extending its service life. Furthermore, the second DBC does not require excessive area design, allowing for precise matching of the heat dissipation requirements of the low-heat-generating chip and avoiding resource waste. Attached Figure Description

[0015] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0016] Figure 1 This is a schematic diagram of the power module provided according to an embodiment of this application; Figure 2 This is a schematic diagram of the structure of the first DBC in the power module according to an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a DBC copper layer in a power module provided according to an embodiment of this application, where a chip with a slow switching speed is provided. Figure 4 This is a schematic diagram of the power module according to another embodiment of this application; Figure 5 This is a schematic diagram of a string photovoltaic inverter provided according to another embodiment of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of this application to enable the reader to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0018] To facilitate understanding of the embodiments of this application, relevant content about string photovoltaic inverters will be introduced first.

[0019] String photovoltaic (PV) inverters are key equipment in solar photovoltaic (PV) power generation systems, primarily used to convert direct current (DC) generated by solar panels into alternating current (AC) for use in homes, businesses, or the power grid. Here's a detailed introduction: String inverters receive DC power and transmit it to the inverter's internal components by connecting strings of multiple solar panels. Their core consists of power modules and control circuitry, using electronic switching technology to achieve DC-AC power conversion. The converted AC power is then connected to the power grid. In a string PV inverter, the power module is the core functional unit for power conversion (DC → AC). It includes power semiconductor devices, which are the "actuators" of the power conversion. They achieve DC-AC conversion through high-frequency switching operations; common examples include IGBTs (Insulated Gate Bipolar Transistors) and SiC MOSFETs (Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistors).

[0020] Traditional layouts mix all transistor positions on a limited-area DBC (Diverterless Circuit Block) according to the circuit topology. This involves using one or two DBCs with the same heat transfer capacity to accommodate all chips, including both high-heat and low-heat chips. When high-heat and low-heat chips are mixed, the heat generated by the high-heat chips is conducted to the surrounding low-heat chips, causing the operating temperature of the low-heat chips to rise, affecting their stability. This leads to severe thermal coupling, forming localized hotspots, and restricting the long-term reliability and current output capability of the module. Furthermore, in multi-transistor parallel applications, fast and slow transistors with different switching speeds can experience gate oscillations in the slow transistors during high-speed switching due to coupling between the drive circuit and the power circuit (common source / common emitter inductor), threatening module safety.

[0021] This application provides a power module. Compared with the prior art, the implementation of this application adopts a core design based on matching the heat transfer efficiency of the DBC (Diverterless Core Controller) according to the heat dissipation requirements of the chips. It designs a first DBC and a second DBC with different heat transfer efficiencies, and configures the first DBC, which has a higher heat transfer efficiency, for high-heat-generating chips, such as high-heat-generating MOS chips. The higher the heat transfer efficiency of the DBC, the better the heat conduction path and the faster the heat diffusion speed, which can efficiently absorb and conduct the heat generated by the high-heat-generating chip, avoiding the junction temperature exceeding the standard due to heat dissipation bottlenecks. Low-heat-generating chips, such as low-voltage-drop IGBT chips for low-frequency switching, are separately arranged in the second DBC. On the one hand, this avoids thermal coupling with the high-heat-generating chip, and the low-heat-generating chip is not affected by the heat radiation / heat conduction of the high-heat-generating area, resulting in a more stable operating temperature. This ensures stable operating temperature and small fluctuations for the low-heat-generating chip, and reduces fatigue stress on the interconnect interface, ensuring long-term operational reliability and improving service life. On the other hand, the second DBC does not require excessive area design, and can accurately match the heat dissipation requirements of the low-heat-generating chip, avoiding resource waste.

[0022] The implementation details of the power module in this embodiment are described below. The following content is only for the convenience of understanding and is not necessary for implementing this solution.

[0023] Example 1: like Figure 1 As shown, the embodiments of this application relate to a power module 100, which includes: a substrate 101, and at least two DBCs with different heat transfer efficiencies disposed on the substrate 101. The substrate 101 is a carrier for multiple DBCs, and the two DBCs include a first DBC 110 and a second DBC 120. The heat transfer efficiency of the first DBC 110 is greater than that of the second DBC 120. Heat transfer efficiency is an indicator of the heat dissipation effect of the DBC on the chip. Multiple first chips 130 are disposed on the first DBC 110, and the first chips 130 are high-heat-generating chips. Multiple second chips 140 are disposed on the second DBC 120, and the second chips 140 are low-heat-generating chips.

[0024] like Figure 1 As shown, DBC (Direct Copper Ceramic Substrate) is a commonly used heat dissipation material in power modules. It possesses excellent thermal conductivity and electrical insulation, serving as the core heat dissipation and electrical connection carrier for power modules in power electronics fields, such as string photovoltaic inverters. DBC is a composite substrate in which copper foil is directly bonded to the surface of a ceramic insulating substrate (such as alumina or aluminum nitride) through a high-temperature sintering process. It combines electrical conduction and efficient heat dissipation, acting as a crucial intermediate layer connecting power electronic devices, such as IGBT chips and SiC MOSFET chips, to external heat sinks. The copper foil layer can be etched to form specific circuit patterns, enabling the integration of multiple chips.

[0025] The power module in this application includes at least two DBCs with different heat transfer efficiencies, namely a first DBC110 and a second DBC120, where the heat transfer efficiency of the first DBC110 is greater than that of the second DBC120. Heat transfer efficiency is an indicator used to reflect the DBC's heat dissipation effect on the chip. It can be characterized by at least one of the following factors: ceramic material, physical area, copper layer thickness, and thermal resistance of the substrate heat transfer path, reflecting the heat density and heat dissipation efficiency of the DBC. For example, heat transfer efficiency can also be evaluated by comprehensively considering multiple factors such as ceramic material, physical area, copper layer thickness, and heat sink thermal resistance. The physical area of ​​the DBC is the actual geometric area of ​​the DBC, the copper layer thickness of the DBC is the actual thickness of the copper-clad layer of the DBC, and the total thermal resistance of the heat sink is the total thermal resistance from the copper layer of the DBC to the heat sink environment.

[0026] For example, in terms of power consumption, chips such as IGBTs and SiC MOSFETs in power semiconductors have a single-chip power density of 200W / cm². 2 Chips of 70°C and above can be considered high-heat-generating chips. These chips are the main source of power consumption in electronic devices or modules, generating significant heat; insufficient heat dissipation can easily lead to excessive junction temperatures. Low-heat-generating chips, on the other hand, consume little power and generate little heat, generally requiring no special heat dissipation design. The power density of a single low-heat-generating chip is less than 100W / cm². 2 Chips at and below this level are mostly low-frequency switching chips with low on-state voltage drop. The first DBC110, with its high heat transfer efficiency, is assigned to the first chip 130, and the second DBC120, with its lower heat transfer efficiency, is assigned to the second chip 140. This avoids wasting heat dissipation resources and improves the overall heat dissipation efficiency of the module. For example, SiC chips can be placed in the first DBC110, and Si chips can be placed in the second DBC120.

[0027] By assigning high-heat and low-heat chips to the first and second thermal management circuits (DBCs) respectively, a clear heat dissipation functional zone is formed. Specifically, the higher the heat transfer efficiency, the stronger the heat transfer efficiency of the DBC. Therefore, the chips adopt a zoned thermal management layout, and the zoned thermal management layout rules can be set as follows: high-heat chips are placed in DBCs with high heat transfer efficiency, and low-heat chips are placed in DBCs with low heat transfer efficiency. Essentially, high-heat chips are matched with large heat dissipation areas and high thermal conductivity materials, while low-heat chips are matched with compatible materials, thereby achieving a match between heat and heat transfer efficiency and avoiding local overheating.

[0028] The power module provided in this embodiment adopts a core design based on matching the heat transfer efficiency of the DBC (Digital Converter) to the heat dissipation requirements of the chips. It features a first DBC and a second DBC with different heat transfer efficiencies. The first DBC, with its higher heat transfer efficiency, is used to concentrate high-heat-generating chips, such as high-heat-generating MOS chips. Higher heat transfer efficiency results in a better heat conduction path and faster heat diffusion, efficiently absorbing and conducting the heat generated by the high-heat-generating chip, preventing junction temperature exceedances due to heat dissipation bottlenecks. Low-heat-generating chips, such as low-voltage-drop IGBT chips for low-frequency switching, are separately arranged in the second DBC. This avoids thermal coupling with the high-heat-generating chips, ensuring the low-heat-generating chips are not affected by heat radiation / conduction from the high-heat-generating areas, resulting in more stable operating temperatures and less fluctuation. This also reduces fatigue stress on the interconnect interfaces, ensuring long-term reliability and extending the chip's lifespan. Furthermore, the second DBC substrate does not require excessive area design, allowing for precise matching of the heat dissipation requirements of the low-heat-generating chips and avoiding resource waste.

[0029] For example, such as Figure 1 As shown, when the area of ​​the first chip 130 is smaller than the area of ​​the second chip 140, the physical areas of the first DBC 110 and the second DBC 120 can also be the same, such as... Figure 4 As shown, when the first chip 130 and the second chip 140 have the same area, the physical areas of the first DBC110 and the second DBC120 can also be different.

[0030] For example, when the heat transfer efficiency is determined by the physical area, the physical areas and aspect ratios of the first DBC110 and the second DBC120 can be different, such as... Figure 4As shown, exemplarily, the physical area of ​​the first DBC110 is different from that of the second DBC120, and DBCs with different physical areas can respectively support different types of chips. By concentrating the first chip 130 on the first DBC110 with a larger physical area, the ample substrate area can increase the layout spacing between the first chips 130. In this embodiment, the high heat transfer efficiency of the first DBC110 is adapted to the heat dissipation requirements of the first chip 130. The second chip 140 is concentrated on the second DBC120 with a smaller physical area. The physical area of ​​the second DBC120 is designed with the principle of just accommodating the second chip 140 to avoid wasting heat dissipation resources. This on-demand allocation design ensures heat dissipation effect without excessively increasing the overall size of the power module 100, taking into account both integration and cost control, and meeting the requirements of string photovoltaic inverters for efficient and compact design.

[0031] For example, when the heat transfer efficiency is determined by the ceramic material, the first DBC110 can use a ceramic material with a higher thermal conductivity, such as Si3N4, while the second DBC120 can use a ceramic material with a relatively lower thermal conductivity, such as Al2O3. The calculation of the heat transfer efficiency of the DBC in the power module can also revolve around the thermal resistance model, combining the structural characteristics of the DBC, such as the ceramic layer and the upper and lower copper layers, the material's thermal properties, and the actual heat dissipation boundary conditions. Methods such as analytical methods (theoretical formulas), equivalent thermal resistance methods, and numerical simulations can be used to determine the efficiency. There are also simplified estimation methods for engineering applications. The accuracy, applicable scenarios, and computational complexity of different methods vary significantly. The heat transfer efficiency of the DBC in the power module can be determined using any method available in the prior art, without specific limitations.

[0032] For example, the first DBC110 can centrally arrange the first chip 130, which accounts for more than 50% of the total loss of the first DBC110. Specifically, in the power module 100 of the string photovoltaic inverter, the first chips 130 that account for more than 50% of the total heat loss of the entire first DBC110 can be centrally placed on the same DBC (such as the first DBC110) and not dispersed to other DBCs (such as the second DBC120). Essentially, this achieves precise thermal management by centralizing the heat source and matching it with strong heat dissipation.

[0033] like Figure 2As shown, in the layout design of the first chip 130 of the first DBC110, the single-chip layout area can satisfy the requirement that the distance between adjacent first chips 130 is ≥ 1 / 2 of the side length of the first chip 130. The single-chip layout area refers to the physical area occupied by a single chip on the DBC, which includes the size of the chip itself and the surrounding space reserved to avoid thermal coupling and electrical interference (such as the distance with adjacent chips). That is, the single-chip layout area includes the chip size and the adjacent spacing. Therefore, the single-chip layout area can be a design parameter that balances chip heat dissipation, electrical performance and module integration.

[0034] The second chip 140, which accounts for less than 50% of the total loss of the second DBC120, is arranged in the power module 100 of the string photovoltaic inverter, and its physical area only meets the basic layout requirements. Specifically, the second chip 140, which accounts for less than 50% of the total loss of the second DBC120 when the total heat loss of all chips is added up, can be centrally arranged on another independent DBC (such as the second DBC120), physically separated from the first chip 130 of the first DBC110. Essentially, this is also a low-heat source matching and adaptation heat dissipation, avoiding the occupation of high heat dissipation resources, while balancing the integration of the power module 100.

[0035] In this embodiment, by centrally arranging the first chips 130 on the first DBC 110, which has a larger physical area, the ample substrate area allows for increased spacing between the first chips 130, such as a spacing between adjacent first chips ≥ 1 / 2 of their own side length, reducing the "thermal coupling effect" of heat conduction. The second chip 140 is arranged on the second DBC 120, which has a smaller physical area, avoiding competition for heat dissipation space with the first chip 130. Ultimately, this achieves a uniform overall temperature distribution of the module, eliminates local hot spots, reduces the junction temperature of the first chip 130 by 15%-25%, and extends chip lifespan by more than 30%.

[0036] In one embodiment, such as Figure 1 As shown, the first DBC110 and the second DBC120 are electrically interconnected via a low-inductance connector 150. The low-inductance connector 150 is at least one of the following: a flat copper strip with a silver-plated surface, an aluminum strip, or a bonding wire. By using the low-inductance connector 150, the upper and lower connectors are concentrated in the middle of the module, allowing the current "going" and "return" paths to highly overlap. This significantly optimizes the circuit parasitic parameters geometrically, reduces voltage spikes during switching, prevents chip damage due to overvoltage, and improves the module's conversion efficiency.

[0037] In one embodiment, such as Figure 1As shown, the ratio of the total heat dissipation power of the first chips 130 arranged on the first DBC110 to the single-chip layout area of ​​the multiple first chips 130 is greater than the ratio of the total heat dissipation power of the second chips on the second DBC120 to the single-chip layout area of ​​the multiple second chips. Specifically, the total heat dissipation power refers to the total power loss of all chips arranged on the DBC under rated operating conditions, where the total power loss includes conduction loss and switching loss, and the unit is watts (W). For example, if two high-frequency switching external transistors (high-heat dissipation chips) with NPC three-level topology are arranged on the first DBC110, with a single chip loss of 50W, then the total heat dissipation power is 100W. If one internal transistor and one clamping transistor are arranged on the second DBC120, with a single chip loss of 15W, then the total heat dissipation power is 30W. For example, the first DBC110 has a physical area of ​​100 cm², with only 80 cm² used to arrange high-heat-generating chips, resulting in a total single-chip layout area of ​​80 cm². The second DBC120 has a physical area of ​​80 cm², with 70 cm² used to arrange low-heat-generating chips, resulting in a total single-chip layout area of ​​70 cm². The ratio of total heat generation power to the total single-chip layout area can be considered as the heat density per unit area (heat flux density, unit W / m² or W / cm²). This ratio can be directly quantified by a formula: Let the total heat generation power of the first DBC110 be P1, and the total single-chip layout area be A1; let the total heat generation power of the second DBC120 be P2, and the total single-chip layout area be A2. Then, it must satisfy: P1 / A1 > P2 / A2. This relationship strongly correlates the physical characteristics (area, material) of the DBC with its heat transfer efficiency. Specifically, when the first DBC110... When the physical area of ​​the first DBC110 is larger than that of the second DBC120, a higher P1 / A1 is needed to ensure that the large physical area of ​​the first DBC110 is not wasted. If the P1 / A1 of the first DBC110 is the same as the P2 / A2 of the second DBC120, then the large area means that the total heat dissipation power needs to be increased proportionally. For example, if A1=2A2, then P1=2P2. However, in reality, the total power loss of the first chip 130 is much more than twice that of the second chip 140. Therefore, P1 / A1 must be greater than P2 / A2 to ensure that the large area of ​​the first DBC110 and the strong heat dissipation can fully meet the high heat dissipation requirements. This ratio can be used as a quantitative judgment standard for the thermal management design of power modules to avoid imbalances in heat dissipation design.

[0038] Example 2: According to an exemplary embodiment, most of the power module in this embodiment is the same as that in the above embodiments. The difference between this embodiment and the above embodiments is that in this embodiment, at least one first chip and / or at least one second chip are also slow-switching chips. For example, the second chip disposed on the second DBC is a slow-switching chip, which is, for example, a silicon-based IGBT chip with a switching time greater than 200 ns. The copper layer at the location of the slow-switching chip includes a separately disposed power current copper layer 310 and a drive signal copper layer 320. The power current copper layer 310 is used to transmit power current, and the drive signal copper layer 320 is used to transmit drive signals.

[0039] In this embodiment, such as Figure 3 As shown, for example, taking the second chip 140 with a slow switching speed in the second DBC120, the copper layer of the chip with the slow switching speed in the second DBC120 is separated into a power current copper layer 310 and a drive signal copper layer 320 to eliminate coupling interference caused by common source / common emitter inductance, significantly reduce gate oscillation when the slow switching chip and the fast switching chip are connected in parallel, and avoid false triggering or chip damage.

[0040] In one embodiment, the DBC equipped with a slow-switching chip also features a Kelvin connection structure (not shown in the figure). This is to eliminate common-source / common-emitter inductance by employing a Kelvin lead design for the slow-switching chip (slow transistor). The Kelvin connection structure design targets the first and / or second slow-switching chips, based on the principle of eliminating common-emitter / common-source inductance using a Kelvin design to prevent high di / dt from causing gate voltage oscillation in the slow-switching chip.

[0041] like Figure 3 As shown, the drive signal copper layer 320 connected to the Kelvin pin 410 is connected to the chip surface through an independent bonding wire 160 to form a control loop that is not affected by the power current copper layer 310. This can reduce the influence of high-frequency changes in power current on the drive signal, ensure the accurate switching timing of the slow-switching chip, and improve the stability of the module.

[0042] In one embodiment, the copper layer thickness of the power current copper cladding layer 310 is 300μm-500μm.

[0043] In one embodiment, the copper layer thickness of the drive signal copper layer 320 is the same as the copper layer thickness of the power current copper layer 310; the distance between the power current copper layer 310 and the drive signal copper layer 320 is greater than or equal to 0.5 mm, and an insulating dielectric layer is provided between them, with a breakdown voltage of the insulating dielectric layer not less than 4000 V.

[0044] The spacing between the power current copper layer 310 and the drive signal copper layer 320 is ≥0.5mm, and an insulating dielectric layer with a breakdown voltage ≥4000V is provided in between. This ensures the electrical safety of the module by avoiding leakage or breakdown between the power current and the drive signal circuit through sufficient copper layer spacing and a high breakdown voltage insulating layer.

[0045] Example 3: The power module layout in this embodiment is applied to either an NPC or an ANPC topology circuit. Multiple high-heat-generating chips (first chips) are, for example, high-frequency switching external transistors in an NPC topology or high-frequency switching internal transistors in an ANPC topology. Low-heat-generating chips (second chips) are, for example, low-frequency switching internal transistors, clamping transistors, and corresponding diodes in an NPC topology.

[0046] Taking the layout and application of power modules in NPC topology circuits as an example, combined with Figure 1 and Figure 4 As shown, the power module includes a substrate 101, and a first DBC 110 and a second DBC 120 disposed on the substrate 101. The physical area of ​​the first DBC 110 is larger than that of the second DBC 120, and the heat transfer efficiency of the first DBC 110 is greater than that of the second DBC 120. The two high-heat-generating external transistors and their diodes in the NPC three-level topology circuit are concentrated and spaced on a large first DBC 110. This large DBC provides ample layout area, allowing for maximum spacing between the external transistor chips, thereby significantly reducing the thermal resistance of the main heat sources and thermal coupling between them. The low-heat-generating low-frequency switching transistor, its diode, and the clamping transistor are disposed on a smaller second DBC 120. The area of ​​this second DBC is precisely designed to accommodate these chips without requiring additional area.

[0047] In this embodiment, the outer tube and its diode chip (first chip 130) on the large-size first DBC110 can be upgraded to a SiC chip, and the second chip on the small-size second DBC120 is a Si chip. The first DBC110 and the second DBC120 are electrically interconnected through low-inductance copper strips, bonding wires or other bridging methods, which can realize the path separation of Si process and SiC process.

[0048] In this embodiment, a Kelvin connection structure can be provided for the inner tube of the low-frequency switching transistor. Combined with... Figure 3 As shown, on the copper layer of the DBC where the low-frequency switching transistor (a chip with a slow switching speed) is located, there are separate power current copper layer 310 area and drive signal copper layer 320 area. The drive signal copper layer 320 on the chip surface is connected to the lead-out pin 410 of the Kelvin pin through an independent bonding wire 160.

[0049] Example 4: This application also provides a string photovoltaic inverter 200, including the power module 100 as described in any of the above embodiments. See also Figure 5 As shown, the string photovoltaic inverter also includes a housing 220, a cover plate 230, and a heat sink. The first DBC 110 is located in the orthographic projection area where the combined thermal resistance of the substrate 101 and the heat sink is minimized. The combined thermal resistance is the sum of the conductive thermal resistance from the DBC to the bottom surface of the integrated heat sink substrate and the convective thermal resistance between the integrated heat sink substrate and the cooling medium.

[0050] In this embodiment, the substrate 101 can be an integrated heat dissipation substrate, such as adding a heat dissipation fin structure to the back of a regular flat substrate as a direct liquid cooling heat sink. The denser the heat dissipation fin structure, the stronger the heat dissipation capacity. Figure 5 As shown, the density of the heat dissipation pins below the substrate 101 corresponding to the first DBC110 is greater than the density of the heat dissipation pins below the substrate corresponding to the second DBC120.

[0051] In this embodiment, the two types of DBCs can be arranged in a parallel or adjacent layout. The DBC with higher heat transfer efficiency (or physical area) should be preferentially placed in the area with the highest heat dissipation efficiency, such as the projected area where the combined thermal resistance of the substrate and heat sink is minimized. The DBC with lower heat transfer efficiency (or physical area) can be arranged at the edge or in non-core heat dissipation areas. The heat generated by the high-heat-generating chip on the first DBC110 needs to be transferred sequentially through the first DBC110 and the substrate 101 to the heat sink for dissipation. The combined thermal resistance is the core obstacle in the heat transfer process; the smaller its value, the higher the heat conduction efficiency. Therefore, placing the first DBC110 in the area with the lowest combined thermal resistance allows the heat from the high-heat-generating chip to be quickly conducted to the heat sink with minimal obstruction, significantly reducing the chip junction temperature. This avoids problems such as decreased carrier mobility and increased leakage current due to overheating, prevents the inverter from triggering overheat protection shutdown, and ensures uninterrupted power conversion, especially suitable for the long-term full-load operation requirements of outdoor string inverters. It should be understood that the terms "mechanism," "device," "component," etc., used in this application are merely one method of distinguishing different components, elements, parts, sections, or assemblies at different levels. However, if other terms can achieve the same purpose, they can be replaced by other expressions.

[0052] Those skilled in the art will understand that the above embodiments are specific examples of implementing this application. In practical applications, the technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification, and various changes can be made to them in form and detail without departing from the spirit and scope of this application.

Claims

1. A power module, characterized in that, The power module includes: a substrate and two DBCs with different heat transfer efficiencies disposed on the substrate, wherein a first DBC with higher heat transfer efficiency is provided with multiple first chips, and a second DBC with lower heat transfer efficiency is provided with multiple second chips, wherein the first chips are high-heat-generating chips and the second chips are low-heat-generating chips.

2. The power module according to claim 1, characterized in that, The physical area of ​​the first DBC is larger than that of the second DBC, and the heat loss of the plurality of first chips accounts for more than or equal to 50% of the total heat loss of the first DBC; the heat loss of the plurality of second chips accounts for less than 50% of the total heat loss of the second DBC.

3. The power module according to claim 1 or 2, characterized in that, The first DBC and the second DBC are electrically interconnected through a low-inductance connector, which is at least one of the following: a flat copper strip with a silver-plated surface, an aluminum strip, or a bonding wire.

4. The power module according to claim 1, characterized in that, The ratio of the total heat generation power of the plurality of first chips to the total single-chip layout area of ​​the plurality of first chips is greater than the ratio of the total heat generation power of the plurality of second chips to the total single-chip layout area of ​​the plurality of second chips.

5. The power module according to claim 1, characterized in that, At least one of the first chips and / or at least one of the second chips are also slow-switching chips, wherein the switching time of the slow-switching chip is greater than 200 ns; the copper layer at the location of the slow-switching chip includes a power current copper layer and a drive signal copper layer that are separately disposed.

6. The power module according to claim 5, characterized in that, The DBC equipped with the slow switching speed chip also includes: a Kelvin connection structure; The drive signal is connected to the surface of the slow-switching chip via the Kelvin connection structure and independent bonding wires to form a drive control loop.

7. The power module according to claim 6, characterized in that, The copper layer thickness of the power current copper cladding layer is 300μm-500μm.

8. The power module according to claim 7, characterized in that, The spacing between the power current copper layer and the drive signal copper layer is greater than or equal to 0.5 mm, and an insulating dielectric layer is provided between them, the breakdown voltage of the insulating dielectric layer is greater than or equal to 4000 V.

9. A string photovoltaic inverter, characterized in that, Includes the power module as described in any one of claims 1 to 8.

10. The string photovoltaic inverter according to claim 9, characterized in that, Also includes: The heat sink has a first DBC with high heat transfer efficiency located in the orthographic projection area where the combined thermal resistance of the substrate and the heat sink is minimized. The combined thermal resistance is the sum of the conduction thermal resistance from the DBC to the substrate, the contact thermal resistance between the substrate and the heat sink, and the heat sink's own thermal resistance.

Images