A charge domain global exposure pixel structure, image sensor, manufacturing method and working method
By designing a gradient potential well structure and a charge domain global exposure pixel structure with a shared mask, the problems of low charge transfer efficiency and high process complexity were solved, achieving efficient and low-cost charge transfer and image sensor performance improvement.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN XINTU INTELLIGENT SENSE TECH CO LTD
- Filing Date
- 2026-06-11
- Publication Date
- 2026-07-14
AI Technical Summary
Existing charge domain global exposure pixel structures suffer from low charge transfer efficiency, high process complexity, and high manufacturing costs, making it difficult to meet the application requirements of high-resolution, high-performance image sensors.
A gradient potential well structure for global exposure pixel architecture is designed, comprising a photodiode, a charge storage node, and a charge-voltage conversion node. By using a shared mask and an obtuse angle design, the process flow is simplified, and the charge transfer efficiency and process tolerance are improved.
It improves charge transport efficiency, reduces process complexity and cost, enhances process yield, reduces dark current and noise, improves gate reliability, and avoids image lag.
Smart Images
Figure CN122396079A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of image sensor technology, and in particular to a charge domain global exposure pixel structure, an image sensor, a manufacturing method, and a working method. Background Technology
[0002] Image sensors, as key devices that convert optical images into electrical signals, play a central role in numerous vision applications. Among them, global shutter CMOS image sensors, by simultaneously exposing all pixels, effectively avoid the rolling shutter effect caused by shuttering, making them particularly suitable for scenarios with high image integrity requirements, such as machine vision, industrial automation, and security monitoring. Global shutter technology includes voltage-domain global shutter technology and charge-domain global shutter technology. Voltage-domain global shutter technology refers to converting charge into voltage within a pixel for storage and readout, while charge-domain global shutter technology refers to transferring and storing charge packets throughout the process before finally converting them into voltage.
[0003] Compared to voltage-domain global exposure (GLOB) technology, charge-domain GLOB is achieved by integrating and reading out the signal during the charge transfer stage, resulting in superior noise performance and facilitating the design of large-array, high-resolution sensors. However, GLOB image sensors also have certain limitations. First, to achieve efficient charge transfer and storage, the pixel structure is typically complex, requiring precise control of the depth and shape of multiple potential well regions, leading to a larger chip area. Second, its design is more challenging and the process requirements are more stringent, necessitating multiple masks to define the potential well structures of the photodiode region and charge storage nodes, increasing manufacturing costs and process complexity. Furthermore, the charge transport path design in existing technologies is not optimized, exhibiting low tolerance for process variations, and the charge transfer efficiency needs improvement. These factors, to some extent, restrict the widespread application and further development of GLOB image sensors.
[0004] Therefore, there is an urgent need for an improved charge domain global exposure pixel structure that can simplify the process, reduce costs, improve charge transfer efficiency and pixel performance, and meet the application requirements of high-resolution, high-performance image sensors. Summary of the Invention
[0005] This application aims to solve the technical problems of low charge transfer efficiency, high process complexity, and high manufacturing cost of existing charge domain global exposure pixel structures, and provides an improved charge domain global exposure pixel structure, image sensor, manufacturing method, and working method.
[0006] In a first aspect, this application provides a charge domain global exposure pixel structure, including: Semiconductor substrate; A photodiode, formed in the semiconductor substrate, for converting incident light into a charge signal; A charge storage node, for storing the charges generated by the photodiode; A charge-voltage conversion node, for converting the charge signal into a voltage signal; A photodiode reset gate, for controlling the reset operation of the photodiode; A charge storage gate, disposed between the photodiode and the charge storage node, for controlling the transfer of charges from the photodiode to the charge storage node; A transfer gate, disposed between the charge storage node and the charge-voltage conversion node, for controlling the transfer of charges from the charge storage node to the charge-voltage conversion node; Wherein, the potential well depths of the photodiode region, the charge storage node, and the charge-voltage conversion node gradually become shallower, forming a gradient potential well structure.
[0007] In some embodiments, the semiconductor substrate is a P-type semiconductor substrate; and / or, the region of the photodiode in the semiconductor substrate is octagonal; and / or, the photodiode reset gate and the charge storage gate are P-type doped polysilicon gates.
[0008] In some embodiments, the region where the photodiode is formed in the P-type semiconductor substrate is defined by an N-type potential well, and the size of the active region of the photodiode is determined by the lateral geometry and longitudinal depth of the N-type potential well.
[0009] In some embodiments, the photodiode includes: a first deep N-type potential well, for providing charge storage capacity; a first shallow N-type potential well, for receiving the photo-generated charges transmitted upward from the first deep N-type potential well to provide a transition platform.
[0010] In some embodiments, the charge storage node includes a second shallow N-type potential well and a second deep N-type potential well. The second shallow N-type potential well is located below the charge storage gate, and the second deep N-type potential well is located below the second shallow N-type potential well, for providing a charge temporary storage space.
[0011] In some embodiments, the first shallow N-type potential well of the photodiode and the second deep N-type potential well of the charge storage node are patterned through the same mask; and / or, the second deep N-type potential well in the charge storage node is in a "return" shape or a "mountain" shape; and / or, the second shallow N-type potential well in the charge storage node includes an auxiliary potential well region that is close to the transfer gate and overlaps with the transfer gate. [[ID=***]]
[0012] In some embodiments, by designing different doping energies for the first deep N-type potential well, the first shallow N-type potential well, the second shallow N-type potential well, and the charge-voltage conversion node, the depth of the highest potential region of the photodiode region is greater than the depth of the highest potential region of the charge storage node, and the depth of the highest potential region of the charge storage node is greater than the depth of the highest potential region of the charge-voltage conversion node.
[0013] In some embodiments, the highest potential in the photodiode region is lower than the highest potential in the charge storage node, and the highest potential in the charge storage node is lower than the highest potential in the charge-voltage conversion node.
[0014] In some embodiments, a P-type doped mask is covered over the photodiode reset gate and charge storage gate for P-type doping of the photodiode reset gate and charge storage gate.
[0015] In some embodiments, the angle between the first charge transport path direction of the photodiode to the charge storage node and the second charge transport path direction of the charge storage node to the charge voltage conversion node is an obtuse angle; and / or, the angle between the first charge transport path direction of the photodiode to the charge storage node and the second charge transport path direction of the charge storage node to the charge voltage conversion node is 135°.
[0016] Secondly, this application also provides a charge domain global exposure image sensor, including the pixel structure as described in the first aspect.
[0017] Thirdly, this application also provides a method for manufacturing a charge domain global exposure pixel structure, comprising the following steps: Provide semiconductor substrates; Forming a photodiode in a semiconductor substrate; Charge storage nodes are formed in a semiconductor substrate; Forming charge-voltage conversion nodes in a semiconductor substrate; A photodiode reset gate, a charge storage gate, and a transport gate are formed on a semiconductor substrate; The potential well depths of the photodiode region, charge storage node, and charge-voltage conversion node decrease sequentially.
[0018] Fourthly, this application also provides a method for operating a charge domain global exposure pixel structure, comprising the following steps: Exposure stage: The photodiode receives the light signal and generates an electric charge; Charge transfer stage: Open the charge storage gate to transfer the charge in the photodiode to the charge storage node for storage; Charge readout stage: Open the transfer gate, transfer the charge in the charge storage node to the charge-voltage conversion node, and read and quantify it through an external circuit. Among them, the potential well depths of the photodiode region, the charge storage node, and the charge-voltage conversion node gradually become shallower, forming a gradient potential well structure to promote unidirectional charge transfer.
[0019] Compared with the prior art, the present invention has the following beneficial technical effects: (1) Improved charge transfer efficiency: By making the potential well depths of the photodiode region, the charge storage node, and the charge-voltage conversion node gradually become shallower, forming a gradient potential well structure, charges can efficiently transfer unidirectionally from the photodiode to the charge storage node and then to the charge-voltage conversion node under the action of the potential difference, reducing charge residue and image lag.
[0020] (2) Increased process redundancy: By setting the charge transfer path direction from the photodiode to the charge storage node and the charge transfer path direction from the charge storage node to the charge-voltage conversion node to be obtuse angles, making the charge transfer path closer to a straight line, compared with the traditional 90° turning design, it leaves a larger redundant space for process fluctuations and improves the manufacturing yield.
[0021] (3) Reduced process cost: By sharing the same N-type potential well mask for the photodiode and the charge storage node, compared with the traditional technology that requires four mask plates (two for the photodiode and two for the charge storage node) to be defined separately, the present invention only requires three mask plates to complete, significantly reducing the mask plate cost and process complexity.
[0022] (4)兼顾满阱容量与传输效率:通过将电荷存储节点内的深层N型势阱设计为"回"字形或"山"字形,在保证电荷传输通道畅通的同时,最大限度地保留了高掺杂浓度的电荷存储区域,实现了大满阱容量与高效电荷传输的兼顾。
[0023] (5) Reduced dark current and noise: By using a P-type doped photodiode reset gate and charge storage gate, the work function of the gate is changed, making the lower on the silicon surface under the gate under the same external voltage, enhancing the ability to accumulate holes on the surface area during turn-off, and effectively reducing the dark current and noise generated by interface states.
[0024] (6) Improved gate reliability: For a P-type doped gate, a higher (closer to 0V) gate terminal voltage (negative value) can be used during turn-off to make the silicon surface reach the same electric potential, which reduces the potential difference between the on-state and the off-state, reduces the electric field stress on the gate oxide layer, and thus improves the reliability and service life of the gate. Description of the Drawings
[0025] To more clearly illustrate the technical solutions in the related art or in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the related art or the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, rather than all embodiments. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0026] Figure 1 Schematic diagram of the architecture of the pixel structure provided by the embodiment of the present application; Figure 2 Schematic diagram of the potential well position profile constructed by PDN, PDN2 and FD provided by the embodiment of the present application; Figure 3 Schematic diagram of the highest potential value and position in the potential wells of the PD region, MN region and FD region provided by the embodiment of the present application; Figure 4 Schematic diagram of the charge transfer path provided by the embodiment of the present application; Figure 5 Schematic diagram of a special PDN shape (in the shape of a "return" character) in the MN region provided by the embodiment of the present application; Figure 6 Schematic diagram of a special PDN shape (in the shape of a "mountain" character) in the MN region provided by the embodiment of the present application; Figure 7 Schematic diagram of the potential change effect of a special PDN shape in the MN provided by the embodiment of the present application.
[0027] Explanation of reference numerals: 10 - Semiconductor substrate (P-sub); 20 - Photoelectric diode (PD); 21 - First shallow N-type potential well (PDN); 22 - First deep N-type potential well (DPDN); 30 - Charge storage node (MN); 31 - Second shallow N-type potential well (PDN2); 32 - Second deep N-type potential well (PDN); 40 - Charge voltage conversion node (FD); 50 - Photoelectric diode reset gate (Grst); 60 - Charge storage gate (MG); 70 - Transfer gate (TG); 80 - P-type doping mask plate (PinG); T1 - First charge transfer path direction; T2 - Second charge transfer path direction. Detailed implementation manners
[0028] To make the objectives, technical solutions, and advantages of this application more apparent and understandable, this application will be clearly and completely described below in conjunction with its embodiments and corresponding drawings. Throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. It should be understood that the various embodiments of this application described below are merely illustrative of this application and are not intended to limit this application. That is, all other embodiments obtained by those skilled in the art based on the various embodiments of this application without creative effort are within the scope of protection of this application. Furthermore, the technical features involved in the various embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0029] Figures 1 to 7 This is a schematic diagram of a charge domain global exposure pixel structure according to this application. The pixel structure includes a semiconductor substrate 10 and multiple pixel units integrated on the semiconductor substrate 10. The multiple pixel units are arranged in a two-dimensional array on the semiconductor substrate 10 for imaging the object under test to obtain image information containing the object under test. Each pixel unit includes a photodiode 20 (PD), a charge storage node 30 (MN), a charge-voltage conversion node 40 (Floating Diffusion, FD), a photodiode reset gate 50 (Grst), a charge storage gate 60 (Memory Gate, MG), and a transfer gate 70 (Transfer Gate, TG).
[0030] In some embodiments, the semiconductor substrate 10 is a P-type silicon substrate (P-sub) as the basis of the entire pixel structure; a photodiode 20 (PD) is formed in the semiconductor substrate 10 to convert incident light into a charge signal; a charge storage node 30 (MN) is used to store the charge generated by the photodiode 20; a charge-to-voltage conversion node 40 (FD) is formed in the semiconductor substrate 10 through an N-type doped region to convert the charge signal into a voltage signal; a photodiode reset gate 50 (Grst) is located above the semiconductor substrate 10 to control the reset operation of the photodiode 20; a charge storage gate 60 (MG) is disposed between the photodiode 20 and the charge storage node 30 to control the transfer of charge from the photodiode 20 to the charge storage node 30; and a transfer gate 70 (TG) is disposed between the charge storage node 30 and the charge-to-voltage conversion node 40 to control the transfer of charge from the charge storage node 30 to the charge-to-voltage conversion node 40.
[0031] In one embodiment, the region where the photodiode 20 is formed on the P-type semiconductor substrate is defined by an N-type potential well. Specifically, N-type ions are implanted into a specific region of the P-type semiconductor substrate 10 through processes such as ion implantation, thereby forming a local N-type region, which is the region where the photodiode 20 is located. The local N-type region forms a PN junction with the surrounding P-type substrate. At the PN junction, due to the difference in carrier concentration, a built-in electric field is generated from the N region to the P region, and a band bend is formed where the N region has a relatively low potential and the P region has a relatively high potential. When light from the object under test is received by the pixel, electron-hole pairs are generated, namely positively charged holes and negatively charged free electrons. For the negatively charged free electrons, the N region with lower potential energy is a "potential well". Once the free electrons diffuse to this region, they are quickly swept into the N-region potential well by the built-in electric field and collected, while the holes are swept into the P-type substrate. The free electrons collected by the N-type potential well are the signal charges formed by the incident light received by the photodiode 20. In other words, the size of the active region of the photodiode 20 is determined by the lateral geometry and longitudinal depth of the N-type potential well.
[0032] It should be noted that the localized N-type region formed by implanting N-type ions into a specific area of the semiconductor substrate 10 through processes such as ion implantation can be of various shapes, such as quadrilaterals, hexagons, or similar shapes. Figure 2 The octagonal or other polygons shown can be used as long as they can achieve a larger effective photosensitive area with the same pixel area; this application does not impose any restrictions on them.
[0033] Furthermore, the N-type potential well corresponding to the photodiode 20 is divided into a first shallow N-type potential well 21 (PDN) and a first deep N-type potential well 22 (DPDN) in the vertical direction. The first deep N-type potential well is formed by high-energy, low-concentration N-type ion implantation and is deeper, which is used to provide the main charge storage capacity. The first shallow N-type potential well is located above the first deep N-type potential well with lower energy and higher concentration, and receives the photogenerated charge transmitted upward from the first deep N-type potential well 22 to provide a transition platform.
[0034] In some embodiments, the charge storage node 30 includes a second shallow N-type potential well 31 (PDN2) and a second deep N-type potential well 32 (PDN). The second shallow N-type potential well 31 is located below the charge storage gate 60, and the second deep N-type potential well 32 is located below the second shallow N-type potential well 31. The second shallow N-type potential well 31 and the second deep N-type potential well 32 together constitute the complete N-type potential well of the charge storage node 30, providing temporary charge storage space.
[0035] In traditional designs, to optimize charge transport in the photodiode 20 and charge storage node 30 to form shallow and deep N-type potential wells, four independent photolithography steps are typically required. This means two photomasks are needed for the photodiode and two for the charge storage node, totaling four photomasks. In this embodiment, the photodiode 20 and charge storage node 30 are located below the charge storage gate 60 on both sides, allowing the second deep N-type potential well 32 (PDN) of the charge storage node 30 to share the same photomask patterning as the first shallow N-type potential well 21 (PDN) of the photodiode 20. This means that the first shallow N-type potential well 21 of the photodiode 20 and the second deep N-type potential well 32 of the charge storage node 30 are formed simultaneously through a single ion implantation and the same photolithography layer, creating a physically continuous N-type charge transport channel between the photodiode 20 region and the charge storage node 30 region. By sharing a PDN mask, only three masks are needed, significantly reducing mask costs and process complexity.
[0036] Since the charge-voltage conversion node 40 is formed in the semiconductor substrate 10 through an N-type doped region, that is, the charge-voltage conversion node 40 also has an N-type potential well. In some embodiments, such as Figure 2 and Figure 3 As shown, the potential well depths of the photodiode 20, charge storage node 30, and charge-to-voltage conversion node 40 gradually decrease, forming a gradient potential well structure. Specifically, by designing different doping energies for the first deep N-type potential well 22 (DPDN), the first shallow N-type potential well 21 (PDN), the second shallow N-type potential well 31 (PDN2), and the charge-to-voltage conversion node 40, the depth of the highest potential region in the photodiode 20 is greater than that in the charge storage node 30, and the depth of the highest potential region in the charge storage node 30 is greater than that in the charge-to-voltage conversion node 40. Simultaneously, by designing different doping concentrations, the highest potential VP in the photodiode 20 region is... PD Below the highest potential VP within the charge storage node 30 MN The highest potential VP within charge storage node 30 MN Below the highest potential VP within the charge-voltage transition node 40 FD Thus, this gradient potential well structure enables efficient unidirectional charge transfer from the photodiode 20 to the charge storage node 30 and then to the charge-voltage conversion node 40 under the influence of the potential difference.
[0037] Furthermore, to improve charge transport efficiency, such as Figure 4As shown, the included angle between the first charge transfer path direction T1 from the photodiode 20 to the charge storage node 30 and the second charge transfer path direction T2 from the charge storage node 30 to the charge voltage conversion node 40 is designed as an obtuse angle (for example, 135°). This design makes the charge transfer path closer to a straight line. Compared with the traditional 90° turning design, it leaves a larger redundant space for process fluctuations, improving the manufacturing yield and charge transfer efficiency.
[0038] In some embodiments, as Figure 5 and Figure 6 shown, the second deep N-type well 32 (PDN) in the charge storage node 30 is in a "return" shape or a "mountain" shape. The principle of this special shape design is as follows: The doping concentration of the N-type well in the charge storage node 30 determines the full well capacity. The higher the doping concentration, the larger the full well capacity. However, a high doping concentration will lead to a region of the charge storage node with an overall high electric potential, making charge transfer difficult. By designing the second deep N-type well 32 in the charge storage node 30 as a "return" shape or a "mountain" shape, while ensuring a moderate electric potential in the charge transfer channel (the region close to the transfer gate 70), the charge storage region with a high doping concentration is maximally retained, achieving the balance between a large full well capacity and efficient charge transfer. As Figure 7 shown, this design only sacrifices the full well capacity of part of the charge storage node (that is, only part of the region has a lower electric potential), while most regions still maintain a high full well capacity. In addition, the position of the second shallow N-type well 31 (PDN2) is close to the transfer gate 70 and overlaps with the transfer gate 70, further promoting the efficient transfer of charges from the charge storage node 30 to the charge voltage conversion node 40.
[0039] It should be noted that the shape of the PDN in the charge storage node can be appropriately adjusted according to actual layout requirements, such as a "day" shape, an "eye" shape, etc., as long as it can ensure the smoothness of the charge transfer channel while retaining enough charge storage regions.
[0040] In some embodiments, the photodiode reset gate 50 and the charge storage gate 60 are made of P-type doped polysilicon gates. As Figure 1As shown, a gate P-type doping mask plate 80 (PinG) covers the photodiode reset gate 50 and the charge storage gate 60, which is used to perform P-type doping on the photodiode reset gate 50 and the charge storage gate 60. Through P-type doping, the work function of the gate is changed. Compared with traditional N-type doping, under the condition of applying the same voltage, the potential of the silicon surface under the gate is lower, which strengthens the ability of the photodiode reset gate 50 and the charge storage gate 60 to accumulate holes on the surface when turned off, and can effectively reduce the dark current and noise generated by interface states. In addition, for the P-type doped gate, when turned off, compared with the traditional N-type doped gate, a higher (higher means closer to 0V) gate terminal voltage (negative value) can be used to make the silicon surface reach the same potential. This reduces the potential difference between the on-state and the off-state, thereby reducing the electric field stress borne by the gate oxide layer and improving the reliability and service life of the gate.
[0041] It should be understood that the P-type doping concentration of the photodiode reset gate and the charge storage gate can be adjusted according to the requirements of the gate work function and the threshold voltage, as long as it can enhance the ability to accumulate holes on the surface when turned off and reduce the dark current and noise.
[0042] This application also provides a manufacturing method for forming the above pixel structure, including the following steps: Step S1: Provide a P-type semiconductor substrate.
[0043] Step S2: Form a photodiode and a charge storage node in the semiconductor substrate. Specifically, it includes: defining the pattern of the octagonal photodiode photosensitive area through a lithography process; forming the first shallow N-type well and the first deep N-type well of the photodiode, as well as the second shallow N-type well and the second deep N-type well of the charge storage node through an ion implantation process.
[0044] Specifically, the first shallow N-type well (PDN) of the photodiode and the second deep N-type well of the charge storage node are formed simultaneously through a mask plate; the pattern of the mask plate corresponding to the second deep N-type well of the charge storage node is "hui" - shaped or "mountain" - shaped, and the position of the second shallow N-type well is close to the transfer gate and overlaps with the transfer gate.
[0045] Step S3: Form a charge voltage conversion node in the semiconductor substrate. Form an N-type doped region through an ion implantation process.
[0046] Step S4: Form a gate structure above the semiconductor substrate. Specifically, it includes: depositing a polysilicon layer; defining the patterns of the photodiode reset gate, the charge storage gate, and the transfer gate through a lithography and etching process; performing P-type doping on the photodiode reset gate and the charge storage gate through the gate P-type doping mask plate (PinG).
[0047] This application also provides a method for operating a charge domain global exposure pixel structure, including the following stages: Reset phase: A high potential is applied to the reset gate and charge storage gate of the photodiode to reset the photodiode and charge storage node to their initial state.
[0048] Exposure stage: The photodiode receives light signals and generates charges, which accumulate inside the photodiode.
[0049] Charge transfer stage: After global exposure, the charge storage gate is opened (a high potential is applied), and the charge in the photodiode is efficiently transferred to the charge storage node for storage under the influence of the potential difference. Since the potential well depth of the photodiode region, the charge storage node, and the charge-voltage conversion node decreases sequentially, a gradient potential well structure is formed, enabling unidirectional and efficient charge transfer from the photodiode to the charge storage node.
[0050] Charge readout stage: The transfer gate is opened (a high potential is applied), and the charge in the charge storage node is transferred to the charge voltage conversion node under the action of the potential difference. It is read and quantized into a voltage signal by an external circuit (such as a source follower).
[0051] Because the angle between the first charge transport path from the photodiode to the charge storage node and the second charge transport path from the charge storage node to the charge voltage conversion node is an obtuse angle, the charge transport path is closer to a straight line, resulting in high transport efficiency and greater tolerance to process fluctuations.
[0052] This application also provides a charge domain global exposure image sensor, comprising a plurality of pixel structures arranged in an array as described in the above embodiments. The image sensor also includes peripheral circuits such as row driving circuits, column readout circuits, and timing control circuits for controlling the exposure, charge transfer, and signal readout operations of the pixel array.
[0053] In global exposure mode, all pixel photodiodes begin exposure simultaneously. After exposure, they simultaneously transfer charge to their respective charge storage nodes for storage, and then read out the charge from the charge storage nodes row by row or column by column. This working method effectively avoids the rolling shutter effect when imaging moving objects.
[0054] It should be noted that the various embodiments in this application are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0055] It should also be noted that, in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0056] The above description of the disclosed embodiments enables those skilled in the art to implement or use the content of this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined in this application may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A charge domain global exposure pixel structure, characterized in that, Comprising: A semiconductor substrate; A photodiode formed in the semiconductor substrate for converting incident light into a charge signal; the photodiode includes a first deep N-type potential well and a first shallow N-type potential well located above the first deep N-type potential well, the first deep N-type potential well being used to provide a charge storage capacity, and the first shallow N-type potential well being used to receive the photo-generated charges transmitted upward from the first deep N-type potential well; A charge storage node for storing the charges generated by the photodiode; the charge storage node includes a second shallow N-type potential well and a second deep N-type potential well, the second shallow N-type potential well being located below a charge storage gate, and the second deep N-type potential well being located below the second shallow N-type potential well for providing a charge temporary storage space; A charge-voltage conversion node for converting a charge signal into a voltage signal; A photodiode reset gate for controlling the reset operation of the photodiode; A charge storage gate disposed between the photodiode and the charge storage node for controlling the transfer of charges from the photodiode to the charge storage node; A transfer gate disposed between the charge storage node and the charge-voltage conversion node for controlling the transfer of charges from the charge storage node to the charge-voltage conversion node; Wherein, the potential well depths of the photodiode region, the charge storage node, and the charge-voltage conversion node gradually become shallower, forming a gradient potential well structure; the first shallow N-type potential well and the second deep N-type potential well are patterned through the same mask pattern so that the photodiode region and the charge storage node region physically form a continuous N-type charge transfer channel; The second deep N-type potential well is in a "return" shape or a "mountain" shape.
2. The charge domain global exposure pixel structure according to claim 1, characterized in that, The semiconductor substrate is a P-type semiconductor substrate; and / or, the region of the photodiode in the semiconductor substrate is octagonal; and / or, the photodiode reset gate and the charge storage gate are P-type doped polysilicon gates.
3. The charge domain global exposure pixel structure according to claim 2, characterized in that, The region where the photodiode is formed in the P-type semiconductor substrate is defined by an N-type potential well, and the size of the active region of the photodiode is determined by the lateral geometry and longitudinal depth of the N-type potential well.
4. The charge-domain global exposure pixel structure according to claim 1, wherein The second shallow N-type potential well in the charge storage node includes an auxiliary potential well region close to the transfer gate and overlapping with the transfer gate.
5. The charge domain global exposure pixel structure according to claim 1, characterized in that, By designing the different doping energies of the first deep N-type potential well, the first shallow N-type potential well, the second shallow N-type potential well, and the charge-voltage conversion node, it is made that in the depth direction, the depth of the highest potential region of the photodiode region is greater than the depth of the highest potential region of the charge storage node, and the depth of the highest potential region of the charge storage node is greater than the depth of the highest potential region of the charge-voltage conversion node.
6. The charge domain global exposure pixel structure according to claim 5, characterized in that, The highest potential in the photodiode region is lower than the highest potential in the charge storage node, and the highest potential in the charge storage node is lower than the highest potential in the charge-voltage conversion node.
7. The charge domain global exposure pixel structure according to claim 2, characterized in that, A P-type doped mask is placed over the photodiode reset gate and the charge storage gate to perform P-type doping on the photodiode reset gate and the charge storage gate.
8. The charge domain global exposure pixel structure according to any one of claims 1 to 7, characterized in that, The angle between the first charge transport path direction from the photodiode to the charge storage node and the second charge transport path direction from the charge storage node to the charge voltage conversion node is an obtuse angle. And / or, the angle between the first charge transfer path direction of the photodiode to the charge storage node and the second charge transfer path direction of the charge storage node to the charge voltage conversion node is 135°.
9. A charge domain global exposure image sensor, characterized in that, Includes the pixel structure as described in any one of claims 1-8.
10. A method for manufacturing a charge domain global exposure pixel structure, characterized in that, For manufacturing the pixel structure as described in any one of claims 1-8, the following steps are included: Provide semiconductor substrates; A photodiode is formed in the semiconductor substrate; Charge storage nodes are formed in the semiconductor substrate; A charge-voltage conversion node is formed in the semiconductor substrate; A photodiode reset gate, a charge storage gate, and a transport gate are formed on the semiconductor substrate; The potential well depths of the photodiode region, the charge storage node, and the charge-voltage conversion node decrease sequentially.
11. A method for operating a charge domain global exposure pixel structure, characterized in that, Applied to the pixel structure as described in any one of claims 1-8, the method includes the following steps: Exposure stage: The photodiode receives the light signal and generates an electric charge; Charge transfer stage: Open the charge storage gate to transfer the charge in the photodiode to the charge storage node for storage; Charge readout stage: Open the transfer gate to transfer the charge in the charge storage node to the charge-voltage conversion node, and read and quantize it through external circuitry; The potential well depths of the photodiode region, the charge storage node, and the charge-voltage conversion node gradually decrease, forming a gradient potential well structure to promote unidirectional charge transport.