Preparation method of inSe and CuInP2S6 two-dimensional photoelectric device
By constructing an InSe-CuInP2S6 heterojunction and using a two-dimensional material transfer platform, the problem of difficulty in adjusting the detection wavelength of optoelectronic devices caused by the small band gap of InSe was solved, achieving a photoelectric response with high sensitivity and wide dynamic range, and reducing production costs and material waste.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI INST OF CERAMIC CHEM & TECH CHINESE ACAD OF SCI
- Filing Date
- 2025-01-13
- Publication Date
- 2026-07-14
Smart Images
Figure CN122396083A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of two-dimensional material device fabrication technology, specifically relating to a method for fabricating two-dimensional optoelectronic devices using InSe and CuInP2S6. Background Technology
[0002] InSe is a layered semiconductor material belonging to the IV-VI group of compounds with a direct bandgap structure, which gives it excellent light absorption and high carrier mobility in optoelectronic applications. Its layered structure not only endows the material with good mechanical flexibility but also facilitates its fabrication into two-dimensional nanosheets through methods such as exfoliation, which is particularly important for the development of flexible optoelectronic devices. InSe's high absorption coefficient and tunable bandgap width make it a promising candidate for applications in solar cells, photodetectors, and other fields. Furthermore, InSe exhibits relatively good environmental stability, which is beneficial for the manufacture of optoelectronic devices that can operate stably for long periods.
[0003] CuInP2S6 is a quaternary sulfide semiconductor belonging to the I-III-VI2 group of compounds, which has attracted attention in recent years due to its potential applications in photovoltaics and photoelectrochemistry. This material combines the advantages of traditional thin-film solar cell materials such as copper indium gallium selenide (CIGS) and CdTe, including high absorption coefficients, good stability, and potentially low-cost manufacturing processes. The band gap of CuInP2S6 can be optimized through compositional adjustments to match the solar spectrum, thereby improving photoelectric conversion efficiency. Furthermore, its non-toxic elemental composition is more environmentally friendly than materials containing toxic elements such as cadmium, aligning with the requirements of green and sustainable development.
[0004] In practical applications, optoelectronic devices require high sensitivity, high precision, and a wide dynamic range for wavelength adjustment. These requirements ensure that the devices can accurately detect and respond to light signals of different wavelengths under various application environments, thus meeting diverse needs. Due to the inherent bandgap limitation of single two-dimensional transition metal dichalcogenide materials, directly using InSe to construct optoelectronic devices presents challenges. InSe has a relatively small bandgap; at room temperature, the energy difference between its conduction band and valence band is approximately 1.3 eV to 1.4 eV. Therefore, InSe exhibits strong absorption and response to light in the 1.3 eV to 1.4 eV (approximately 850-950 nm) range. This limitation makes it difficult to adjust the detection wavelength to meet practical application requirements. Summary of the Invention
[0005] To address the aforementioned technical problems, the present invention aims to provide a simple, stable, and effective method for fabricating two-dimensional optoelectronic devices using InSe and CuInP2S6. By stacking InSe and CuInP2S6 to construct a van der Waals heterojunction, the electronic properties of the resulting heterostructure can be precisely fine-tuned, allowing for the design of optoelectronic devices with desired functions.
[0006] Specifically, the present invention provides a method for fabricating a two-dimensional optoelectronic device using InSe and CuInP2S6, the method comprising the following steps: Step S1: Fabrication of the InSe / CuInP2S6 heterojunction-silicon substrate composite structure: Step S1.1: Clean and dry the silicon substrate to obtain a clean silicon substrate; Step S1.2: Place the InSe and CuInP2S6 samples on the peeling tape and fold them in half multiple times for mechanical peeling. At the adhesive points of the tape, obtain InSe and CuInP2S6 flakes with smooth dissociation surfaces and relatively small thickness. Step S1.3: Transfer the CuInP2S6 sheet to the clean silicon substrate and select CuInP2S6 sheets of appropriate thickness to obtain a clean silicon substrate with CuInP2S6 sheets bonded together. Step S1.4: Transfer the InSe flakes onto a polydimethylsiloxane PDMS film and screen for InSe flakes with nanoscale thickness to obtain a PDMS film with InSe flakes bonded together. Step S1.5: Place the clean silicon substrate with CuInP2S6 film bonded in step S1.3 onto the sample stage of the two-dimensional material transfer platform and fix it. Place the PDMS film with InSe film bonded in step S1.4 onto the sample end to be transferred and fix it. Use the two-dimensional material transfer platform to transfer the InSe film on the PDMS film onto the CuInP2S6 film and attach it to it to form a heterojunction, thus obtaining the InSe / CuInP2S6 heterojunction-silicon substrate composite structure. Step S2, Metal Electrode Preparation: Step S2.1: Spin-coat PMMA onto the silicon substrate of the InSe / CuInP2S6 heterojunction-silicon substrate composite structure to obtain a silicon substrate with spin-coated PMMA. Step S2.2: Place the spin-coated PMMA silicon substrate in the electron beam cavity of the electron beam exposure system, import the electrode design drawing into the electron beam exposure system, and perform an exposure operation by bombarding the corresponding spin-coated PMMA silicon substrate with an electron beam according to the design drawing to obtain the exposed pattern. At the same time, use CAD software to draw the electrode shape according to the shape of the heterojunction. Step S2.3: Place the exposed silicon substrate in the developer solution for development to remove the PMMA from the exposed area of the silicon substrate and expose the bottom silicon substrate. Then, transfer it to isopropanol to stop development and complete the fixing operation. Step S2.4: Place the fixed silicon substrate in a thermal evaporation vacuum coating machine and deposit a titanium layer and a gold layer in sequence. Step S2.5: Immerse the evaporated silicon substrate in acetone to remove the metal portion in contact with the unexposed PMMA. The remaining metal in contact with the silicon substrate is the metal electrode. Finally, the two-dimensional optoelectronic device consisting of InSe and CuInP2S6 was obtained.
[0007] Preferably, in step S1.1, the silicon substrate comprises heavily doped P-type polycrystalline silicon and a silicon oxide layer on top of it; preferably, the total thickness of the silicon substrate is 500±10um, and the thickness of the silicon oxide layer is 50-300nm.
[0008] Preferably, in step S1.2, the number of folds is 3-5.
[0009] Preferably, in step S1.3, the suitable thickness ranges from 10 to 30 nm.
[0010] Preferably, in step S1.4, the nanoscale thickness ranges from 10 to 30 nm.
[0011] Preferably, in step S1, the ratio of the number of InSe wafers to the number of CuInP2S6 wafers in the InSe / CuInP2S6 heterojunction-silicon substrate composite structure is 1:2.
[0012] Preferably, in step S2.1, the spin coating of PMMA on the silicon substrate is performed on a spin coater and then dried; preferably, the spin coater speed is 6000 rpm, the spin coating time is 60 seconds, the drying time is 900 seconds, and the drying temperature is 90°C.
[0013] Preferably, in step S2.3, the developing time is 50-70s, more preferably 60s; the fixing time is 20-50s, more preferably 25-35s, and even more preferably 30s.
[0014] Preferably, in step S2.4, the vacuum degree of the thermal evaporation vacuum coating instrument is 5 × 10⁻⁶. -6 below torr; The thickness of the titanium layer is 5-10 nm, preferably 10 nm; the deposition rate is... Preferred The thickness of the gold layer is 30-60 nm, preferably 50 nm; the evaporation rate is... The preferred deposition rate for a 10nm thick gold layer is: The rate of the 40nm thick gold layer is
[0015] Preferably, in step S2.5, the soaking and peeling operation time is 100-120 min, preferably 120 min.
[0016] Beneficial effects (1) Low cost: No need for expensive equipment and high energy consumption, which reduces production costs; (2) Simple operation: Mechanical peeling method is simple and easy to implement, reducing the complexity of operation; (3) High material utilization rate: High temperature treatment is avoided, reducing material waste; (4) Structural stability: High-temperature treatment is avoided, ensuring the structural and performance stability of the two-dimensional material. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the two-dimensional transfer platform structure used in this invention; Figure 2 This is a schematic diagram of the structure of the two-dimensional optoelectronic device made of InSe and CuInP2S6 obtained in Example 1; Figure 3 The image shows an optical mirror image of the two-dimensional InSe and CuInP2S6 optoelectronic device prepared in Example 1. Figure 4 The output curve of the photoresponse current-laser power characteristics of the two-dimensional optoelectronic device of InSe and CuInP2S6 prepared in Example 1 is shown. Figure 5 The image shows the dynamic current curve of the photoresponse of the two-dimensional InSe and CuInP2S6 optoelectronic devices prepared in Example 1. Figure 6 The optical mirror image is of the optoelectronic device prepared in Comparative Example 1. Figure 7 The output curves of the optoelectronic device prepared in Comparative Example 1 under 405nm laser irradiation at different powers with the gate voltage maintained at 0.1V are shown. Figure label: 1-Robotic arm; 2-Optical microscope; 3-Slide with InSe film attached; 4-Sample stage; A-Drain of photodetector; B-Source of photodetector. Detailed Implementation
[0018] The present invention will be further illustrated by the following embodiments. It should be understood that the following embodiments are for illustrative purposes only and are not intended to limit the present invention.
[0019] Generally, InSe and CuInP2S6 exhibit lattice mismatch. This lattice mismatch, potentially introduced at the interface, can lead to impurities and discontinuous bandgap alignment, thus reducing device quality and performance, making heterojunction fabrication difficult. This patent utilizes a dry transfer method to precisely control the electronic structure and chemical environment at the interface, enabling fine-tuning of the material's photoelectric properties, reducing the adverse effects of lattice mismatch, and ultimately fabricating a high-quality heterostructure. Furthermore, the fabrication method is pollution-free and controllable.
[0020] The following is an exemplary description of a method for fabricating a two-dimensional optoelectronic device using InSe and CuInP2S6 provided by the present invention. The fabrication method may include the following steps: Step S1: Fabrication of the InSe / CuInP2S6 heterojunction-silicon substrate composite structure: Step S1.1: Clean and dry the silicon substrate to obtain a clean silicon substrate; Step S1.2: Place the InSe and CuInP2S6 samples on the peeling tape and fold them in half multiple times for mechanical peeling. At the adhesive points of the tape, obtain InSe and CuInP2S6 flakes with smooth dissociation surfaces and relatively small thickness. Step S1.3: Transfer the CuInP2S6 sheet to the clean silicon substrate and select CuInP2S6 sheets of appropriate thickness to obtain a clean silicon substrate with CuInP2S6 sheets bonded together. Step S1.4: Transfer the InSe flakes onto a polydimethylsiloxane PDMS film and screen for InSe flakes with nanoscale thickness to obtain a PDMS film with InSe flakes bonded together. Step S1.5: Place the clean silicon substrate with CuInP2S6 film bonded in step S1.3 onto the sample stage of the two-dimensional material transfer platform and fix it. Place the PDMS film with InSe film bonded in step S1.4 onto the sample end to be transferred and fix it. Use the two-dimensional material transfer platform to transfer the InSe film on the PDMS film onto the CuInP2S6 film and attach it to it to form a heterojunction, thus obtaining the InSe / CuInP2S6 heterojunction-silicon substrate composite structure. Step S2, Metal Electrode Preparation: Step S2.1: Spin-coat PMMA onto the silicon substrate of the InSe / CuInP2S6 heterojunction-silicon substrate composite structure to obtain a silicon substrate with spin-coated PMMA. Step S2.2: Place the spin-coated PMMA silicon substrate in the electron beam cavity of the electron beam exposure system, import the electrode design drawing into the electron beam exposure system, and perform an exposure operation by bombarding the corresponding spin-coated PMMA silicon substrate with an electron beam according to the design drawing to obtain the exposed pattern. At the same time, use CAD software to draw the electrode shape according to the shape of the heterojunction. Step S2.3: Place the exposed silicon substrate in the developer solution for development to remove the PMMA from the exposed area of the silicon substrate and expose the bottom silicon substrate. Then, transfer it to isopropanol to stop development and complete the fixing operation. Step S2.4: Place the fixed silicon substrate in a thermal evaporation vacuum coating machine and deposit a titanium layer and a gold layer in sequence. Step S2.5: Immerse the evaporated silicon substrate in acetone to remove the metal portion in contact with the unexposed PMMA. The remaining metal in contact with the silicon substrate is the metal electrode. Finally, the two-dimensional optoelectronic device consisting of InSe and CuInP2S6 was obtained.
[0021] In some embodiments, in step S1.1, the silicon substrate may include heavily doped P-type polysilicon and a silicon oxide layer on top of it, and the heavily doped P-type polysilicon may serve as the bottom gate of the device; preferably, the total thickness of the silicon substrate may be 500±10um, and the thickness of the silicon oxide layer may be 50-300nm (e.g., 300nm).
[0022] In some embodiments, in step S1.1, the silicon substrate cleaning process can be: sequentially ultrasonically cleaning with acetone for 10-20 minutes (e.g., 20 minutes), cleaning with anhydrous ethanol for 10-20 minutes (e.g., 10 minutes), and cleaning with deionized water for 5-10 minutes (e.g., 10 minutes). Acetone is used to remove contaminants such as grease and debris from the silicon wafer; anhydrous ethanol is used to remove residual acetone; and deionized water is used to remove residual ethanol. The drying temperature can be 90°C, and the drying time can be 30 minutes.
[0023] In some implementations, in step S1.2, the number of folds can be 3-5.
[0024] In some embodiments, in step S1.2, the smaller thickness can be in the range of 5-30 nm, preferably 10-30 nm.
[0025] In some embodiments, in step S1.3, the CuInP2S6 sheet can be transferred to a clean silicon substrate by attaching tape with the CuInP2S6 sheet to the clean silicon substrate, letting it stand, and then peeling off the tape.
[0026] In some implementations, the appropriate thickness in step S1.3 can be in the range of 10-30 nm. Excessive thickness: (1) Effective separation of charge carriers is affected, and photoexcited electrons may take longer to move to the interface or recombine with holes before reaching the electrode; in particular, in a thicker CIPS (CuInP2S6) layer, charge carriers may recombine with other charge carriers during transport, resulting in decreased efficiency; (2) Increased interface defects. When the CIPS layer is too thick, the interface of the heterojunction may be affected by poor lattice matching and stress, resulting in increased interface defects.
[0027] In some embodiments, in step S1.4, the process of transferring the InSe sheet onto the polydimethylsiloxane PDMS film can be: attaching the polydimethylsiloxane PDMS film to an adhesive tape with the InSe sheet attached, allowing it to stand, and then peeling off the tape; preferably, the thickness of the PDMS film can be 500 μm.
[0028] It should be noted that the processing method and order of InSe and CuInP2S6 thin films cannot be changed. The main reason is that photogenerated carriers in photodetectors are mainly generated in InSe, and stacking CuInP2S6 on InSe will affect the photoelectric performance.
[0029] In some implementations, the nanoscale thickness in step S1.4 can range from 10 to 30 nm. An excessively thick InSe layer may lead to a decrease in light transmittance, which may hinder the propagation of light in the material, causing most of the light to be reflected or absorbed by the surface of the material.
[0030] It should be noted that the formation principle of heterojunctions mainly lies in the fact that when two different semiconductor materials come into contact, their band structures (such as the positions of the conduction band and valence band) interact to form a built-in electric field, which helps to separate electrons and holes. Among them, the formation of heterojunctions mainly depends on the following factors: (1) lattice matching: the interface quality of the heterojunction is directly related to the difference in lattice constants between the two materials; (2) work function matching: the difference in work function of the materials will affect their band alignment when they come into contact. In this invention, CIPS (CuInP2S6): InSe: c≈7.40. While there is a slight difference in lattice constants between the two, they are still compatible. The work function of CIPS is approximately 4.8-5.1 eV, with the specific value depending on the fabrication method and the state of the film. The work function of InSe is approximately 4.7-5.1 eV, which is close to that of CIPS. The work functions of CIPS and InSe are very close, indicating a good work function match. This means that their band alignment in a heterojunction is unlikely to cause significant band mismatch.
[0031] Furthermore, when CIPS and InSe form a heterojunction, the band alignment creates a built-in electric field at their interface, effectively separating photogenerated electrons and holes, thus improving photoresponse efficiency. Moreover, the band alignment between CIPS and InSe can alter the band gap of InSe. For example, if InSe and CIPS form a Type II heterojunction (i.e., the conduction and valence bands are in different positions), this alignment can cause bending of the InSe's conduction or valence bands, affecting its light absorption characteristics and band gap. Additionally, InSe monolayer or thin film materials often have defects at the interface, which can induce carrier recombination, reducing photoresponse efficiency. Combining with CIPS can alleviate these interface defects, thereby improving the efficient collection of photogenerated carriers.
[0032] In some embodiments, in step S1, the ratio of the number of InSe wafers to the number of CuInP2S6 wafers in the InSe / CuInP2S6 heterojunction-silicon substrate composite structure can be 1:2.
[0033] It should be noted that the InSe / CuInP2S6 heterojunction used in this invention has the following advantages compared with the conventional black phosphorus (BP)-InSe heterojunction: (1) Band gap: CIPS is a wide band gap (~1.5eV), while the band gap of InSe is about 1.3-1.4eV. The difference between the band gaps of CIPS and InSe is small, making it suitable for forming direct or indirect band gap heterojunctions; the band gap of black phosphorus depends on the number of layers (from 1.5eV for a single layer to 0.3eV for bulk materials), while CIPS does not require strict control of the number of layers to regulate the photoelectric performance of the heterojunction; (2) Crystal matching: The crystal structures of CIPS and InSe are relatively similar, with weak interlayer interactions and better interface matching, which reduces interface defects; the crystal structure difference between black phosphorus and InSe is large (black phosphorus is an anisotropic material, while InSe is a non-isotropic material). (3) Built-in electric field: Due to the large difference in work function between CIPS and InSe, the interface may generate a strong built-in electric field, which helps electron-hole separation and thus improves photoelectric conversion efficiency; the work function difference between BP and InSe is small, and the built-in electric field of the interface may be weak; (4) Difference in application scenarios: CIPS-InSe heterojunction is suitable for photodetectors, solar cells and other devices that require high stability and near-infrared response; BP-InSe heterojunction is suitable for wide-band photodetectors, mid-infrared laser detectors and devices that require response to long-wavelength light; (5) Interface stability: CIPS has strong stability in air, while BP has low stability and requires a protective layer such as Al2O3. A strict vacuum environment is required during the material transfer process, which has certain requirements for operating conditions.
[0034] In some embodiments, in step S2.1, the spin coating of PMMA on the silicon substrate can be performed on a spin coater and then dried after spin coating; preferably, the spin coater speed can be 6000 rpm, the spin coating time can be 60 seconds, the drying time can be 900 seconds, and the drying temperature can be 90°C.
[0035] In some embodiments, in step S2.3, the developing time can be 50-70 seconds, preferably 60 seconds; the fixing time can be 20-50 seconds, preferably 25-35 seconds, more preferably 30 seconds. Excessive developing time leads to overdevelopment, pattern loss, increased roughness, and possible over-etching; insufficient developing time leads to incomplete development, residual resist, and blurred patterns. Excessive fixing time leads to resist hardening, pattern distortion, and increased surface roughness; insufficient fixing time may result in unstable patterns, resist detachment, or dissolution.
[0036] In some embodiments, in step S2.4, the vacuum degree of the thermal evaporation vacuum coating instrument can be 5 × 10⁻⁶. - 6 The thickness of the titanium layer can be 5-10 nm, preferably 10 nm; the deposition rate can be below [torr]. (angstroms per second), preferably The thickness of the gold layer can be 30-60 nm, preferably 50 nm; the evaporation rate can be The preferred deposition rate for a 10nm thick gold layer is: The rate of the 40nm thick gold layer is The vapor-deposited titanium layer can serve as an adhesion layer to increase the adhesion between the gold layer and the silicon wafer, preventing the gold layer from peeling off.
[0037] An excessively thick titanium layer will reduce the conductivity of the device, while an excessively thin layer will prevent the gold layer from adsorbing. An excessively thin gold layer will cause the probe to puncture the electrode during subsequent photoelectric performance testing, while an excessively thick gold layer will increase the device fabrication time and material loss.
[0038] In some embodiments, the soaking and peeling operation in step S2.5 can take 100-120 minutes, preferably 120 minutes.
[0039] The two-dimensional optoelectronic device of InSe and CuInP2S6 prepared by the method provided by the present invention exhibits good photoelectric response in the range of 405nm to 900nm, which is larger than that of optoelectronic devices made of InSe alone. In addition, compared with optoelectronic devices prepared with InSe, the device has a high photoresponsivity, which can reach 14.4A / W, and a short photoresponse time, which can reach 51.16ms.
[0040] The following examples further illustrate the present invention in detail. It should also be understood that the following examples are only for further explanation of the present invention and should not be construed as limiting the scope of protection of the present invention. Any non-essential improvements and adjustments made by those skilled in the art based on the above description of the present invention are within the scope of protection of the present invention. The specific process parameters, etc., in the following examples are merely examples within a suitable range; that is, those skilled in the art can make appropriate selections within the range based on the description herein, and are not intended to be limited to the specific values in the examples below. Unless otherwise specified, the technical means used in the examples are conventional means well known to those skilled in the art.
[0041] Example 1
[0042] The fabrication method of the InSe and CuInP2S6 two-dimensional optoelectronic device provided in this embodiment includes the following steps: Step S1: Fabrication of the InSe / CuInP2S6 heterojunction-silicon substrate composite structure: Step S1.1: Pour an appropriate amount of acetone into a clean beaker and place the silicon substrate in it. Place the beaker in an ultrasonic cleaner and clean the silicon substrate with ultrasonic cleaning for 20 minutes. Then, clean the silicon substrate in anhydrous ethanol for 10 minutes, and finally clean it with deionized water for 10 minutes. The silicon substrate consists of heavily doped P-type polycrystalline silicon and a 300nm silicon oxide layer, with a total thickness of 500um. After cleaning, dry it at 90℃ for 30 minutes. Step S1.2: Place the prepared InSe and CuInP2S6 samples on the peeling tape, fold them in half 4 times, and obtain InSe and CuInP2S6 flakes on the tape. Obtain InSe and CuInP2S6 flakes with smooth dissociation surfaces and a thickness of 10-20nm at the tape adhesion point. Cut out this area for later use. Step S1.3: Adhesive tape with CuInP2S6 flakes is attached to the cleaned silicon substrate. After standing for half an hour, the tape is removed, leaving CuInP2S6 flakes on the silicon substrate. Under a microscope, transparent CuInP2S6 flakes with a thickness of 20-30nm are selected to obtain a clean silicon substrate with CuInP2S6 flakes attached. Step S1.4: Cut a 500μm thick polydimethylsiloxane (PDMS) film of appropriate size with double-sided adhesive. Attach one side of the film to a glass slide and the other side to an adhesive tape with InSe flakes. After standing for a period of time, peel off the tape. InSe flakes remain on the PDMS film. Place the InSe flakes / PDMS / glass slide under an optical microscope to find two-dimensional material flakes. The contrast can be used to determine the thickness of the InSe sample. Transparent samples are thinner InSe samples, while thicker samples are silvery and reflective. Select InSe flakes with a thickness of 10-20nm to obtain a PDMS film with InSe flakes attached. Step S1.5: The silicon substrate selected in step S1.3 is placed on the sample stage of the two-dimensional material transfer platform and fixed. The PDMS film with InSe flakes prepared in step S1.4 is placed on the sample end to be transferred and fixed. The InSe flakes on the PDMS film are transferred to the CuInP2S6 flakes using the two-dimensional material transfer platform and bonded to them to form a heterojunction. The structure of the two-dimensional material transfer platform is as follows: Figure 1 As shown, the system consists of three parts: 1 is a robotic arm that can be controlled by software to move in three dimensions; 2 is an optical microscope; 4 is a sample stage, where the silicon wafer with CuInP2S6 thin film attached in step S1.5 is placed on the sample stage; and 3 is a glass slide with InSe thin film attached. First, the position of the InSe thin film is located using an optical microscope. Then, the focus of the lens is raised until PMDS can be clearly observed. The glass slide is moved until the InSe thin film is moved to the center of the lens. The glass slide is then slowly lowered to make the InSe thin film and CuInP2S6 thin film adhere together. After standing for a period of time, the glass slide is raised to observe whether a heterojunction is formed, thus obtaining the InSe / CuInP2S6 heterojunction-silicon substrate composite structure. Step S2, Metal Electrode Preparation: Step S2.1: The silicon substrate with the InSe / CuInP2S6 heterojunction-silicon substrate composite structure is adsorbed on a spin coater, polymethyl methacrylate (PMMA) is uniformly spin-coated and dried. The spin coater speed is set to 6000 rpm, the spin coating time is 60 seconds, the drying time is 900 seconds, and the drying temperature is 90℃. Step S2.2: Place the spin-coated PMMA silicon substrate into the electron beam cavity of the electron beam exposure system, import the electrode design drawing into the electron beam exposure system, and perform an exposure operation by bombarding the corresponding spin-coated PMMA silicon substrate with an electron beam according to the design drawing to obtain the exposed pattern; at the same time, use CAD software to draw the electrode shape according to the shape of the heterojunction. Step S2.3: Place the silicon substrate in the developing solution for development to remove PMMA from the exposed areas of the silicon substrate and expose the bottom silicon substrate; then transfer the silicon substrate to isopropanol to stop development and complete the fixing operation; blow dry the fixed silicon substrate; the development time is 60s and the fixing time is 30s. Step S2.4: Place the dried silicon substrate into the cavity of the thermal evaporation vacuum coating machine, and evacuate the cavity to 5×10⁻⁶. -6 Below torr, first, titanium metal is deposited as an adhesion layer, and then gold is deposited; the rate of titanium metal deposition is... The rate of gold deposition with a thickness of 10 nm before evaporation is: The rate of the last 40nm is The thickness of the titanium vapor deposition is 10 nm, and the thickness of the gold vapor deposition is 50 nm. Step S2.5: Immerse the vapor-deposited silicon substrate in acetone for 120 minutes, peel off the metal part that is in contact with the unexposed PMMA, and the remaining metal in contact with the silicon substrate is the metal electrode that has been prepared. Finally, the two-dimensional optoelectronic device consisting of InSe and CuInP2S6 was obtained.
[0043] The device fabricated in this embodiment is shown in Figure 2 In the middle, the morphology of the nanosheets of the heterostructure is shown Figure 3 In this configuration, metal electrode A, deposited alone on the InSe wafer, serves as the drain, while metal electrode B, deposited on the InSe and CuInP2S6 heterojunction, acts as the source. Heavily doped silicon serves as the gate, and the gate voltage direction is changed by altering the voltage direction within the heavily doped silicon wafer.
[0044] The device fabricated in this embodiment exhibits performance in the following aspects: Figure 4 and Figure 5 The text appears to be a mix of Chinese characters and symbols, possibly representing a corrupted or incomplete translation. A direct translation wouldn't be Figure 4 Output curves of the device with gate voltage maintained at 0.1V under 405nm laser irradiation of different powers; Figure 5 The image shows the photoresponse current curves of the device under laser irradiation with a switching cycle of 20 seconds and 10 seconds. From... Figure 4 As can be seen, the output current increases steadily with increasing laser power, indicating that the device can operate in the near-infrared band; from Figure 5 As can be seen, the device exhibits stable and repeatable photoelectric switching characteristics.
[0045] Comparative Example 1
[0046] The method for fabricating the optoelectronic device provided in this embodiment is the same as in Embodiment 1, with the main difference being that the thickness of the CuInP2S6 thin film is 40-50 nm.
[0047] Figure 6 The image shows an optical mirror image of the optoelectronic device fabricated in Comparative Example 1. Figure 7 The output curves of the optoelectronic device prepared in Comparative Example 1 under 405nm laser irradiation at different powers with the gate voltage maintained at 0.1V are shown in the figure. It can be seen from the figure that the dark current intensity increases compared to the example, while the photocurrent intensity decreases. It can be considered that the thicker CuInP2S6 sheet leads to a decrease in the photoresponsivity of the device.
[0048] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.
Claims
1. A method for fabricating a two-dimensional optoelectronic device using InSe and CuInP2S6, characterized in that, The preparation method includes the following steps: Step S1: Fabrication of the InSe / CuInP2S6 heterojunction-silicon substrate composite structure: Step S1.1: Clean and dry the silicon substrate to obtain a clean silicon substrate; Step S1.2: Place the InSe and CuInP2S6 samples on the peeling tape and fold them in half multiple times for mechanical peeling. At the adhesive points of the tape, obtain InSe and CuInP2S6 flakes with smooth dissociation surfaces and relatively small thickness. Step S1.3: Transfer the CuInP2S6 sheet to the clean silicon substrate and select CuInP2S6 sheets of appropriate thickness to obtain a clean silicon substrate with CuInP2S6 sheets bonded together. Step S1.4: Transfer the InSe flakes onto a polydimethylsiloxane PDMS film and screen for InSe flakes with nanoscale thickness to obtain a PDMS film with InSe flakes bonded together. Step S1.5: Place the clean silicon substrate with CuInP2S6 film bonded in step S1.3 onto the sample stage of the two-dimensional material transfer platform and fix it. Place the PDMS film with InSe film bonded in step S1.4 onto the sample end to be transferred and fix it. Use the two-dimensional material transfer platform to transfer the InSe film on the PDMS film onto the CuInP2S6 film and attach it to it to form a heterojunction, thus obtaining the InSe / CuInP2S6 heterojunction-silicon substrate composite structure. Step S2, Metal Electrode Preparation: Step S2.1: Spin-coat PMMA onto the silicon substrate of the InSe / CuInP2S6 heterojunction-silicon substrate composite structure to obtain a silicon substrate with spin-coated PMMA. Step S2.2: Place the spin-coated PMMA silicon substrate in the electron beam cavity of the electron beam exposure system, import the electrode design drawing into the electron beam exposure system, and perform an exposure operation by bombarding the corresponding spin-coated PMMA silicon substrate with an electron beam according to the design drawing to obtain the exposed pattern. At the same time, use CAD software to draw the electrode shape according to the shape of the heterojunction. Step S2.3: Place the exposed silicon substrate in the developer solution for development to remove the PMMA from the exposed area of the silicon substrate and expose the bottom silicon substrate. Then, transfer it to isopropanol to stop development and complete the fixing operation. Step S2.4: Place the fixed silicon substrate in a thermal evaporation vacuum coating machine and deposit a titanium layer and a gold layer in sequence. Step S2.5: Immerse the evaporated silicon substrate in acetone to remove the metal portion in contact with the unexposed PMMA. The remaining metal in contact with the silicon substrate is the metal electrode. Finally, the two-dimensional optoelectronic device consisting of InSe and CuInP2S6 was obtained.
2. The preparation method according to claim 1, characterized in that, In step S1.1, the silicon substrate includes heavily doped P-type polycrystalline silicon and a silicon oxide layer on top of it; preferably, the total thickness of the silicon substrate is 500±10um and the thickness of the silicon oxide layer is 50-300nm.
3. The preparation method according to claim 1 or 2, characterized in that, In step S1.2, the number of folds is 3-5.
4. The preparation method according to any one of claims 1-3, characterized in that, In step S1.3, the appropriate thickness ranges from 10 to 30 nm.
5. The preparation method according to any one of claims 1-4, characterized in that, In step S1.4, the nanoscale thickness ranges from 10 to 30 nm.
6. The preparation method according to any one of claims 1-5, characterized in that, In step S1, the ratio of the number of InSe wafers to the number of CuInP2S6 wafers in the InSe / CuInP2S6 heterojunction-silicon substrate composite structure is 1:
2.
7. The preparation method according to any one of claims 1-6, characterized in that, In step S2.1, the PMMA is spin-coated onto the silicon substrate on a spin coater and then dried. Preferably, the spin coater speed is 6000 rpm, the spin coating time is 60 seconds, the drying time is 900 seconds, and the drying temperature is 90°C.
8. The preparation method according to any one of claims 1-7, characterized in that, In step S2.3, the developing time is 50-70s, preferably 60s; the fixing time is 20-50s, preferably 25-35s, and more preferably 30s.
9. The preparation method according to any one of claims 1-8, characterized in that, In step S2.4, the vacuum degree of the thermal evaporation vacuum coating instrument is 5×10⁻⁶. -6 below torr; The thickness of the titanium layer is 5-10 nm, preferably 10 nm; the deposition rate is... Preferred The thickness of the gold layer is 30-60 nm, preferably 50 nm; the evaporation rate is... The preferred deposition rate for a 10nm thick gold layer is: The rate of the 40nm thick gold layer is 10. The preparation method according to any one of claims 1-9, characterized in that, In step S2.5, the soaking and peeling operation time is 100-120 min, preferably 120 min.