A diode measurement structure, a diode measurement method and an integrated circuit

Abstract

The application discloses a diode measurement structure, a measurement method and an integrated circuit, and belongs to the technical field of semiconductors. The measurement structure comprises at least three sub-measurement structures, and each sub-measurement structure comprises: a first-type well arranged in a substrate; a second-type doped region arranged in the first-type well, the second-type doped region and the first-type well forming a diode structure; a first-type doped region arranged in the first-type well; a first connecting structure connected with the first-type doped region; and a second connecting structure connected with the second-type doped region; wherein the first-type well, the first-type doped region, the first connecting structure and the second connecting structure in each sub-measurement structure are the same, and the perimeters of the second-type doped regions in each sub-measurement structure are equal but the areas are different. The diode measurement structure, the measurement method and the integrated circuit provided by the application can improve the accuracy of diode modeling.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a diode measurement structure, measurement method, and integrated circuit. Background Technology

[0002] In semiconductor device manufacturing, the accurate construction of semiconductor device models is a core prerequisite for ensuring the reliability of circuit design, and the accuracy of model parameters directly depends on the authenticity of measurement data. However, in diode measurement, the interference of parasitic resistance cannot be effectively eliminated, thus making it impossible to obtain a high-precision diode model.

[0003] On the one hand, parasitic resistance originates from the layout and wiring, such as the inherent resistance of metal wires, solder joint contact resistance, and distributed resistance caused by the wiring topology. On the other hand, parasitic resistance originates from the diode measurement structure itself, such as probe impedance and signal transmission link resistance. When measuring diodes, the interference of parasitic resistance cannot be eliminated, resulting in the inclusion of parasitic resistance in the measured diode-related data, affecting the accuracy and practicality of the diode model. Summary of the Invention

[0004] The purpose of this invention is to provide a diode measurement structure, measurement method, and integrated circuit that can obtain the value of parasitic resistance, thereby solving the problem that parasitic resistance affects the accuracy of diode measurement data.

[0005] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution: This invention provides a diode measurement structure, the measurement structure comprising at least three sub-measurement structures, and each of the sub-measurement structures comprising: The first type of well is disposed in the substrate; A second type of doped region is disposed in the first type of well, and the second type of doped region and the first type of well form a diode structure; A first type of doped region is disposed in a first type of well; A first connection structure is connected to the first type of doped region; and A second connection structure is connected to the second type of doped region; In each of the sub-measurement structures, the first type of well, the first type of doped region, the first connection structure, and the second connection structure are the same, and the perimeter of the second type of doped region in each of the sub-measurement structures is equal but the area is different.

[0006] In one embodiment of the present invention, the depth of the second type of doped region is the same in each of the sub-measurement structures.

[0007] In one embodiment of the present invention, the measurement structure includes a first sub-measurement structure, a second sub-measurement structure, and a third sub-measurement structure, wherein the second type of doped region in the first sub-measurement structure, the second sub-measurement structure, and the third sub-measurement structure is rectangular.

[0008] In one embodiment of the present invention, the first type of doped region is arranged in a ring shape, and the first type of doped region surrounds the second type of doped region.

[0009] In one embodiment of the present invention, the first connection structure includes a first contact hole and a first metal layer, one end of the first contact hole is connected to a first type of doped region, the other end of the first contact hole is connected to one end of the first metal layer, and the other end of the first metal layer is connected to an external pad; the second connection structure includes a second contact hole and a second metal layer, one end of the second contact hole is connected to a second type of doped region, the other end of the second contact hole is connected to one end of the second metal layer, and the other end of the second metal layer is connected to another external pad.

[0010] The present invention also provides a method for measuring a diode, using the diode measurement structure described in any of the above claims, and the diode measurement method includes: A test current is input to each of the sub-measurement structures to obtain the measurement voltages across at least three of the sub-measurement structures. The relationship between the measurement voltages, test currents, diffusion region resistances, parasitic resistances, and diode structure voltages of at least three of the sub-measurement structures is obtained, and the parasitic resistances and test currents are the same in each of the sub-measurement structures. Based on the relationship between the diffusion region resistance and the depth and area of ​​the first type of doped region in the diode structure, the proportional relationship between the diffusion region resistance in the two sub-measurement structures is obtained; Based on the relationship between the diode structure current, the diode structure voltage, and the area of ​​the first type of doped region, the proportional relationship of the diode structure voltage in the two sub-measurement structures is obtained; and Based on at least three sets of measured voltages and test currents, and in conjunction with the relationship between the measured voltage, test current, diffusion region resistance, parasitic resistance, and diode structure voltage in each of the sub-measurement structures, the proportional relationship between the diffusion region resistances in two of the sub-measurement structures, and the proportional relationship between the diode structure voltages in two of the sub-measurement structures, the value of the parasitic resistance in each of the sub-measurement structures is obtained.

[0011] In one embodiment of the present invention, the relationship between the measurement voltage, test current, diffusion region resistance, parasitic resistance, and diode structure voltage of at least three of the sub-measurement structures is obtained by the following formula: U1=I(R D1+ R p)+U D1 ; U2=I(R D2+ R p )+U D2 ; U3=I(R D3+ R p )+U D3 ; Where U1 is the measurement voltage across the first sub-measuring structure, I is the input test current, and R... D1 R is the resistance of the diffusion region in the first sub-measuring structure. p For the equivalent parasitic resistance, U D1 U1 is the diode structure voltage in the first sub-measurement structure, U2 is the measurement voltage across the second sub-measurement structure, and R is the diode structure voltage. D2 U is the resistance of the diffusion region in the second sub-measuring structure. D2 U3 is the diode structure voltage in the second sub-measurement structure, and U4 is the measurement voltage across the third sub-measurement structure. D3 U is the resistance of the diffusion region in the third sub-measuring structure. D3 The diode structure voltage in the third sub-measuring structure.

[0012] In one embodiment of the present invention, the proportional relationship between the diffusion region resistances in the two sub-measuring structures is obtained by the following formula: R D1 / R D2 =A2 / A1; R D1 / R D3 =A3 / A1; R D2 / R D3 =A3 / A2; Among them, R D1 R is the resistance of the diffusion region in the first sub-measuring structure. D2 R is the resistance of the diffusion region in the second sub-measuring structure. D3 A1 is the area of ​​the second type of doped region in the first sub-measurement structure, A2 is the area of ​​the second type of doped region in the second sub-measurement structure, and A3 is the area of ​​the second type of doped region in the third sub-measurement structure.

[0013] In one embodiment of the present invention, the proportional relationship between the diode structure voltages in the two sub-measuring structures is obtained by the following formula: U D1 / U D2 =1+ln(A2 / A1)kT / q; U D1 / UD3 =1+ln(A3 / A1)kT / q; U D2 / U D3 =1+ln(A3 / A2)kT / q; Among them, U D1 For the diode structure voltage in the first sub-measuring structure, U D2 For the diode structure voltage in the second sub-measuring structure, U D3 A1 is the diode structure voltage in the third sub-measurement structure; A2 is the area of ​​the second type doped region in the first sub-measurement structure; A3 is the area of ​​the second type doped region in the second sub-measurement structure; q is the electron charge; k is the Boltzmann constant; and T is the absolute temperature.

[0014] The present invention also provides an integrated circuit including a measurement structure of a diode as described in any of the above claims.

[0015] In summary, the method for fabricating a diode measurement structure provided by this invention has the following unexpected advantages: At least three sub-measurement structures are set in the diode measurement structure, and the first type of well, the first type of doped region, the first connection structure, and the second connection structure are identical in each sub-measurement structure, ensuring that the parasitic resistance value is the same in each sub-measurement structure. The perimeter of the second type of doped region in each sub-measurement structure is equal but the area is different, ensuring that the diffusion region resistance in each sub-measurement structure is only related to the area, thereby obtaining the proportional relationship of the diffusion region resistance in two sub-measurement structures. The same test current is input to each sub-measurement structure, ensuring that the diode structure voltage in each sub-measurement structure is only related to the area, thereby obtaining the proportional relationship of the diode structure voltage in two sub-measurements. Finally, the values ​​of the parasitic resistance in the sub-measurement structures are obtained by combining at least three sets of measurement voltages and test currents, thereby obtaining a more accurate diode model.

[0016] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a top view of the diode measurement structure in one embodiment of this application.

[0019] Figure 2for Figure 1 A cross-sectional view of the diode's measurement structure at point A-A'.

[0020] Figure 3 This is a flowchart of a diode measurement method in one embodiment of this application.

[0021] Figure 4 This is an equivalent circuit diagram of the first sub-measurement structure in the diode measurement structure of one embodiment of this application.

[0022] Figure 5 This is an equivalent circuit diagram of the second sub-measurement structure in the diode measurement structure of one embodiment of this application.

[0023] Figure 6 This is an equivalent circuit diagram of the third sub-measurement structure in the diode measurement structure of one embodiment of this application.

[0024] Label Explanation: 11. First sub-measurement structure; 12. Second sub-measurement structure; 13. Third sub-measurement structure; 100. Substrate; 101. First type well; 102. Second type doped region; 103. First type doped region; 1041. First contact hole; 1042. Second contact hole; 1051. First metal layer; 1052. Second metal layer; 106. Interlayer dielectric layer; 107. Dielectric layer. Detailed Implementation

[0025] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0026] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0027] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0028] In semiconductor integrated circuits, multiple semiconductor devices are integrated onto a single silicon wafer. These semiconductor devices can include common control transistors such as transistors or thyristors, common diodes used in circuits, or specialized devices for specific applications such as photodiodes or field-effect transistors. After forming multiple semiconductor devices on the silicon wafer, a metal interconnect layer needs to be formed on top of them. This metal interconnect layer includes a dielectric layer and multiple metal layers within the dielectric layer. The dielectric layer prevents signal crosstalk between adjacent metal layers, and adjacent metal layers are connected via vias, electrically linking each semiconductor device according to the designed circuit.

[0029] Please see Figures 1 to 6 As shown, this application provides a diode measurement structure and measurement method. The diode measurement structure can be disposed, for example, in a dicing channel or in a semiconductor device region near the dicing channel. The measurement structure provided in this application includes at least three sub-measurement structures, each sub-measurement structure including a diode structure and a connection structure between the diode structure and an external pad. In each sub-measurement structure, the perimeter of the doped region of the diode structure is equal, but the area is different. When using this diode measurement structure for measurement, under the same test current, the measurement voltages of at least three sub-measurement structures are obtained. The magnitude of the parasitic resistance is obtained by combining the relationship between the measurement voltage, test current, diffusion region resistance, parasitic resistance, and diode structure voltage; the relationship between the diffusion region resistance and the diode structure; and the relationship between the diode structure current, diode voltage, and the diode structure.

[0030] Please see Figure 1 As shown, in one embodiment of the present invention, the diode measurement structure includes three sub-measurement structures: a first sub-measurement structure 11, a second sub-measurement structure 12, and a third sub-measurement structure 13. In other embodiments, in addition to the first sub-measurement structure 11, the second sub-measurement structure 12, and the third sub-measurement structure 13, the diode measurement structure may also include a fourth sub-measurement structure and a fifth sub-measurement structure, etc.

[0031] Please see Figure 1 and Figure 2As shown, in one embodiment of the present invention, each sub-measurement structure includes a first type well 101, a second type doped region 102, a first type doped region 103, a first connection structure, and a second connection structure. The first type well 101 is disposed in the substrate 100, and the second type doped region 102 is disposed in the first type well 101, forming a diode structure with the second type doped region 102 and the first type well 101. The first type doped region 103 is disposed in the first type well 101, connecting the first type well 101 to the connection structure, thus forming an ohmic contact between the first type well 101 and the connection structure. The first connection structure connects the first type doped region 103 to an external pad, and the second connection structure connects the second type doped region 102 to an external pad.

[0032] It is important to note that you should combine this with... Figure 1 and Figure 2 As shown, the first type well 101, first type doped region 103, first connection structure, and second connection structure in each sub-measurement structure are configured identically to the first type well 101, first type doped region 103, first connection structure, and second connection structure in the diode within the semiconductor device region. The second type doped region 102 in each sub-measurement structure is configured identically to the second type doped region 102 in the diode within the semiconductor device region, except for its area. Alternatively, the diode and its connection structure within the semiconductor device can be directly used as a sub-measurement structure in this application.

[0033] Please see Figure 1 and Figure 2 As shown, in this application, the number of first-type wells 101 is set according to the number of sub-measurement structures in the diode's measurement structure. In one embodiment of the present invention, three first-type wells 101 are provided on the substrate 100, and the three first-type wells 101 belong to the first sub-measurement structure 11, the second sub-measurement structure 12, and the third sub-measurement structure 13, respectively. The three first-type wells 101 can be arranged side by side or adjacent to each other.

[0034] Please see Figure 1 and Figure 2As shown, this application does not limit the specific doping type of the first type well 101; that is, the first type well 101 can be an N-type well or a P-type well. In one embodiment of the present invention, the first type well 101 is described as an N-type well. Specifically, a silicon substrate such as single-crystal silicon is first selected as the substrate 100 material, a patterned photoresist layer is formed on the surface of the substrate 100 to define the first type well region, and N-type impurities such as phosphorus (P) or arsenic (As) are implanted in the first type well region. Then, the impurities are activated by high-temperature annealing of the ion implantation region to form an N-type well as the first type well 101. In this application, the first type well 101 structures in the first sub-measurement structure 11, the second sub-measurement structure 12, and the third sub-measurement structure 13 are the same and have the same ion doping concentration.

[0035] Please see Figure 1 and Figure 2 As shown, in this application, a second-type doped region 102 is provided within the first-type well 101 in each sub-measurement structure. This application does not limit the specific doping type of the second-type doped region 102; that is, the second-type doped region 102 can be a P-type doped region or an N-type doped region, as long as the doping type of the second-type doped region 102 is opposite to the doping type of the first-type well 101. In one embodiment of the present invention, the second-type doped region 102 is described as a P-type doped region. Specifically, after forming the first-type well 101, a patterned photoresist layer is formed on the surface of the substrate 100 to define the second-type doped region. P-type impurities such as boron (B) are implanted into the second-type doped region, and then the ion implantation region is subjected to high-temperature annealing to activate the impurities, forming a P-type doped region as the second-type doped region 102. The ion doping concentrations of the multiple second-type doped regions 102 in the multiple first-type wells 101 are the same, and the ion doping concentration in the second-type doped region 102 is greater than the ion doping concentration in the first-type well 101. The depths of the multiple second-type doped regions 102 in the multiple first-type wells 101 are the same, and the depths of the second-type doped regions 102 are less than the depths of the first-type wells 101.

[0036] Please see Figure 1 and Figure 2As shown, in this application, the first type well 101 and the second type doped region 102 are respectively an N-type doped region and a P-type doped region. The N-type doped region contains a large number of free electrons, and the P-type doped region contains a large number of holes. When the second type doped region 102 is set in the first type well 101, the diffused electrons and holes recombine at the interface between the first type well 101 and the second type doped region 102, leaving positive ions in the N-type doped region and negative ions in the P-type doped region, forming a depletion region without charge carriers. The positive and negative ions in the depletion region generate a built-in electric field, pointing from the N-type doped region to the P-type doped region, which hinders the continued diffusion of charge carriers. Eventually, diffusion and drift reach equilibrium, and a stable PN junction is formed at the interface between the first type well 101 and the second type doped region 102. The unidirectional conductivity of the PN junction forms a diode structure.

[0037] Please see Figure 1 and Figure 2 As shown, in this application, the first type well 101 in each sub-measurement structure has the same shape, and the second type doped region 102 in each sub-measurement structure has the same perimeter but different areas. Furthermore, this application does not limit the specific shapes of the first type well 101 and the second type doped region 102; they can be rectangular, polygonal, circular, elliptical, or irregular shapes, etc. In one embodiment of the invention, the shapes of the first type well 101 and the second type doped region 102 are, for example, rectangular. In the first sub-measurement structure 11, the length L1 of the second type doped region 102 is, for example, 10 μm, and the width W1 is, for example, 10 μm. Therefore, the perimeter of the second type doped region 102 in the first sub-measurement structure 11 is 40 μm, and the area is 100 μm. 2 In the second sub-measurement structure 12, the length L2 of the second type doped region 102 is, for example, 15 μm, and the width W2 is, for example, 5 μm. Therefore, the perimeter of the second type doped region 102 in the second sub-measurement structure 12 is 40 μm, and the area is 75 μm. 2 In the third sub-measurement structure 13, the length L3 of the second-type doped region 102 is, for example, 16 μm, and the width W3 is, for example, 4 μm. Therefore, the perimeter of the second-type doped region 102 in the third sub-measurement structure 13 is 40 μm, and the area is 64 μm. 2 .

[0038] Please see Figure 1 and Figure 2As shown, in this application, a first-type doped region 103 is provided within the first-type well 101 in each sub-measurement structure. This application does not limit the specific doping type of the first-type doped region 103; that is, the first-type doped region 103 can be an N-type doped region or a P-type doped region, as long as the doping type of the first-type doped region 103 is the same as the doping type of the first-type well 101. In one embodiment of the present invention, the first-type doped region 103 is described as an N-type doped region. Specifically, after forming the second-type doped region 102, a patterned photoresist layer is formed on the surface of the substrate 100 to define the first-type doped region. N-type impurities such as phosphorus (P) or arsenic (As) are implanted into the first-type doped region. Then, the ion implantation region is subjected to high-temperature annealing to activate the impurities, forming an N-type doped region as the first-type doped region 103. The ion doping concentration of the multiple first-type doped regions 103 in the multiple first-type wells 101 is the same. Furthermore, the ion doping concentration in the first-type doped region 103 is greater than the ion doping concentration in the first-type well 101. Furthermore, the ion doping concentration in the first type doped region 103 can be equal to the ion doping concentration in the second type doped region 102. In this case, the first type doped region 103 can form an ohmic contact with the subsequently formed connection structure, ensuring the input of the test current. The multiple first type doped regions 103 in the multiple first type wells 101 have the same depth, and the depth of the first type doped region 103 is less than the depth of the first type well 101, but equal to the depth of the second type doped region 102.

[0039] Please see Figure 1 and Figure 2 As shown in this application, the first type doped region 103 in each sub-measurement structure has the same shape, but this application does not limit the specific shape of the first type doped region 103, which can be annular, semi-annular, rectangular, polygonal, circular, elliptical, or irregular in shape, etc. In one embodiment of the present invention, the first type doped region 103 is arranged in annular shape, and the annular first type doped region 103 surrounds the second type doped region 102, which can enhance the contact between the first type doped region 103 and the first type well 101.

[0040] Please see Figure 1 and Figure 2As shown, in one embodiment of the present invention, each sub-measurement structure is provided with a first connection structure and a second connection structure. One end of the first connection structure is connected to a first type doped region 103, and the other end is connected to an external pad. One end of the second connection structure is connected to a second type doped region 102, and the other end is connected to another external pad. Specifically, the first and second connection structures include contact holes and metal layers. The contact holes are disposed in an inter-layer dielectric (ILD) 106 on the semiconductor device, connecting the semiconductor device formed on the substrate 100 and the metal layer in the metal interconnect layer. The metal layer is disposed in a dielectric layer 107, connecting the contact holes to the external pads. Through the contact holes and the metal layer, the semiconductor devices formed on the substrate 100 can be connected according to the designed circuit, and the semiconductor devices can be connected to the external pads.

[0041] Please see Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the first connection structure includes a first contact hole 1041 and a first metal layer 1051. One end of the first contact hole 1041 is connected to a first type doped region 103, and the other end is connected to one end of the first metal layer 1051. The other end of the first metal layer 1051 is connected to an external pad. The second connection structure includes a second contact hole 1042 and a second metal layer 1052. One end of the second contact hole 1042 is connected to a second type doped region 102, and the other end is connected to one end of the second metal layer 1052. The other end of the second metal layer 1052 is connected to another external pad. Electrical signals can be input to the sub-measurement structure through the two external pads. The first contact hole 1041 and the second contact hole 1042 pass through the interlayer dielectric layer 106, connecting the doped region and the metal layer. The first metal layer 1051 and the second metal layer 1052 are disposed in the dielectric layer 107.

[0042] Please see Figure 3 As shown, the present invention also provides a method for measuring a diode, which uses the diode measurement structure described above, and the diode measurement method includes steps S101 to S104.

[0043] Step S101: Input a test current into each sub-measurement structure, obtain the measurement voltage across at least three sub-measurement structures, and obtain the relationship between the measurement voltage, test current, diffusion region resistance, parasitic resistance, and diode structure voltage of at least three sub-measurement structures.

[0044] Please combine Figure 1 and Figure 6As shown, in one embodiment of the present invention, after forming the diode measurement structure, a test current is input to each sub-measurement structure. Specifically, the test current can be input from an external pad connected to the first connection structure in each sub-measurement structure, and the test current can be output from an external pad connected to the second connection structure in each sub-measurement structure. The voltage between the two pads is measured, which is the measured voltage. At this time, the equivalent circuit diagram of the diode test structure is as follows. Figures 4 to 6 As shown. Among them, Figure 4 The equivalent circuit diagram of the first sub-measuring structure 11 is shown below. Figure 5 The equivalent circuit diagram for the second sub-measuring structure 12 is shown below. Figure 6 The equivalent circuit diagram for the third sub-measuring structure 13.

[0045] like Figure 4 As shown, in the first sub-measurement structure 11, U1 is the measurement voltage across the first sub-measurement structure 11, I1 is the test current input to the first sub-measurement structure 11, D1 is the diode structure in the first sub-measurement structure 11, and R... D1 For the first sub-measuring structure 11, the resistance of the diffusion region, R P1 The parasitic resistance in the first sub-measuring structure 11. For example... Figure 5 As shown, in the second sub-measurement structure 12, U2 is the measurement voltage across the second sub-measurement structure 12, I2 is the test current input to the second sub-measurement structure 12, D2 is the diode structure in the second sub-measurement structure 12, and R... D2 For the second sub-measuring structure 12, the diffusion region resistance, R P2 The parasitic resistance in the second sub-measuring structure 12 is measured. For example... Figure 6 As shown, in the third sub-measurement structure 13, U3 is the measurement voltage across the third sub-measurement structure 13, I3 is the test current input to the third sub-measurement structure 13, D3 is the diode structure in the third sub-measurement structure 13, and R... D3 For measuring the diffusion region resistance and R in the third sub-structure 13 P3 The parasitic resistance in the third sub-measuring structure 13 is measured.

[0046] Please see Figure 1 , Figure 4 , Figure 5 and Figure 6 As shown in this application, since the test current of each sub-measurement structure is the same as the input test current, the test current I1 input to the first sub-measurement structure 11, the test current I2 input to the second sub-measurement structure 12, and the test current I3 input to the third sub-measurement structure 13 are all equal to the input test current I. Since the first connection structure and the second connection structure in each sub-measurement structure are the same, and the external measurement structure is also the same, the parasitic resistance R in the first sub-measurement structure 11 is... P1Parasitic resistance R in the second sub-measuring structure 12 P2 Parasitic resistance R in the third sub-measuring structure 13 P3 They are equal, both equal to the equivalent parasitic resistance R. P Therefore, the relationship between the measurement voltage, test current, diffusion region resistance, parasitic resistance, and diode structure voltage in each sub-measurement structure can be obtained through the following formula: U1=I(R D1+ R p )+U D1 ; U2=I(R D2+ R p )+U D2 ; U3=I(R D3+ R p )+U D3 ; Where U1 is the measurement voltage across the first sub-measuring structure, I is the input test current, and R... D1 For the resistance of the diffusion region in the first substructure, R p For the equivalent parasitic resistance, U D1 U1 is the diode structure voltage in the first sub-measurement structure, U2 is the measurement voltage across the second sub-measurement structure, and R is the diode structure voltage. D2 For the resistance of the diffusion region in the second sub-measuring structure, U D2 U3 is the diode structure voltage in the second sub-measurement structure, and R is the measured voltage across the third sub-measurement structure. D3 For the diffusion region resistance in the third substructure, U D3 The diode structure voltage in the third sub-measurement structure.

[0047] Step S102: Based on the relationship between the diffusion region resistance and the depth and area of ​​the first type of doped region in the diode structure, obtain the proportional relationship of the diffusion region resistance in the two sub-measurement structures.

[0048] Specifically, the resistance of the diffusion region is obtained using the following formula: R D =pL / A; Among them, R D Let be the resistance of the diffusion region in the sub-measurement structure, p be the resistivity of the diffusion region, L be the depth of the diffusion region, i.e., the depth of the second type doped region in each sub-measurement structure, and A be the area of ​​the diffusion region, i.e., the area of ​​the second type doped region in each sub-measurement structure.

[0049] In this application, the materials and ion implantation concentrations of the well region and doped region are the same in each sub-measurement structure, so the resistivity p of the diffusion region is the same in each sub-measurement structure, and the depth L of each sub-measurement structure is the same. Therefore, the proportional relationship of the diffusion region resistance in the two sub-measurement structures is obtained by the following formula: R D1 / R D2 =A2 / A1; R D1 / R D3 =A3 / A1; R D2 / R D3 =A3 / A2; Among them, R D1 R is the resistance of the diffusion region in the first sub-measuring structure. D2 R is the resistance of the diffusion region in the second sub-measuring structure. D3 A1 is the area of ​​the second type of doped region in the first sub-measurement structure, A2 is the area of ​​the second type of doped region in the second sub-measurement structure, and A3 is the area of ​​the second type of doped region in the third sub-measurement structure.

[0050] Please combine Figure 1 As shown, in one embodiment of the present invention, when the area of ​​the second type doped region 102 in the first sub-measurement structure 11 is 100 μm 2 The area of ​​the second type doped region 102 in the second sub-measurement structure 12 is 75 μm. 2 The area of ​​the second type doped region 102 in the third sub-measurement structure 13 is 64 μm. 2 At that time, R D1 / R D2 =75 / 100; R D1 / R D3 =64 / 100; R D2 / R D3 =64 / 75.

[0051] Step S103: Based on the relationship between diode structure current, diode structure voltage and the area of ​​the first type of doped region, obtain the proportional relationship of diode structure voltage in the two sub-measurement structures.

[0052] In one embodiment of the present invention, the diode structure current is obtained by the following formula: I=I0(e qV / kT -1); Where I0 is the reverse saturation current, which is proportional to the area of ​​the second type doped region 102, q is the electron charge, k is the Boltzmann constant, T is the absolute temperature, and V is the diode structure voltage, i.e., V is the U in this application. DThe value of the electron charge q is 1.6 × 10⁻⁶. -19 C, the value of Boltzmann's constant k is 1.38 × 10 -23 J / K, absolute temperature T is taken as 300K at room temperature, so kT / q≈0.026V.

[0053] Please combine Figure 1 As shown, in this application, the diode current in the first sub-measuring structure 11, the diode current in the second sub-measuring structure 12, and the diode current in the third sub-measuring structure 13 are all equal to the input test current. Therefore, the following relationship holds: A1(e qUD1 / kT -1)=A2(e qUD2 / kT -1); A1(e qUD1 / kT -1)=A3(e qUD3 / kT -1); A2(e qUD2 / kT -1)=A3(e qUD3 / kT -1); The proportional relationship between the diode structure voltages in the two sub-measuring structures can be obtained using the following formula: U D1 / U D2 =1+ln(A2 / A1)kT / q; U D1 / U D3 =1+ln(A3 / A1)kT / q; U D2 / U D3 =1+ln(A3 / A2)kT / q; Among them, U D1 The diode structure voltage, U, in the first sub-measuring structure D2 The diode structure voltage, U, in the second sub-measuring structure D3 The diode structure voltage in the third sub-measurement structure; A1 is the area of ​​the second type doped region in the first sub-measurement structure, A2 is the area of ​​the second type doped region in the second sub-measurement structure, A3 is the area of ​​the second type doped region in the third sub-measurement structure, q is the electron charge, k is the Boltzmann constant, and T is the absolute temperature.

[0054] Step S104: Obtain the value of parasitic resistance.

[0055] Please see Figure 3As shown, in this application, the value of parasitic resistance is obtained based on at least three sets of measured voltages and test currents, and in combination with the relationship between the measured voltage, test current, diffusion region resistance, parasitic resistance and diode structure voltage in each sub-measurement structure, the proportional relationship of the diffusion region resistance in the sub-measurement structure, and the proportional relationship of the diode structure voltage in the sub-measurement structure.

[0056] Please see Figure 3 As shown, in one embodiment of the present invention, the specific steps for obtaining the value of parasitic resistance are as follows: First, R... D1 / R D2 =A2 / A1=75 / 100 Substituting into U2=I(R) D2+ R p )+U D2 and subtract U1=I(R) from it. D1+ R p )+U D1 Then we get the following formula: 25 / 75×I×R D1 +U D2 -U D1 =U2-U1. Then U D1 / U D2 =1+ln(A2 / A1)kT / q=1+ln(75 / 100)×0.026=0.9925 Substitute into 25 / 75×I×R D1 +U D2 -U D1 =U2-U1, then obtain 25 / 75×I×R D1 -0.0075U D1 =U2-U1. Then R D1 / R D3 =A3 / A1=64 / 100 Substituting into U3=I(R) D3+ R p )+U D3 and subtract U1=I(R) from it. D1+ R p )+U D1 Then we get the following formula: 36 / 64 × I × R D1 +U D3 -U D1 =U3-U1. Then U D1 / U D3 =1+ln(A3 / A1)kT / q=1+ln(64 / 100)×0.026=0.9884 Substitute into 36 / 64×I×R D1 +U D3 -U D1 =U3-U1, then obtain 25 / 75×I×R D1 -0.0116U D1=U3-U1. In 25 / 75×I×R D1 -0.0075U D1 =U2-U1 and 25 / 75×I×R D1 -0.0116U D1 In the two formulas, =U3-U1, I represents the input test current, U1 is the measured voltage across the first sub-measuring structure 11, U2 is the measured voltage across the second sub-measuring structure 12, and U3 is the measured voltage across the third sub-measuring structure 13, all of which can be obtained through measurement. Therefore, the diffusion region resistance R in the first sub-measuring structure 11 can be obtained through two linear equations in two variables. D1 and the diode structure voltage U in the first sub-measuring structure 11 D1 The value of U1 is obtained, and then U1=I(R) is obtained. D1+ R p )+U D1 The value of parasitic resistance in the middle.

[0057] In summary, this invention provides a diode measurement structure, measurement method, and integrated circuit. The diode measurement structure includes at least three sub-measurement structures, and each sub-measurement structure includes: a first type well disposed in a substrate; a second type doped region disposed in the first type well, the second type doped region and the first type well forming a diode structure; a first type doped region disposed in the first type well; a first connection structure connected to the first type doped region; and a second connection structure connected to the second type doped region. The first type well, first type doped region, first connection structure, and second connection structure are identical in each sub-measurement structure, and the perimeter of the second type doped region in each sub-measurement structure is equal but the area is different. An unexpected effect is that by setting at least three sub-measurement structures in the diode measurement structure, and ensuring that the parasitic resistance value is the same in each sub-measurement structure, and that the perimeter of the second type doped region in each sub-measurement structure is equal but the area is different, the diffusion region resistance in each sub-measurement structure is only related to the area, thereby obtaining the proportional relationship of the diffusion region resistance in two sub-measurement structures. By inputting the same test current into each sub-measurement structure, the diode structure voltage in each sub-measurement structure is ensured to be dependent only on its area, thereby obtaining the proportional relationship between the diode structure voltages in the two sub-measurements. Finally, by combining at least three sets of measured voltages and test currents, the parasitic resistance value in the sub-measurement structure is obtained, thus yielding a more accurate diode model.

[0058] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A measurement structure for a diode, characterized in that, The measurement structure includes at least three sub-measurement structures, and each of the sub-measurement structures includes: The first type of well is disposed in the substrate; A second type of doped region is disposed in the first type of well, and the second type of doped region and the first type of well form a diode structure; A first type of doped region is disposed in a first type of well; A first connection structure is connected to the first type of doped region; and A second connection structure is connected to the second type of doped region; In each of the sub-measurement structures, the first type of well, the first type of doped region, the first connection structure, and the second connection structure are the same, and the perimeter of the second type of doped region in each of the sub-measurement structures is equal but the area is different.

2. The diode measurement structure according to claim 1, characterized in that, The depth of the second type of doped region is the same in each of the sub-measurement structures.

3. The diode measurement structure according to claim 1, characterized in that, The measurement structure includes a first sub-measurement structure, a second sub-measurement structure, and a third sub-measurement structure, wherein the second type of doped region in the first sub-measurement structure, the second sub-measurement structure, and the third sub-measurement structure is rectangular.

4. The diode measurement structure according to claim 1, characterized in that, The first type of doped region is arranged in a ring shape, and the first type of doped region surrounds the second type of doped region.

5. The diode measurement structure according to claim 1, characterized in that, The first connection structure includes a first contact hole and a first metal layer. One end of the first contact hole is connected to the first type of doped region, and the other end of the first contact hole is connected to one end of the first metal layer. The other end of the first metal layer is connected to an external pad. The second connection structure includes a second contact hole and a second metal layer. One end of the second contact hole is connected to the second type of doped region, and the other end of the second contact hole is connected to one end of the second metal layer. The other end of the second metal layer is connected to another external pad.

6. A method for measuring a diode, characterized in that, Using the measurement structure of the diode as described in any one of claims 1 to 5, and the method for measuring the diode includes: A test current is input to each of the sub-measurement structures to obtain the measurement voltages across at least three of the sub-measurement structures. The relationship between the measurement voltages, test currents, diffusion region resistances, parasitic resistances, and diode structure voltages of at least three of the sub-measurement structures is obtained, and the parasitic resistances and test currents are the same in each of the sub-measurement structures. Based on the relationship between the diffusion region resistance and the depth and area of ​​the first type of doped region in the diode structure, the proportional relationship between the diffusion region resistance in the two sub-measurement structures is obtained; Based on the relationship between the diode structure current, the diode structure voltage, and the area of ​​the first type of doped region, the proportional relationship of the diode structure voltage in the two sub-measurement structures is obtained; and Based on at least three sets of measured voltages and test currents, and in conjunction with the relationship between the measured voltage, test current, diffusion region resistance, parasitic resistance, and diode structure voltage in each of the sub-measurement structures, the proportional relationship between the diffusion region resistances in two of the sub-measurement structures, and the proportional relationship between the diode structure voltages in two of the sub-measurement structures, the value of the parasitic resistance in each of the sub-measurement structures is obtained.

7. The diode measurement method according to claim 6, characterized in that, The relationships between the measurement voltage, test current, diffusion region resistance, parasitic resistance, and diode structure voltage of at least three of the aforementioned sub-measurement structures are obtained using the following formula: U1=I(R D1+ R p )+U D1 ; U2=I(R D2+ R p ) +U D2 ; U3=I(R D3+ R p )+U D3 ; Where U1 is the measurement voltage across the first sub-measuring structure, I is the input test current, and R... D1 R is the resistance of the diffusion region in the first sub-measuring structure. p For the equivalent parasitic resistance, U D1 U1 is the diode structure voltage in the first sub-measurement structure, U2 is the measurement voltage across the second sub-measurement structure, and R is the diode structure voltage. D2 U is the resistance of the diffusion region in the second sub-measuring structure. D2 U3 is the diode structure voltage in the second sub-measurement structure, and U4 is the measurement voltage across the third sub-measurement structure. D3 U is the resistance of the diffusion region in the third sub-measuring structure. D3 The diode structure voltage in the third sub-measuring structure.

8. The diode measurement method according to claim 6, characterized in that, The proportional relationship between the resistances of the diffusion regions in the two sub-measuring structures is obtained by the following formula: R D1 / R D2 =A2 / A1; R D1 / R D3 =A3 / A1; R D2 / R D3 =A3 / A2; Among them, R D1 R is the resistance of the diffusion region in the first sub-measuring structure. D2 R is the resistance of the diffusion region in the second sub-measuring structure. D3 A1 is the area of ​​the second type of doped region in the first sub-measurement structure, A2 is the area of ​​the second type of doped region in the second sub-measurement structure, and A3 is the area of ​​the second type of doped region in the third sub-measurement structure.

9. The diode measurement method according to claim 6, characterized in that, The proportional relationship between the diode structure voltages in the two sub-measuring structures is obtained by the following formula: U D1 / U D2 =1+ln(A2 / A1)kT / q; U D1 / U D3 =1+ln(A3 / A1)kT / q; U D2 / U D3 =1+ln(A3 / A2)kT / q; Among them, U D1 For the diode structure voltage in the first sub-measuring structure, U D2 For the diode structure voltage in the second sub-measuring structure, U D3 A1 is the diode structure voltage in the third sub-measurement structure; A2 is the area of ​​the second type doped region in the first sub-measurement structure; A3 is the area of ​​the second type doped region in the second sub-measurement structure; q is the electron charge; k is the Boltzmann constant; and T is the absolute temperature.

10. An integrated circuit, characterized in that, The measurement structure includes the diode as described in any one of claims 1 to 5.

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