Semiconductor device with first isolation trench and method of manufacture

Abstract

A semiconductor device includes a lower semiconductor substrate layer of a first conductivity type, an upper semiconductor substrate layer, a patterned buried semiconductor substrate layer interposed between the lower semiconductor substrate layer and the upper semiconductor substrate layer. The patterned buried semiconductor substrate layer includes a first portion of a second conductivity type, a second portion of the second conductivity type laterally spaced apart from the first portion, an intermediate region laterally disposed between the first portion and the second portion. The semiconductor device includes a first isolation trench formed at an upper major surface of the upper semiconductor substrate layer and extending in a vertical direction through the upper semiconductor substrate layer and through the intermediate region of the patterned buried semiconductor substrate layer into the lower semiconductor substrate layer. The first isolation trench is spaced apart from the first portion of the patterned buried semiconductor substrate layer and the second portion of the patterned buried semiconductor substrate layer. The first isolation trench includes a first insulating material formed at an inner sidewall of the first isolation trench, and the first isolation trench is filled with a first conductive material.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device having a first isolation trench, and a method of manufacturing the semiconductor device. Background Technology

[0002] Integrated power technology has evolved to the point where entire electronic systems are built into a single integrated circuit chip. This single chip combines analog, digital / logic, and / or power functions to provide system functionality. A single chip replaces multiple integrated circuit chips, enabling manufacturers to build smaller systems. Applications include systems in the automotive, industrial, telecommunications, and data processing sectors. A single chip can be manufactured via bipolar complementary metal-oxide-semiconductor (CMOS) or double-diffused metal-oxide-semiconductor (DMOS) processes (known as the BCD process). Within a single chip, electrical isolation is required between chip components operating at different voltage levels. For example, electrical isolation is needed between blocks operating at high voltages and blocks operating at lower voltages. Summary of the Invention

[0003] According to an example of a semiconductor device, the semiconductor device includes a lower semiconductor substrate layer and an upper semiconductor substrate layer of a first conductivity type. The semiconductor device further includes a patterned buried semiconductor substrate layer interposed between the lower and upper semiconductor substrate layers. The patterned buried semiconductor substrate layer includes a first portion of a second conductivity type, a second portion of the second conductivity type laterally spaced from the first portion, and an intermediate region laterally disposed between the first and second portions. The semiconductor device further includes a first isolation trench formed at the upper main surface of the upper semiconductor substrate layer and extending vertically through the upper semiconductor substrate layer and through the intermediate region of the patterned buried semiconductor substrate layer into the lower semiconductor substrate layer. The first isolation trench is spaced apart from the first and second portions of the patterned buried semiconductor substrate layer. The first isolation trench includes a first insulating material formed on the inner sidewall of the first isolation trench, and the first isolation trench is filled with a first conductive material.

[0004] According to an example of a method for manufacturing a semiconductor device, the method includes forming a buried semiconductor substrate layer over a lower semiconductor substrate layer of a first conductivity type. The method further includes patterning the buried semiconductor substrate layer to form a first portion of a second conductivity type, a second portion of the second conductivity type laterally spaced from the first portion, and an intermediate region laterally disposed between the first and second portions. The method further includes forming an upper semiconductor substrate layer over the patterned buried semiconductor substrate layer. The method further includes forming a first isolation trench extending vertically from an upper main surface of the upper semiconductor substrate layer, through the upper semiconductor substrate layer, and through the intermediate region of the patterned buried semiconductor substrate layer into the lower semiconductor substrate layer. The first isolation trench is spaced apart from the first portion and the second portion of the patterned buried semiconductor substrate layer. The method further includes forming a first insulating material covering the inner sidewalls of the first isolation trench and filling the first isolation trench with a first conductive material.

[0005] Those skilled in the art will recognize the additional features and advantages upon reading the following detailed description and viewing the accompanying drawings. Attached Figure Description

[0006] In the accompanying figures, this disclosure is illustrated by way of example rather than limitation, wherein similar reference numerals in the figures refer to similar or identical elements unless otherwise indicated. The elements in the figures are not necessarily drawn to scale relative to each other. Features of the various illustrated examples can be combined unless they are mutually exclusive.

[0007] Figures 1A-1G The illustration shows a partial cross-sectional view of an exemplary semiconductor device; Figure 2A and Figure 2B A partial top view of an exemplary semiconductor device is illustrated; Figures 3A-3I , Figures 4A-4G , Figures 5A-5F A series of cross-sectional views are illustrated in the illustration of an exemplary method for manufacturing a semiconductor device; Figure 6 The illustration shows a partial cross-sectional view of an exemplary semiconductor device; and Figures 7A-7G , Figures 8A-8H , Figures 9A-9E A series of cross-sectional views are illustrated in the figure, showing an exemplary method for manufacturing a semiconductor device. Detailed Implementation

[0008] The following discussion details the making and use of several examples. However, it should be understood that this invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific examples discussed are merely illustrative of specific ways of making and using the invention and do not limit the scope of the invention.

[0009] The terms “having,” “comprising,” “including,” “containing,” and the like are open-ended and indicate the presence of the stated structure, element, or feature, but do not exclude the presence of additional elements or features. The articles “a,” “an,” and “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise.

[0010] Unless otherwise expressly stated, the expression “and / or” shall be interpreted to include all possible combinations of conjunctions and disjunctions. For example, the expression “A and / or B” shall be interpreted to mean only A, only B, or both A and B. The expression “...at least one of…” shall be interpreted in the same manner as “and / or”, unless otherwise expressly stated. For example, the expression “at least one of A and B” shall be interpreted to mean only A, only B, or both A and B.

[0011] The terms “on” and “above” should not be interpreted as meaning only “directly on” and “directly above”. Rather, if an element is positioned “on” or “above” another element (e.g., a layer on or “above” another layer or on or “above” a substrate), then additional components (e.g., additional layers) may be positioned between the two elements (e.g., if a layer is “on” or “above” a substrate, then additional layers may be positioned between said layer and said substrate).

[0012] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “above,” “below,” and the like are used herein to describe the relationship of an element or feature to one or more other elements or features illustrated in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or oriented in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0013] Figure 1AA partial cross-sectional view of an exemplary semiconductor device 100A is schematically illustrated. The semiconductor device 100A includes a semiconductor substrate 102. The semiconductor substrate 102 may include one or more of a wide variety of semiconductor materials used to form the semiconductor device. For example, the semiconductor substrate 102 may include a single-element semiconductor (e.g., Si, Ge, etc.), a silicon-on-insulator semiconductor, a binary semiconductor (e.g., SiC, GaN, GaAs, SiGe, etc.), or a ternary semiconductor (e.g., AlGaN, InGaAs, InAlAs, etc.). The semiconductor substrate 102 has a first main surface 102_1 and a second main surface (not shown) opposite to the first main surface 102_1. The first main surface 102_1 may be referred to as the front surface, and the second main surface may be referred to as the rear surface. A first direction x is parallel to the first main surface 102_1 of the semiconductor substrate 102. The first direction x may be referred to as the horizontal direction, the lateral direction x, or the x-direction.

[0014] Semiconductor substrate 102 includes a lower semiconductor substrate layer 104 and an upper semiconductor substrate layer 108 of a first conductivity type. The upper main surface 102_1 of the upper semiconductor substrate layer 108 coincides with the first main surface 102_1 of the semiconductor substrate 102. The upper main surface 102_1 of the upper semiconductor substrate layer 108 may be referred to as the first main surface 102_1 of the upper semiconductor substrate layer 108. Semiconductor substrate 102 further includes a buried semiconductor substrate layer 106 of a second conductivity type, opposite to the first conductivity type. The buried semiconductor substrate layer 106 is interposed between the lower semiconductor substrate layer 104 and the upper semiconductor substrate layer 108 in a second direction y perpendicular to the first direction x. The second direction y may be referred to as the vertical direction y or the y-direction.

[0015] The buried semiconductor substrate 106 is a conductive layer that can be formed, for example, by implanting a dopant into the semiconductor substrate 102, depositing a doped semiconductor material, or epitaxially growing a semiconductor material. The buried semiconductor substrate 106 may be referred to as the buried layer 106. In one example, the lower semiconductor substrate 104 is p-type and has a lower dopant concentration than the n-type buried layer 106. The buried layer 106 may have a thickness in the y-direction ranging from 0.5 µm to 3 µm and a sheet resistance in the range of 5 to 50 ohms / square. The buried layer 106 may be positioned directly on the lower semiconductor substrate 104. Alternatively, one or more intermediate layers may be interposed between the buried layer 106 and the lower semiconductor substrate 104. The buried layer 106 is a patterned buried layer 106 comprising a first portion 106_1 of a second conductivity type, a second portion 106_2 of a second conductivity type, and an intermediate region laterally disposed between the first portion 106_1 and the second portion 106_2. This means that the intermediate region 106_3 separates the first portion 106_1 from the second portion 106_2 in the lateral direction x. The first portion 106_1 and the second portion 106_2 have a constant doping concentration along the x-direction within manufacturing tolerances. The doping of the intermediate region 106_3 varies in the x-direction, including lateral diffusion of regions of a second conductivity type from the first portion 106_1 and the second portion 106_2. The doping concentration of the intermediate region 106_3 decreases in the x-direction from the first portion 106_1 and the second portion 106_2 toward the middle of the intermediate region 106_3, respectively. In one example, the doping concentration decreases by an order of magnitude. The intermediate region 106_3 can be produced such that it is covered with photoresist while the first portion 106_1 and the second portion 106_2 of the patterned buried layer 106 are implanted. The intermediate region 106_3 may also include regions of a first conductivity type, which are laterally separated from regions of a second conductivity type.

[0016] The upper semiconductor substrate 108 can be directly positioned on the patterned buried layer 106. Alternatively, one or more intermediate layers can be inserted between the upper semiconductor substrate 108 and the patterned buried layer 106. The upper semiconductor substrate 108 is a conductive layer, for example, formed by epitaxial growth of a semiconductor material. The upper semiconductor substrate 108 can be of a first conductivity type or a second conductivity type. In one example, the upper semiconductor substrate 108 has the same conductivity type as the patterned buried layer 106 and has a lower dopant concentration than the patterned buried layer 106. In another example, the upper semiconductor substrate 108 has a conductivity type opposite to the patterned buried layer 106 and has a lower dopant concentration than the patterned buried layer 106. The doping concentration of the upper semiconductor layer 108 can range from 1e14 cm⁻³ to 5e16 cm⁻³. The thickness of the upper semiconductor layer 108 can range from 4 μm to 20 μm. The upper semiconductor substrate 108 includes well regions and / or doped regions, which form at least part of a functional device formed within the upper semiconductor substrate 108. The functional device may be an active or passive semiconductor device.

[0017] like Figure 1A As illustrated, a first isolation trench 110 is provided at the first main surface 102_1 of the upper semiconductor substrate 108. The first isolation trench 110 extends vertically in the y-direction through the upper semiconductor substrate 108 and through the middle region 106_3 of the patterned buried semiconductor substrate 106 into the lower semiconductor substrate 104. This means that, starting from the first main surface 102_1 of the upper semiconductor substrate 108, the first isolation trench 110 penetrates the upper semiconductor substrate 108 and extends through the middle region 106_3 of the patterned buried semiconductor substrate 106 into the lower semiconductor substrate 104. The bottom of the first isolation trench 110 resides within the lower semiconductor substrate 104. This means that the bottom of the first isolation trench 110 does not reach the lower surface of the lower semiconductor substrate 104. The first isolation trench 110 may be referred to as deep trench isolation (DTI).

[0018] like Figure 1A As further illustrated, the first isolation trench 110 is laterally spaced from a first portion 106_1 and a second portion 106_2 of the patterned buried semiconductor substrate 106. The first isolation trench 110 is spaced from the first portion 106_1 of the patterned buried semiconductor substrate 106 by a first distance da in the lateral direction x. Furthermore, the first isolation trench 110 is spaced from the second portion 106_2 of the patterned buried semiconductor substrate 106 by a second distance db in the lateral direction x. For example, the first distance da and / or the second distance db is less than 20 µm, for example, its range can be from 3 µm to 15 µm.

[0019] like Figure 1A As further illustrated, the first isolation trench 110 includes a first insulating material 112 that lines the inner sidewalls 124_1, 126_1 of the first isolation trench 110. The first insulating material 112 may be referred to as a liner. For example, the first insulating material 112 may include grown and / or deposited oxides, nitrides, or other dielectric materials. Furthermore, the first isolation trench 110 is filled with a first conductive material 114. The first conductive material 114 may include highly doped polycrystalline silicon, metal semiconductor compounds, metals, and / or metal alloys. In one example, the first conductive material 114 is polycrystalline silicon and has the same conductivity type as the lower semiconductor substrate 104, but has a higher dopant concentration than the lower semiconductor substrate 104, for example, 1e17 cm⁻³ to 1e20 cm⁻³. The first conductive material 114 is laterally separated from the upper semiconductor substrate 108 and the lower semiconductor substrate 104 by the first insulating material 112. The bottom portion of the first isolation trench 110 has no insulating material 112, and therefore the first conductive material 114 contacts the lower semiconductor substrate 104 at the bottom portion of the first isolation trench 110.

[0020] exist Figure 1A In one example, the lower semiconductor substrate 104 is configured to be set to a potential P via an opening in the first conductive material 114 and the first insulating material 112 at the bottom of the first isolation trench 110. In another example, the lower semiconductor substrate 104 is configured to be set to a voltage supply potential P and / or a ground potential P. By biasing the lower semiconductor substrate 104 to a defined voltage potential P, such as ground potential P, the formation of parasitic devices within the semiconductor device 100A can be suppressed or degraded. In one example, the first conductive material 114 is configured to be set to ground potential P or a low voltage potential to bias the lower semiconductor substrate 104. The current gain of the parasitic bipolar transistor having the lower semiconductor substrate 104 as a substrate is reduced. It should be noted that... Figure 1A A schematic representation of the connection between the first conductive material 114 and the potential P is shown. For ease of illustration, the conductive layer formed on the semiconductor substrate 102 and forming part of this connection is not shown. Figure 1A The image is shown in the middle. Although in Figure 1A In one example, the lower semiconductor substrate 104 is configured to be set to potential P via an opening in the first conductive material 114 and the first insulating material 112 at the bottom of the first isolation trench 110. However, in other examples, the lower semiconductor substrate 104 is configured to be set to potential P in a different manner, for example by using a sinker.

[0021] like Figure 1AAs further illustrated, a first isolation trench 110 is disposed in an interface region 116 of the semiconductor device 100A. In one example, the first isolation trench 110 extends longitudinally within the interface region 116 along a first main surface 102_1 of the upper semiconductor substrate 108 in a third direction z perpendicular to a first direction x and a second direction y. The third direction z may be referred to as an additional horizontal direction or an additional lateral direction z. The interface region 116 separates a first functional device region 118 from a second functional device region 120. The first functional device region 118 is different from the second functional device region 120. The first functional device region 118, the second functional device region 120, and the interface region 116 are monolithically integrated in the same semiconductor die. The interface region 116 is disposed between the first functional device region 118 and the second functional device region 120. The first functional device region 118 includes at least one active or passive semiconductor device, and the second functional device region 120 includes at least one active or passive semiconductor device. In one example, the passive semiconductor device may be at least one of an inductor, a capacitor, or a resistor. In one example, the active semiconductor device can be at least one of a transistor or a diode, such as a power transistor or a power diode. At least one active or passive semiconductor device in the first functional device region 118 and the second functional device region 120 can be implemented using hybrid techniques. Such hybrid techniques can be used, for example, to form analog circuit blocks using bipolar devices, digital circuit blocks using CMOS (complementary metal-oxide-semiconductor) devices, and low, medium, or high voltage or power blocks using DMOS (dual diffused metal-oxide-semiconductor) devices. For example, when bipolar and CMOS technologies are combined, such hybrid techniques are referred to as BCD (bipolar CMOS DMOS) technology, SPT (smart power technology), or BiCMOS technology.

[0022] The first functional device region 118 includes well regions and / or doped regions in the upper semiconductor substrate 108, forming a portion of at least one active or passive semiconductor device of the first functional device region 118. Similarly, the second functional device region 120 includes well regions and / or doped regions in the upper semiconductor substrate 108, forming a portion of at least one active or passive semiconductor device of the second functional device region 120. In one example, at least one active or passive semiconductor device of the first functional device region 118 is configured to operate at a different voltage level than at least one active or passive semiconductor device of the second functional device region 120. In one example, at least one active or passive semiconductor device of the first functional device region 118 has a different breakdown voltage than at least one active or passive semiconductor device of the second functional device region 120. Furthermore, a first portion 106_1 of the patterned buried semiconductor substrate 106 in the first functional device region 118 is configured to be biased to a different voltage level than a second portion 106_2 of the patterned buried semiconductor substrate in the second functional device region 120. In one example, a first portion 106_1 of the patterned buried semiconductor substrate 106 in the first functional device region 118 and a second portion 106_2 of the patterned buried semiconductor substrate in the second functional device region 120 are respectively configured to be biased by connecting them to a voltage potential via a sink region, as will be described in more detail below.

[0023] In one example, the active or passive semiconductor device in the second functional device region 120 is configured to operate at a higher voltage level than the active or passive semiconductor device in the first functional device region 118. This means that the active or passive semiconductor device included in the second functional device region 120 has a higher operating voltage or a wider operating range than the active or passive semiconductor device included in the first functional device region 118. During operation of the semiconductor device 100A, the upper semiconductor substrate 108 in the second functional device region 120 is at a higher voltage level than the upper semiconductor substrate 108 in the first functional device region 118. Similarly, the second portion 106_2 of the patterned buried semiconductor substrate in the second functional device region 120 is biased to a higher voltage level than the first portion 106_1 of the patterned buried semiconductor substrate in the first functional device region 118. In one example, the active or passive semiconductor device in the second functional device region 120 is rated to operate in the range of 40V to 200V or even higher. In one example, the active or passive semiconductor devices in the first functional device region 118 are rated to operate at voltages ranging from 1.5 V to 40 V.

[0024] A first isolation trench 110 electrically isolates the first functional device region 118 from the second functional device region 120. More specifically, the first isolation trench 110 separates the upper semiconductor substrate layer 108 in the second functional device region 120 from the upper semiconductor substrate layer 108 in the first functional device region 118. Furthermore, the first isolation trench 110 extends through the intermediate region 106_3 of the patterned buried semiconductor substrate layer 106. A first sidewall 124 of the first isolation trench 110 is disposed at a first distance da from a first portion 106_1 of the patterned buried semiconductor substrate layer 106. A second sidewall 126, opposite to the first sidewall 124, is disposed at a second distance db from the first portion 106_1 of the patterned buried semiconductor substrate layer 106. The first distance da may be the same as or different from the second distance db. By spacing the first isolation trench 110 from the first portion 106_1 and the second portion 106_2 of the patterned buried semiconductor substrate 106, the electric field density at the pn junction formed between the patterned buried semiconductor substrate 106 and the lower semiconductor substrate 104 is reduced. By reducing the electric field density at the pn junction, breakdown at the pn junction can be avoided and / or the breakdown voltage of the pn junction can be increased. For example, in an embodiment where the first conductive material 114 is set to ground potential P, pn junction breakdown can be prevented. Simultaneously, as described above, the formation of a parasitic bipolar transistor having the lower semiconductor substrate 104 as a substrate is avoided.

[0025] Figure 1B A further partial cross-sectional view of the exemplary semiconductor device 100B is schematically illustrated. Figure 1B The semiconductor device 100B is similar to a combination Figure 1A The illustrated and described semiconductor device 100A differs in that... Figure 1B The lower semiconductor substrate 104 of the semiconductor device 100B includes a region 122 at the bottom of the first isolation trench 110 with a locally increased dopant concentration. This means that region 122 has the same conductivity type as the lower semiconductor substrate 104, but has a higher dopant concentration. Region 122 allows for improved electrical contact between the first conductive material 114 and the lower semiconductor substrate 104.

[0026] Figure 1C A further partial cross-sectional view of an exemplary semiconductor device 100C is schematically illustrated. Figure 1C The semiconductor device 100C is similar to a combination Figure 1AThe illustrated and described semiconductor device 100A differs from the semiconductor device 100C, which includes a first sink region 128 formed on the upper main surface 102_1 of the upper semiconductor substrate 108 and extending in the vertical y-direction along at least a portion of the outer sidewalls 124_2, 126_2 of the first isolation trench 110. The first sink region 128 has a second conductivity type and can be formed by ion implantation and / or diffusion, as will be described in more detail below. The doping concentration of the first sink region 128 decreases along the lateral direction x. The first sink region 128 includes a highly doped region formed on the outer sidewalls 124_2, 126_2 of the first isolation trench 110. Within the highly doped region, the doping concentration decreases by less than an order of magnitude. The highly doped region of the first sink region 128 is spaced apart from a first portion 106_1 and a second portion 106_2 of the patterned buried semiconductor substrate 106. The first subsidence region 128 extends from the upper main surface 102_1 of the upper semiconductor substrate 108 to a depth dc defined by the upper main surface 106_4 of the patterned buried semiconductor substrate 106. Figure 1C In the example, the first sink region 128 extends deeper than the depth dc, but not to the depth defined by the lower main surface 106_5 of the patterned buried semiconductor substrate layer 106. Figure 1C Examples can be compared with Figure 1B Examples of phase combinations, and regions 122 with locally increased dopant concentration can be formed in Figure 1C At the bottom of the first isolation trench 110.

[0027] Figure 1D-Figure 1G A further partial cross-sectional view of an exemplary semiconductor device 100D-100G is schematically illustrated, the exemplary semiconductor device 100D-100G comprising as described above. Figures 1A-1C The first isolation trench 110 is illustrated and described in any example. The semiconductor device 100D-100G further includes a second isolation trench 130 formed at a first main surface 102_1 of the upper semiconductor substrate layer 108 and extending in the vertical direction y. The second isolation trench 130 includes a second insulating material 132 formed at the inner sidewalls 134_1, 136_1 and the bottom of the second isolation trench 130. For example, the second insulating material 132 may include grown and / or deposited oxide, nitride, or other dielectric materials. Figure 1D-Figure 1GIn one example, the second isolation trench 130 contains no conductive material. This means that the second isolation trench 130 does not contain any conductive material. Instead, the second insulating material 132 completely fills the second isolation trench 130. In other examples, the second isolation trench 130 is partially filled with a second conductive material (not shown). The second conductive material may include highly doped polysilicon, metal semiconductor compounds, metals, and / or metal alloys. The second conductive material is separated from the semiconductor substrate 102 by the second insulating material 132.

[0028] A second isolation trench 130 is disposed in the interface region 116 and may extend longitudinally, at least partially parallel to the first isolation trench 110, along the first main surface 102_1 of the upper semiconductor substrate 108 in the third direction z. A first sidewall 134 of the second isolation trench 130 is opposite to a second sidewall 136 of the second isolation trench 130. The first isolation trench 110 and the second isolation trench 130 electrically isolate the first functional device region 118 from the second functional device region 120. More specifically, the first isolation trench 110 and the second isolation trench 130 separate the upper semiconductor substrate 108 in the second functional device region 120 from the upper semiconductor substrate 108 in the first functional device region 118. The first isolation trench 110 and the second isolation trench 130 are configured to act as a capacitive voltage divider, which divides the higher operating voltage or higher voltage level of the second functional device region 120 down to the lower operating voltage or lower voltage level of the first functional device region 118. The first isolation trench 110 and the second isolation trench 130 may be referred to as a dual trench isolation structure or a double trench isolation structure. It should be noted that in some examples, the interface area 116 may include additional isolation trenches similar to or the same as the first isolation trench 110 and / or the second isolation trench 130.

[0029] In the example of semiconductor device 100D-100G, the region of the upper semiconductor substrate 108 between the first isolation trench 110 and the second isolation trench 130 does not contain functional devices. This means that the upper semiconductor substrate 108 in the interface region 116 may not include any portion of active or passive semiconductor devices. The distance d3 between the first isolation trench 110 and the second isolation trench 130 is measured along a first direction x at the location of the first main surface 102_1 of the semiconductor substrate 102. In one example, the distance d3 is in the range of 1 µm to 5 µm. In other examples (not shown), the second isolation trench 130 is arranged further away from the first isolation trench 110, and the region of the upper semiconductor substrate 108 between the first isolation trench 110 and the second isolation trench 130 includes functional devices.

[0030] The first isolation trench 110 has a first width w1, and the second isolation trench 130 has a second width w2, with the first width w1 being greater than the second width w2. The first width w1 and the second width w2 can be measured at a location on the first main surface 102_1 of the upper semiconductor substrate 108. In one example, the first width w1 is in the range of 2 µm to 5 µm, and the second width w2 is in the range of 1 µm to 4 µm. Furthermore, the first isolation trench 110 has a first depth d1, and the second isolation trench 130 has a second depth d2, with the first depth d1 being greater than the second depth d2. The first depth d1 and the second depth d2 can be measured from a location on the first main surface 102_1 of the upper semiconductor substrate 108 to the bottom of the first isolation trench 110 and the second isolation trench 130, respectively. In one example, as will be described in more detail below, the first isolation trench 110 and the second isolation trench 130 are manufactured in the same processing step. The second width w2 can be sized such that the second isolation trench 130 is completely filled with a second insulating material 132. In contrast, the first width w1 is defined such that the first insulating material 112 only covers the inner sidewall of the first isolation trench 110.

[0031] exist Figure 1D In the exemplary semiconductor device 100D, a second isolation trench 130 extends through an upper semiconductor substrate 108 and through a patterned buried semiconductor substrate 106 into a lower semiconductor substrate 104. This means that, starting from a first main surface 102_1 of the upper semiconductor substrate 108, the second isolation trench 130 penetrates the upper semiconductor substrate 108 and the patterned buried semiconductor substrate 106, and extends into the lower semiconductor substrate 104. The bottom of the second isolation trench 130 resides within the lower semiconductor substrate 104. At the location where the second isolation trench 130 extends through the patterned buried semiconductor substrate 106, there are no gaps within the patterned buried semiconductor substrate 106. The second isolation trench 130 isolates a portion of the patterned buried semiconductor substrate 106 disposed in the second functional device region 120 from a portion of the patterned buried semiconductor substrate 106 disposed in the interface region 116.

[0032] exist Figure 1E In the exemplary semiconductor device 100E, the second isolation trench 130 extends through the upper semiconductor substrate 108 to the upper main surface 106_4 of the patterned buried semiconductor substrate 106, but does not extend through the patterned buried semiconductor substrate 106. In one example, the second isolation trench 130 extends through the upper semiconductor substrate 108 at least to the upper main surface 106_4 of the patterned buried semiconductor substrate 106, but does not extend through the patterned buried semiconductor substrate 106.

[0033] Figure 1F and Figure 1G A further partial cross-sectional view of the exemplary semiconductor device 100F-100G is schematically illustrated. The exemplary semiconductor device 100F-100G includes the components as described above. Figures 1A-1C The first isolation trench 110 in any example illustrated and described, and including as combined above. Figure 1D and Figure 1E The second isolation trench 130 is illustrated in any example of the diagram and description. Semiconductor devices 100F and 100G include a second sink region 138 formed at the upper main surface 102_1 of the upper semiconductor substrate layer 108 and extending in the vertical y-direction along at least a portion of the outer sidewalls 134_2, 136_2 of the second isolation trench 130. The second sink region 138 has a second conductivity type and can be formed by ion implantation and / or diffusion, as will be described in more detail below.

[0034] exist Figure 1F In the exemplary semiconductor device 100F, a second recessed region 138 extends from the upper main surface 102_1 of the upper semiconductor substrate 108 through the upper semiconductor substrate 108, extending at least to the upper main surface 106_4 of the patterned buried semiconductor substrate 106. The second recessed region 138 provides a low-ohm electrical connection to the patterned buried semiconductor substrate 106. The second recessed region 138 may not extend through the patterned buried semiconductor substrate 106.

[0035] exist Figure 1G In the exemplary semiconductor device 100G, a second recessed region 138 extends from the upper main surface 102_1 of the upper semiconductor substrate 108 into the upper semiconductor substrate 108. The second recessed region 138 does not extend to the upper main surface 106_4 of the patterned buried semiconductor substrate 106.

[0036] Figure 2A A partial top view of an exemplary semiconductor device 200A is schematically illustrated. The semiconductor device 200A includes components as described above. Figures 1A-1C Semiconductor devices 100A-100C are illustrated and described. Semiconductor device 200A includes a second functional device region 120 surrounded by a first isolation trench 110. Semiconductor device 200A also includes a first functional device region 118 located on the side 110_1 of the first isolation trench 110 opposite to the second functional device region 120. Although in Figure 2AIn one example, the second functional device region 120 is completely surrounded by the first isolation trench 110, but in other examples, the first isolation trench 110 is interrupted and / or segmented. This means that the first isolation trench 110 at least partially surrounds the second functional device region 120. In the top view, the first isolation trench 110 can be annular, circular, elliptical, square, rectangular, trapezoidal, or hexagonal, or can have other shapes.

[0037] In one example, the active or passive semiconductor device of the second functional device region 120 is configured to operate at a higher voltage level than the active or passive semiconductor device of the first functional device region 118. In other examples, this can be reversed. In one example, additional isolation trenches branching from the first isolation trench 110 may exist, such as those formed by... Figure 2A The dashed lines in the diagram indicate this. In addition, functional device regions that operate at the same or different voltage levels as the first functional device region 118 and / or the second functional device region 120 may also exist.

[0038] Figure 2B A further partial top view of the exemplary semiconductor device 200B is schematically illustrated. Figure 2B The semiconductor device 200B is similar to a combination Figure 2A The illustrated and described semiconductor device 200A differs in that, in addition to the first isolation trench 110, semiconductor device 200B also includes a second isolation trench 130, as shown above. Figures 1D-1F Semiconductor devices 100D-100F are illustrated and described. Semiconductor device 200B includes a second functional device region 120 surrounded by a second isolation trench 130. Semiconductor device 200B further includes a first isolation trench 110 surrounding the second isolation trench 130. This means that the second functional device region 120 is located on the side 130_1 of the second isolation trench 130 opposite to the first isolation trench 110. Semiconductor device 200B further includes a first functional device region 118, which is located on the side 110_1 of the first isolation trench 110 opposite to the second isolation trench 130. The area between the first isolation trench 110 and the second isolation trench 130 does not include any functional devices.

[0039] Although Figure 2BIn one example, the second functional device region 120 is completely surrounded by the second isolation trench 130, and the second isolation trench 130 is completely surrounded by the first isolation trench 110. However, in other examples, the first isolation trench 110 and / or the second isolation trench 130 are interrupted and / or segmented. In one example, the second functional device region 120 is at least partially surrounded by the second isolation trench 130. Similarly, the second isolation trench 130 is at least partially surrounded by the first isolation trench 110. The first isolation trench 110 and the second isolation trench 130 may have the same or different shapes. In a top view, the first isolation trench 110 and the second isolation trench 130 may be annular, circular, elliptical, square, rectangular, trapezoidal, or hexagonal, or may have other shapes. Although in Figure 2B In one example, the first isolation trench 110 travels parallel to the second isolation trench 130; however, in other examples, the first isolation trench 110 and the second isolation trench 130 do not travel parallel to each other. In one example, one or more additional isolation trenches may be provided between the first functional device region 118 and the second functional device region 120. The one or more additional isolation trenches may be similar to or identical to the first isolation trench 110 and / or the second isolation trench 120. The one or more additional isolation trenches may provide improved electrical isolation between functional devices located in the first functional device region 118 and functional devices located in the second functional device region 120.

[0040] Figures 3A-3I A series of cross-sectional views are schematically illustrated in an exemplary method of manufacturing a semiconductor device 300. In one example, such as combining... Figures 3A-3I The method described above can be used to manufacture similar products as the combination described above. Figures 1A-1G , Figure 2A and Figure 2B At least a portion of one of the semiconductor devices 100A-100G, 200A, and 200B illustrated and described. In another example, as combined... Figures 3A-3I The methods described can be used to manufacture at least some of the different semiconductor devices.

[0041] like Figure 3AAs illustrated, a semiconductor substrate 102 is provided, including a patterned buried semiconductor substrate layer 106 formed over a lower semiconductor substrate layer 104. The lower semiconductor substrate layer 104 has a first conductivity type. The patterned buried semiconductor substrate layer 106 includes a first portion 106_1 of a second conductivity type, a second portion 106_2 of the second conductivity type, and an intermediate region 106_3 laterally disposed between the first portion 106_1 and the second portion 106_2. The second conductivity type is opposite to the first conductivity type. The lower semiconductor substrate layer 104 may be a bulk substrate, at least a portion of a silicon-on-insulator (SOI) substrate, or an epitaxial layer. The first portion 106_1 and the second portion 106_2 of the patterned buried semiconductor substrate layer 106 may be formed by implanting at least one dopant (e.g., arsenic (As) and / or phosphorus (P)) into the semiconductor substrate 102, by in-situ deposition of doped semiconductor material using, for example, a chemical vapor deposition (CVD) process, and / or by epitaxial growth of semiconductor material. The first portion 106_1 and the second portion 106_2 have a constant doping concentration along the x-direction within manufacturing tolerances. The doping of the intermediate region 106_3 varies in the x-direction, including laterally diffused regions of a second conductivity type from the first portion 106_1 and the second portion 106_2. In one example, the doping concentration is reduced by an order of magnitude. The intermediate region 106_3 can be produced such that it is covered with photoresist while the first portion 106_1 and the second portion 106_2 of the patterned buried layer 106 are implanted. The intermediate region 106_3 may also include regions of a first conductivity type laterally separated from regions of a second conductivity type.

[0042] The semiconductor substrate 102 further includes an upper semiconductor substrate layer 108 formed on the patterned buried semiconductor substrate layer 106. In one example, the upper semiconductor substrate layer 108 has a second conductivity type and a lower dopant concentration than the patterned buried semiconductor substrate layer 106. In other examples, the upper semiconductor substrate layer 108 has a first conductivity type and / or a different dopant concentration. The upper semiconductor substrate layer 108 can be formed by depositing doped semiconductor material using, for example, a chemical vapor deposition (CVD) process, and / or by epitaxially growing semiconductor material on top of the patterned buried semiconductor substrate layer 106.

[0043] A hard mask 340 is formed on the upper semiconductor substrate 108. The hard mask 340 may include one or more layers, including at least one of silicon nitride, oxide, polysilicon, borosilicate glass (BSG), or borophosphosilicate glass (BPSG). A mask layer 342 is formed on the hard mask 340. The mask layer 342 is structured to expose the location where the first isolation trench 110 will be formed. The structured mask layer 342 includes a first opening having a first width o1 to form the first isolation trench 110. The first opening of the structured mask layer 342 is formed on the intermediate region 106_3 of the patterned buried semiconductor substrate 106. The mask layer 342 may include a photoresist, which may be referred to as a photoresist layer, and may be structured using photolithography. Figure 3A The semiconductor device 300 after an etching step is shown. During the etching step, a mask layer 342 is used to form a first opening 344 in a hard mask 340. The opening 344 in the hard mask 340 extends through the hard mask 340 and provides a patterned hard mask 340.

[0044] Figure 3B The semiconductor device 300 is shown after the mask layer 342 has been removed and after a further etching step has been performed. This further etching step is the first etching step in a multi-step etching process. During the first etching step, a first isolation trench 110 is formed in the semiconductor substrate 102 using a hard mask 340 as a mask layer. The first isolation trench 110 is etched to extend from the first main surface 102_1 of the upper semiconductor substrate layer 108 to an intermediate trench depth. Figure 3B In the example, the first isolation trench 110 extends through the upper semiconductor substrate 108 into an intermediate trench depth between the upper main surface 106_4 and the lower main surface 106_5 of the patterned buried semiconductor substrate 106. Generally, after the first etching step, the first isolation trench 110 may not extend deeper than the lower main surface 106_5 of the patterned buried semiconductor substrate 106. After the first etching step, the first isolation trench 110 is spaced apart from the first portion 106_1 and the second portion 106_2 of the patterned buried semiconductor substrate 106. In one example (not shown), a portion of the hard mask 340 is removed during the first etching step of a multi-step etching process.

[0045] Figures 3C-3EA series of cross-sectional views schematically illustrate two different methods of fabricating a first recessed region 128, which extends from the upper main surface 102_1 of the upper semiconductor substrate 108 along at least a portion of the outer sidewalls 124_2, 126_2 of the first isolation trench 110. In one example, the first recessed region 128 extends from the upper main surface 102_1 of the upper semiconductor substrate 108 to at least a depth defined by the upper main surface 106_4 of the patterned buried semiconductor substrate 106. It should be noted that the formation of the first recessed region 128 is optional, and semiconductor devices 300 may exist without the first recessed region 128. Figure 3C and Figure 3D A first method is shown for using PSG (phosphosilicate glass) diffusion to form the first sinking region 128. Figure 3E A second method for forming the first sinking region 128 using ion implantation is shown.

[0046] like Figure 3C As illustrated, PSG 346 is formed to cover the inner walls 124_1, 126_1 and the bottom of the first isolation trench 110. Figure 3C In the example, the first isolation trench 110 is completely filled with PSG 346, which can be formed by a CVD process. Figure 3D The diagram shows the semiconductor device 300 after phosphorus from PSG 346 has diffused outwards into the outer walls 124_2, 126_2 and bottom of the first isolation trench 110 to form the first sink region 128, and after the PSG 346 has been removed. PSG 346 can be removed by etching. Note that the first sink region 128 can also be formed using vapor diffusion instead of deposited PSG 346. The first sink region 128 has a second conductivity type and extends along the outer walls 124_2, 126_2 of the first isolation trench 110. The first sink region 128 extends through the upper semiconductor substrate layer 108 to a depth between the upper main surface 106_4 and the lower main surface 106_5 of the patterned buried semiconductor substrate layer 106. The doping concentration of the first sink region 128 decreases along the lateral direction x. The first sink region 128 includes highly doped regions formed on the outer sidewalls 124_2 and 126_2 of the first isolation trench 110. Within the highly doped regions, the doping concentration is reduced by less than an order of magnitude. The highly doped regions of the first sink region 128 are spaced apart from the first portion 106_1 and the second portion 106_2 of the patterned buried semiconductor substrate 106.

[0047] As mentioned above, Figure 3E An alternative method for forming the first sinking zone 128 is shown. For example... Figure 3EAs illustrated, ions 348 are implanted through the inner sidewalls 124_1 and 126_1 of the first isolation trench into the outer sidewalls 124_2 and 126_2 of the first isolation trench 110 to form a first sinking region 128. The ions may be dopants of a second conductivity type, including arsenic (As) and / or phosphorus (P), and may be implanted at an angle along the inner sidewalls 124_1 and 126_1. The first sinking region 128 extends through the upper semiconductor substrate layer 108 to a depth between the upper main surface 106_4 and the lower main surface 106_5 of the patterned buried semiconductor substrate layer 106. The highly doped region of the first sinking region 128 is spaced apart from the first portion 106_1 and the second portion 106_2 of the patterned buried semiconductor substrate layer 106.

[0048] Figure 3F The semiconductor device 300 is shown after a further etching step has been performed. This further etching step is the second etching step in a multi-step etching process. During the second etching step, a hard mask 340 is used as a mask layer to extend the trench depth of the first isolation trench 110. After the second etching step, the first isolation trench 110 has its final first depth d1, and the second etching step is the final etching step in the multi-step etching process. The first isolation trench 110 extends through the upper semiconductor substrate layer 108 and through the middle region 106_3 of the patterned buried semiconductor substrate layer 106 into the lower semiconductor substrate layer 104. After the second etching step, the first isolation trench 110 is spaced apart from the first portion 106_1 and the second portion 106_2 of the patterned buried semiconductor substrate layer 106.

[0049] like Figure 3G As illustrated, a first insulating material 112 is formed covering the inner sidewalls 124_1, 126_1 and bottom of the first isolation trench 110. The first insulating material 112 is further formed on the surface of the hard mask 340 opposite to the first main surface 102_1 of the upper semiconductor substrate layer 108. The first insulating material 112 comprises an electrically insulating material. In one example, the first insulating material 112 comprises a dielectric material. In one example, the first insulating material 112 comprises at least one of an oxide or nitride grown and / or deposited. A chemical vapor deposition (CVD) process can be used for deposition. In other examples, the first insulating material 112 comprises other materials or combinations thereof that are electrically insulating.

[0050] Figure 3HThe semiconductor device 300 is shown after the first insulating material 112 has been removed from the bottom of the first isolation trench 110 to form an opening of the first insulating material 112 at the bottom of the first isolation trench 110. Furthermore, the first insulating material 112 is removed from the surface of the hard mask 340 opposite to the first main surface 102_1 of the upper semiconductor substrate layer 108. The first insulating material 112 can be removed using an etching process. Figure 3H The semiconductor device 300 is further illustrated after an optional processing step has been performed. In this optional processing step, for example by self-aligned ion implantation, a dopant of a first conductivity type is introduced into the bottom of a first isolation trench 110 to form a region 122 of a lower semiconductor substrate layer 104. Region 122 has a locally increased dopant concentration and is disposed at the bottom of the first isolation trench 110.

[0051] like Figure 3I As illustrated, the first isolation trench 110 is filled with a first conductive material 114. In one example, the first conductive material 114 comprises at least one of polysilicon or metal. In other examples, the first conductive material comprises other materials or combinations thereof. Filling the first isolation trench 110 includes filling the first conductive material 114 into an opening in a first insulating material 112 at the bottom of the first isolation trench 110 to provide a connection of the first conductive material 114 to a lower semiconductor substrate 104. The lower semiconductor substrate 104 can be biased to a predefined voltage level via the first conductive material 114, which extends through the opening in the first insulating material 112 at the bottom of the first isolation trench 110. Note that in other examples, with Figure 3H Conversely, in the illustration, the first insulating material 112 may not be removed from the bottom of the first isolation trench 110, and the first conductive material 114 may not be attached to the lower semiconductor substrate 104 at the bottom of the first isolation trench 110. This means that the first conductive material 114 is separated from the semiconductor substrate 102 at both the sidewalls and the bottom by the first insulating material 112. In this other example, the lower semiconductor substrate 104 may be configured to be set to a potential in a different manner, for example, by using a sink region. Figure 3I As further illustrated, the hard mask 340 has been removed from the first main surface 102_1 of the upper semiconductor substrate layer 108. The hard mask 340 can be removed by using an etching process and / or a chemical mechanical polishing (CMP) process.

[0052] Figures 4A-4G A series of cross-sectional views schematically illustrate an exemplary method of manufacturing another semiconductor device 400. In one example, such as combining... Figures 4A-4G The method described above can be used to manufacture similar products as the combination described above. Figure 1D-Figure 1G , Figure 2B The illustrated and described semiconductor device is at least a portion of one of the semiconductor devices 100D-100G and 200B. In another example, as combined... Figures 4A-4G The methods described can be used to manufacture at least some of the different semiconductor devices.

[0053] Figure 4A Semiconductor device 400 is similar to Figure 3A The semiconductor device 300 differs in that the structured mask layer 342 further includes a second opening having a second width o2 to form a second isolation trench 130. The first width o1 is greater than the second width o2. The second opening of the structured mask layer 342 is formed on a second portion 106_2 of the patterned buried semiconductor substrate layer 106. There is no intermediate region of the patterned buried semiconductor substrate layer 106 below the second opening of the structured mask layer 342. Figure 4A The semiconductor device 400 is shown after an etching step has been performed. During the etching step, a mask layer 342 is used to form a second opening 350 in a hard mask 340. The second opening 350 extends through the hard mask 340.

[0054] Figure 4B Semiconductor device 400 is similar to Figure 3B The semiconductor device 300 differs in that, during the first etching step of the two-step etching process, the second isolation trench 130 is also etched to the intermediate trench depth. The second isolation trench 130 is formed in the semiconductor substrate 102 using a hard mask 340 as a mask layer. The second isolation trench 130 is etched to extend from the first main surface 102_1 of the upper semiconductor substrate layer 108 to the intermediate trench depth. Figure 4B In one example, the second isolation trench 130 extends through the upper semiconductor substrate 108 to the upper main surface 106_4 of the patterned buried semiconductor substrate 106. In other examples, after the first etching step, the second isolation trench 130 extends into the upper semiconductor substrate 108 but does not reach the upper main surface 106_4 of the patterned buried semiconductor substrate 106. Generally, after the first etching step, the second isolation trench 130 may not extend deeper than the lower main surface 106_5 of the patterned buried semiconductor substrate 106. Figure 4B In the example, after the first etching step, the first isolation trench 110 extends to the intermediate trench depth below the lower main surface 106_5 of the patterned buried semiconductor substrate layer 106.

[0055] The first isolation trench 110 has a first width w1, and the second isolation trench 130 has a second width w2, with the first width w1 being greater than the second width w2. The first width w1 and the second width w2 can be measured at a position on the first main surface 102_1 of the upper semiconductor substrate 108. The first isolation trench 110 has a first intermediate trench depth, and the second isolation trench 130 has a second intermediate trench depth, with the first intermediate trench depth being greater than the second intermediate trench depth. The first intermediate trench depth and the second intermediate trench depth can be measured from a position on the first main surface 102_1 of the upper semiconductor substrate 108 to the bottom of the first isolation trench 110 and the second isolation trench 130, respectively. As a result of the first isolation trench 110 having a greater width than the second isolation trench 130, the first isolation trench 110 has a greater intermediate trench depth than the second isolation trench 130.

[0056] Figures 4C-4E A series of cross-sectional views schematically illustrate two different methods of fabricating the second recessed region 138, which extends from the upper main surface 102_1 of the upper semiconductor substrate 108 along at least a portion of the outer sidewalls 134_2, 136_2 of the second isolation trench 130. It should be noted that the formation of the second recessed region 138 is optional, and semiconductor devices 400 may exist without the second recessed region 138. Figures 4C-4D The first method for forming the second sinking region 138 using PSG diffusion is shown. This first method is combined with the method described above. Figures 3C-3D The first method illustrated and described for the first subsidence zone 128 of the first isolation trench 110 is similar to or the same as the first method. Figure 4E A second method for forming the second subsidence region 138 using ion implantation is shown. This second method is combined with the one described above. Figure 3E The second method illustrated and described for the first subsidence zone 128 of the first isolation trench 110 is similar or the same.

[0057] exist Figure 4D and Figure 4E In one example, the second recessed region 138 extends through the upper semiconductor substrate 108 to at least the upper main surface 106_4 of the patterned buried semiconductor substrate 106. In other examples, the second recessed region 138 does not reach the upper main surface 106_4 of the patterned buried semiconductor substrate 106. Figure 4D and Figure 4E In one example, a first sinking area 128 is not formed at the first isolation trench 110. In other examples, a first sinking area 128 may be formed at the first isolation trench 110, in conjunction with the above. Figures 3C-3EThe illustrations and descriptions are similar or identical. The first recessed region 128 and the second recessed region 138 can be formed simultaneously or sequentially. The simultaneous formation of the first recessed region 128 and the second recessed region 138 allows for cost-effective manufacturing of the semiconductor device 400.

[0058] Figure 4F The semiconductor device 400 is shown after the second etching step in a two-step etching process. During the second etching step, a hard mask 340 is used as a mask layer to extend the trench depths of the first isolation trench 110 and the second isolation trench 130. After the second etching step, the first isolation trench 110 has its final first depth d1, and the second isolation trench 130 has its final second depth d2. The first depth d1 is greater than the second depth d2. Figure 4F In one example, the second isolation trench 130 extends through the upper semiconductor substrate 108 and through the patterned buried semiconductor substrate 106 into the lower semiconductor substrate 104. In other examples, the second isolation trench 130 extends through the upper semiconductor substrate 108 at least to the upper main surface 106_4 of the patterned buried semiconductor substrate 106, but does not extend through the patterned buried semiconductor substrate 106.

[0059] Figure 4G A semiconductor device 400 is shown after a first insulating material 112 and a first conductive material 114 have been formed in a first isolation trench 110 and after a second insulating material 132 has been formed in a second isolation trench 130. The second insulating material 132 may be similar to or the same as the first insulating material 112. The second insulating material 132 covers the inner sidewalls 134_1, 136_1, and the bottom of the second isolation trench 130. Figure 4G In one example, the second isolation trench 130 is completely filled with a second insulating material 132. In other examples, the second isolation trench 130 may be partially filled with a second conductive material similar to or the same as the first conductive material 114. Figure 4G As further illustrated, the hard mask 340 has been removed from the first main surface 102_1 of the upper semiconductor substrate layer 108. Optional processing steps (not shown) may be performed before filling with the first conductive material 114 to form a region with a locally increased dopant concentration at the bottom of the first isolation trench 110.

[0060] Although Figures 4A-4G In this example, the first isolation trench 110 and the second isolation trench 130 are formed simultaneously. However, it should be noted that in other examples, the first isolation trench 110 and the second isolation trench 130 can be formed in consecutive processing steps. The simultaneous formation of the first isolation trench 110 and the second isolation trench allows for cost-effective manufacturing of the semiconductor device 400.

[0061] Figures 5A-5F A series of cross-sectional views schematically illustrate an exemplary method of manufacturing another semiconductor device 500. In one example, such as combining... Figures 5A-5F The method described above can be used to manufacture similar products as the combination described above. Figure 1D-Figure 1G , Figure 2B The illustrated and described semiconductor device is at least a portion of one of the semiconductor devices 100D-100G and 200B. In another example, as combined... Figures 5A-5F The methods described can be used to manufacture at least some of the different semiconductor devices.

[0062] Figures 5A-5F The manufacturing method is similar to Figures 4A-4G The manufacturing method differs in that the first isolation trench 110 is formed in a single etching step, while the second isolation trench 130 is formed in a single etching step. In one example, the first isolation trench 110 and the second isolation trench 130 are formed simultaneously in a single etching step. The simultaneous formation of the first isolation trench 110 and the second isolation trench 130 allows for cost-effective manufacturing of the semiconductor device 500.

[0063] Figure 5A Semiconductor devices 500 and Figure 4A The semiconductor device 400 is similar to or the same, wherein the structured mask layer 342 has a first opening and a second opening, and has a hard mask 340.

[0064] Figure 5B Semiconductor devices 500 and Figure 4B The semiconductor device 400 is similar to or the same as the semiconductor device 400. The difference is that, during the one-step etching process, the first isolation trench 110 is etched to a final first depth d1. During the one-step etching process, the second isolation trench 130 is also etched to a final second depth d2.

[0065] Figures 5C-5E A series of cross-sectional views schematically illustrate two different methods of manufacturing an optional second recessed area 138, which is formed along at least a portion of the outer walls 134_2, 136_2 of the second isolation trench 130. These two different methods are related to... Figures 4C-4E The two different methods are similar or identical. An optional first sinking zone 128 (not shown) can be formed at the first isolation trench 110, in conjunction with the above. Figures 4C-4E The descriptions are similar or identical.

[0066] Figure 5F Semiconductor devices 500 and Figure 4GThe semiconductor device 400 is similar to or identical to the semiconductor device 400, wherein insulating materials 112, 132 and conductive material 114 are formed in a first isolation trench 110 and a second isolation trench 130. The hard mask 340 has been removed, and optional processing steps (not shown) can be performed to form a region with a locally increased dopant concentration at the bottom of the first isolation trench 110.

[0067] Figure 6 A further partial cross-sectional view of an exemplary semiconductor device 600 is schematically illustrated. The semiconductor device 600 includes a semiconductor substrate 102. The semiconductor substrate 102 includes a lower semiconductor substrate layer 104 and an upper semiconductor substrate layer 108 of a first conductivity type. The semiconductor substrate 102, the lower semiconductor substrate layer 104, and the upper semiconductor substrate layer 108 are... Figure 1A The semiconductor substrate 102, lower semiconductor substrate layer 104, and upper semiconductor substrate layer 108 are similar or identical. The semiconductor substrate 102 further includes a buried semiconductor substrate layer 654 of a second conductivity type, which is interposed between the lower semiconductor substrate layer 104 and the upper semiconductor substrate layer 108 in the vertical direction y. The buried semiconductor substrate layer 654 and... Figure 1A The patterned buried semiconductor substrate 106 is similar to but not the same. Figure 6 The buried semiconductor substrate 654 does not include Figure 1A The middle region 106_3 of the patterned buried semiconductor substrate layer 106.

[0068] A first isolation trench 110 is provided at the first main surface 102_1 of the upper semiconductor substrate 108. The first isolation trench 110 extends in the vertical direction y through the upper semiconductor substrate 108 and through the buried semiconductor substrate 654 into the lower semiconductor substrate 104. Figure 1A The first isolation trench 110 is similar to or the same. However, Figure 6 The first isolation trench 110 is integrated into the semiconductor substrate 102 differently Figure 1A The first isolation trench 110 is integrated into the semiconductor substrate 102. Figure 6 The first isolation trench 110 is adjacent to the buried semiconductor substrate 654, and there is no distance between the sidewalls 124, 126 of the first isolation trench 110 and the buried semiconductor substrate 654. This means that the first isolation trench 110 separates the buried semiconductor substrate 654 of the second functional device region 120 from the buried semiconductor substrate 654 of the first functional device region 118. Figure 6 The first isolation trench 110 includes a first insulating material 112 formed on the inner sidewalls 124_1 and 126_1 of the first isolation trench 110, and the first isolation trench 110 is made of a material similar to... Figure 1A The first conductive material 114 fills the first isolation trench 110.

[0069] An optional first recessed region 128 is formed at the upper main surface 102_1 of the upper semiconductor substrate layer 108 and extends in the vertical direction y along at least a portion of the outer sidewalls 124_2, 126_2 of the first isolation trench 110. Figure 6 The first sinking zone 128 is similar to Figure 1C The first subsidence zone is 128. The difference is... Figure 6 The first recessed region 128 extends to the upper main surface 654_1 of the buried semiconductor substrate 654. Generally, the first recessed region 128 extends at least to the upper main surface 654_1 of the buried semiconductor substrate 654. Figure 6 The first sink region 128 contacts the buried semiconductor substrate 654 to provide a low-ohmic electrical connection to the buried semiconductor substrate 654.

[0070] An optional region 122 of the lower semiconductor substrate 104 is disposed at the bottom of the first isolation trench 110. Region 122 has a locally increased dopant concentration to provide improved electrical contact between the first conductive material 114 and the lower semiconductor substrate 104.

[0071] Semiconductor device 600 includes a second isolation trench 130 formed at a first main surface 102_1 of an upper semiconductor substrate layer 108 and extending in the vertical direction y. The second isolation trench 130 and Figure 1D-Figure 1G The second isolation trench 130 is similar to or identical to the second isolation trench 130, and includes a second insulating material 132 formed on the inner sidewalls 134_1, 136_1 and the bottom of the second isolation trench 130. Figure 6 In one example, the second isolation trench 130 extends through the upper semiconductor substrate 108 and through the buried semiconductor substrate 654 into the lower semiconductor substrate 104. In other examples, the second isolation trench 130 extends through the upper semiconductor substrate 108 at least to the upper main surface 654_1 of the buried semiconductor substrate 654, but does not extend through the buried semiconductor substrate 654. The first isolation trench 110 has a first width w1, and the second isolation trench 130 has a second width w2, with the first width w1 being greater than the second width w2. The first width w1 and the second width w2 can be measured at the location of the first main surface 102_1 of the upper semiconductor substrate 108. Furthermore, the first isolation trench 110 has a first depth d1, and the second isolation trench 130 has a second depth d2, with the first depth d1 being greater than the second depth d2. The first depth d1 and the second depth d2 can be measured from the location of the first main surface 102_1 of the upper semiconductor substrate 108 to the bottom of the first isolation trench 110 and the second isolation trench 130, respectively.

[0072] like Figure 6As illustrated, the second recessed region 138 is formed at the upper main surface 102_1 of the upper semiconductor substrate layer 108 and extends in the vertical direction y along at least a portion of the outer sidewalls 134_2 and 136_2 of the second isolation trench 130. The second recessed region 138 and... Figure 1G The second sinking region 138 is similar to or the same as the upper main surface 102_1 of the upper semiconductor substrate 108 and extends into the upper semiconductor substrate 108. The second sinking region 138 does not extend to the upper main surface 654_1 of the buried semiconductor substrate 654.

[0073] Figures 7A-7G A series of cross-sectional views schematically illustrate an exemplary method of manufacturing another semiconductor device 700. In one example, such as combining Figures 7A-7G The method described above can be used to manufacture similar combinations. Figure 6 The illustrated and described semiconductor device 600 is at least a portion of the semiconductor device. In another example, as will be combined Figures 7A-7G The methods described can be used to manufacture at least some of the different semiconductor devices. Figures 7A-7G Manufacturing method and Figures 4A-4G The manufacturing methods are similar but not the same.

[0074] Figure 7A The semiconductor device 700 is similar to Figure 4A The semiconductor device 400 has a structured mask layer 342 with a first opening and a second opening, and a hard mask 340. The difference is that... Figure 7A The buried semiconductor substrate 654 is not included in the middle region of the buried semiconductor substrate 654 below the first opening having a first width o1.

[0075] Figure 7B The semiconductor device 700 is similar to Figure 4B The semiconductor device 400 differs in that, after the first etching step of the two-step etching process, the first isolation trench 110 extends through the upper semiconductor substrate 108 into the intermediate trench depth between the upper main surface 654_1 of the buried semiconductor substrate 654 and the lower main surface 654_2 of the buried semiconductor substrate 106. Generally, after the first etching step, the first isolation trench 110 may not extend deeper than the lower main surface 654_2 of the buried semiconductor substrate 654. Figure 4B Another difference is that during the first etching step, the second isolation trench 130 is etched to the intermediate trench depth above the upper main surface 654_1 of the buried semiconductor substrate 654. This means that after the first etching step, the second isolation trench 130 extends into the upper semiconductor substrate 108, but does not reach the upper main surface 654_1 of the buried semiconductor substrate 654.

[0076] Figures 7C-7E A series of cross-sectional views schematically illustrate two different methods of fabricating the second recessed region 138, which extends from the upper main surface 102_1 of the upper semiconductor substrate 108 along at least a portion of the outer sidewalls 134_2, 136_2 of the second isolation trench 130, similar to... Figures 4C-4E The semiconductor device 400. The difference is... Figures 7C-7E The second recessed region 138 extends from the upper main surface 102_1 of the upper semiconductor substrate 108 into the upper semiconductor substrate 108, but does not extend into the upper main surface 654_1 of the buried semiconductor substrate 654. Figures 4C-4E Another difference is that an optional first sinking zone 128 is formed at the first isolation trench 110, which is combined with the above. Figures 3C-3E The illustrations and descriptions are similar or identical. An optional first recessed region 128 extends from the upper main surface 102_1 of the upper semiconductor substrate 108 to the upper main surface 654_1 of the buried semiconductor substrate 654 to provide a low-ohmic electrical connection to the buried semiconductor substrate 654. Although in Figure 3C In one example, the first isolation trench 110 is completely filled with PSG, but in other examples, the first isolation trench 110 is only partially filled with PSG. Figure 7C In the example, the PSG is formed to cover the inner sidewalls 124_1, 126_1 and the bottom of the first isolation trench 110. The first recessed region 128 and the second recessed region 138 can be formed simultaneously or sequentially. The simultaneous formation of the first recessed region 128 and the second recessed region 138 allows for cost-effective manufacturing of the semiconductor device 700.

[0077] Figure 7F The semiconductor device 700 is similar to Figure 4F The semiconductor device 400 extends the trench depths of a first isolation trench 110 and a second isolation trench 130 during a second etching step of a two-step etching process. After the second etching step, the first isolation trench 110 has a final first depth d1, and the second isolation trench 130 has a final second depth d2. The first depth d1 is greater than the second depth d2. Optional processing steps (not shown) may be performed to form a region with a locally increased dopant concentration at the bottom of the first isolation trench 110.

[0078] Figure 7G The semiconductor device 700 is similar to Figure 4G The semiconductor device 400, wherein a first isolation trench 110 and a second isolation trench 130 are filled with a first insulating material 112, a second insulating material 132, a first conductive material 114 and an optional second conductive material (not shown).

[0079] Figures 8A-8H A series of cross-sectional views are schematically illustrated in an exemplary method of manufacturing another semiconductor device 800. Figures 8A-8H The manufacturing method is similar to that of combining Figures 3A-3D and Figures 3F-3I The manufacturing method is illustrated and described. The difference is that the buried semiconductor substrate 654 of the semiconductor device 800 does not include the middle region of the buried semiconductor substrate 654 below the first opening having a first width o1.

[0080] exist Figures 8A-8D In the first etching step of the two-step etching process, the first isolation trench 110 is etched to the intermediate trench depth. A first recessed area 128 is formed using a PSG 346. Although in Figure 8C In the example above, the first isolation trench 110 is completely filled with PSG 346, but in other examples, the first isolation trench 110 is only partially filled with PSG 346, as described above. Figure 7C Illustrations and descriptions. Figure 8E In the second etching step, the trench depth of the first isolation trench 110 extends to its final depth d1. Figure 8F In the middle, the first isolation trench 110 is filled with the first insulating material 112. Figure 8G In this process, an optional region 122 with a locally increased dopant concentration is formed at the bottom of the first isolation trench 110. Figure 8H In the middle, the first isolation trench 110 is filled with the first conductive material 114.

[0081] Although Figures 8A-8H In the example, a two-step etching process is used to form the first isolation trench 110, but in other examples, a one-step etching process can be used. In some examples, a second isolation trench (not shown) can be formed, which is similar to or identical to the second isolation trench 130 illustrated and described in conjunction with the examples above. The first isolation trench 110 and the second isolation trench 130 can be formed simultaneously. The second recessed region (not shown) can be formed using PSG, and is similar to or identical to the second recessed region 138 illustrated and described in conjunction with the examples above. The first recessed region 128 and the second recessed region 138 can be formed simultaneously.

[0082] Figures 9A-9E A series of cross-sectional views are schematically illustrated in an exemplary method of manufacturing another semiconductor device 900. Figures 9A-9E The manufacturing method is similar to combining Figures 3A-3D and Figure 3FThe manufacturing method is illustrated and described. The difference is that the buried semiconductor substrate 654 of the semiconductor device 900 does not include the middle region of the buried semiconductor substrate 654 below the first opening having a first width o1.

[0083] exist Figures 9A-9D In the process, a first isolation trench 110 and a second isolation trench 130 are etched. A second recessed area 138 is formed using a PSG 346. Figure 9E In the process, the first isolation trench 110 and the second isolation trench 130 are filled with the first insulating material 112, the second insulating material 132 and the first conductive material 114.

[0084] Although Figures 9A-9D In this example, a one-step etching process is used to form the first isolation trench 110 and the second isolation trench 130, but in other examples, a multi-step etching process can be used. The first isolation trench 110 and the second isolation trench 130 can be formed simultaneously. An optional first recessed region 128 (not shown) can be formed in conjunction with the above. Figures 3C-3E The illustrations and descriptions are similar or identical. An optional first subsidence region 128 may be formed using PSG. The first subsidence region 128 and the second subsidence region 138 may be formed simultaneously. Optional processing steps (not shown) may be performed to form a region with a locally increased dopant concentration at the bottom of the first isolation trench 110.

[0085] Combination Figures 3A-3I , Figures 4A-4G , Figures 5A-5F , Figures 7A-7G , Figures 8A-8H , Figures 9A-9E The methods for fabricating semiconductor devices 300, 400, 500, 700, 800, and 900 illustrated and described are provided as examples. Unless otherwise indicated, the fabrication steps described do not necessarily have to be performed in the given order. Some of the fabrication steps may be performed simultaneously. Different, additional, and / or intermediate fabrication steps may be present. In one example, well regions and / or doped regions may be formed in the upper semiconductor substrate 108 to form portions of a functional device. These well regions and / or doped regions may be formed by diffusion and / or implantation. In one example, interface regions may be formed to electrically isolate the device structures from each other. These interface regions may be formed at least partially within the upper semiconductor substrate 108. These interface regions may include shallow trench isolation (STI) and / or localized oxidation of silicon (LOCOS) structures.

[0086] Examples of the invention are summarized herein. Other examples may also be understood from the description and claims submitted herein in their entirety.

[0087] Example 1: A semiconductor device comprising: Lower semiconductor substrate of the first conductivity type; Upper semiconductor substrate layer; A patterned buried semiconductor substrate layer is interposed between a lower semiconductor substrate layer and an upper semiconductor substrate layer, wherein the patterned buried semiconductor substrate layer comprises: The first part of the second conductivity type The second part of the second conductivity type, which is laterally spaced from the first part, and The intermediate area, which is arranged laterally between the first and second parts; and A first isolation trench is formed on the upper main surface of the upper semiconductor substrate and extends vertically through the upper semiconductor substrate and through the middle region of the patterned buried semiconductor substrate into the lower semiconductor substrate. The first isolation trench is spaced apart from the first portion of the patterned buried semiconductor substrate and the second portion of the patterned buried semiconductor substrate; The first isolation trench includes a first insulating material formed on the inner sidewall of the first isolation trench, and The first isolation trench is filled with a first conductive material.

[0088] Example 2: The semiconductor device according to Example 1 further includes: A first recessed region is formed on the upper main surface of the upper semiconductor substrate and extends vertically along at least a portion of the outer sidewall of the first isolation trench.

[0089] Example 3: The semiconductor device according to Example 2, wherein the highly doped portion of the first sink region is spaced apart from the first portion of the patterned buried semiconductor substrate and the second portion of the patterned buried semiconductor substrate.

[0090] Example 4: A semiconductor device according to any one of Examples 2 or 3, wherein the first sink region extends from the upper main surface of the upper semiconductor substrate layer to a depth defined by the upper main surface of the patterned buried semiconductor substrate layer.

[0091] Example 5: The semiconductor device according to any one of the foregoing examples further includes: A region of the lower semiconductor substrate layer disposed at the bottom of the first isolation trench, wherein the region has a locally increased dopant concentration.

[0092] Example 6: The semiconductor device according to any one of the foregoing examples further includes: A second isolation trench is formed on a first main surface of the upper semiconductor substrate and extends in a vertical direction, wherein the second isolation trench includes a second insulating material formed on the inner sidewall and bottom of the second isolation trench.

[0093] Example 7: The semiconductor device according to Example 6, wherein the second isolation trench extends through the upper semiconductor substrate layer and through the patterned buried semiconductor substrate layer into the lower semiconductor substrate layer.

[0094] Example 8: The semiconductor device according to Example 6, wherein the second isolation trench extends through the upper semiconductor substrate layer to at least the upper main surface of the patterned buried semiconductor substrate layer, but does not extend through the patterned buried semiconductor substrate layer.

[0095] Example 9: A semiconductor device according to any one of Examples 6 to 8, wherein the second isolation trench has a second width, and the first isolation trench has a first width greater than the second width, and / or The second isolation trench has a second depth, and the first isolation trench has a first depth greater than the second depth.

[0096] Example 10: The semiconductor device according to any one of Examples 6 to 9 further comprises: The second sinking region is formed on the upper main surface of the upper semiconductor substrate and extends vertically along at least a portion of the outer sidewall of the second isolation trench.

[0097] Example 11: The semiconductor device according to Example 10, wherein the second sink region extends from the upper main surface of the upper semiconductor substrate layer through the upper semiconductor substrate layer to at least the upper main surface of the patterned buried semiconductor substrate layer.

[0098] Example 12: A method of manufacturing a semiconductor device, comprising: A buried semiconductor substrate is formed on a lower semiconductor substrate of the first conductivity type; The buried semiconductor substrate is patterned to form a first portion of a second conductivity type, a second portion of the second conductivity type laterally spaced from the first portion, and an intermediate region laterally disposed between the first portion and the second portion. An upper semiconductor substrate is formed on top of a patterned buried semiconductor substrate; A first isolation trench is formed, which extends vertically from the upper main surface of the upper semiconductor substrate, passes through the upper semiconductor substrate, passes through the middle region of the patterned buried semiconductor substrate, and enters the lower semiconductor substrate. The first isolation trench is spaced apart from the first portion of the patterned buried semiconductor substrate and the second portion of the patterned buried semiconductor substrate; A first insulating material is formed covering the inner wall of the first isolation trench, and The first isolation trench is filled with a first conductive material.

[0099] Example 13: The method described in Example 12 further includes: Before filling the first isolation trench with the first conductive material, a dopant of the first conductivity type is introduced into the first isolation trench to form a region of the lower semiconductor substrate layer disposed at the bottom of the first isolation trench, wherein the region has a locally increased dopant concentration.

[0100] Example 14: The method according to any one of Examples 12 or 13, wherein forming the first isolation trench includes an etching step.

[0101] Example 15: The method according to any one of Examples 12 or 13, wherein forming the first isolation trench includes a multi-step etching process. In the first etching step of the multi-step etching process, the first isolation trench is etched to the depth of the intermediate trench, and In the second etching step of the multi-step etching process, the trench depth of the first isolation trench is extended.

[0102] Example 16: The method according to any one of Examples 12 to 15 further includes: A first sink region is formed, which extends vertically from the upper main surface of the upper semiconductor substrate along at least a portion of the outer sidewall of the first isolation trench.

[0103] Example 17: The method according to Example 16, wherein the highly doped portion of the first sink region is spaced apart from the first portion of the patterned buried semiconductor substrate and the second portion of the patterned buried semiconductor substrate.

[0104] Example 18: The method according to any one of Examples 16 or 17, wherein the first sink region extends from the upper main surface of the upper semiconductor substrate layer to a depth defined by the upper main surface of the patterned buried semiconductor substrate layer.

[0105] Example 19: The method according to any one of Examples 16 to 18, wherein forming the first sinking zone includes: Before the first insulating material is formed, ions are implanted into the outer wall of the first isolation trench through the inner wall of the first isolation trench.

[0106] Example 20: The method according to any one of Examples 16 to 18, wherein forming the first sinking zone includes: Before forming the first insulating material, a PSG (phosphosilicate glass) is formed covering the inner walls and bottom of the first insulating trench, and The phosphorus in the PSG is diffused into the outer wall of the first isolation trench.

[0107] Example 21: The method according to any one of Examples 16 to 20 combined with Example 14, wherein the first sinking region is formed after a one-step etching process.

[0108] Example 22: The method according to any one of Examples 16 to 20 in combination with Example 15, wherein the first sink region is formed after the first etching step of the multi-step etching process and before the second etching step of the multi-step etching process.

[0109] Example 23: The method according to any one of Examples 12 to 22 further includes: A second isolation trench is formed, which extends vertically from the upper main surface of the upper semiconductor substrate layer, and A second insulating material is formed to cover the inner wall and bottom of the second isolation trench.

[0110] Example 24: The method according to Example 23, wherein the second isolation trench extends through the upper semiconductor substrate and through the patterned buried semiconductor substrate into the lower semiconductor substrate.

[0111] Example 25: The method according to Example 23, wherein the second isolation trench extends through the upper semiconductor substrate layer to at least the upper main surface of the patterned buried semiconductor substrate layer, but does not extend through the patterned buried semiconductor substrate layer.

[0112] Example 26: The method according to any one of Examples 23 to 25, wherein the second isolation trench has a second width, and the first isolation trench has a first width greater than the second width, and / or The second isolation trench has a second depth, and the first isolation trench has a first depth greater than the second depth.

[0113] Example 27: The method according to any one of Examples 23 to 26, wherein forming the second isolation trench includes an etching step.

[0114] Example 28: The method according to any one of Examples 23 to 26, wherein forming the second isolation trench includes a multi-step etching process. In the first etching step of the multi-step etching process, the second isolation trench is etched to the depth of the intermediate trench, and In the second etching step of the multi-step etching process, the trench depth of the second isolation trench is extended.

[0115] Example 29: The method according to any one of Examples 23 to 28, wherein the first isolation trench and the second isolation trench are formed simultaneously.

[0116] Example 30: The method according to any one of Examples 23 to 29 further includes: A second sink region is formed, which extends vertically from the upper main surface of the upper semiconductor substrate along at least a portion of the outer sidewall of the second isolation trench.

[0117] Example 31: According to the method of Example 30, the second sink region extends from the upper main surface of the upper semiconductor substrate through the upper semiconductor substrate to at least the upper main surface of the patterned buried semiconductor substrate.

[0118] Example 32: The method according to any one of Examples 30 or 31, wherein forming the second sinking zone comprises: Before forming the second insulating material, ions are implanted into the outer wall of the second isolation trench through the inner wall of the second isolation trench.

[0119] Example 33: The method according to any one of Examples 30 or 31, wherein forming the second sinking zone comprises: Before forming the second insulating material, a PSG (phosphosilicate glass) is formed to at least cover the inner walls and bottom of the second insulating trench, and The phosphorus in the PSG is diffused into the outer wall of the second isolation trench.

[0120] Example 34: The method according to any one of Examples 30 to 33 in combination with Example 27, wherein the second sinking region is formed after a one-step etching process of the second isolation trench.

[0121] Example 35: The method according to any one of Examples 30 to 33 in combination with Example 28, wherein a second sinking region is formed after the first etching step of the multi-step etching process of the second isolation trench and before the second etching step of the multi-step etching process of the second isolation trench.

[0122] Example 36: The method described in combination with Example 16 according to any one of Examples 30 to 35, wherein the first sinking region and the second sinking region are formed simultaneously.

[0123] Example 37: A semiconductor device comprising: Lower semiconductor substrate of the first conductivity type; Upper semiconductor substrate layer; A buried semiconductor substrate of the second conductivity type is inserted between a lower semiconductor substrate and an upper semiconductor substrate. A first isolation trench is formed on the upper main surface of the upper semiconductor substrate and extends vertically through the upper semiconductor substrate and the buried semiconductor substrate into the lower semiconductor substrate. The first isolation trench includes a first insulating material formed on the inner sidewall of the first isolation trench, and The first isolation trench is filled with a first conductive material. The second isolation trench is formed on the first main surface of the upper semiconductor substrate and extends in the vertical direction. The second isolation trench includes a second insulating material formed on the inner wall and bottom of the second isolation trench, and The second recessed region is formed on the upper main surface of the upper semiconductor substrate layer and extends vertically along at least a portion of the outer sidewall of the second isolation trench. The second sinking region extends from the upper main surface of the upper semiconductor substrate to the upper semiconductor substrate, but does not extend to the upper main surface of the buried semiconductor substrate.

[0124] Example 38: The semiconductor device according to Example 37 further includes: A first recessed region is formed on the upper main surface of the upper semiconductor substrate and extends vertically along at least a portion of the outer sidewall of the first isolation trench.

[0125] Example 39: The semiconductor device according to Example 38, wherein the first sink region extends from the upper main surface of the upper semiconductor substrate layer to at least the upper main surface of the buried semiconductor substrate layer.

[0126] Example 40: The semiconductor device according to any one of Examples 37 to 39 further comprises: A region of the lower semiconductor substrate layer disposed at the bottom of the first isolation trench, wherein the region has a locally increased dopant concentration.

[0127] Example 41: A semiconductor device according to any one of Examples 37 to 40, wherein a second isolation trench extends through an upper semiconductor substrate and through a buried semiconductor substrate into a lower semiconductor substrate.

[0128] Example 42: A semiconductor device according to any one of Examples 37 to 40, wherein the second isolation trench extends through the upper semiconductor substrate layer to at least the upper main surface of the buried semiconductor substrate layer, but does not extend through the buried semiconductor substrate layer.

[0129] Example 43: A semiconductor device according to any one of Examples 37 to 42, wherein the second isolation trench has a second width, and the first isolation trench has a first width greater than the second width, and / or The second isolation trench has a second depth, and the first isolation trench has a first depth greater than the second depth.

[0130] Example 44: A method of manufacturing a semiconductor device, comprising: A buried semiconductor substrate of the second conductivity type is formed on a lower semiconductor substrate of the first conductivity type; An upper semiconductor substrate layer is formed on top of a buried semiconductor substrate layer; A first isolation trench is formed, which extends vertically from the upper main surface of the upper semiconductor substrate, through the upper semiconductor substrate, and through the buried semiconductor substrate into the lower semiconductor substrate. A first insulating material is formed to cover the inner wall of the first isolation trench; The first isolation trench is filled with a first conductive material; A second isolation trench is formed, which extends vertically from the upper main surface of the upper semiconductor substrate layer; A second insulating material is formed covering the inner wall and bottom of the second isolation trench; and A second recessed region is formed, which extends vertically from the upper main surface of the upper semiconductor substrate layer along at least a portion of the outer sidewall of the second isolation trench. The second sinking region extends from the upper main surface of the upper semiconductor substrate to the upper semiconductor substrate, but does not extend to the upper main surface of the buried semiconductor substrate.

[0131] Example 45: The method described in Example 44 further includes: Before filling the first isolation trench with the first conductive material, a dopant of the first conductivity type is introduced into the first isolation trench to form a region of the lower semiconductor substrate layer disposed at the bottom of the first isolation trench, wherein the region has a locally increased dopant concentration.

[0132] Example 46: The method according to any one of Examples 44 or 45, wherein forming the first isolation trench includes a multi-step etching process. In the first etching step of the multi-step etching process, the first isolation trench is etched to the depth of the intermediate trench, and In the second etching step of the multi-step etching process, the trench depth of the first isolation trench is extended.

[0133] Example 47: The method according to any one of Examples 44 to 46 further includes: A first sink region is formed, which extends vertically from the upper main surface of the upper semiconductor substrate along at least a portion of the outer sidewall of the first isolation trench.

[0134] Example 48: The method according to Example 47, wherein the first sink region extends from the upper main surface of the upper semiconductor substrate layer to at least the upper main surface of the buried semiconductor substrate layer.

[0135] Example 49: The method according to any one of Examples 47 or 48, wherein forming the first sinking zone includes: Before the first insulating material is formed, ions are implanted into the outer wall of the first isolation trench through the inner wall of the first isolation trench.

[0136] Example 50: The method according to any one of Examples 47 or 48, wherein forming the first sinking zone includes: Before forming the first insulating material, a PSG (phosphosilicate glass) is formed covering the inner walls and bottom of the first insulating trench, and The phosphorus in the PSG is diffused into the outer wall of the first isolation trench.

[0137] Example 51: The method according to any one of Examples 47 to 50 in combination with Example 46, wherein the first sinking region is formed after the first etching step of the multi-step etching process and before the second etching step of the multi-step etching process.

[0138] Example 52: The method according to any one of Examples 44 to 51, wherein the second isolation trench extends through the upper semiconductor substrate layer and through the buried semiconductor substrate layer into the lower semiconductor substrate layer.

[0139] Example 53: The method according to any one of Examples 44 to 51, wherein the second isolation trench extends through the upper semiconductor substrate layer at least to the upper main surface of the buried semiconductor substrate layer, but does not extend through the buried semiconductor substrate layer.

[0140] Example 54: The method according to any one of Examples 44 to 53, wherein the second isolation trench has a second width, and the first isolation trench has a first width greater than the second width, and / or The second isolation trench has a second depth, and the first isolation trench has a first depth greater than the second depth.

[0141] Example 55: The method according to any one of Examples 44 to 54, wherein forming the second isolation trench includes a multi-step etching process. In the first etching step of the multi-step etching process, the second isolation trench is etched to the depth of the intermediate trench, and In the second etching step of the multi-step etching process, the trench depth of the second isolation trench is extended.

[0142] Example 56: According to the method of Example 55, a second sinking region is formed after the first etching step of the multi-step etching process of the second isolation trench and before the second etching step of the multi-step etching process of the second isolation trench.

[0143] Example 57: The method according to any one of Examples 44 to 56, wherein the first isolation trench and the second isolation trench are formed simultaneously.

[0144] Example 58: The method according to any one of Examples 44 to 57, wherein forming the second sinking zone comprises: Before forming the second insulating material, ions are implanted into the outer wall of the second isolation trench through the inner wall of the second isolation trench.

[0145] Example 59: The method according to any one of Examples 44 to 57, wherein forming the second sinking zone comprises: Before forming the second insulating material, a PSG (phosphosilicate glass) is formed to at least cover the inner walls and bottom of the second insulating trench, and The phosphorus in the PSG is diffused into the outer wall of the second isolation trench.

[0146] Example 60: The method according to any one of Examples 47 to 59, wherein the first sinking zone and the second sinking zone are formed simultaneously.

[0147] Example 61: A method of manufacturing a semiconductor device, comprising: A buried semiconductor substrate of the second conductivity type is formed on a lower semiconductor substrate of the first conductivity type; An upper semiconductor substrate layer is formed on top of a buried semiconductor substrate layer; A first isolation trench is formed, which extends vertically from the upper main surface of the upper semiconductor substrate, through the upper semiconductor substrate, and through the buried semiconductor substrate into the lower semiconductor substrate. A first insulating material is formed to cover the inner wall of the first isolation trench; The first isolation trench is filled with a first conductive material; and A first recessed region is formed, which extends vertically from the upper main surface of the upper semiconductor substrate layer along at least a portion of the outer sidewall of the first isolation trench, wherein forming the first recessed region includes: Before forming the first insulating material, a PSG (phosphosilicate glass) is formed covering the inner wall and bottom of the first isolation trench, and the phosphorus of the PSG is diffused into the outer wall of the first isolation trench.

[0148] Example 62: The method according to Example 61, wherein forming the first isolation trench includes an etching step.

[0149] Example 63: The method according to Example 61, wherein forming the first isolation trench includes a multi-step etching process. In the first etching step of the multi-step etching process, the first isolation trench is etched to the depth of the intermediate trench. In the second etching step of the multi-step etching process, the trench depth of the first isolation trench is extended, and The first sinking zone is formed after the first etching step of the multi-step etching process and before the second etching step of the multi-step etching process.

[0150] Example 64: The method according to any one of Examples 61 to 63 further includes: A second isolation trench is formed, which extends vertically from the upper main surface of the upper semiconductor substrate layer. A second insulating material is formed to cover the inner wall and bottom of the second isolation trench. A second recessed region is formed, which extends vertically from the upper main surface of the upper semiconductor substrate layer along at least a portion of the outer sidewall of the second isolation trench. The formation of the second subsidence zone includes: Before forming the second insulating material, a PSG (phosphosilicate glass) is formed to at least cover the inner walls and bottom of the second insulating trench, and The phosphorus in the PSG is diffused into the outer wall of the second isolation trench.

[0151] Example 65: The method described in Example 64, wherein the first isolation trench and the second isolation trench are formed simultaneously.

[0152] Example 66: A method of manufacturing a semiconductor device, comprising: A buried semiconductor substrate of the second conductivity type is formed on a lower semiconductor substrate of the first conductivity type; An upper semiconductor substrate layer is formed on top of a buried semiconductor substrate layer; A first isolation trench is formed, which extends vertically from the upper main surface of the upper semiconductor substrate, through the upper semiconductor substrate, and through the buried semiconductor substrate into the lower semiconductor substrate. A first insulating material is formed to cover the inner wall of the first isolation trench; The first isolation trench is filled with a first conductive material; A second isolation trench is formed, which extends vertically from the upper main surface of the upper semiconductor substrate layer, and A second insulating material is formed to cover the inner wall and bottom of the second isolation trench; Forming a second sink region that extends vertically from the upper main surface of the upper semiconductor substrate along at least a portion of the outer sidewall of the second isolation trench, wherein forming the second sink region includes: Before forming the second insulating material, a PSG (phosphosilicate glass) is formed to at least cover the inner walls and bottom of the second insulating trench, and The phosphorus in the PSG is diffused into the outer wall of the second isolation trench.

[0153] Example 67: The method according to Example 66, wherein forming the second isolation trench includes an etching process.

[0154] Example 68: The method according to Example 66, wherein forming the second isolation trench includes a multi-step etching process. In the first etching step of the multi-step etching process, the second isolation trench is etched to the depth of the intermediate trench. In the second etching step of the multi-step etching process, the trench depth of the second isolation trench is extended, and The second subsidence zone is formed after the first etching step of the multi-step etching process and before the second etching step of the multi-step etching process.

[0155] Example 69: The method according to any one of Examples 66 to 68, wherein the first isolation trench and the second isolation trench are formed simultaneously.

[0156] Although the invention has been described with reference to illustrative examples, this description is not intended to be limiting. Various modifications and combinations of the illustrative examples and other examples will be apparent to those skilled in the art during the description. Therefore, the appended claims are intended to cover any such modifications or examples.

Claims

1. A semiconductor device (100A-100G, 200A and 200B, 300-500), comprising: Lower semiconductor substrate (104) of the first conductivity type. Upper semiconductor substrate (108); A patterned buried semiconductor substrate (106) is interposed between a lower semiconductor substrate (104) and an upper semiconductor substrate (108), wherein the patterned buried semiconductor substrate (106) comprises: The first part of the second conductivity type (106_1). The second part (106_2) of the second conductivity type is laterally spaced from the first part (106_1), and The intermediate section (106_3) is arranged laterally between the first part (106_1) and the second part (106_2); and A first isolation trench (110) is formed on the upper main surface (102_1) of the upper semiconductor substrate (108) and extends in the vertical direction (y) through the upper semiconductor substrate (108) and through the middle region (106_3) of the patterned buried semiconductor substrate (106) into the lower semiconductor substrate (104). The first isolation trench (110) is spaced apart from the first portion (106_1) and the second portion (106_2) of the patterned buried semiconductor substrate (106); The first isolation trench (110) includes a first insulating material (112) formed on the inner sidewalls (124_1, 126_1) of the first isolation trench (110), and The first isolation trench (110) is filled with a first conductive material (114).

2. The semiconductor device (100C–100G, 200A and 200B, 300–500) according to claim 1, further comprising: The first recessed region (128) is formed on the upper main surface (102_1) of the upper semiconductor substrate layer (108) and extends in the vertical direction (y) along at least a portion of the outer sidewalls (124_2, 126_2) of the first isolation trench (110).

3. The semiconductor device (100C-100G, 200A and 200B, 300-500) according to claim 2, wherein the highly doped portion of the first subsidence region (128) is spaced apart from the first portion (106_1) and the second portion (106_2) of the patterned buried semiconductor substrate (106).

4. The semiconductor device (100C-100G, 200A and 200B, 300-500) according to any one of claims 2 or 3, wherein the first recessed region (128) extends from the upper main surface (102_1) of the upper semiconductor substrate (108) to a depth (dc) defined by the upper main surface (106_4) of the patterned buried semiconductor substrate (106).

5. The semiconductor device (100B, 300) according to any one of the preceding claims further comprises: A region (122) of the lower semiconductor substrate layer (104) arranged at the bottom of the first isolation trench (110), wherein the region (122) has a locally increased dopant concentration.

6. The semiconductor device (100D–100G, 200B, 400, and 500) according to any one of the preceding claims further comprises: A second isolation trench (130) is formed on a first main surface (102_1) of an upper semiconductor substrate layer (108) and extends in a vertical direction (y), wherein the second isolation trench (130) includes a second insulating material (132) formed on the inner sidewalls (134_1, 136_1) and the bottom of the second isolation trench (130).

7. The semiconductor device (100D, 100G, 200B, 400) according to claim 6, wherein the second isolation trench (130) extends through the upper semiconductor substrate (108) and through the patterned buried semiconductor substrate (106) into the lower semiconductor substrate (104).

8. The semiconductor device (100E, 100F, 200B, 500) according to claim 6, wherein the second isolation trench (130) extends through the upper semiconductor substrate (108) at least to the upper main surface (106_4) of the patterned buried semiconductor substrate (106), but does not extend through the patterned buried semiconductor substrate (106).

9. The semiconductor device (100G–100G, 200B, 400, and 500) according to any one of claims 6 to 8, wherein the second isolation trench (130) has a second width (w2), and the first isolation trench (110) has a first width (w1) greater than the second width (w2), and / or The second isolation trench (130) has a second depth (d2), and the first isolation trench (110) has a first depth (d1) greater than the second depth (d2).

10. The semiconductor device (100F and 100G, 200B, 400 and 500) according to any one of claims 6 to 9, further comprising: The second recessed region (138) is formed on the upper main surface (102_1) of the upper semiconductor substrate layer (108) and extends in the vertical direction (y) along at least a portion of the outer sidewalls (134_2, 136_2) of the second isolation trench (130).

11. The semiconductor device (100F, 200B, 400 and 500) according to claim 10, wherein the second sink region (138) extends from the upper main surface (102_1) of the upper semiconductor substrate (108) through the upper semiconductor substrate (108) to at least the upper main surface (106_4) of the patterned buried semiconductor substrate (106).

12. A method for manufacturing semiconductor devices (100A-100G, 200A and 200B, 300-500), comprising: A buried semiconductor substrate is formed on a lower semiconductor substrate (104) of the first conductivity type; The buried semiconductor substrate is patterned to form a first portion (106_1) of a second conductivity type, a second portion (106_2) of the second conductivity type laterally spaced from the first portion (106_1), and an intermediate region (106_3) laterally arranged between the first portion (106_1) and the second portion (106_2). An upper semiconductor substrate (108) is formed on top of a patterned buried semiconductor substrate (106). A first isolation trench (110) is formed, which extends in the vertical direction (y) from the upper main surface (102_1) of the upper semiconductor substrate (108), through the upper semiconductor substrate (108), and through the middle region (106_3) of the patterned buried semiconductor substrate (106) into the lower semiconductor substrate (104). The first isolation trench (110) is spaced apart from the first portion (106_1) and the second portion (106_2) of the patterned buried semiconductor substrate (106); A first insulating material (112) is formed to cover the inner sidewalls (124_1, 126_1) of the first insulating trench (110), and The first isolation trench (110) is filled with the first conductive material (114).

13. The method of claim 12, further comprising: Before filling the first isolation trench (110) with the first conductive material (114), a dopant of the first conductivity type is introduced into the first isolation trench (110) to form a region (122) of the lower semiconductor substrate layer (104) disposed at the bottom of the first isolation trench (110), wherein the region (122) has a locally increased dopant concentration.

14. The method according to any one of claims 12 or 13, further comprising: A first recessed region (128) is formed, which extends in the vertical direction (y) from the upper main surface (102_1) of the upper semiconductor substrate layer (108) along at least a portion of the outer sidewalls (124_2, 126_2) of the first isolation trench (110).

15. The method of claim 14, wherein the highly doped portion of the first subsidence region (128) is spaced apart from the first portion (106_1) and the second portion (106_2) of the patterned buried semiconductor substrate (106).

16. The method according to any one of claims 14 or 15, wherein forming the first sinking region (128) comprises: Before forming the first insulating material (112), a PSG (phosphosilicate glass) is formed covering the inner sidewalls (124_1, 126_1) and bottom of the first insulating trench (110), and The phosphorus of PSG is diffused into the outer walls (124_2, 126_2) of the first isolation trench (110).

17. The method according to any one of claims 12 to 16, further comprising: A second isolation trench (130) is formed, which extends vertically (y) from the upper main surface (102_1) of the upper semiconductor substrate layer (108), and A second insulating material (132) is formed covering the inner wall (134_1, 136_1) and bottom of the second isolation trench (130).

18. The method of claim 17, wherein the second isolation trench (130) has a second width (w2), and the first isolation trench (110) has a first width (w1) greater than the second width (w2), and / or The second isolation trench (130) has a second depth (d2), and the first isolation trench (110) has a first depth (d1) greater than the second depth (d2).

19. The method according to any one of claims 17 or 18, further comprising: A second sink region (138) is formed, which extends in the vertical direction (y) from the upper main surface (102_1) of the upper semiconductor substrate layer (108) along at least a portion of the outer sidewalls (134_2, 136_2) of the second isolation trench (130).

20. The method of claim 19, wherein forming the second sinking region (138) comprises: Before forming the second insulating material (132), a PSG (phosphosilicate glass) is formed that at least covers the inner sidewalls (134_1, 136_1) and bottom of the second insulating trench (130), and The phosphorus of PSG is diffused into the outer walls (134_2, 136_2) of the second isolation trench (130).

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