A method for manufacturing a semiconductor structure
By forming an etch stop layer, an oxide layer, and a silicon nitride layer in a semiconductor structure and performing patterning, the problem of protrusion morphology caused by aluminum redistribution layers is solved, achieving the effects of simplified process and improved electrical performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HANGZHOU FULLSEMI SEMICON CO LTD
- Filing Date
- 2026-04-28
- Publication Date
- 2026-07-14
AI Technical Summary
In 90 nm/55 nm and more advanced processes, aluminum redistribution layers (Al RDL) cause obvious protrusions on the surface of the outermost passivation layer of the chip, making it difficult to meet the electrical performance, process simplification and device reliability requirements of subsequent etching and packaging processes.
By sequentially forming an etch stop layer, an oxide layer, and a silicon nitride layer on the metal interconnect layer and performing patterning, the exposed etch stop layer is removed by etching to form a window in the metal circuit layer, and byproducts on the inner wall of the window are removed, simplifying the passivation layer preparation process, and encapsulating with a copper redistribution layer (Cu RDL).
This technology achieves a flat semiconductor structure surface, simplifies the fabrication process, improves the electrical performance and reliability of the device, meets the requirements of subsequent etching and packaging processes, reduces fabrication costs, and improves the device's density, shielding performance, and chemical stability.
Smart Images
Figure CN122396291A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and relates to a method for preparing a semiconductor structure. Background Technology
[0002] In current 90 nm / 55 nm and more advanced processes, aluminum is often used as a metal interconnect material due to its low resistivity and good self-passivation properties. Typically, after completing the aluminum redistribution layer (Al RDL), passivation layer, and vias on the metal interconnect layer, the wafer can be shipped to the packaging and testing plant for packaging. However, when aluminum RDLs are set up alone, the thickness of the aluminum lines can cause obvious protrusions on the surface of the outermost passivation layer of the chip, making it difficult to meet the specific requirements of customers in subsequent packaging and testing plants regarding related processes, electrical performance, process simplification, and device reliability.
[0003] Therefore, how to provide a method for fabricating semiconductor structures to meet customers' needs in subsequent etching and packaging processes, improve the electrical performance and reliability of devices, and simplify the fabrication process has become an important problem that needs to be solved by those skilled in the art.
[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention
[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for fabricating a semiconductor structure to solve the problem that when aluminum RDL is set alone in the prior art, the thickness of the aluminum line will cause obvious bulge morphology on the surface of the outermost passivation layer of the chip, which makes it difficult to meet the specific needs of customers in terms of subsequent etching processes, electrical performance, process simplification and device reliability.
[0006] To achieve the above and other related objectives, the present invention provides a method for preparing a semiconductor structure, comprising the following steps:
[0007] A substrate is provided, on which at least one metal interconnect layer is formed, the metal interconnect layer including an insulating dielectric layer and a metal circuit layer located in the insulating dielectric layer;
[0008] An etch stop layer, an oxide layer, and a silicon nitride layer are sequentially formed on the metal interconnect layer;
[0009] The silicon nitride layer and the oxide layer are patterned to form an opening that exposes a portion of the etch stop layer;
[0010] An etching process is used to remove the exposed etching stop layer, forming a window that exposes a portion of the metal circuit layer;
[0011] By removing the byproducts from the inner wall of the window, a semiconductor structure is obtained.
[0012] Optionally, patterning the silicon nitride layer and the oxide layer to form an opening that exposes a portion of the etch stop layer includes the following steps:
[0013] A patterned photoresist layer is formed on the silicon nitride layer;
[0014] Photolithography is performed on the silicon nitride layer and the oxide layer based on the photoresist layer to obtain the opening that exposes part of the etch stop layer, and then the photoresist layer is removed.
[0015] Optionally, before forming the photoresist layer, the step of forming a sacrificial layer on the silicon nitride layer is further included.
[0016] Optionally, the ratio of the thickness of the sacrificial layer to the thickness of the etch stop layer is in the range of 0.5 to 1.5.
[0017] Optionally, the material of the sacrificial layer includes silicon oxide, amorphous carbon, titanium nitride, or tantalum nitride.
[0018] Optionally, removing byproducts from the inner wall of the window includes the following steps:
[0019] The inner wall of the window is dry-cleaned.
[0020] Optionally, the etching gas used in the dry cleaning includes one or more of O2, N2, H2, CF4, NF3, SF6, and NH3.
[0021] Optionally, the number of metal interconnect layers may be multiple.
[0022] Optionally, the metal wiring layers in adjacent metal interconnect layers are electrically connected by metal pillars, and the window exposes a portion of the uppermost metal wiring layer.
[0023] Optionally, the metal pillar penetrates the insulating dielectric layer between adjacent metal circuit layers.
[0024] As described above, the method for fabricating a semiconductor structure according to the present invention includes the following steps: providing a substrate, on which at least one metal interconnect layer is formed, the metal interconnect layer including an insulating dielectric layer and a metal circuit layer located in the insulating dielectric layer; sequentially forming an etch stop layer, an oxide layer, and a silicon nitride layer on the metal interconnect layer; patterning the silicon nitride layer and the oxide layer to form an opening exposing a portion of the etch stop layer; removing the exposed etch stop layer using an etching process to form a window exposing a portion of the metal circuit layer; removing byproducts on the inner wall of the window to obtain a semiconductor structure. The method for fabricating a semiconductor structure according to the present invention can meet the needs of customers in subsequent etching and packaging processes, simplifying the fabrication process while improving the electrical performance and reliability of the device. Attached Figure Description
[0025] Figure 1 The diagram shows a schematic of the substrate structure in a method for fabricating a redistribution layer.
[0026] Figure 2 This diagram illustrates the structure obtained after forming a patterned photoresist layer in a method for fabricating a redistribution layer.
[0027] Figure 3 This is a schematic diagram of the structure obtained after photolithography of the first passivation layer in a method for fabricating a redistribution layer.
[0028] Figure 4 This diagram illustrates the structure obtained after removing the photoresist layer in a method for fabricating a redistribution layer.
[0029] Figure 5 This diagram illustrates the structure obtained after forming the first window in a method for fabricating a redistribution layer.
[0030] Figure 6 This diagram illustrates the structure obtained after removing byproducts from the inner wall of a window in a method for preparing a redistribution layer.
[0031] Figure 7 This diagram illustrates the structure obtained after forming an aluminum layer in a method for preparing a redistribution layer.
[0032] Figure 8 This diagram illustrates the structure obtained after forming an aluminum circuit layer in a method for preparing a redistribution layer.
[0033] Figure 9 This diagram illustrates the structure obtained after forming a second passivation layer in a method for fabricating a redistribution layer.
[0034] Figure 10 This diagram illustrates the structure obtained after forming a second window in a method for fabricating a redistribution layer.
[0035] Figure 11 The diagram shown is a process flow chart of the semiconductor fabrication method of the present invention.
[0036] Figure 12 The diagram shows a schematic of the substrate structure in the semiconductor fabrication method of the present invention.
[0037] Figure 13 This diagram illustrates the structure obtained after forming an etch stop layer, an oxide layer, and a silicon nitride layer in a method for fabricating a redistribution layer.
[0038] Figure 14 This diagram illustrates the structure obtained after patterning a silicon nitride layer and an oxide layer in a method for fabricating a redistribution layer.
[0039] Figure 15 This diagram illustrates the structure obtained after forming a patterned photoresist layer in a method for fabricating a redistribution layer.
[0040] Figure 16 This diagram illustrates the structure obtained after photolithography of a silicon nitride layer and an oxide layer in a method for fabricating a redistribution layer.
[0041] Figure 17 This diagram illustrates the structure obtained after removing the photoresist layer in a method for fabricating a redistribution layer.
[0042] Figure 18 This diagram illustrates the structure obtained after windowing in a method for fabricating a redistribution layer.
[0043] Figure 19 This diagram illustrates the structure obtained by removing byproducts from the inner wall of a window during a method for preparing a redistribution layer.
[0044] Explanation of reference numerals in the attached figures
[0045] 101、201 substrate 102、202 Metal interconnect layer 1021、2021 Insulating dielectric layer 1022、2022 Metallic circuit layer 103、203 Etching stop layer 104 First passivation layer 1041 First oxide layer 1042 First silicon nitride layer 1043 Second oxide layer 105、206 Photoresist layer 106 First window 107、209 byproducts 108 aluminum layer 109 Aluminum circuit layer 110 Second passivation layer 1101 Third oxide layer 1102 Second silicon nitride layer 111 Second window 204 Oxide layer 205 silicon nitride layer 207 Sacrificial layer 208 Open the window S1~S5 step Detailed Implementation
[0046] Currently, in 90 nm / 55 nm and more advanced processes, aluminum is often used as a metal wiring material due to its low resistivity and good self-passivation properties. After the aluminum redistribution layer (Al RDL) process is completed in the wafer fab, the wafer is shipped to the packaging and testing plant for packaging. The specific fabrication steps of this redistribution layer are as follows:
[0047] (1) Please refer to Figure 1A substrate 101 is provided, on which a metal interconnect layer 102 is formed. The metal interconnect layer 102 includes an insulating dielectric layer 1021 and a metal line layer 1022 located in the insulating dielectric layer 1021. An etch stop layer 103 and a first passivation layer 104 are sequentially formed on the metal interconnect layer 102. The first passivation layer 104 includes a first oxide layer 1041, a first silicon nitride layer 1042 and a second oxide layer 1043 stacked from bottom to top.
[0048] (2) Please refer to Figure 2 A patterned photoresist layer 105 is formed on the first passivation layer 104.
[0049] (3) Please refer to Figure 3 Based on the photoresist layer 105, the first passivation layer 104 is photolithographically etched to expose a portion of the etching stop layer 103.
[0050] (4) Please refer to Figure 4 Remove the photoresist layer 105.
[0051] (5) Please refer to Figure 5 The exposed etching stop layer 103 is removed by etching process to form the first window 106 of the exposed metal circuit layer 1022. It should be noted that this step is completed in the same etching chamber as steps (3) and (4).
[0052] (6) Please refer to the following: Figure 5 and 6 Remove the byproducts 107 from the inner wall of the first window 106.
[0053] (7) Please refer to Figure 7 An aluminum layer 108 is formed on the first passivation layer 104, and the aluminum layer 108 fills the first window 106.
[0054] (8) Please refer to Figure 8 The aluminum layer 108 is graphically represented to form an aluminum circuit layer 109.
[0055] (9) Please refer to Figure 9 A second passivation layer 110 is formed on the first passivation layer 104. The second passivation layer 110 covers the aluminum circuit layer 109, and the second passivation layer 110 includes a third oxide layer 1101 and a second silicon nitride layer 1102 stacked sequentially from bottom to top.
[0056] (10) Please refer to Figure 10 The second passivation layer 110 is patterned to form a second window 111 that exposes the aluminum circuit layer 109.
[0057] The thickness of the aluminum circuit layer 109 causes obvious protrusions on the surface of the second passivation layer 110. Furthermore, during the etching process of the second window 111, the second silicon nitride layer 1102 in the second passivation layer 110 has a large contact area with the etching gas, which easily generates a lot of byproducts. This makes it difficult to meet the customer's specific requirements in terms of subsequent etching processes, electrical performance, process simplification, and device reliability.
[0058] In response, this application provides a method for fabricating a semiconductor structure. By integrating the deposition and etching of the first passivation layer 104 and the second passivation layer 110 into the same step, a flat upper surface can be prepared without the use of chemical mechanical polishing (CMP). This simplifies the passivation layer fabrication process and can meet the needs of customers in subsequent etching and packaging processes. Furthermore, new processes such as copper redistribution layer (Cu RDL) packaging can be used to improve the electrical performance of the device.
[0059] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0060] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.
[0061] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.
[0062] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.
[0063] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.
[0064] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0065] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0066] Please see Figure 11 The diagram shows a process flow chart of the semiconductor structure fabrication method of the present invention, including the following steps:
[0067] S1: A substrate is provided, on which at least one metal interconnect layer is formed, the metal interconnect layer including an insulating dielectric layer and a metal line layer located in the insulating dielectric layer;
[0068] S2: An etch stop layer, an oxide layer, and a silicon nitride layer are sequentially formed on the metal interconnect layer;
[0069] S3: Pattern the silicon nitride layer and the oxide layer to form an opening that exposes a portion of the etch stop layer;
[0070] S4: Use an etching process to remove the exposed etching stop layer, forming a window that exposes part of the metal circuit layer;
[0071] S5: Remove the byproducts on the inner wall of the window to obtain a semiconductor structure.
[0072] The following section, using a structural diagram, details the specific implementation methods for each of the above steps.
[0073] First, please refer to Figure 12Step S1: Provide a substrate 201, on which at least one metal interconnect layer 202 is formed, the metal interconnect layer 202 including an insulating dielectric layer 2021 and a metal circuit layer 2022 located in the insulating dielectric layer 2021.
[0074] Specifically, the material of the metal circuit layer 2022 includes copper.
[0075] As an example, the metal interconnect layer 202 has multiple layers.
[0076] As an example, the metal wiring layers 2022 in adjacent metal interconnect layers 202 are electrically connected by metal pillars, and the window 208 exposes a portion of the uppermost metal wiring layer 2022.
[0077] As an example, the metal pillar penetrates the insulating dielectric layer 2021 between adjacent metal circuit layers 2022.
[0078] As an example, a dielectric barrier layer is also provided between adjacent metal interconnect layers 202, and the metal pillars penetrate the dielectric barrier layer to electrically connect the adjacent metal circuit layers 2022.
[0079] Please see again Figure 13 Step S2: Sequentially form an etch stop layer 203, an oxide layer 204, and a silicon nitride layer 205 on the metal interconnect layer 202.
[0080] Specifically, the oxide layer 204 and the silicon nitride layer 205 together constitute the passivation layer of the semiconductor structure to be prepared.
[0081] Please see again Figure 14 Step S3: Pattern the silicon nitride layer 205 and the oxide layer 204 to form an opening that exposes part of the etch stop layer 203.
[0082] As an example, patterning the silicon nitride layer 205 and the oxide layer 204 to form an opening that exposes a portion of the etch stop layer 203 includes the following steps:
[0083] (1) Please refer to Figure 15 A patterned photoresist layer 206 is formed on the silicon nitride layer 205;
[0084] (2) Please refer to Figure 16 and Figure 17 Photolithography is performed on the silicon nitride layer 205 and the oxide layer 204 based on the photoresist layer 206 to expose the opening of the etch stop layer 203, and then the photoresist layer 206 is removed.
[0085] Please see again Figure 18 Step S4: Use an etching process to remove the exposed etching stop layer 203, forming a window 208 that exposes a portion of the metal circuit layer 2022.
[0086] As an example, the etching process includes dry etching.
[0087] Please see again Figure 19 Step S5: Remove the byproduct 209 on the inner wall of the window 208 to obtain the semiconductor structure.
[0088] As an example, removing byproducts 209 from the inner wall of the window 208 includes the following steps: dry cleaning the inner wall of the window 208.
[0089] As an example, the etching gas used in the dry cleaning includes one or more of O2, N2, H2, CF4, NF3, SF6, and NH3.
[0090] Specifically, during the etching process to remove the exposed etching stop layer 203, the silicon nitride layer 205 reacts with the etching gas, easily generating a large amount of byproducts 209 on the inner wall of the window 208. This is because the bond energy of the nitrogen-silicon bond in silicon nitride is smaller than that of the oxygen-silicon bond in silicon oxide, so more nitrogen-silicon bonds break under the same energy, resulting in more nitrogen ions participating in the reaction. On the other hand, the product of the reaction between nitrogen ions and carbon ions is non-volatile, thus generating a large amount of byproducts 209 (polymer) during the opening process of the window 208. In other words, the silicon nitride layer 205, the topmost passivation layer of the top metal circuit layer 2022, generates a large amount of byproducts 209 during the opening of the etching stop layer 203, which are difficult to remove with wet cleaning. Therefore, it is necessary to use special gases such as H2, O2, and CF4 in the dry etching step to remove byproducts 209 and reduce the generation of defects.
[0091] For example, please refer to [link / reference]. Figure 15 Before forming the photoresist layer 206, the process also includes the step of forming a sacrificial layer 207 on the silicon nitride layer 205.
[0092] Specifically, during the dry cleaning process to remove byproduct 209, the addition of etching gas during dry cleaning can easily reduce the adhesion between the top metal circuit layer 2022 and the oxide layer 204, leading to cracks between the metal interconnect layer 202 and the passivation layer, which in turn causes packaging failure and affects the reliability of the device. Therefore, in this embodiment, before forming the photoresist layer 206, a sacrificial layer 207 is formed on the silicon nitride layer 205. Please refer to [link to previous text]. Figure 16During the etching process to remove the exposed etch stop layer 203, the sacrificial layer 207 can cover the silicon nitride layer 205, preventing the silicon nitride layer 205 from reacting with the etching gas to produce byproduct 209. It also serves as an etching sacrificial layer in the etching stop layer etching step, thereby reducing the generation of byproduct 209, reducing or eliminating the use of etching gas in dry etching, improving the adhesion between the metal interconnect layer 202 and the upper material, and improving the reliability of the device.
[0093] As an example, the ratio of the thickness of the sacrificial layer 207 to the thickness of the etch stop layer 203 is in the range of 0.5 to 1.5.
[0094] As an example, the material of the sacrificial layer 207 includes silicon oxide, amorphous carbon, titanium nitride, or tantalum nitride.
[0095] In the above preparation method, the topmost metal interconnect layer 2022 is directly used as the top metal, and an oxide layer 204 and a silicon nitride layer 205 are deposited for passivation protection. Compared with the structure of preparing an aluminum redistribution layer and a passivation layer on the metal interconnect layer 202 (see...), this method... Figure 10 This reduces the resistivity of the top metal, resulting in superior electrical performance and a simplified fabrication process. It eliminates the need for additional equipment purchases, improving fabrication efficiency and reducing costs. After creating the window 208, the device can be shipped directly and subsequently packaged at a packaging and testing facility using a copper redistribution layer. This results in excellent density, shielding performance, and good mechanical and chemical stability.
[0096] In summary, the semiconductor structure fabrication method of the present invention includes the following steps: providing a substrate, on which at least one metal interconnect layer is formed, the metal interconnect layer including an insulating dielectric layer and a metal circuit layer located in the insulating dielectric layer; sequentially forming an etch stop layer, an oxide layer, and a silicon nitride layer on the metal interconnect layer; patterning the silicon nitride layer and the oxide layer to form an opening exposing a portion of the etch stop layer; removing the exposed etch stop layer using an etching process to form a window exposing a portion of the metal circuit layer; and removing byproducts on the inner wall of the window to obtain the semiconductor structure. The semiconductor structure fabrication method of the present invention can meet the needs of customers in subsequent etching and packaging processes, simplify the fabrication process, and improve the electrical performance and reliability of the device. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.
[0097] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided, on which at least one metal interconnect layer is formed, the metal interconnect layer including an insulating dielectric layer and a metal circuit layer located in the insulating dielectric layer; An etch stop layer, an oxide layer, and a silicon nitride layer are sequentially formed on the metal interconnect layer; The silicon nitride layer and the oxide layer are patterned to form an opening that exposes a portion of the etch stop layer; An etching process is used to remove the exposed etching stop layer, forming a window that exposes a portion of the metal circuit layer; By removing the byproducts from the inner wall of the window, a semiconductor structure is obtained.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that, Patterning the silicon nitride layer and the oxide layer to form an opening that exposes a portion of the etch stop layer includes the following steps: A patterned photoresist layer is formed on the silicon nitride layer; Photolithography is performed on the silicon nitride layer and the oxide layer based on the photoresist layer to obtain the opening that exposes part of the etch stop layer, and then the photoresist layer is removed.
3. The method for preparing a semiconductor structure according to claim 2, characterized in that: Before forming the photoresist layer, the process further includes the step of forming a sacrificial layer on the silicon nitride layer.
4. The method for preparing a semiconductor structure according to claim 3, characterized in that: The ratio of the thickness of the sacrificial layer to the thickness of the etch stop layer is in the range of 0.5 to 1.
5.
5. The method for preparing a semiconductor structure according to claim 3, characterized in that: The materials of the sacrificial layer include silicon oxide, amorphous carbon, titanium nitride, or tantalum nitride.
6. The method for preparing a semiconductor structure according to claim 1, characterized in that, Removing byproducts from the inner wall of the window includes the following steps: dry cleaning the inner wall of the window.
7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The etching gases used in the dry cleaning process include one or more of O2, N2, H2, CF4, NF3, SF6, and NH3.
8. The method for preparing a semiconductor structure according to claim 1, characterized in that: The number of metal interconnect layers is multiple.
9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The metal circuit layers in adjacent metal interconnect layers are electrically connected by metal pillars, and the window exposes a portion of the uppermost metal circuit layer.
10. The method for preparing a semiconductor structure according to claim 9, characterized in that: The metal pillar penetrates the insulating dielectric layer between adjacent metal circuit layers.