Semiconductor structure and method of manufacturing the same

Abstract

A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a staircase structure, a conductive pillar on the staircase structure, and an insulating structure through the staircase structure and connecting the conductive pillar. The staircase structure includes a plurality of conductive layers and a plurality of insulating layers stacked alternately.

Description

Technical Field

[0001] This invention relates to semiconductor structures and methods for manufacturing the same, and more particularly to three-dimensional semiconductor structures and methods for manufacturing the same. Background Technology

[0002] As the size of semiconductor structures continues to shrink, forming interconnect structures, such as conductive pillars, within them becomes increasingly difficult. For instance, the shrinking of semiconductor structures reduces the thickness of the conductive layers. Thinner conductive layers make it difficult for the etching process used to form interconnect structures to stop on the target conductive layer (e.g., over-etching). Over-etching of interconnect structures can lead to electrical connections between the interconnect structures and unintended conductive layers, resulting in a degraded electrical performance of the semiconductor structure. Summary of the Invention

[0003] This invention provides a semiconductor structure and a method for manufacturing the same. The component configuration of the semiconductor structure and manufacturing method of this invention can avoid the problem of difficult-to-control etching and can improve the electrical performance of the semiconductor structure.

[0004] According to some embodiments of the present invention, a semiconductor structure is provided. The semiconductor structure includes a stepped structure, conductive pillars on the stepped structure, and an insulating structure penetrating the stepped structure and connecting the conductive pillars. The stepped structure includes a plurality of conductive layers and a plurality of insulating layers stacked in an alternating manner.

[0005] According to some embodiments of the present invention, a method for manufacturing a semiconductor structure is provided. The method includes: forming a stepped structure, the stepped structure including a plurality of conductive layers and a plurality of insulating layers stacked in an alternating manner; forming an insulating structure penetrating the stepped structure; and forming conductive pillars above the stepped structure and the insulating structure.

[0006] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 This is a schematic cross-sectional view illustrating a semiconductor structure according to some embodiments of the present invention;

[0008] Figure 1A It is a drawing Figure 1 A top view of a semiconductor structure;

[0009] Figure 1B It is a drawing Figure 1 A top view of a semiconductor structure; and

[0010] Figures 2 to 9 This is a schematic cross-sectional view illustrating multiple stages of a method for manufacturing a semiconductor structure according to some embodiments of the present invention.

[0011] Explanation of reference numerals in the attached figures:

[0012] 10: Semiconductor Structure

[0013] 110: Substrate

[0014] 110U: Top surface

[0015] 120, 120A, 120B: Stepped structure

[0016] 120S: Sidewall

[0017] 120U: Top surface

[0018] 121, 121B, 122, 122B, 123, 123B: Insulation layer

[0019] 121A, 122A, 123A: First insulating layer

[0020] 124, 124A, 125, 125A, 126, 126A: Conductive layers

[0021] 130: Conductive post

[0022] 130L: Lower surface

[0023] 130S, 141S: Outer surface

[0024] 140: Insulation structure

[0025] 141: Insulating Post

[0026] 142: Insulating element

[0027] 150, 150A, 150B: Dielectric structure

[0028] 150U: Top surface

[0029] 160: Insulating film

[0030] 220: Insulating stepped structure

[0031] 224, 225, 226: Second insulating layer

[0032] 570, 580, 680: Holes

[0033] 670: Alcoholic cavity

[0034] 570W, 670W, 680W: Width

[0035] 790: Insulating materials

[0036] 880: Space

[0037] D1: First Direction

[0038] D2: Second Direction

[0039] D3: Third direction

[0040] W1, W2, W3, W4: Width Detailed Implementation

[0041] The drawings are simplified to clearly illustrate the embodiments, and the dimensions in the drawings are not drawn to scale with the actual product. In the following manufacturing methods, one or more additional operations may be present between the operations, and the order of the operations may vary. Therefore, the specification and drawings are for illustrative purposes only and are not intended to limit the scope of protection of the invention. The following description uses the same / similar symbols to denote the same / similar elements.

[0042] The ordinal numbers used to modify elements in the specification and claims, such as "first," "second," etc., do not imply or represent a specific position, arrangement, or manufacturing order in the structure; these ordinal numbers are merely used to clearly distinguish multiple elements with the same name. Spatial terms used in the specification and claims, such as "above," "over," "above," "higher than," "top," "below," "below," "below," "lower than," "bottom," etc., describe the relative spatial or positional relationship between one element and another in the drawings, and these spatial or positional relationships can be direct or indirect (with other elements disposed between the two elements), unless otherwise specified. Spatial terms may cover structures shown in other orientations, not limited to those shown in the drawings. Structures can be flipped or rotated at various angles, and the spatial terms used herein can be interpreted accordingly. The singular forms "a" and "the" used in the specification and claims are also intended to include the plural forms, unless the context clearly indicates otherwise. The use of "and / or" in the specification and claims includes any and all combinations of one or more of the listed items.

[0043] Furthermore, the term "electrical connection" used in the specification and appended claims can mean that multiple elements form an ohmic contact, that current flows between multiple elements, or that multiple elements have an operational relationship. An operational relationship can be, for example, one element driving another element, but the current may not flow directly between the two elements. The term "adjacent" used in the specification and appended claims means "adjacent and in contact." The term "deposition" used in the specification and appended claims includes, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and epitaxial growth. Depending on the type of material to be formed, those skilled in the art can select a suitable technique for forming the material. The term "etching" used in the specification and appended claims includes, but is not limited to, dry etching and wet etching. The term "polishing" used in the specification and appended claims includes, but is not limited to, chemical-mechanical planarization (CMP) and ion milling. The terms "etching" and "grinding" used in the specification and appended claims are interchangeable, and those skilled in the art can select the appropriate removal technique based on the structure and materials.

[0044] Embodiments of the present invention can be applied to various types of three-dimensional semiconductor structures. For example, multiple embodiments of the present invention can be applied to, but are not limited to, three-dimensional NAND flash memory devices, three-dimensional ovonic threshold switch (OTS) memory devices, or any type of three-dimensional memory device. Embodiments of the present invention can be applied to the stepped region of a memory device.

[0045] Please refer to Figure 1 , Figure 1A and Figure 1B . Figure 1 This is a schematic cross-sectional view illustrating a semiconductor structure 10 according to some embodiments of the present invention. Figure 1A It is a drawing Figure 1 A partial top view of the semiconductor structure 10, corresponding to the plane of the insulating layer 123. Figure 1B It is a drawing Figure 1 The diagram shows a partial top view of the semiconductor structure 10, corresponding to the plane of the conductive layer 126. The semiconductor structure 10 includes a substrate 110, a stepped structure 120, one or more conductive pillars 130, one or more insulating structures 140, a dielectric structure 150, and one or more insulating films 160. The number of elements in the semiconductor structure 10 is not limited to the number shown in the diagram; the number of each element in the semiconductor structure 10 can be adjusted according to actual needs.

[0046] A stepped structure 120 is disposed on the upper surface 110U of the substrate 110 along a first direction D1. The stepped structure 120 includes a plurality of insulating layers 121-123 and a plurality of conductive layers 124-126 staggered in the first direction D1. The plurality of insulating layers 121-123 separate the plurality of conductive layers 124-126 from each other. The plurality of insulating layers 121-123 and the plurality of conductive layers 124-126 may extend in a second direction D2 and a third direction D3. The plurality of insulating layers 121-123 may have different dimensions; the dimensions are, for example, the area (also referred to as cross-sectional area) on the plane formed by the second direction D2 and the third direction D3, or the width (also referred to as lateral width) in the second direction D2, or the width (also referred to as lateral width) in the third direction D3. The multiple conductive layers 124-126 may have different dimensions; the dimensions are, for example, the area (also called cross-sectional area) on the plane formed by the second direction D2 and the third direction D3, or the width (also called lateral width) on the second direction D2, or the width (also called lateral width) on the third direction D3. For example, the cross-sectional area of ​​the conductive layers 124-126 gradually decreases along the direction away from the substrate 110. For example, the cross-sectional area of ​​the conductive layer 124 located in a lower layer (the layer closer to the substrate 110) is larger than the cross-sectional area of ​​the conductive layer 125 located in a higher layer (the layer farther from the substrate 110).

[0047] The first direction D1 is, for example, the normal direction of the upper surface 110U of the substrate 110. The second direction D2 and the third direction D3 are, for example, directions parallel to the upper surface 110U of the substrate 110. The first direction D1, the second direction D2, and the third direction D3 are perpendicular to each other.

[0048] A dielectric structure 150 is present on the substrate 110 and the stepped structure 120. The dielectric structure 150 may cover a portion of the upper surface 110U of the substrate 110, the upper surface 120U of the stepped structure 120, and the sidewalls 120S of the stepped structure 120. In this embodiment, the upper surface 120U of the stepped structure 120 includes the upper surfaces of conductive layers 124, 125, and 126. In this embodiment, the sidewalls 120S of the stepped structure 120 include the sidewalls of insulating layers 121, 122, and 123, the sidewalls of conductive layers 124, 125, and 126.

[0049] Conductive posts 130 are located on the upper surface 120U of the stepped structure 120. Multiple conductive posts 130 may be separated from each other. Conductive posts 130 are located within the dielectric structure 150. Conductive posts 130 may extend along a first direction D1 and penetrate the dielectric structure 150. Multiple conductive posts 130 may be disposed on (or in contact with) different conductive layers, and each conductive post 130 may be electrically connected to its respective conductive layer. For example, one conductive post 130 may be disposed on and electrically connected to conductive layer 124, one conductive post 130 may be disposed on and electrically connected to conductive layer 125, and one conductive post 130 may be disposed on and electrically connected to conductive layer 126. Each conductive post 130 may be electrically connected to its respective conductive layer and electrically isolated from other conductive layers. For example, conductive pillars 130 disposed on and electrically connected to conductive layer 124 can be electrically isolated from conductive layers 125 and 126; conductive pillars 130 disposed on and electrically connected to conductive layer 125 can be electrically isolated from conductive layers 124 and 126; and conductive pillars 130 disposed on and electrically connected to conductive layer 126 can be electrically isolated from conductive layers 124 and 125. The conductive pillars 130 are columnar. The cross-section of the conductive pillar 130 in the plane formed by the second direction D2 and the third direction D3 can have any shape. For example, the cross-section of the conductive pillar 130 in the plane formed by the second direction D2 and the third direction D3 can be circular, elliptical, square, rectangular, or polygonal.

[0050] An insulating film 160 is located on the upper surface 120U of the stepped structure 120. The insulating film 160 is within the dielectric structure 150. The insulating film 160 may extend along a first direction D1 and penetrate the dielectric structure 150. The insulating film 160 may be disposed on the outer surface 130S of the conductive pillar 130. The insulating film 160 may surround the conductive pillar 130. Multiple insulating films 160 may be disposed on (or in contact with) different conductive layers. The insulating film 160 may be tubular or hollow columnar.

[0051] An insulating structure 140 is located within a stepped structure 120. The insulating structure 140 extends through the stepped structure 120 and connects to the conductive post 130. The insulating structure 140 may be disposed below the conductive post 130. The insulating structure 140 may be located between the substrate 110 and the conductive post 130. The insulating structure 140 includes an insulating post 141 and one or more insulating elements 142. The insulating element 142 is disposed on the outer surface 141S of the insulating post 141. The insulating element 142 protrudes from the outer surface 141S of the insulating post 141. Figure 1AAs shown, insulating elements 142 may surround insulating pillars 141. A plurality of insulating elements 142 are disposed separately on the outer surface 141S of insulating pillars 141. Insulating pillars 141 may extend along a first direction D1 from the upper surface 110U of substrate 110 to the lower surface 130L of conductive pillars 130. Each insulating element 142 may be adjacent to an insulating layer in a second direction D2 and a third direction D3, the insulating layer and the insulating element 142 being on the same level (i.e., having the same height in the first direction D1). Insulating elements 142 may be located between two adjacent conductive layers in the first direction D1. For example, insulating element 142 may be located between conductive layers 124 and 125, or between conductive layers 125 and 126. Insulating element 142 may be located between conductive layer 124 and substrate 110. Conductive layers 124-126 may isolate the insulating element 142 from the conductive pillars 130. The conductive layers 124-126 allow the multiple insulating elements 142 to be separated from each other. The insulating pillar 141 is columnar. The insulating element 142 is annular.

[0052] The insulating structure 140 electrically isolates the conductive post 130 from one or more conductive layers beneath the conductive layer on which the conductive post 130 is located. For example, the insulating structure 140 electrically isolates the conductive post 130 disposed on conductive layer 125 from conductive layer 124, and the insulating structure 140 electrically isolates the conductive post 130 disposed on conductive layer 126 from both conductive layers 125 and 124. Providing the insulating structure 140 ensures that the conductive post 130 is electrically connected to a target conductive layer, but not electrically connected to a non-target conductive layer.

[0053] In one embodiment, the area of ​​the insulating post 141 on the plane formed by the second direction D2 and the third direction D3 is smaller than the area of ​​the conductive post 130 on the plane formed by the second direction D2 and the third direction D3. In one embodiment, the width W1 of the insulating post 141 in the second direction D2 is smaller than the width W2 of the conductive post 130 in the second direction D2. In one embodiment, the width of the insulating post 141 in the third direction D3 is smaller than the width of the conductive post 130 in the third direction D3. In one embodiment, the width W3 of the insulating film 160 in the second direction D2 is equal to or substantially equal to the width W4 of the insulating element 142 in the second direction D2.

[0054] In one embodiment, the semiconductor structure 10 can be used in the stepped region of the memory device. In one embodiment, the conductive layers 124-126 can serve as word lines of the memory device, and the conductive pillars 130 can serve as word line contact structures of the memory device.

[0055] Figures 2 to 9 This illustrates a method for manufacturing a semiconductor structure according to some embodiments of the present invention.

[0056] Please refer to Figure 2 . Figure 2 This is a schematic cross-sectional view of a stage in a method for manufacturing a semiconductor structure. A substrate 110 is provided. An insulating staircase structure 220 is formed on the substrate 110. The insulating staircase structure 220 includes a plurality of first insulating layers 121A, 122A, and 123A and a plurality of second insulating layers 224-226 staggered in a first direction D1. The plurality of first insulating layers 121A-123A separates the plurality of second insulating layers 224-226 from each other. The plurality of first insulating layers 121A-123A and the plurality of second insulating layers 224-226 may extend in a second direction D2 and a third direction D3. The plurality of first insulating layers 121A-123A may have different dimensions; the dimensions are, for example, the area (also referred to as cross-sectional area) on the plane formed by the second direction D2 and the third direction D3, or the width (also referred to as lateral width) in the second direction D2, or the width (also referred to as lateral width) in the third direction D3. The multiple second insulating layers 224-226 may have different dimensions; the dimensions are, for example, the area (also called cross-sectional area) on the plane formed by the second direction D2 and the third direction D3, or the width (also called lateral width) on the second direction D2, or the width (also called lateral width) on the third direction D3. For example, the cross-sectional area of ​​the second insulating layers 224-226 gradually decreases along the direction away from the substrate 110. For example, the cross-sectional area of ​​the second insulating layer 224 located in a lower layer (the layer closer to the substrate 110) is larger than the cross-sectional area of ​​the second insulating layer 225 located in a higher layer (the layer farther from the substrate 110).

[0057] The substrate 110 may be a semiconductor substrate. The substrate 110 may contain semiconductor materials, such as doped or undoped single-crystal silicon, doped or undoped polycrystalline silicon, germanium, etc. The materials of the plurality of first insulating layers 121A-123A may differ from the materials of the plurality of second insulating layers 224-226. The first insulating layers 121A-123A may contain insulating materials, such as oxides. The second insulating layers 224-226 may contain insulating materials, such as nitrides. In one embodiment, the first insulating layers 121A-123A contain silicon oxide. In one embodiment, the second insulating layers 224-226 contain silicon nitride. The first insulating layers 121A-123A and the plurality of second insulating layers 224-226 may be alternately formed on the upper surface 110U of the substrate 110 by a deposition process to form an insulating staircase structure 220.

[0058] Please refer to Figure 3 . Figure 3This is a schematic cross-sectional view of a stage in a method for manufacturing a semiconductor structure. A dielectric structure 150A is formed on an insulating step structure 220. The dielectric structure 150A is on a substrate 110 and an insulating step structure 220. The dielectric structure 150A may cover a portion of the upper surface 110U of the substrate 110, the upper surface 220U of the insulating step structure 220, and the sidewalls 220S of the insulating step structure 220. In this embodiment, the upper surface 220U of the insulating step structure 220 includes the upper surfaces of the second insulating layers 224-226. In this embodiment, the sidewalls 220S of the insulating step structure 220 include the sidewalls of the second insulating layers 224-226 and the sidewalls of the first insulating layers 121A-123A. The dielectric structure 150A may contact the insulating step structure 220 and the substrate 110. The dielectric structure 150A may contain a dielectric material, such as an oxide. In one embodiment, the dielectric structure 150A contains silicon oxide. In one embodiment, the oxide density of the dielectric structure 150A is lower than the oxide density contained in the first insulating layers 121A-123A. In another embodiment, the dielectric structure 150A and the first insulating layers 121A-123A contain the same material. The dielectric structure 150A can be formed on the substrate 110 and the insulating step structure 220 by deposition and polishing processes.

[0059] Please refer to Figure 4 . Figure 4 This is a schematic cross-sectional view of a stage in a method for manufacturing a semiconductor structure. A stepped structure 120A is formed. A dielectric structure 150A is formed on the stepped structure 120A. The stepped structure 120A includes a plurality of conductive layers 124A-126A and a plurality of first insulating layers 121A-123A that are staggered and stacked in a first direction D1. The plurality of conductive layers 124A-126A are located between the plurality of first insulating layers 121A-123A. The plurality of conductive layers 124A-126A may extend in a second direction D2 and a third direction D3. Figure 3 In the illustrated stepped insulating structure 220, the second insulating layers 224-226 are replaced by conductive layers 124A-126A, respectively, to form the stepped structure 120A. The conductive layers 124A-126A may contain conductive materials, such as doped or undoped polysilicon, metals, titanium nitride, or combinations thereof. The conductive layers 124A-126A may contain a combination of conductive materials and high-dielectric-constant dielectric materials. The conductive layers 124A-126A may contain a multilayer structure, such as a multilayer structure formed by multiple conductive materials or a multilayer structure formed by one or more conductive materials and one or more high-dielectric-constant dielectric layers. High-dielectric-constant dielectric materials represent materials with a dielectric constant higher than 3.9. High-dielectric-constant dielectric materials may be, but are not limited to, AlO. x , Si3N4, La2O3, Ta2O5, Y2O3, TiO2, HfO x ZrOx And so on, where x is greater than 0. In one embodiment, the conductive layers 124A-126A comprise an AlOx / TiN / W multilayer structure. The second insulating layers 224-226 between the first insulating layers 121A-123A can be removed by etching, and then the conductive layers 124A-126A can be formed between the first insulating layers 121A-123A by deposition to form a stepped structure 120A.

[0060] Please refer to Figure 5 . Figure 5 This is a schematic cross-sectional view of a stage in a method for manufacturing a semiconductor structure. Multiple holes 570 and multiple holes 580 are formed. The multiple holes 570 are separated from each other. The holes 570 extend along a first direction D1 and penetrate the stepped structure 120B. The holes 570 expose the upper surface 110U of the substrate 110, the sidewalls of the insulating layers 121B-123B, and the sidewalls of the conductive layers 124-126. The multiple holes 580 are separated from each other. The holes 580 extend along the first direction D1 and penetrate the dielectric structure 150B. The holes 580 expose the sidewalls of the dielectric structure 150B. The holes 580 may be above the holes 570. The holes 570 and 580 may have a one-to-one correspondence; that is, the number of holes 570 may be the same as the number of holes 580, and each hole 570 at least partially overlaps the corresponding hole 580 in the first direction D1. Hole 570 can be connected (or linked) to corresponding hole 580. The area (also called cross-sectional area) of hole 570 on the plane formed by the second direction D2 and the third direction D3 can be the same as the area (also called cross-sectional area) of hole 580 on the plane formed by the second direction D2 and the third direction D3. Holes 570 and 580 are columnar. The cross-sections of holes 570 and 580 on the plane formed by the second direction D2 and the third direction D3 can have any shape, such as circular, elliptical, square, rectangular, or polygonal. Parts of the first insulating layer 121A~123A (e.g., ...) can be removed by etching. Figure 4 As shown), the conductive layers 124A~126A (e.g.) Figure 4 As shown), and part of the dielectric structure 150A (such as Figure 4 (As shown) to form holes 570 and 580. The portions of the first insulating layers 121A-123A that are retained are insulating layers 121B-123B. The portions of the conductive layers 124A-126A that are retained are conductive layers 124-126. The stepped structure 120B includes insulating layers 121B-123B and conductive layers 124-126. The portion of the dielectric structure 150A that is retained is dielectric structure 150B. The etching process used to form holes 570 can stop at the upper surface 110U of the substrate 110.

[0061] Please refer to Figure 6 . Figure 6 This is a schematic cross-sectional view of a stage in a method for manufacturing a semiconductor structure. Multiple recesses 670 are formed. Multiple holes 680 are formed. The multiple recesses 670 are arranged separately from each other in the stepped structure 120. The recesses 670 surround the holes 570. The recesses 670 are connected (or communicate) with the holes 570 surrounded by these recesses 670. The multiple recesses 670 connected to the same hole 570 may be arranged along a first direction D1. Conductive layers 124-126 separate the multiple recesses 670 from each other. The recesses 670 may be annular. The recesses 670 expose the upper surface of the conductive layers 124-126, the lower surface of the conductive layers 124-126, and the sidewalls of the insulating layers 121-123 in the stepped structure 120. The recesses 670 may be located between two adjacent conductive layers in the first direction D1. For example, recess 670 may be located between adjacent conductive layers 126 and 125 in the first direction D1, and recess 670 may be located between adjacent conductive layers 125 and 124 in the first direction D1. Recess 670 may be located between conductive layer 124 and substrate 110.

[0062] Multiple holes 680 are disposed separately in the dielectric structure 150. The holes 680 extend along a first direction D1 and penetrate the dielectric structure 150. The holes 680 expose the sidewalls of the dielectric structure 150. The holes 680 expose the upper surfaces of the conductive layers 124-126. The holes 680 may be above the holes 570. There may be a one-to-one correspondence between the holes 680 and the holes 570; that is, the number of holes 680 may be the same as the number of holes 570, and each hole 680 overlaps the corresponding hole 570 in the first direction D1. The holes 680 may be connected (or linked) to the corresponding holes 570. The holes 680 are columnar. The cross-section of the hole 680 in the plane formed by the second direction D2 and the third direction D3 may have any shape, such as circular, elliptical, square, rectangular, or polygonal. In one embodiment, the width 680W of the hole 680 in the second direction D2 is greater than the width 570W of the hole 570 in the second direction D2. In one embodiment, the width of the hole 680 in the third direction D3 is greater than the width of the hole 570 in the third direction D3. The widths of the hole 680 in the second direction D2 and the third direction D3 can be understood as lateral widths. In one embodiment, the width 680W of the hole 680 in the second direction D2 is equal to or substantially equal to the width 670W of the recess 670 in the second direction D2. In one embodiment, the width 570W of the hole 570 is the maximum lateral width of the hole 570. In one embodiment, the width 670W of the recess 670 is the maximum lateral width of the recess 670. In one embodiment, the width 680W of the hole 680 is the maximum lateral width of the hole 680.

[0063] Part of the insulating layers 121B~123B in the stepped structure 120B can be removed by etching (e.g. Figure 5 As shown), a recess 670 is formed in the stepped structure 120. The portions of insulating layers 121B-123B that are retained are insulating layers 121-123. The stepped structure 120 includes insulating layers 121-123 and conductive layers 124-126. A portion of the dielectric structure 150B (as shown) can be removed by etching. Figure 5 (As shown) to form holes 680 on the stepped structure 120. The portion of dielectric structure 150B that is retained is called dielectric structure 150. In one embodiment, the etching process used to form the recess 670 and the hole 680 is an isotropic etching process. In one embodiment, a portion of the insulating layer 121B~123B in the stepped structure 120B can be removed through the hole 570 to form the recess 670. In one embodiment, a portion of the dielectric structure 150B can be removed through the hole 580 to form the hole 680.

[0064] Please refer to Figure 7 . Figure 7 This is a schematic cross-sectional view of a stage in a method for manufacturing a semiconductor structure. An insulating material 790 is formed. A portion (first portion) of the insulating material 790 may be formed in the recess 670 and the hole 570; a portion (second portion) of the insulating material 790 may be formed in the hole 680; and a portion (third portion) of the insulating material 790 may be formed on the upper surface 150U of the dielectric structure 150. The first portion of the insulating material 790 may fill the recess 670 and the hole 570. The second portion of the insulating material 790 may occupy a portion of the space in the hole 680. The second portion of the insulating material 790 may be formed on the sidewalls of the dielectric structure 150 exposed by the hole 680 and on the upper surfaces of the conductive layers 124-126 exposed by the hole 680. The insulating material 790 may comprise oxides or other insulating materials. For example, the insulating material 790 may comprise or be aluminum oxide (Al2O3), hafnium dioxide (HfO2), silicon oxide (SiO2), or titanium oxide (TiO2). The insulating material 790 can be formed in the recesses 670, pores 570, and pores 680 by a deposition process. In one embodiment, the deposition process used to form the insulating material 790 is atomic layer deposition.

[0065] Please refer to Figure 8 . Figure 8This is a schematic cross-sectional view of a stage in a method for manufacturing a semiconductor structure. An insulating structure 140 and an insulating film 160 are formed. The insulating structure 140 is within a stepped structure 120. The insulating film 160 is above the stepped structure 120. The insulating film 160 is in contact with conductive layers 124-126 and the dielectric structure 150. Multiple insulating structures 140 may have different heights in the first direction D1. For example, the upper surface of one insulating structure 140 and the upper surface of the conductive layer 126 may have the same height in the first direction D1; the upper surface of another insulating structure 140 and the upper surface of the conductive layer 125 may have the same height in the first direction D1; and the upper surface of another insulating structure 140 and the upper surface of the conductive layer 124 may have the same height in the first direction D1. The upper surface of the insulating structure 140 may be coplanar with the upper surface of the stepped structure 120. The insulating structure 140 may be separated from the insulating film 160. The insulating material 790 (e.g., ...) can be removed by etching. Figure 7 The portion of the insulating material 790 located on the upper surface of the stepped structure 120 and the portion of the insulating material 790 located on the upper surface 150U of the dielectric structure 150, the portion of the insulating material 790 located in the recess 670, the portion of the insulating material 790 located in the hole 570, and the portion of the insulating material 790 located on the sidewall of the dielectric structure 150 exposed by the hole 680 are all retained. The portion of the insulating material 790 located in the recess 670 is the insulating element 142. The portion of the insulating material 790 located in the hole 570 is the insulating pillar 141. The insulating structure 140 may include the insulating pillar 141 and one or more insulating elements 142 surrounding the insulating pillar. The portion of the insulating material 790 located on the sidewall of the dielectric structure 150 exposed by the hole 680 is the insulating film 160. In this stage, the remaining space of the hole 680 (i.e., the space not occupied by the insulating film 160) is the space 880. The space 880 may be surrounded by the insulating film 160. In one embodiment, the etching process used to form the insulating structure 140 and the insulating film 160 is reactive ion etching (RIE). The insulating film 160, the insulating pillar 141, and the insulating element 142 may comprise the same material. The insulating film 160, the insulating pillar 141, and the insulating element 142 may be made of the same material.

[0066] Please refer to Figure 9 . Figure 9This is a schematic cross-sectional view of a stage in a method for manufacturing a semiconductor structure. Conductive pillars 130 are formed above the stepped structure 120 and the insulating structure 140. The conductive pillars 130 are in contact with the insulating film 160. The conductive pillars 130 are located in space 880. The conductive pillars 130 are on the upper surfaces of the conductive layers 124-126 exposed by space 880 (or the upper surfaces of the conductive layers 124-126 exposed by aperture 680). The conductive pillars 130 are electrically connected to the conductive layers 124-126 exposed by space 880 (or the conductive layers 124-126 exposed by aperture 680). The conductive pillars 130 may contain a conductive material, such as tungsten. The conductive pillars 130 can be formed in space 880 by a deposition process.

[0067] In one embodiment, by performing an exemplary drawing... Figures 2 to 9 The method can yield results such as Figure 1 The semiconductor structure 10 is shown.

[0068] In the semiconductor structure and method for forming the semiconductor structure provided by the present invention, the insulating structure penetrates the stepped structure and connects to the conductive pillars, and the etching process for forming the conductive pillars can penetrate the stepped structure (e.g., Figure 5 and Figure 6 The steps shown in this invention (without stopping at a specific conductive layer) avoid the problem of conductive pillars electrically connecting to unintended conductive layers due to over-etching, thus improving the electrical performance of the semiconductor structure. The configuration of this invention avoids short-circuit problems caused by conductive pillars electrically connecting to unintended conductive layers. Furthermore, this invention does not require increasing the thickness of the conductive layer (e.g., the thickness in the first direction D1) to avoid over-etching; therefore, this invention improves the difficulty in controlling etching while maintaining a thin conductive layer, ensuring both the electrical performance and miniaturization of the semiconductor structure.

[0069] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A semiconductor structure comprising: A single-step structure comprising multiple conductive layers and multiple insulating layers stacked in an alternating manner; A conductive post, on the stepped structure; and An insulating structure extends through the stepped structure and connects to the conductive post.

2. The semiconductor structure according to claim 1, wherein the insulating structure comprises an insulating pillar and an insulating element, the insulating element being disposed on an outer surface of the insulating pillar and protruding from the outer surface.

3. The semiconductor structure of claim 2, wherein the conductive layers isolate the insulating element from the conductive pillar.

4. The semiconductor structure of claim 2, wherein the insulating element surrounds the insulating pillar.

5. The semiconductor structure according to claim 2 further comprises an insulating film surrounding the conductive pillar, the insulating film, the insulating pillar, and the insulating element comprising the same material.

6. The semiconductor structure of claim 2, further comprising a substrate, the stepped structure being on an upper surface of the substrate, the insulating pillar extending from the upper surface of the substrate to a lower surface of the conductive pillar.

7. The semiconductor structure of claim 1, wherein the insulating structure comprises an insulating pillar and a plurality of insulating elements disposed separately on an outer surface of the insulating pillar.

8. The semiconductor structure of claim 1, wherein the conductive pillar is disposed on one of the conductive layers and electrically connected to the conductive layer.

9. A method for manufacturing a semiconductor structure, comprising: A stepped structure is formed, which includes multiple conductive layers and multiple insulating layers stacked in an alternating manner; An insulating structure is formed that runs through the stepped structure; and A conductive pillar is formed above the stepped structure and the insulating structure.

10. The method of claim 9, further comprising: A first hole is formed that penetrates the stepped structure; and A recessed chamber is formed around the first hole in the stepped structure, and the recessed chamber is connected to the first hole.

11. The method of claim 9, further comprising: A dielectric structure is formed on this stepped structure; A first hole is formed that penetrates the stepped structure; A recessed chamber is formed around the first opening in the stepped structure, the recessed chamber being connected to the first opening; and A second hole is formed through the dielectric structure, the first hole is connected to the second hole, and the width of the second hole is greater than the width of the first hole.

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