Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof. A protection ring structure is formed on a semiconductor substrate, the protection ring structure surrounds an electrostatic discharge structure and a spacing ring is formed between the protection ring structure and the electrostatic discharge structure. The step transition of the electrostatic discharge structure is gentle through the protection ring structure, so that the problems of thin photoresist on the step top of the interlayer dielectric layer caused by the step, abnormal etching on the step top, exposure of the electrostatic discharge structure and / or rough surface after abnormal etching leading to metal residue can be avoided, and the problem of gate-source short circuit caused by the above problems can be avoided. In addition, the protection ring structure comprises a first ring part and a second ring part, and the first ring part and the second ring part have a spacing area therebetween, so that the step transition of the protection ring structure corresponding to the spacing area is gentle, and metal etching residue can be avoided at the corresponding position, and the occurrence of gate-source short circuit can be effectively avoided through the protection ring structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] In the semiconductor manufacturing and application fields, electrostatic discharge (ESD) is one of the most common causes of semiconductor device failure. ESD occurs when the charge stored in a semiconductor device or on the human body is discharged due to contact or electrostatic induction. Currently, as the feature size of semiconductor devices becomes smaller and smaller, the problems caused by ESD will become increasingly serious.

[0003] Electrostatic discharge (ESD) structures can release static electricity generated instantaneously in semiconductor devices, effectively protecting them from electrostatic damage. Currently, ESD structures in MOS transistors primarily involve forming a polysilicon layer on the substrate surface. However, existing MOS transistors with ESD structures are prone to gate-source short circuits, leading to device failure. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and its manufacturing method to solve the problem that MOS transistors with electrostatic discharge structures in the prior art are prone to gate-source short circuits, leading to device failure.

[0005] To address the aforementioned technical problems, the present invention provides a semiconductor device, the semiconductor device comprising:

[0006] Semiconductor substrate;

[0007] An electrostatic discharge structure located on the semiconductor substrate;

[0008] A protective ring structure located on the semiconductor substrate, the protective ring structure surrounding the electrostatic discharge structure and forming a spacer ring between the protective ring structure and the electrostatic discharge structure, the protective ring structure including a first ring portion and a second ring portion, and a spacer region between the first ring portion and the second ring portion;

[0009] An interlayer dielectric layer covering the electrostatic discharge structure, the guard ring structure, and the semiconductor substrate;

[0010] A source metal layer is located on the semiconductor substrate, the source metal layer covering the first portion of the electrostatic discharge structure and extending to cover the first ring portion; and,

[0011] A gate metal layer is located on the semiconductor substrate, the gate metal layer covers the second portion of the electrostatic discharge structure and extends to cover the second ring portion.

[0012] Optionally, in the semiconductor device, the spacer ring has a uniform or non-uniform structure, and the ring width of the spacer ring is between 0.1 μm and 3 μm.

[0013] Optionally, in the semiconductor device, the spacer region is a uniform or non-uniform structure, and the width of the spacer region is between 0.1 μm and 3 μm.

[0014] Optionally, in the semiconductor device, the semiconductor device includes one or more of the guard ring structures.

[0015] Optionally, in the semiconductor device, the semiconductor device includes two guard ring structures, the two guard ring structures including a first guard ring structure close to the electrostatic discharge structure and a second guard ring structure away from the electrostatic discharge structure, the first guard ring structure having a first spacing region, the second guard ring structure having a second spacing region, the first spacing region and the second spacing region being aligned or staggered.

[0016] Optionally, in the semiconductor device, both the electrostatic discharge structure and the guard ring structure include a stacked dielectric layer and a polysilicon layer.

[0017] Optionally, in the semiconductor device, the source metal layer covers part or all of the first ring portion; the gate metal layer covers part or all of the second ring portion.

[0018] Optionally, in the semiconductor device, the semiconductor device further includes: a first conductive plug and a second conductive plug located in the interlayer dielectric layer, the source metal layer being connected to the electrostatic discharge structure through the first conductive plug, and the gate metal layer being connected to the electrostatic discharge structure through the second conductive plug.

[0019] Optionally, in the semiconductor device, the semiconductor device further includes a passivation layer that covers the source metal layer and the gate metal layer.

[0020] The present invention also provides a method for manufacturing a semiconductor device, the method comprising:

[0021] Provide semiconductor substrates;

[0022] An electrostatic discharge structure and a protective ring structure are formed on the semiconductor substrate. The protective ring structure surrounds the electrostatic discharge structure and has a spacer ring between it and the electrostatic discharge structure. The protective ring structure includes a first ring portion and a second ring portion, and a spacer region is provided between the first ring portion and the second ring portion.

[0023] An interlayer dielectric layer is formed, the interlayer dielectric layer covering the electrostatic discharge structure, the guard ring structure, and the semiconductor substrate; and,

[0024] A source metal layer and a gate metal layer are formed, wherein the source metal layer covers the first portion of the electrostatic discharge structure and extends to cover the first ring portion, and the gate metal layer covers the second portion of the electrostatic discharge structure and extends to cover the second ring portion.

[0025] In existing MOS transistors with electrostatic discharge (ESD) structures, there is a problem of gate-source short circuits leading to device failure. After in-depth research, the inventors discovered that the cause of this problem is that the ESD structure in existing MOS transistors introduces steps on the substrate surface. This results in thin photoresist at the top of the interlayer dielectric layer steps, which is insufficient to block the etching process. This leads to abnormal over-etching at the top of the steps, which easily exposes the ESD structure and / or causes surface roughness after abnormal etching, resulting in metal residue. This, in turn, easily leads to gate-source short circuits and device failure. In addition, after metal deposition, the bottom of the steps is also prone to back-etching residue, which can also cause gate-source short circuits.

[0026] In the semiconductor device and its manufacturing method provided by this invention, a guard ring structure is formed on a semiconductor substrate. The guard ring structure surrounds the electrostatic discharge (ESD) structure and has a spacer ring between it and the ESD structure. The guard ring structure makes the step transition of the ESD structure smooth, thereby avoiding the problems of thin photoresist at the top of the interlayer dielectric layer step and abnormal over-etching at the top of the step caused by the step. Correspondingly, it avoids the problems of exposed ESD structure and / or surface roughness after abnormal etching leading to metal residue, thus avoiding the gate-source short circuit problem caused by this. In addition, the guard ring structure includes a first ring portion and a second ring portion, and there is a spacer region between the first ring portion and the second ring portion, so that the step transition of the guard ring structure corresponding to the spacer region is smooth, thereby avoiding the formation of metal back-etch residue at the corresponding position. The guard ring structure effectively avoids the occurrence of gate-source short circuit. Attached Figure Description

[0027] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0028] Figure 1 This is a scanning electron microscope (SEM) schematic diagram of an electrostatic discharge structure after an interlayer dielectric layer has been formed.

[0029] Figure 2 This is another scanning electron microscope schematic diagram of the formation of an interlayer dielectric layer on an electrostatic discharge structure in the prior art.

[0030] Figure 3 This is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0031] Figure 4 This is a top view schematic diagram of another semiconductor device according to an embodiment of the present invention.

[0032] Figure 5 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0033] Figure 6 This is a cross-sectional schematic diagram of another semiconductor device according to an embodiment of the present invention.

[0034] Figure 7 It is along Figure 3 Cross-sectional view along the AA' direction.

[0035] Figure 8 It is along Figure 3 Cross-sectional view along the BB' direction.

[0036] Figure 9 This is a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0037] The reference numerals in the attached figures are explained as follows:

[0038] 100, 100' - electrostatic discharge structure; 102, 102' - substrate; 104, 104' - step; 106, 106' - interlayer dielectric layer; 108 - metal residue.

[0039] 200 - Semiconductor device; 202 - Semiconductor substrate; 204 - Electrostatic discharge structure; 206 - Guard ring structure; 206A - First guard ring structure; 206B - Second guard ring structure; 2060, 2060A, 2060B - First ring portion; 2062, 2062A, 2062B - Second ring portion; 2064 - Spacer region; 2064A - First spacer region; 2064B - Second spacer region; 208 - Spacer ring; 208A - Auxiliary spacer ring; 210 - Interlayer dielectric layer; 212 - Source metal layer; 214 - Gate metal layer; 216 - Dielectric layer; 218 - Polysilicon layer; 220 - Trench gate; 222 - Source; 224 - First conductive plug; 226 - Second conductive plug; 228 - Third conductive plug; 230 - Passivation layer.

[0040] W1 - Ring width; W2 - Width; W3 - Width. Detailed Implementation

[0041] The semiconductor device and its manufacturing method according to the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0042] The terminology used in this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. Unless otherwise defined in this application, the technical or scientific terms used in this invention should be understood in their ordinary sense by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "a" or "one," and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. "A plurality" or "several" indicates two or more. Unless otherwise stated, terms such as "front," "rear," "lower," and / or "upper" are for ease of description only and are not limited to a location or spatial orientation. Terms such as "comprising" or "including" indicate that the element or object preceding "comprising" encompasses the element or object listed following "comprising" or its equivalents, and do not exclude other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect. The singular forms “a,” “the,” and “the” used in this specification and appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0043] Please refer to Figure 1 This is a scanning electron microscope (SEM) schematic diagram of an electrostatic discharge structure after an interlayer dielectric layer has been formed. For example... Figure 1 As shown, the electrostatic discharge structure 100 in the existing MOS transistor introduces a step 104 on the surface of the substrate 102. After the photoresist (not shown in the figure) is coated, it will flow down the step, making the photoresist at the top edge of the step 104 thin. During etching, the photoresist is not enough to block the etching, and the top edge of the step is abnormally over-etched. This can easily cause the electrostatic discharge structure 100 to be exposed and / or the surface to be rough after abnormal etching, resulting in metal residue. This can easily lead to gate-source short circuit and device failure.

[0044] Please refer to Figure 2 This is another scanning electron microscope (SEM) schematic diagram of an electrostatic discharge structure after an interlayer dielectric layer has been formed. For example... Figure 2 As shown, the electrostatic discharge structure 100' in the existing MOS transistor introduces a step 104' on the surface of the substrate 102', which makes the interlayer dielectric layer 106' formed on it not smooth enough. During the subsequent metal layer deposition and etch-back process, metal residue 108 is easily formed, which can also cause gate-source short circuit.

[0045] The core idea of ​​this invention is to provide a semiconductor device and its manufacturing method. A guard ring structure is formed on a semiconductor substrate. The guard ring structure surrounds an electrostatic discharge (ESD) structure and has a spacer ring between it and the ESD structure. This guard ring structure allows for a smooth transition of the ESD structure's steps, thus avoiding problems such as thin photoresist at the top of the interlayer dielectric step and abnormal over-etching at the step top. Consequently, it avoids the problems of exposed ESD structure and / or surface roughness after abnormal etching leading to metal residue, thus preventing gate-source short circuits. Furthermore, the guard ring structure includes a first ring portion and a second ring portion, with a spacer region between them. This allows for a smooth transition of the steps corresponding to the spacer region, preventing metal back-etching residue at the corresponding location. The guard ring structure effectively prevents gate-source short circuits.

[0046] Please refer to Figures 3 to 8 ,in, Figure 3 and Figure 4 This is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 5 and Figure 6 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 7 and Figure 8 It is along Figure 3 Cross-sectional views along the AA' and BB' directions. (See attached diagram.) Figures 3 to 8As shown, this application provides a semiconductor device 200, which includes: a semiconductor substrate 202; an electrostatic discharge structure 204 located on the semiconductor substrate 202; and a protective ring structure 206 located on the semiconductor substrate 202. The protective ring structure 206 surrounds the electrostatic discharge structure 204 and forms a spacer ring 208 between the protective ring structure 206 and the electrostatic discharge structure 204. The protective ring structure 206 includes a first ring portion 2060 and a second ring portion 2062, with a spacer between the first ring portion 2060 and the second ring portion 2062. Region 2064; interlayer dielectric layer 210, the interlayer dielectric layer 210 covering the electrostatic discharge structure 204, the guard ring structure 206 and the semiconductor substrate 202; source metal layer 212 located on the semiconductor substrate 202, the source metal layer 212 covering a first portion of the electrostatic discharge structure 204 and extending to cover the first ring portion 2060; and gate metal layer 214 located on the semiconductor substrate 202, the gate metal layer 214 covering a second portion of the electrostatic discharge structure 204 and extending to cover the second ring portion 2062.

[0047] Please refer to the reference. Figures 3 to 8 In this embodiment of the application, the protective ring structure 206 can make the step transition of the electrostatic discharge structure 204 smooth (e.g., Figure 7 As shown), this avoids the problems of thin photoresist at the top of the interlayer dielectric layer step caused by the step, and abnormal over-etching at the top of the step. Correspondingly, it avoids the problems of exposed electrostatic discharge structure and / or surface roughness after abnormal etching leading to metal residue, thus avoiding the gate-source short circuit problem caused by these issues. In addition, the presence of a gap region 2064 between the first ring portion 2060 and the second ring portion 2062 makes the transition of the step of the guard ring structure 206 corresponding to the gap region 2064 smooth (as shown). Figure 8 As shown in the figure, this can prevent the formation of metal back etching residue at the corresponding position, and the gate-source short circuit is effectively avoided by the protection ring structure 206.

[0048] Please continue to refer to this. Figure 3 and Figure 4In this embodiment, the source metal layer 212 and the gate metal layer 214 expose a third portion of the electrostatic discharge structure 204. The third portion of the electrostatic discharge structure 204 is located between the first portion of the electrostatic discharge structure 204 and the second portion of the electrostatic discharge structure 204. That is, in this embodiment, the projection of the source metal layer 212 onto the electrostatic discharge structure 204 covers the first portion of the electrostatic discharge structure 204, the projection of the gate metal layer 214 onto the electrostatic discharge structure 204 covers the second portion of the electrostatic discharge structure 204, and the third portion of the electrostatic discharge structure 204 is not covered by the projection of the source metal layer 212 or the projection of the gate metal layer 214.

[0049] In this embodiment, the source metal layer 212 covers the entire first ring portion 2060, and the gate metal layer 214 covers the entire second ring portion 2062. That is, the projection of the source metal layer 212 onto the first ring portion 2060 covers the entire first ring portion 2060, and the projection of the gate metal layer 214 onto the second ring portion 2062 covers the entire second ring portion 2062. In other embodiments of this application, the source metal layer 212 may also cover a portion of the first ring portion 2060, and the gate metal layer 214 may also cover a portion of the second ring portion 2062.

[0050] Please refer to Figure 3 In this embodiment, the spacer ring 208 has a uniform or non-uniform structure, meaning that the cross-sectional width of the spacer ring 208 may be the same or different at different locations. The ring width W1 of the spacer ring 208 is between 0.1 μm and 3 μm; for example, the ring width W1 of the spacer ring 208 can be 0.1 μm, 0.5 μm, 1.2 μm, 1.8 μm, 2.5 μm, or 3 μm, etc.

[0051] In this embodiment, the spacing region 2064 has a uniform or non-uniform structure, meaning that the cross-sectional width of the spacing region 2064 may be the same or different at different locations. The width W2 of the spacing region 2064 is between 0.1 μm and 3 μm; for example, the width W2 of the spacing region 2064 can be 0.1 μm, 0.5 μm, 1.2 μm, 1.8 μm, 2.5 μm, or 3 μm, etc. Figure 3 As shown in the embodiment of this application, there are two interval regions 2064 between the first ring portion 2060 and the second ring portion 2062, wherein the two interval regions 2064 may be the same or different. For example, one interval region 2064 may be a uniform structure and the other interval region 2064 may be a non-uniform structure; or, both interval regions 2064 may be uniform structures, but their widths are different.

[0052] In this embodiment, the protective ring structure 206 is a uniform or non-uniform structure. Specifically, the first ring portion 2060 and the second ring portion 2062 are uniform or non-uniform, meaning their widths may be the same or different at various points. The width W3 of the protective ring structure 206 is between 0.1 μm and 10 μm. For example, the width W3 can be 0.1 μm, 0.5 μm, 1.2 μm, 1.8 μm, 2.5 μm, 3 μm, 5 μm, 6.8 μm, 8.5 μm, or 10 μm, etc.

[0053] In some embodiments of this application, the semiconductor device 200 includes one of the guard ring structures 206, such as... Figure 3 As shown. In some other embodiments of this application, the semiconductor device 200 may also include a plurality of the guard ring structures 206. The plurality of guard ring structures 206 may be sequentially arranged around the guard ring structure 206, with adjacent guard ring structures 206 spaced apart, wherein an auxiliary spacer ring is provided between adjacent guard ring structures 206.

[0054] like Figure 4 As shown, in one embodiment of this application, the semiconductor device 200 includes two guard ring structures 206. The two guard ring structures 206 include a first guard ring structure 206A close to the electrostatic discharge structure 204 and a second guard ring structure 206B away from the electrostatic discharge structure 204. A spacer ring 208 is formed between the first guard ring structure 206A and the electrostatic discharge structure 204, and an auxiliary spacer ring 208A is formed between the second guard ring structure 206B and the first guard ring structure 206A. That is, in this embodiment, the second guard ring structure 206B and the electrostatic discharge structure 204 are spaced apart by the auxiliary spacer ring 208A, the first guard ring structure 206A, and the spacer ring 208.

[0055] Please continue to refer to this. Figure 4In this embodiment, the spacing region 2064 includes a first spacing region 2064A and a second spacing region 2064B. The first protective ring structure 206A has the first spacing region 2064A, and the second protective ring structure 206B has the second spacing region 2064B. The first spacing region 2064A and the second spacing region 2064B are aligned. The first protective ring structure 206A includes a first ring portion 2060A and a second ring portion 2062A, which are spaced apart by the first spacing region 2064A. The second protective ring structure 206B includes a first ring portion 2060B and a second ring portion 2062B, which are spaced apart by the second spacing region 2064B. In other embodiments of this application, the first interval region 2064A and the second interval region 2064B may also be staggered, wherein the first interval region 2064A and the second interval region 2064B may be partially staggered or completely staggered.

[0056] In some embodiments of this application, multiple protective ring structures 206 can serve as redundant backup structures to better adjust the smoothness of the steps introduced by the electrostatic discharge structure 204.

[0057] Please refer to Figure 5 and Figure 6 In this embodiment, both the electrostatic discharge structure 204 and the guard ring structure 206 include a stacked dielectric layer 216 and a polysilicon layer 218. The dielectric layer 216 may include a silicon nitride layer and / or a silicon oxide layer. In some embodiments of this application, the electrostatic discharge structure 204 and the guard ring structure 206 can be formed simultaneously using the same semiconductor process.

[0058] Please continue to refer to this. Figure 5 and Figure 6 In this embodiment of the application, the semiconductor device 200 further includes a trench gate 220 and a source 222 located in the semiconductor substrate 202, wherein the source 222 is located in the semiconductor substrate 202 on the side of the trench gate 220.

[0059] In this embodiment, the semiconductor device 200 further includes a first conductive plug 224, a second conductive plug 226, a third conductive plug 228, and a fourth conductive plug (not shown) located in the interlayer dielectric layer 210. The source metal layer 212 is connected to the electrostatic discharge structure 204 via the first conductive plug 224, the gate metal layer 214 is connected to the electrostatic discharge structure 204 via the second conductive plug 226, the source metal layer 212 is also connected to the source 222 via the third conductive plug 228, and the gate metal layer 214 is also connected to the trench gate 220 via the fourth conductive plug (not shown).

[0060] Please continue to refer to this. Figure 6 In some embodiments of this application, the semiconductor device 200 further includes a passivation layer 230, which covers the source metal layer 212 and the gate metal layer 214 to protect the semiconductor device 200.

[0061] Next, please refer to Figure 9 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 9 As shown, the method for manufacturing the semiconductor device includes:

[0062] Step S10: Provide a semiconductor substrate;

[0063] Step S20: An electrostatic discharge structure and a guard ring structure are formed on the semiconductor substrate. The guard ring structure surrounds the electrostatic discharge structure and a spacer ring is formed between the guard ring structure and the electrostatic discharge structure. The guard ring structure includes a first ring portion and a second ring portion, and a spacer region is formed between the first ring portion and the second ring portion.

[0064] Step S30: Form an interlayer dielectric layer, the interlayer dielectric layer covering the electrostatic discharge structure, the guard ring structure, and the semiconductor substrate; and,

[0065] Step S40: Form a source metal layer and a gate metal layer, wherein the source metal layer covers the first portion of the electrostatic discharge structure and extends to cover the first ring portion, and the gate metal layer covers the second portion of the electrostatic discharge structure and extends to cover the second ring portion.

[0066] Please refer to the reference. Figures 3 to 8 In this embodiment, the electrostatic discharge structure 204 and the guard ring structure 206 are formed simultaneously using a co-process. In some embodiments of this application, a dielectric layer 216 and a polysilicon layer 218 may be deposited sequentially, and then the dielectric layer 216 and the polysilicon layer 218 may be etched to form the electrostatic discharge structure 204 and the guard ring structure 206.

[0067] In this embodiment of the application, after performing step S30 and before performing step S40, the following steps may then be performed:

[0068] Step S31: Coat photoresist and form a first patterned photoresist layer through photolithography, wherein the first patterned photoresist layer exposes part of the interlayer dielectric layer;

[0069] Step S32: Etch the exposed interlayer dielectric layer to form a plurality of vias in the interlayer dielectric layer; and,

[0070] Step S33: Deposit metallic tungsten in the interlayer dielectric layer to form the first conductive plug, the second conductive plug, the third conductive plug, and the fourth conductive plug.

[0071] In this embodiment, the protective ring structure 206 allows for a smooth transition of the steps in the electrostatic discharge structure 204. This ensures that the photoresist on the interlayer dielectric layer 210 corresponding to the top edge of the steps in the electrostatic discharge structure 204 maintains a uniform and appropriate thickness during formation. Consequently, the interlayer dielectric layer 210 on the electrostatic discharge structure 204 maintains a uniform and appropriate thickness and a smooth surface after etching. This avoids the problems of exposed electrostatic discharge structure 204 and / or rough surface after abnormal etching, which can lead to metal residue. For example, it avoids the residue of tungsten metal at the top edge of the electrostatic discharge structure 204 during the formation of conductive plugs, thereby preventing gate-source short circuits and improving device reliability.

[0072] In this embodiment of the application, step S40 may include:

[0073] Step S41: Deposit a copper layer on the interlayer dielectric layer, the copper layer covering the electrostatic discharge structure and the protective ring structure;

[0074] Step S42: Apply photoresist and form a second patterned photoresist layer using a photolithography process, wherein the second patterned photoresist layer exposes a portion of the copper metal layer; and,

[0075] Step S43: Etch the exposed copper layer to form the source metal layer and the gate metal layer.

[0076] In the semiconductor device and its manufacturing method provided by this invention, a guard ring structure is formed on a semiconductor substrate. The guard ring structure surrounds the electrostatic discharge (ESD) structure and has a spacer ring between it and the ESD structure. The guard ring structure makes the step transition of the ESD structure smooth, thereby avoiding the problems of thin photoresist at the top of the interlayer dielectric layer step and abnormal over-etching at the top of the step caused by the step. Correspondingly, it avoids the problems of exposed ESD structure and / or surface roughness after abnormal etching leading to metal residue, thus avoiding the gate-source short circuit problem caused by this. In addition, the guard ring structure includes a first ring portion and a second ring portion, and there is a spacer region between the first ring portion and the second ring portion, so that the step transition of the guard ring structure corresponding to the spacer region is smooth, thereby avoiding the formation of metal back-etch residue at the corresponding position. The guard ring structure effectively avoids the occurrence of gate-source short circuit.

[0077] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: Semiconductor substrate; An electrostatic discharge structure located on the semiconductor substrate; A protective ring structure located on the semiconductor substrate, the protective ring structure surrounding the electrostatic discharge structure and forming a spacer ring between the protective ring structure and the electrostatic discharge structure, the protective ring structure including a first ring portion and a second ring portion, and a spacer region between the first ring portion and the second ring portion; An interlayer dielectric layer covering the electrostatic discharge structure, the guard ring structure, and the semiconductor substrate; A source metal layer is located on the semiconductor substrate, the source metal layer covering the first portion of the electrostatic discharge structure and extending to cover the first ring portion; and, A gate metal layer is located on the semiconductor substrate, the gate metal layer covers the second portion of the electrostatic discharge structure and extends to cover the second ring portion.

2. The semiconductor device as claimed in claim 1, characterized in that, The spacer ring has a uniform or non-uniform structure, and the ring width of the spacer ring is between 0.1 μm and 3 μm.

3. The semiconductor device as described in claim 1, characterized in that, The interval region has a uniform or non-uniform structure, and the width of the interval region is between 0.1 μm and 3 μm.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The semiconductor device includes one or more of the guard ring structures.

5. The semiconductor device according to any one of claims 1 to 3, characterized in that, The semiconductor device includes two guard ring structures, each including a first guard ring structure close to the electrostatic discharge structure and a second guard ring structure away from the electrostatic discharge structure. The first guard ring structure has a first spacing region, and the second guard ring structure has a second spacing region. The first spacing region and the second spacing region are aligned or staggered.

6. The semiconductor device according to any one of claims 1 to 3, characterized in that, Both the electrostatic discharge structure and the protective ring structure include a stacked dielectric layer and a polysilicon layer.

7. The semiconductor device according to any one of claims 1 to 3, characterized in that, The source metal layer covers part or all of the first ring portion; the gate metal layer covers part or all of the second ring portion.

8. The semiconductor device according to any one of claims 1 to 3, characterized in that, The semiconductor device further includes: a first conductive plug and a second conductive plug located in the interlayer dielectric layer, the source metal layer being connected to the electrostatic discharge structure through the first conductive plug, and the gate metal layer being connected to the electrostatic discharge structure through the second conductive plug.

9. The semiconductor device according to any one of claims 1 to 3, characterized in that, The semiconductor device further includes a passivation layer that covers the source metal layer and the gate metal layer.

10. A method for manufacturing a semiconductor device, characterized in that, The method for manufacturing the semiconductor device includes: Provide semiconductor substrates; An electrostatic discharge structure and a protective ring structure are formed on the semiconductor substrate. The protective ring structure surrounds the electrostatic discharge structure and has a spacer ring between it and the electrostatic discharge structure. The protective ring structure includes a first ring portion and a second ring portion, and a spacer region is provided between the first ring portion and the second ring portion. An interlayer dielectric layer is formed, the interlayer dielectric layer covering the electrostatic discharge structure, the guard ring structure, and the semiconductor substrate; and, A source metal layer and a gate metal layer are formed, wherein the source metal layer covers the first portion of the electrostatic discharge structure and extends to cover the first ring portion, and the gate metal layer covers the second portion of the electrostatic discharge structure and extends to cover the second ring portion.

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