Silicon photonics chip compression molding encapsulation type wafer level fan-out packaging method and structure

Abstract

The application discloses a kind of silicon photonic chip compression moulding plastic encapsulation type wafer level fan-out packaging method and structure, including to the back of silicon photonic wafer is thinned, TSV hole preparation and first copper column filling;Preparation optical waveguide interlayer and optical interface on wafer surface;Cutting obtains photonic chip die;Preparation first fan-out type conductive structure on glass substrate, install EIC chip, laser chip and carry out compression moulding plastic encapsulation;After preparation second fan-out type conductive structure, flip chip ASIC chip and photonic chip die are bonded, and form optical interconnection channel;Again compression moulding plastic encapsulation forms integrated plastic encapsulation layer, internal integration cooling channel, finally bond PCB board and communicate cooling system.Through optical waveguide interlayer and optical interconnection channel, realize high-precision photoelectric coupling, reduce optical loss;Wafer level fan-out process is used to realize mass production;Built-in cooling channel and fin significantly improve heat dissipation efficiency, avoid heat accumulation.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, specifically to a wafer-level fan-out packaging method and structure for silicon photonic chips using a molding process. It is particularly suitable for wafer-level fan-out heterogeneous integration of silicon photonic chips with chips such as electronic integrated circuits (EICs), vertical-cavity surface-emitting lasers (VCSELs), and application-specific integrated circuits (ASICs), and belongs to the molding process wafer-level packaging technology system. Background Technology

[0002] Silicon photonic chips, using light waves as signal carriers, possess advantages such as high speed, low loss, and strong interference resistance, and have become core devices for next-generation high-speed communication and computing. However, as optoelectronic integration develops towards higher density, smaller size, and higher power, traditional packaging technologies can no longer meet industrialization demands, mainly exhibiting the following shortcomings:

[0003] 1. Heterogeneous integration of silicon photonic chips with electronic chips such as EIC, VCSEL, and ASIC is difficult, resulting in high optical signal transmission loss, insufficient optical interface positioning accuracy, and low photoelectric conversion efficiency.

[0004] 2. Traditional silicon photonic chip packaging mostly adopts chip-level single-piece packaging, which cannot achieve wafer-level mass production. It has low packaging efficiency, high cost, poor mechanical stability, and is prone to delamination and cracking.

[0005] 3. Silicon photonic chips and their supporting optoelectronic chips generate concentrated heat during operation. Existing packaging structures do not have dedicated heat dissipation channels designed for the heat generation characteristics and rely solely on the natural heat dissipation of the packaging material, resulting in significant heat accumulation problems, which leads to degradation of the chip's optoelectronic performance and a substantial reduction in its working life.

[0006] 4. Conventional molding processes do not include protective designs for precision optoelectronic devices such as optical waveguides and grating couplers in silicon photonic chips. Molding materials can easily penetrate the effective transmission area of ​​the optical waveguide, causing optical loss. Furthermore, the bonding force between the reconstructed layer and the chip substrate is insufficient after molding, resulting in low package reliability.

[0007] 5. Existing wafer-level fan-out packaging technology is mostly applied to pure electronic chips, without considering the optical signal transmission requirements of silicon photonic chips. There is no corresponding optical waveguide interposer design, and it cannot meet the multiple requirements of low-loss optical signal transmission, high-density electrical signal interconnection and miniaturization of the package. Summary of the Invention

[0008] The purpose of this invention is to provide a wafer-level fan-out packaging method and structure for silicon photonics chips through molding and encapsulation, which solves the problems of difficult optoelectronic heterogeneous integration, high signal loss, low packaging efficiency, poor heat dissipation, and easy damage to precision components in the existing silicon photonics chip packaging technology.

[0009] The objective of this invention is achieved through the following technical solution:

[0010] A method for wafer-level fan-out packaging of silicon photonics chips via molding and encapsulation includes the following steps:

[0011] Step 1, Pre-processing of silicon photonic chip: The surface of the silicon photonic wafer is etched using an O2 plasma etching machine to form the first through-hole corresponding to the PD position inside the silicon photonic wafer; and through-hole etching is performed on the silicon photonic wafer to form TSV holes and metal filling to form the first copper pillar;

[0012] Step 2, Optical waveguide interposer layer fabrication: An organic dielectric material is spin-coated onto the surface of a silicon photonic wafer to form a reconstruction layer, which fills the first via; an optical waveguide interposer layer and an optical interface are fabricated on the reconstruction layer by photolithography and etching, and the optical interface corresponds to the detector inside the silicon photonic wafer;

[0013] Step 3, Photonic Chip Die Fabrication: The wafer obtained in Step 2 is bonded to a carrier plate and then cut and separated into individual photonic chip dies;

[0014] Step 4, Organic Dielectric Reconstruction Layer Preparation: A pyrolytic adhesive layer and a first fan-out conductive structure are formed on a glass substrate to prepare an EIC chip and its conductive copper pillars. The first fan-out conductive structure is electrically connected to a second copper pillar, a third copper pillar, a laser chip, and an EIC chip. Then, an EMC encapsulation layer A is formed on the first fan-out conductive structure by compression molding. After grinding, a second fan-out conductive structure is prepared. The second fan-out conductive structure is electrically connected to the second copper pillar, the third copper pillar, and the conductive copper pillars on the EIC chip. The second fan-out conductive structure is provided with a second through-hole corresponding to the emitting end of the laser chip.

[0015] Step 5, Heterogeneous bonding of optoelectronic chips: Microbumps are prepared on the second fan-out conductive structure (29), ASIC chips and photonic chip dies are flip-chip bonded, and an optical waveguide interconnect channel is prepared between the optical waveguide interposer and the second via. The outer periphery of the optical waveguide interconnect channel is covered with an insulating layer.

[0016] Step 6, Compression molding: A compression molding process is used to form an integrated molding layer. The molding layer has a reserved area for processing cooling channels. After grinding, the upper surface of the molding layer is plated with a SiO2 protective layer B.

[0017] Step 7, Heat dissipation structure integration: Cooling channels are etched in the molding layer, heat sinks are bonded to the SiO2 protective layer B, the glass substrate is removed, the package is bonded to the PCB board, and the cooling system is connected.

[0018] As a further improvement of the present invention, in step 1: the back side of the silicon photonic wafer is first thinned to 50~80μm, and a SiO2 protective layer A is deposited on the front side; a first through-hole is etched and temporarily sealed; a TSV hole is formed by DRIE etching; a SiO2 / Al2O3 composite film is deposited on the inner wall of the TSV hole using ALD; a first copper pillar is formed by electroplating titanium copper in the TSV hole; the excess SiO2 / Al2O3 composite film and SiO2 protective layer A around the first copper pillar are removed by grinding, and the first through-hole is exposed, while the first copper pillar of 5~10μm is retained as an interconnect interface.

[0019] As a further improvement of the present invention, in step 2: spin-coating Si3N4 organic dielectric material with a reconstruction layer thickness of 20~30μm; preparing an optical waveguide interposer layer using electron beam lithography (EBL) and inductively coupled plasma etching (ICP-RIE), wherein the optical interface has a reserved accuracy of ≤±3μm.

[0020] As a further improvement of the present invention, in step 4, the compression molding is carried out using epoxy molding compound (EMC), the molding temperature is 120~150℃, the pressure is 5~10MPa, and the warpage of the package is ≤50μm / inch.

[0021] As a further improvement of the present invention, in step 5, the flip bonding temperature is 200~220℃, the pressure is 5~8MPa, the void ratio is ≤5%, and the alignment accuracy of the optical interconnect channel is ≤±5μm.

[0022] As a further improvement of the present invention, in step 7, the heat sink is bonded with AuSn adhesive; the cooling system is integrated on the PCB board and connected to the cooling channel through pipes.

[0023] A silicon photonics chip compression molding type wafer-level fan-out package structure, fabricated using the above method, includes:

[0024] The PCB board on which the cooling system and molding encapsulation components are bonded;

[0025] The compression molding assembly includes a first fan-out conductive structure bonded to a PCB board. The first fan-out conductive structure is provided with a second copper pillar, a third copper pillar, an EIC chip, and a laser chip. The EIC chip is provided with conductive copper pillars. The second fan-out conductive structure is interconnected with the conductive copper pillars, the second copper pillar, and the third copper pillar.

[0026] The emitting end of the laser chip corresponds to the second through hole on the second fan-out conductive structure. The second through hole is provided with an optical interconnect channel that extends to the optical waveguide intermediary layer to achieve optical coupling with an alignment accuracy of ≤±5μm.

[0027] An ASIC chip is fixed on the second fan-out conductive structure, and the ASIC chip is electrically connected to the first fan-out conductive structure through the second copper pillar;

[0028] The overall structure is covered by a molding compound, which has a reserved cooling channel that is connected to the cooling system on the PCB board; a SiO2 protective layer B and a heat sink are provided above the molding compound.

[0029] The above technical solution has the following beneficial effects:

[0030] 1. Through the optical waveguide interposer and optical waveguide interconnection channel, high-precision optical-electric coupling between silicon photonic chips and chips such as EIC, VCSEL, and ASIC is achieved. The optical interface alignment accuracy is ≤±3~5μm, and the surface roughness of the optical waveguide is low (Ra≤0.1μm), which significantly reduces optical signal transmission loss and improves photoelectric conversion efficiency.

[0031] 2. By adopting wafer-level fan-out packaging technology and combining it with compression molding technology, multi-chip heterogeneous integration and packaging can be completed at the wafer level, avoiding the low efficiency and high cost of traditional chip-level single-piece packaging, resulting in high packaging efficiency and good consistency.

[0032] 3. Cooling channels are integrated inside the plastic encapsulation layer and work with the external cooling system to form a complete heat dissipation circuit. At the same time, heat sinks are added to precisely target the heat-generating chips (laser chips, photonic chips), effectively dissipating heat, avoiding heat accumulation, preventing photoelectric performance degradation, and extending working life.

[0033] 4. In the pre-processing stage, a SiO2 protective layer and temporary sealing vias are used to prevent molding materials and etching gases from intruding into precision structures such as optical waveguides and grating couplers; the reconstructed layer has strong adhesion to the chip substrate, avoiding delamination and cracking, and the package has low warpage (≤50μm / inch) and high reliability;

[0034] 5. The electrical signal redistribution is achieved through the first and second fan-out conductive structures (such as 3P2M), while the optical waveguide interlayer adopts a silicon-based micro-nano optical waveguide with refractive index matching to meet the 250GHz optical signal transmission requirements, realizing the miniaturization and multi-functional integration of the package.

[0035] 6. It adopts epoxy molding compound (EMC) for integral compression molding to form an integrated molding layer, combined with a SiO2 protective layer, providing excellent mechanical protection, insulation and electromagnetic interference resistance, preventing signal crosstalk, and adapting to complex working environments. Attached Figure Description

[0036] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are merely exemplary, and those skilled in the art can derive other embodiments based on the provided drawings without creative effort.

[0037] The structures, proportions, sizes, etc. shown in this specification are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0038] Figure 1 This is a schematic diagram of the process provided by the present invention.

[0039] Figure 2 A schematic diagram of the product structure prepared in step 14.

[0040] Figure 3 A schematic diagram of the product structure prepared in step 16.

[0041] Figure 4 A schematic diagram of the product structure prepared in step 22.

[0042] Figure 5 A schematic diagram of the product structure prepared in step 23.

[0043] Figure 6 A schematic diagram of the product structure prepared in step 43.

[0044] Figure 7 A schematic diagram of the product structure prepared in step 44.

[0045] Figure 8 A schematic diagram of the product structure prepared in step 53.

[0046] Figure 9 A schematic diagram of the main structure of the product prepared in step 62.

[0047] Figure 10 A schematic diagram of the side view structure of the product prepared in step 62.

[0048] Figure 11 A schematic diagram of the main structure of the product prepared in step 71.

[0049] Figure 12 A schematic diagram of the side view structure of the product prepared in step 71.

[0050] Figure 13 A schematic diagram of the main structure of the product prepared in step 73.

[0051] Figure 14 A schematic diagram of the side view structure of the product prepared in step 73.

[0052] In the picture:

[0053] 11. Silicon photonic wafer; 12. First via; 13. SiO2 protective layer A; 14. TSV via; 15. SiO2 / Al2O3 composite film; 16. First copper pillar; 17. Reconstruction layer; 18. Optical waveguide interposer; 19. Optical interface; 20. Carrier board; 21. Glass substrate; 22. First fan-out conductive structure; 23. Second copper pillar; 24. Third copper pillar; 25. EIC chip; 26. Conductive copper pillar; 27. Laser chip; 28. EMC packaging layer A; 29. ​​Second fan-out conductive structure; 291. Second via; 30. ASIC chip; 31. Optical interconnect channel; 32. Cooling channel; 33. SiO2 protective layer B; 34. Heat sink; 35. PCB board; 36. Cooling system; 37. Molding layer. Detailed Implementation

[0054] In this invention, unless otherwise stated, directional terms such as "upper," "lower," "top," and "bottom" are generally used in relation to the direction shown in the accompanying drawings, or in relation to the vertical, perpendicular, or gravitational direction of the component itself; similarly, for ease of understanding and description, "inner" and "outer" refer to the inner and outer contours of each component itself, but the above directional terms are not intended to limit this invention.

[0055] First embodiment, such as Figure 1 As shown, a wafer-level fan-out packaging method for silicon photonics chips via molding and encapsulation includes the following steps:

[0056] Step 1: Preprocessing of silicon photonics chips:

[0057] Step 11: First, take the fabricated silicon photonic chip (hereinafter referred to as silicon photonic wafer 11). This silicon photonic chip integrates core optoelectronic devices such as detectors (PD), modulators (MOD), waveguides (WG), and grating couplers (GC). Each device is integrated according to a preset circuit and optical path layout to ensure the normal transmission of optical and electrical signals. First, use a wafer grinder to perform back-side thinning grinding on silicon photonic wafer 11 to a target thickness of 50~80μm, removing excess silicon layer on the back side of the wafer and reducing the overall thickness of the wafer. After grinding, use a PECVD coating machine to deposit a SiO2 protective layer A13 on the front side of silicon photonic wafer 11, with a coating uniformity ≥95%. This protective layer can effectively isolate external impurities, prevent wafer surface contamination, and protect internal optoelectronic devices from damage in subsequent processes.

[0058] Step 12: Then, an O2 plasma etching machine is used to etch the SiO2 protective layer A13 and surface impurities on the surface of the silicon photonic wafer 11, precisely etching out the first via 12 that corresponds one-to-one with the position of the PD (detector) inside the silicon photonic wafer 11. The etching accuracy is controlled within ≤±2μm to ensure that the first via 12 can be accurately aligned with the signal output end of the PD device, providing a stable basic channel for subsequent electrical signal transmission.

[0059] Step 13: A SiO2 thin film is deposited above the first via 12 using a PECVD coating machine to temporarily seal the upper opening of the first via 12, preventing etching gas and impurities from entering the via and damaging the PD device during subsequent deep silicon etching. Based on this, a DRIE deep silicon etching machine is used to perform deep silicon etching at predetermined locations on the silicon photonic wafer 11, etching to a preset depth to form TSV holes 14. TSV holes 14 are used for subsequent vertical interconnects of the chips, ensuring efficient transmission of electrical signals.

[0060] Step 14: Subsequently, an ALD coating machine is used to deposit a SiO2 / Al2O3 composite film 15 on the surface of the pretreated silicon photonic wafer 11 and the inner wall of the TSV hole 14. This composite film completely covers the wafer surface and the inner wall of the TSV hole 14. The mass ratio of SiO2 to Al2O3 is 70:30. In equivalent embodiments, the mass ratio of SiO2 to Al2O3 can be finely adjusted between 68:32 and 72:28 while still ensuring the insulation and protection performance of the composite film. The ALD coating process can achieve atomic-level thin film deposition, ensuring uniform composite film thickness and no pinholes, effectively improving the insulation performance of the TSV hole 14 and avoiding signal crosstalk. The structure of the prepared product is as follows: Figure 2 As shown.

[0061] Step 15: Electroplating titanium-copper into the TSV hole 14 to form the first copper pillar 16. Before electroplating, the wafer surface and the inner wall of the TSV hole 14 are activated to remove the surface oxide layer and impurities, ensuring a tight bond between the titanium-copper plating layer and the substrate. During the electroplating process, the current density is controlled at 1-3 A / dm² to ensure uniform plating. The height of the first copper pillar 16 matches the depth of the TSV hole 14, filling the entire TSV hole 14 and slightly exceeding the wafer surface.

[0062] Step 16: The surface of the silicon photonic wafer 11 is polished using a wafer polishing machine. During polishing, the force and speed are precisely controlled to expose the lower end of the first copper pillar 16, while completely removing the SiO2 / Al2O3 composite film 15 and the SiO2 protective layer A13 from the surface of the silicon photonic wafer 11. After polishing, the thickness of the silicon photonic wafer 11 is precisely controlled to 50-80 μm. At this point, the upper opening of the first via 12, which was temporarily blocked, is exposed as the surface protective film is removed, providing a channel for the signal output of subsequent PD devices. A portion of the exposed upper end of the first copper pillar 16 is retained during polishing, with a retention length of 5-10 μm. This retained portion serves as the interface for subsequent electrical interconnection with other devices, ensuring the stability and reliability of the interconnection. The resulting product structure is shown below. Figure 3 As shown.

[0063] Step 2, Fabrication of the optical waveguide interposer:

[0064] Step 21: The surface of the silicon photonic wafer 11 after grinding and thinning in step 16 is subjected to plasma cleaning treatment using plasma cleaning equipment. The cleaning power is precisely controlled at 300~500W and the cleaning time is set to 3~5min. Through the bombardment of plasma, impurities, residual grinding powder and surface oxide layer attached to the wafer surface are effectively removed. At the same time, the hydrophilicity and adhesion of the wafer surface are improved, laying a solid foundation for the subsequent coating and bonding of the reconstruction layer.

[0065] Step 22: Using a spin coater, an organic dielectric material (Si3N4) is uniformly spin-coated onto the pre-cleaned silicon photonic wafer 11. During spin coating, the rotation speed is controlled at 3000~5000 r / min and the ambient temperature at 25~30℃ to ensure that the organic dielectric material fully penetrates and fills the first via 12, avoiding voids within the via that could affect subsequent signal transmission. Simultaneously, a complete and flat reconstruction layer 17 is formed on the surface of the silicon photonic wafer 11. During the fabrication of the reconstruction layer 17, the first copper pillar 16 is precisely avoided to prevent covering the copper pillar from affecting subsequent electrical interconnects. The thickness of the reconstruction layer 17 is precisely controlled at 20~30 μm. The resulting product structure is as follows. Figure 4 As shown.

[0066] Step 23: After the reconstructed layer 17 is formed, it is photolithographically processed using an electron beam lithography (EBL) machine. During the photolithography process, the exposure dose and exposure time are precisely controlled to ensure that the photolithography accuracy meets the requirements for micro-nano structure fabrication, ensuring that the photolithographic pattern precisely matches the preset optical waveguide and optical interface pattern without offset or distortion. Subsequently, the photolithographically processed reconstructed layer 17 is etched using an etching machine (ICP-RIE) to etch out the optical waveguide interposer layer 18 and the reserved optical interface 19.

[0067] The optical interface 19 precisely corresponds to the PD (detector) within the silicon photonic wafer 11, ensuring smooth coupling and transmission of optical signals. The optical interface has a reserved precision control of ≤±3μm, and the surface roughness Ra of the optical waveguide after etching is ≤0.1μm to avoid surface roughness affecting optical signal transmission efficiency. The aforementioned optical waveguide interposer 18 uses a silicon-based micro / nano optical waveguide, whose refractive index precisely matches the transmission characteristics of 250GHz optical signals, ensuring lossless optical signal transmission. The fabricated product structure is as follows... Figure 5 As shown.

[0068] Step 3, Photonic Chip Die Fabrication: This step is used to separate the silicon photonic wafer with the fabricated optical waveguide interposer layer into individual dies, in preparation for subsequent molding and encapsulation, while ensuring the integrity of the die performance.

[0069] First, a silicon photonic wafer 11 with a pre-fabricated optical waveguide interposer layer 18 is stably bonded to the surface of a carrier substrate 20 using encapsulating adhesive. During bonding, the bonding temperature is precisely controlled between 80 and 100°C, and the bonding time is maintained at 15 to 20 minutes. A pressing device is used to assist in bonding, ensuring a stable bond between the silicon photonic wafer 11 and the carrier substrate 20, with no air bubbles or loosening at the interface. The encapsulating adhesive must meet the following requirements: a coefficient of thermal expansion (CTE) matching error of <5% with the silicon photonic wafer 11, and an interfacial shear strength ≥20 MPa. This effectively mitigates technical problems such as encapsulation layer warpage and interlayer delamination caused by differences in thermal expansion and contraction during the encapsulation process, ensuring the reliability of subsequent encapsulation.

[0070] After bonding, the silicon photonic wafer 11 bonded to the carrier 20 is cut using a laser cutting device, with the laser cutting precision strictly controlled within ±5μm. During the cutting process, parameters such as laser power and cutting speed are precisely controlled to avoid damage to the micro-nano waveguide structure already prepared in the reconstruction layer 17 due to high laser temperature, ensuring that the optical and electrical properties of the bare wafer are not affected, and obtaining a single independent photonic chip bare wafer after cutting.

[0071] Step 4, Organic dielectric reconstruction layer preparation: This step is used to construct the carrier substrate and conductive interconnect structure for fan-out packaging, providing support for the subsequent packaging and signal transmission of photonic chip dies.

[0072] Step 41: Select glass substrate 21 as the carrier substrate. Glass substrate has the characteristics of high flatness, good thermal stability, and excellent insulation performance, which is suitable for the structural requirements of fan-out packaging. First, a pyrolytic adhesive layer is uniformly coated on the surface of glass substrate 21, with the coating thickness controlled at 10~15μm to ensure uniform coating without omissions or bubbles. This pyrolytic adhesive layer mainly serves to temporarily fix the subsequent structure and facilitate peeling after packaging, making it easy to recycle and reuse the glass substrate. Then, a 3P2M (3 dielectric layers, 2 metal layers) first fan-out conductive structure 22 is prepared on the surface of the pyrolytic adhesive layer using RDL (redistribution layer) technology. This structure can realize the redistribution and spread of electrical signals, which is suitable for the signal lead-out requirements of the chip die.

[0073] Step 42: Select EIC chip 25. The core functional units of EIC chip 25 include laser driver and transimpedance amplifier (TIA), which are used to realize the driving control and electrical signal amplification processing of optoelectronic devices.

[0074] Subsequently, a series of processes were carried out on the surface of the EIC chip 25 to prepare conductive copper pillars 26: First, a titanium-copper layer was deposited by sputtering. The titanium layer can enhance the bonding force between the copper layer and the chip substrate and suppress metal interdiffusion. The copper layer serves as the conductive base layer. Then, photoresist exposure and development were performed in sequence to form a preset copper pillar forming mask. Copper plating was then performed with the mask as the limit to ensure that the copper material is accurately deposited in the target area. After that, the photoresist was removed (photoresist removal) and the excess titanium-copper layer was etched away. Finally, independent and insulating conductive copper pillars 26 were formed on the chip surface for subsequent interconnection.

[0075] Finally, the back of the EIC chip 25 is ground and thinned to reduce the overall thickness of the chip to meet the space requirements of subsequent heterogeneous integration, thus forming the EIC chip assembly.

[0076] Step 43: After preparation, copper pins are installed on both sides of the upper surface of the first fan-out conductive structure 22 to form the second copper pillar 23 and the third copper pillar 24. The diameter of the copper pins is controlled at 10~15μm to ensure firm installation and good conductivity. The laser chip 27 is then upside down and installed in the preset position of the first fan-out conductive structure 22. The two are bonded together with AuSn adhesive. The bonding temperature is controlled at 150~180℃ and the bonding time is 5~8min to ensure a stable bond and excellent thermal and electrical conductivity. Similarly, the back of the EIC chip 25 is bonded to the corresponding area of ​​the first fan-out conductive structure 22 with AuSn adhesive. The second copper pillar 23, the third copper pillar 24, the EIC chip 25, and the laser chip 27 are all precisely interconnected with the bottom of the first fan-out conductive structure 22 to ensure efficient transmission of electrical signals between components. The structure of the prepared product is as follows: Figure 6 As shown.

[0077] Step 44: Using a compression molding encapsulation device, perform overall molding encapsulation on the surfaces of the first fan-out conductive structure 22, the bonded EIC chip assembly, the laser chip 27, the second copper pillar 23, and the third copper pillar 24, using epoxy molding compound (EMC) to form the EMC encapsulation layer A28. This encapsulation layer provides reliable mechanical protection for the internal components and conductive structures, preventing damage to the internal structure from external impacts and contaminants. It also possesses excellent insulation properties and electromagnetic interference resistance, avoiding signal crosstalk between components and ensuring stable device operation.

[0078] After packaging, the surface of the EMC packaging layer A28 is precisely ground using a grinding equipment. The grinding thickness is precisely controlled to completely remove excess packaging material from the surface, so that the conductive copper pillars 26, the emitter of the laser chip 27, the upper surfaces of the second copper pillar 23 and the third copper pillar 24 on the EIC chip assembly are completely exposed, ensuring the smoothness of subsequent electrical interconnection and optical signal coupling.

[0079] Finally, a 3P2M (3 dielectric layers, 2 metal layers) second fan-out conductive structure 29 was fabricated on the polished surface of the EMC packaging layer A28 using RDL (redistribution layer) technology. During fabrication, precise alignment of this structure with the exposed conductive copper pillars 26, 23, and 24 was ensured to achieve stable electrical connection, thereby extending and redistributing the electrical signal and meeting the subsequent signal extraction requirements of the chip. Simultaneously, the second fan-out conductive structure 29 needed to precisely avoid the second via 291 at the laser chip 27's emitting end, as well as the micro-bump vias of the conductive copper pillars 26, 23, and 24, to prevent structural interference. The fabricated product structure is shown below. Figure 7 As shown.

[0080] Step 5, Heterogeneous bonding of optoelectronic chips: This step is used to achieve precise interconnection between various chips and structures, build a complete optical-electric signal transmission path, and ensure the overall optoelectronic performance of the chip is stable. It is a key interconnection step in the packaging process.

[0081] Step 51: On the second fan-out conductive structure 29, a series of processes are performed to fabricate microbumps at the preset microbump vias for subsequent precise interconnection with each chip. The specific process is as follows: First, a preset microbump forming mask is formed through photoresist exposure and development processes. The mask accuracy is controlled within ≤±1μm to ensure accurate microbump positioning after forming. Then, using this mask as a constraint, a titanium-copper plating process is used for deposition, controlling the copper plating current density to 1~2A / dm², so that copper material is precisely deposited in the target via area, and the microbump height is controlled within 10~15μm. Afterwards, the photoresist is removed through a photoresist removal process, and then the excess titanium-copper layer on the surface is etched away using etching equipment. Finally, independent microbumps are formed on the second fan-out conductive structure 29, providing a reliable interconnection interface for subsequent flip-chip bonding.

[0082] Step 52: Perform flip-chip bonding. The ASIC chip 30 is flip-chip bonded to the microbumps corresponding to the second copper pillar 23, forming a stable copper-copper interconnect structure. During bonding, the bonding temperature is controlled at 200~220℃ and the bonding pressure at 5~8MPa to ensure that the bonded joints are free of voids and vacancies, with the void ratio strictly controlled to ≤5%, ensuring efficient electrical signal transmission. Simultaneously, the first copper pillar 16 on the photonic chip die prepared in Step 3 is flip-chip bonded to the microbumps of the conductive copper pillar 26 corresponding to the EIC chip assembly, also forming a copper-copper interconnect. The bonding parameters are consistent with those of the ASIC chip bonding to ensure the solder joint quality meets the standards, with a void ratio ≤5%. After bonding, the optical waveguide interposer 18 on the photonic chip die is located precisely on the upper surface of the second fan-out conductive structure 29, laying the foundation for subsequent optical signal coupling.

[0083] Step 53: On the surface of the second fan-out conductive structure 29 between the optical waveguide interposer 18 and the second via 291, a first insulating layer is uniformly spin-coated using a spin-coating device. The spin-coating thickness is controlled at 5~10μm to ensure uniform coating without bubbles or missed areas. The first insulating layer extends to the inner wall of the second via 291, providing insulation and protection. Subsequently, an optical interconnect channel 31 is fabricated on the first insulating layer. This optical interconnect channel 31 extends from the emitting end of the laser chip 27 to the optical waveguide interposer 18, precisely aligning the laser chip 27 with the PD (detector) inside the silicon photonic wafer 11 with an alignment accuracy ≤±5μm, ensuring smooth coupling and transmission of optical signals. Finally, a second insulating layer is spin-coated on the outer surface of the optical waveguide interposer 18, with the same spin-coating thickness as the first insulating layer. The first and second insulating layers work together to completely enclose the optical waveguide interposer 18, preventing it from being contaminated or damaged by external factors, and avoiding signal crosstalk with other conductive structures. The resulting product structure is as follows. Figure 8 As shown.

[0084] Step 6, Compression Molding: This step is used to encapsulate and protect the bonded chips and structures as a whole, forming a complete package, improving the mechanical strength, insulation performance and anti-interference ability of the chips, and ensuring long-term stable operation of the chips.

[0085] Step 61: The area of ​​the glass substrate 21 is larger than that of the first fan-out conductive structure 22, and a region for processing cooling channels is reserved at a preset position of the first fan-out conductive structure 22, reserving space for the subsequent preparation of the heat dissipation structure of the package. Using a compression molding equipment, the overall structure is molded and packaged on the pyrolytic adhesive layer of the glass substrate 21. Epoxy molding compound (EMC) is selected to form the EMC encapsulation layer B. The EMC encapsulation layer B completely covers the second fan-out conductive structure 29 and the ASIC chip 30 and photonic chip die on it, and is tightly fused with the previously prepared EMC encapsulation layer A28 to form an integrated molding layer 37.

[0086] During the molding process, the molding temperature is precisely controlled at 120~150℃ and the molding pressure is 510MPa to ensure that the molding layer 37 is free of missing or overflowing glue, and that the internal structure is uniformly covered without gaps. After molding, the warpage of the package is strictly controlled to ≤50μm / inch to avoid damage to the internal interconnect structure and abnormal signal transmission caused by warpage.

[0087] Step 62: After molding, the surface of the molding layer 37 is precision ground using a grinding machine to remove excess packaging material, making the surface of the molding layer 37 smooth and flat. After grinding, a SiO2 protective layer B33 is deposited on the surface of the molding layer 37 using a PECVD coating machine, with a coating uniformity of ≥95%. This protective layer further enhances the insulation performance and anti-contamination ability of the package, preventing external moisture and impurities from penetrating the package and protecting the internal chip and interconnect structure. The resulting product structure is as follows. Figure 9 , Figure 10 As shown.

[0088] Step 7, Heat Dissipation Structure Integration: This step is used to integrate the heat dissipation system to promptly remove the heat generated during chip operation, preventing high temperatures from affecting the chip's optoelectronic performance and lifespan. At the same time, it completes the interconnection between the package and the PCB board to form the finished product.

[0089] Step 71: Using etching equipment, precisely etch the cooling channel 32 in the pre-reserved cooling channel processing area of ​​the molding layer 37. During etching, strictly control the etching precision to ensure that the cooling channel 32 avoids the first fan-out conductive structure 22 and the second fan-out conductive structure 29, preventing damage to the conductive structures that could lead to signal crosstalk or open circuits. The cooling channel 32 must precisely correspond to the heat-generating chips (laser chip 27 and photonic chip die) to ensure efficient heat conduction into the channel. Only a pre-reserved opening is left at the upper end of the cooling channel 32 for subsequent connection to the cooling system; the other areas are sealed with encapsulation material to prevent cooling medium leakage. Subsequently, a heat sink 34 is bonded and fixed to the SiO2 protective layer B33 using AuSn adhesive. The bonding temperature is controlled at 150~180℃ to ensure a stable bond. The heat sink 34 is used to assist in dissipating heat from the surface of the molding layer, improving heat dissipation efficiency. The resulting product structure is as follows: Figure 11 , Figure 12 As shown.

[0090] Step 72: The pyrolytic adhesive layer is heated using a heating device to decompose the adhesive, thereby removing the glass substrate 21. After debonding, ensure that there is no residual adhesive on the surface of the package to avoid affecting subsequent interconnection and heat dissipation. Then, on the lower end face of the first fan-out conductive structure 22, pads are prepared and balls are implanted using an electroplating process. The size of the pads and solder balls matches the interface of the PCB board 35. Subsequently, the package is bonded to the PCB board 35 to ensure a stable bond and good electrical connectivity. A cooling system 36 is also integrated on the PCB board 35. The cooling system 36 is precisely connected to the reserved opening of the cooling channel 32 through a dedicated pipeline to form a complete heat dissipation loop.

[0091] Step 73: Using epoxy encapsulation adhesive, seal the connection points between the PCB board 35, the cooling system 36, and the first fan-out conductive structure 22 to completely seal any gaps, prevent external moisture and impurities from entering, and avoid electromagnetic interference affecting chip operation. After encapsulation, performance testing is performed to obtain a finished silicon photonics chip die-molded wafer-level fan-out package that meets design requirements. The structure of the prepared product is as follows: Figure 13 , Figure 14 As shown.

[0092] like Figure 13 , Figure 14 As shown, a silicon photonics chip compression molding wafer-level fan-out package structure is fabricated using the above-mentioned packaging method. The overall structure is compact and rationally laid out, enabling efficient transmission of optical-electrical signals and good heat dissipation, ensuring long-term stable operation of the chip. The specific structure is as follows:

[0093] The packaging structure includes a PCB board 35, which serves as the foundation for the entire packaging structure. It has excellent conductivity and mechanical support properties. The upper surface of the PCB board is fixedly connected to the cooling system 36 and the compression molding assembly through a bonding process. There are no poor solder joints or voids at the bonding points, ensuring a stable connection and good electrical continuity.

[0094] The aforementioned compression molding assembly is the core part of the packaging structure, including a first fan-out conductive structure 22 precisely bonded to the PCB board 35. This first fan-out conductive structure adopts a 3P2M (3 dielectric layers, 2 metal layers) structure to achieve signal redistribution and expansion. In equivalent embodiments, a 2P1M or 4P3M structure can be used instead, still achieving the same signal transmission effect. A second copper pillar 23, a third copper pillar 24, an EIC chip 25, and a laser chip 27 are fixedly arranged on the first fan-out conductive structure 22 according to a preset layout. The second copper pillar 23 and the third copper pillar 24 serve as intermediate carriers for electrical interconnection. Conductive copper pillars 26 are fabricated on the surface of the EIC chip 25. The second copper pillar 23, the third copper pillar 24, and the conductive copper pillar 26 are all precisely aligned and stably connected to the second fan-out conductive structure 29, achieving electrical conduction between the components.

[0095] The emitting end of the laser chip 27 corresponds to the second through-hole 291 on the second fan-out conductive structure 29. A light-guiding interconnect channel 31 is provided at the second through-hole 291, extending from the emitting end of the laser chip 27 to the optical waveguide interposer 18. With an alignment accuracy of ≤±5μm, this channel precisely aligns the laser chip 27 with the PD (detector) within the silicon photonic wafer 11, ensuring lossless coupling and transmission of optical signals. An ASIC chip 30 is fixedly mounted on the second fan-out conductive structure 29. The ASIC chip 30 is electrically connected to the first fan-out conductive structure 22 via the second copper pillar 23, working in conjunction with the EIC chip 25 to complete the driving control, signal amplification, and processing functions of the optoelectronic device.

[0096] All the aforementioned components are encapsulated by a molding compound 37, which is formed by the fusion of EMC encapsulation layer A and EMC encapsulation layer B. It is free of missing or overflowing adhesive, and the warpage of the encapsulation is ≤50μm / inch, providing reliable mechanical protection, insulation, and electromagnetic interference immunity for the internal structure. Cooling channels 32 are pre-installed within the molding compound 37, avoiding all conductive structures and precisely corresponding to the heat-generating chips (the laser chip 27 and the photonic chip die corresponding to the silicon photonic wafer 11). The cooling channels 32 are connected to the cooling system 36 on the PCB board 35 via dedicated piping, forming a complete heat dissipation circuit. A heat sink 34 is bonded to the SiO2 protective layer B above the molding compound 37 using AuSn adhesive to assist in dissipating heat from the surface of the molding compound, further improving heat dissipation efficiency.

[0097] In summary, the embodiments of the present invention achieve the following technical effects: The present invention achieves high-precision optical-electric coupling between silicon photonic chips and chips such as EIC, VCSEL, and ASIC through optical waveguide interposers and optical interconnects, thereby reducing optical loss; mass production is achieved by using wafer-level fan-out technology; built-in cooling channels and heat sinks significantly improve heat dissipation efficiency; and the molding layer combined with the protective layer enhances mechanical strength and anti-interference capabilities, effectively solving the problems of difficult heterogeneous integration, high signal loss, low packaging efficiency, and poor heat dissipation.

[0098] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0099] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0100] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A wafer-level fan-out packaging method for silicon photonics chips using compression molding, characterized in that, Includes the following steps: Step 1, Pre-processing of silicon photonic chip: The surface of silicon photonic wafer (11) is etched using an O2 plasma etching machine to form a first through hole (12) corresponding to the PD position inside the silicon photonic wafer (11); and through hole etching is performed on the silicon photonic wafer (11) to form a TSV hole (14) and metal filling is performed to form a first copper pillar (16). Step 2, Optical waveguide interposer layer fabrication: An organic dielectric material is spin-coated on the surface of a silicon photonic wafer (11) to form a reconstruction layer (17), which fills the first via (12); an optical waveguide interposer layer (18) and an optical interface (19) are fabricated on the reconstruction layer (17) by photolithography and etching, and the optical interface (19) corresponds to the detector (PD) in the silicon photonic wafer (11); Step 3, Photonic Chip Die Fabrication: The wafer obtained in Step 2 is bonded to the carrier plate (20) and cut and separated into independent photonic chip dies; Step 4, Organic dielectric reconstruction layer preparation: A pyrolytic adhesive layer and a first fan-out conductive structure (22) are formed on a glass substrate (21) to prepare an EIC chip (25) and its conductive copper pillars (26); the first fan-out conductive structure (22) is electrically connected to a second copper pillar (23), a third copper pillar (24), a laser chip (27) and an EIC chip (25); then, an EMC encapsulation layer A (28) is formed on the first fan-out conductive structure (22) by compression molding; after grinding, a second fan-out conductive structure (29) is prepared; the second fan-out conductive structure (29) is electrically connected to the second copper pillar (23), the third copper pillar (24) and the conductive copper pillars (26) on the EIC chip (25); the second fan-out conductive structure (29) is provided with a second through hole (291) corresponding to the emitter end of the laser chip (27); Step 5, Heterogeneous bonding of optoelectronic chips: Microbumps are prepared on the second fan-out conductive structure (29), ASIC chip (30) and photonic chip die are flip-chip bonded, and an optical waveguide interconnect channel (31) is prepared between the optical waveguide interposer (18) and the second via (291). The outer periphery of the optical waveguide interconnect channel (31) is covered with an insulating layer. Step 6, Compression molding: A compression molding is used to form an integrated molding layer (37). The molding layer (37) has a reserved area for processing cooling channels. After grinding, the upper end face of the molding layer (37) is plated with a SiO2 protective layer B (33). Step 7, heat dissipation structure integration: etch cooling channels (32) in the molding layer (37), bond heat sinks (34) to the SiO2 protective layer B (33), remove the glass substrate (21), bond the package to the PCB board (35), and connect the cooling system (36).

2. The silicon photonics chip compression molding and encapsulation wafer-level fan-out packaging method according to claim 1, characterized in that, In step 1: the back side of the silicon photonic wafer (11) is thinned to 50~80μm, and a SiO2 protective layer A (13) is deposited on the front side; the first through hole (12) is etched and temporarily sealed; a TSV hole (14) is formed by DRIE etching; a SiO2 / Al2O3 composite film (15) is deposited on the inner wall of the TSV hole (14) using ALD; a first copper pillar (16) is formed by electroplating titanium copper in the TSV hole (14); the excess SiO2 / Al2O3 composite film (15) and SiO2 protective layer A (13) around the first copper pillar (16) are removed by grinding, and the first through hole (12) is exposed, while the first copper pillar (16) of 5~10μm is retained as an interconnect interface.

3. The silicon photonics chip compression molding and encapsulation wafer-level fan-out packaging method according to claim 1, characterized in that, In step 2: spin-coating Si3N4 organic dielectric material, the thickness of the reconstruction layer (17) is 20~30μm; the optical waveguide interposer layer (18) is prepared by electron beam lithography (EBL) and inductively coupled plasma etching (ICP-RIE), and the optical interface (19) has a reserved accuracy of ≤±3μm.

4. The silicon photonics chip compression molding and encapsulation wafer-level fan-out packaging method according to claim 1, characterized in that, In step 4, epoxy molding compound (EMC) is used for compression molding. The molding temperature is 120~150℃, the pressure is 5~10MPa, and the warpage of the package is ≤50μm / inch.

5. The silicon photonics chip compression molding and encapsulation wafer-level fan-out packaging method according to claim 1, characterized in that, In step 5, the flip bonding temperature is 200~220℃, the pressure is 5~8MPa, and the void ratio is ≤5%; the alignment accuracy of the optical interconnect channel (31) is ≤±5μm.

6. The silicon photonics chip compression molding and encapsulation wafer-level fan-out packaging method according to claim 1, characterized in that, In step 7, the heat sink (34) is bonded with AuSn adhesive; the PCB board (35) integrates a cooling system (36) and is connected to the cooling channel (32) through pipes.

7. A silicon photonics chip compression molding encapsulation wafer-level fan-out packaging structure, characterized in that, Prepared by the method according to any one of claims 1 to 6, comprising: A PCB board (35) on which a cooling system (36) and a molding assembly are bonded; The compression molding assembly includes a first fan-out conductive structure (22) bonded to a PCB board (35), wherein a second copper pillar (23), a third copper pillar (24), an EIC chip (25), and a laser chip (27) are disposed on the first fan-out conductive structure (22); the EIC chip (25) is provided with conductive copper pillars (26); the second fan-out conductive structure (29) is interconnected with the conductive copper pillars (26), the second copper pillar (23), and the third copper pillar (24); The emitter of the laser chip (27) corresponds to the second through hole (291) on the second fan-out conductive structure (29). The second through hole (291) is provided with an optical interconnect channel (31), which extends to the optical waveguide intermediary layer (18) to achieve optical coupling with an alignment accuracy of ≤ ±5μm. An ASIC chip (30) is fixed on the second fan-out conductive structure (29), and the ASIC chip (30) is electrically connected to the first fan-out conductive structure (22) through the second copper pillar (23); The overall structure is covered by a molding layer (37), and a cooling channel (32) is reserved in the molding layer (37). The cooling channel (32) is connected to the cooling system (36) on the PCB board (35). A SiO2 protective layer B (33) and a heat sink (34) are provided above the molding layer (37).

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