A package form of power diode and a packaging process thereof

Abstract

The application relates to a packaging form of a power diode and a packaging process thereof, the power diode comprising an upper frame, a lower frame, a chip and an ultrathin packaging layer, the lower frame comprising a lower pin and a lower electrode area, the upper frame comprising an upper pin, an upper electrode area higher than the upper pin and a connecting area connecting the upper pin and the upper electrode area, the chip being welded between the upper electrode area and the lower electrode area, the ultrathin packaging layer being arranged on the four peripheral sides of the chip or simultaneously arranged on the four peripheral sides of the chip and the surface of the upper electrode area, the ultrathin packaging layer, the upper electrode area, the chip and the lower electrode area jointly forming a packaging body, and the connecting area being located outside the packaging body. The application has the advantages that the connecting area is designed outside the packaging body, the connecting area has a certain stress releasing capacity, the thickness of the packaging layer can be reduced, the size of the power diode is reduced, and the development trend of electronic components to chip type and miniaturization is met.

Description

Technical Field

[0001] This invention relates to the field of diode packaging, and particularly to a packaging form for a power diode, as well as a packaging process for implementing the aforementioned power diode packaging form. Background Technology

[0002] Power diodes are key components of circuit systems and are widely used in civilian products such as high-frequency inverters, digital products, generators, televisions, photovoltaics, and power supplies, as well as in military applications such as satellite receivers, missiles, aircraft, and various advanced weapon control systems and instruments.

[0003] Currently, in the production process of power diodes, in order to prevent impurities in the air from corroding the chip circuit and causing a decline in electrical performance, and also for the convenience of installation and transportation, the power diode chip usually needs to be packaged. The conventional packaging form of power diodes is usually plastic encapsulation.

[0004] For example, patent CN110931579A mentions a thin-film photovoltaic bypass diode in the field of solar energy, as well as its manufacturing process and installation method, which belong to the field of semiconductor electrical component technology. It includes a diode negative lead and a diode positive lead, with a diode chip disposed between the diode negative lead and the diode positive lead. A bonding jumper is connected above the diode chip. The diode chip is placed on the diode negative lead, and the diode negative lead is connected to the diode positive lead through the diode chip and the bonding jumper. A frame chip mounting surface is disposed below the diode chip, and a diode encapsulation body is disposed outside the diode chip. A backplate heat sink is disposed on the back of the diode body at a position corresponding to the frame chip mounting surface.

[0005] For example, patent CN207217552U mentions an environmentally friendly ultra-thin chip power diode, which includes a body, a lower chip frame and an upper chip frame. A die is provided between the upper chip frame and the lower chip frame, and a boss surface is provided between the upper chip frame and the die. The boss surface is square, and the body adopts SMAF packaging.

[0006] The SOD-123 packaged diode mentioned in patent CN202268342U includes a feed sheet, a feed sheet, and a chip. Its innovation lies in the following: the feed sheet is a planar structure, the feed sheet is bent into a Z-shape, the bottom edge of the Z-shape of the feed sheet is flush with the feed sheet, and the chip is soldered between the top edge of the Z-shape of the feed sheet and the feed sheet; the chip is encapsulated with a black adhesive body.

[0007] The diode packaging methods mentioned in the aforementioned patents all employ plastic encapsulation. During diode design, the leads of the diode's negative terminal (lower frame) and positive terminal (upper frame) need to be flush. Since the chip is soldered to the electrode areas of both, a height difference inevitably arises. Therefore, at least one of the diode's negative terminal (lower frame) or positive terminal (upper frame) needs to adopt a Z-shaped design to create a gap between the two electrode areas for chip mounting. This structure forms a connection area between the electrode area and the lead to compensate for the height difference. In the aforementioned patents, the electrode area, chip, and connection area are all encapsulated within a plastic package, resulting in a thick plastic layer and a large overall size. However, as electronic components evolve towards surface-mount and miniaturization, these large power diodes can no longer meet the demands of this development. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a small-sized power diode package and a packaging process for realizing the above-mentioned power diode package.

[0009] To solve the above-mentioned technical problems, the technical solution of the present invention is as follows: a power diode packaging form, the power diode including an upper frame, a lower frame and a chip, the lower frame including a lower pin and a lower electrode area, the upper frame including an upper pin, an upper electrode area higher than the upper pin and a connection area connecting the upper pin and the upper electrode area, the chip being soldered between the upper electrode area and the lower electrode area, characterized in that: it further includes an ultra-thin packaging layer, the ultra-thin packaging layer being disposed on the four sides of the chip or simultaneously disposed on the four sides of the chip and the surface of the upper electrode area, the ultra-thin packaging layer, the upper electrode area, the chip and the lower electrode area together forming a package, the connection area being located outside the package, and the ultra-thin packaging layer being a flexible packaging layer with a thickness between 5μm and 35μm.

[0010] Furthermore, the Shore hardness of the flexible encapsulation layer is 55-65HA.

[0011] Furthermore, an upwardly bent arc-shaped stress relief area is provided between the lower pin and the lower electrode area of ​​the lower frame.

[0012] An innovative aspect of a packaging process for implementing the above-mentioned power diode package is: First, the upper frame and lower frame are soldered to the chip. The lower surface of the upper electrode area of ​​the upper frame is soldered to the upper surface of the chip, and the upper surface of the lower electrode area of ​​the lower frame is soldered to the lower surface of the chip. Then, an ultra-thin encapsulation layer is formed on the outer periphery of the chip using a flexible encapsulation material. The ultra-thin encapsulation layer is controlled to be located only on the outer periphery of the chip, or the ultra-thin encapsulation layer is controlled to be located on the outer periphery of the chip and the upper surface of the upper electrode area, thus completing the encapsulation.

[0013] Furthermore, the flexible encapsulation material is a UV insulating protective adhesive or silicone. During encapsulation, a scraper is used to apply the liquid UV insulating protective adhesive or silicone only to the outer peripheral surface of the chip or simultaneously to the outer peripheral surface of the chip and the upper surface of the upper electrode area, ensuring that the chip is evenly coated with UV insulating protective adhesive or silicone around its perimeter. Then, the liquid UV insulating protective adhesive or silicone is cured to form the required ultra-thin encapsulation layer.

[0014] The advantages of this invention are: by designing the connection area outside the package body, the connection area has a certain stress release capability, thereby reducing the thickness of the package layer and thus reducing the size of the power diode, which meets the trend of electronic components towards chip-type and miniaturized development.

[0015] By designing the ultra-thin packaging layer only on the four sides of the chip, or only on the four sides of the chip and the top electrode area, the overall thickness of the package can be reduced, further reducing the size of the power diode.

[0016] The ultra-thin packaging layer adopts a flexible packaging layer design, which utilizes the flexibility of the flexible packaging layer itself to release stress. While ensuring chip packaging, the thickness of the packaging layer can be further reduced, providing a basis for realizing ultra-thin design.

[0017] An arc-shaped stress relief area is set between the lower pin and the lower electrode area, so that the lower frame also has a certain stress relief capability, thereby further reducing the thickness of the package layer.

[0018] The encapsulation method of this invention achieves encapsulation by forming an ultra-thin encapsulation layer using a flexible encapsulation material. Compared to plastic encapsulation, it eliminates the generation of large amounts of non-degradable solid waste. It also reduces energy consumption by eliminating the need for high-temperature injection molding. Furthermore, the absence of high temperatures prevents oxidation of the upper and lower frame surfaces, thus avoiding the need for subsequent electroplating and the resulting wastewater, facilitating environmentally friendly production. Moreover, the elimination of electroplating shortens the production cycle and improves production efficiency. Using UV insulating protective adhesive or silicone as the flexible encapsulation material also results in a shorter curing time compared to plastic encapsulation, further reducing the production cycle. Attached Figure Description

[0019] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0020] Figure 1 This is a schematic diagram of the package configuration of the power diode of the present invention.

[0021] Figure 2 This is a schematic diagram of the upper frame in this invention.

[0022] Figure 3 This is a schematic diagram of the lower frame in this invention. Detailed Implementation

[0023] The following embodiments are intended to enable those skilled in the art to more fully understand the present invention, but do not limit the invention to the scope of the embodiments described.

[0024] like Figures 1-3 The diagram shows a package configuration for a power diode, which includes an upper frame 1, a lower frame 2, a chip 3, and an ultra-thin packaging layer 4.

[0025] The upper frame 1 is made of copper plate, such as Figure 2 As shown, the upper frame 1 includes an upper pin 11, an upper electrode area 12 that is higher than the upper pin 11, and a connecting area 13 that connects the upper pin 11 and the upper electrode area 12. The two sides of the connecting area 13 are respectively connected to the upper pin 11 and the upper electrode area 12 by an arc transition. The upper pin 11, the upper electrode area 12 and the connecting area 13 are connected together to form a Z-shaped upper frame 1 or an S-shaped upper frame 1.

[0026] The lower frame 2 is also made of copper plate, such as Figure 3 As shown, the lower frame 2 includes a lower pin 21 and a lower electrode area 22. An upwardly bent arc-shaped stress relief area 23 is also provided between the lower pin 21 and the lower electrode area 22. The two sides of the arc-shaped stress relief area 23 are connected to the lower pin 21 and the lower electrode area 22 by arc-shaped transitions, giving the lower frame 2 a straight-line shape. The arc-shaped stress relief area 23 between the lower pin 21 and the lower electrode area 22 provides the lower frame 2 with a certain stress relief capability, thereby further reducing the thickness of the encapsulation layer.

[0027] Chip 3 is soldered between upper electrode region 12 and lower electrode region 22. A first solder paste layer 5 is also provided between chip 3 and lower electrode region 22, and a second solder paste layer 6 is also provided between chip 3 and upper electrode region 12.

[0028] An ultra-thin encapsulation layer 4 is disposed on all four sides of the chip 3, or simultaneously on all four sides of the chip 3 and the surface of the upper electrode region 12. The ultra-thin encapsulation layer 4, the upper electrode region 12, the chip 3, and the lower electrode region 22 together form an encapsulation body. The connecting region 13 is located outside the encapsulation body. The ultra-thin encapsulation layer 4 is a flexible encapsulation layer with a thickness between 5μm and 35μm and a Shore hardness of 55-65HA. The ultra-thin encapsulation layer 4 adopts a flexible encapsulation layer design, utilizing the flexibility of the flexible encapsulation layer itself to achieve a certain stress relief effect. While ensuring chip encapsulation, the thickness of the encapsulation layer can be further reduced, providing a basis for realizing an ultra-thin design.

[0029] The above-mentioned power diodes are packaged using the following steps: First, the upper frame 1, the lower frame 2, and the chip 3 are soldered together. The lower surface of the upper electrode region 12 of the upper frame 1 is soldered to the upper surface of the chip 3, and a second solder paste layer 6 is formed between the lower surface of the upper electrode region 12 and the upper surface of the chip 3. The upper surface of the lower electrode region 22 of the lower frame 2 is soldered to the lower surface of the chip 3, and a first solder paste layer 5 is formed between the upper surface of the lower electrode region 22 and the lower surface of the chip 3.

[0030] Then, an ultra-thin encapsulation layer 4 is formed on the outer peripheral surface of the chip using encapsulation material. The ultra-thin encapsulation layer 4 is controlled to be located only on the outer peripheral surface of the chip 3, or the ultra-thin encapsulation layer 4 is controlled to be located on the outer peripheral surface of the chip 3 and the upper surface of the upper electrode region 12, thus completing the encapsulation.

[0031] The following is a specific explanation using UV insulating protective adhesive or silicone as the encapsulation material: When using UV insulating protective adhesive as an encapsulation material, the following steps are taken to achieve the encapsulation: S1: First, place the UV insulating protective adhesive in a constant temperature chamber at 60-100℃ for 4 hours to obtain the desired liquid UV insulating protective adhesive with suitable viscosity and flowability.

[0032] S2: Then, align the material formed by welding the upper frame 1, lower frame 2 and chip 3 with the squeegee.

[0033] S3: Add an appropriate amount of liquid UV insulating protective adhesive to the glue groove of the scraper.

[0034] S4: Use a scraper to scrape the liquid UV insulating protective adhesive back and forth on the material surface once to ensure that the thickness of the UV insulating protective adhesive is 5-10 micrometers, and ensure that the UV insulating protective adhesive is evenly applied around the chip 4.

[0035] S5: Transfer the material with the applied UV insulating protective adhesive under a UV lamp for UV curing. The UV lamp wavelength should be 365-390nm.

[0036] S6: The material passes through the UV lamp at a uniform speed, and the UV insulating protective adhesive is fixed by the UV lamp. The material passes through the UV lamp for 6-15 seconds, so that the UV insulating protective adhesive can be cured to form the required ultra-thin encapsulation layer 4, thus completing the encapsulation process.

[0037] S7: After the material comes out from under the UV lamp, it is moved into the rebar cutting process for subsequent rebar cutting tests.

[0038] Tables 1 and 2 compare power diodes encapsulated with UV insulating protective adhesive and power diodes encapsulated with plastic encapsulation. Table 1 compares the production of one million power diodes, and Table 2 compares their performance. Examples 1, 2, and 3 are three power diodes encapsulated with UV insulating protective adhesive, while Comparative Examples 1, 2, and 3 are three power diodes encapsulated with plastic encapsulation. Table 1 Table 2 When using silicone as an encapsulation material, the following steps are taken to achieve the encapsulation: S1: Place the silicone on a roller and coat it evenly for 10 hours to obtain the desired liquid silicone with suitable viscosity and flowability.

[0039] S2: Align the material formed by welding the upper frame 1, lower frame 2 and chip 3 with the squeegee.

[0040] S3: Add an appropriate amount of liquid silicone to the glue groove of the scraper.

[0041] S4: Use a scraper to scrape the liquid silicone back and forth on the material surface once to ensure that the thickness of the liquid silicone is 10-20 micrometers and that the liquid silicone is evenly coated around the chip.

[0042] S5: Transfer the material with the applied adhesive into the tooling and wait for the adhesive to cure.

[0043] S6: Set the temperature profile for the adhesive curing oven.

[0044] S7: Place the materials in layers into the adhesive curing oven.

[0045] S8: Turn on the nitrogen gas and start the oven to heat up the liquid silicone on the material surface to cure it. Use nitrogen gas to protect the upper frame 1 and the lower frame 2 to prevent oxidation.

[0046] S9: After curing, when the oven temperature drops below 80°C, remove the material from the oven. At this time, the cured silicone forms the required ultra-thin encapsulation layer 4 on the chip surface, completing the encapsulation process.

[0047] S10: Finally, the material is moved to the rebar cutting process for subsequent rebar cutting tests.

[0048] Tables 3 and 4 compare power diodes encapsulated with silicone and power diodes encapsulated with plastic. Table 3 compares the production of one million power diodes, and Table 4 compares their performance. Examples 4, 5, and 6 show three power diodes encapsulated with silicone, while Comparative Examples 4, 5, and 6 show three power diodes encapsulated with plastic. Table 3 Table 4 As can be seen from the data in Tables 1 and 3, using plastic encapsulation for power diodes generates 80-100 kg of non-degradable solid waste per million power diodes, with a volume of nearly 0.5 cubic meters. The energy consumption is as high as 450 kWh, and the electroplating wastewater generated is about 2 tons. Moreover, the wastewater contains sulfuric acid, hydrochloric acid, phosphoric acid, tin ions, stannous ions, copper ions, and a large number of acid radicals, which cannot be directly discharged and require further treatment before discharge. The production cycle is 8-15 days.

[0049] Using the UV insulating protective adhesive and silicone as encapsulation materials in this invention will result in virtually no solid waste or wastewater generated. Moreover, the energy consumption is as low as 128 KW.H. The production cycle for encapsulation with UV insulating protective adhesive is only 1 day, while the production cycle for encapsulation with silicone is 2 days, both of which are much shorter than the plastic sealing cycle. The production cycle is greatly reduced, and the product qualification rate is slightly higher than that of plastic sealing.

[0050] After randomly selecting 100,000 products from millions of products and conducting a 1,000-hour aging test, the failure rate of the power diodes encapsulated using the UV insulating protective adhesive and silicone of this invention as encapsulation materials was 0 ppm, while the failure rate of the power diodes encapsulated using plastic encapsulation materials was 25-30 ppm. Therefore, the encapsulation method of this invention fully meets the performance requirements and has better performance stability than the plastic encapsulation method.

[0051] As can be seen from the data in Tables 2 and 4, when UV insulating protective adhesive and silicone are used as encapsulation materials, the Shore hardness of UV insulating protective adhesive and silicone is much lower than that of plastic encapsulation. This allows the ultra-thin encapsulation layer 4 formed by UV insulating protective adhesive and silicone to have a certain stress release effect, providing a basis for reducing the thickness of the encapsulation layer.

[0052] Therefore, the power diodes produced by the packaging method and packaging method of the present invention can fully meet the application requirements. Not only does it achieve an ultra-thin design, but compared with plastic encapsulation, it does not generate a large amount of non-degradable solid waste, nor does it require high-temperature injection molding, thus reducing energy consumption. Furthermore, because it does not require high temperatures, it avoids the oxidation of the upper and lower frame surfaces, thus eliminating the need for subsequent electroplating of the upper and lower frames and avoiding wastewater generated by electroplating and a series of subsequent treatments, achieving environmental protection. The entire production cycle is also greatly shortened.

[0053] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A package form for a power diode, the power diode comprising an upper frame, a lower frame, and a chip, wherein the lower frame includes a lower pin and a lower electrode region, the upper frame includes an upper pin, an upper electrode region above the upper pin, and a connection region connecting the upper pin and the upper electrode region, and the chip is soldered between the upper electrode region and the lower electrode region, characterized in that: It also includes an ultra-thin encapsulation layer, which is disposed on the four sides of the chip or simultaneously on the four sides of the chip and the surface of the upper electrode area. The ultra-thin encapsulation layer, the upper electrode area, the chip and the lower electrode area together form an encapsulation body. The connecting area is located outside the encapsulation body, and the ultra-thin encapsulation layer is a flexible encapsulation layer with a thickness between 5μm and 35μm.

2. The packaging form of the power diode according to claim 1, characterized in that: The Shore hardness of the flexible encapsulation layer is 55-65HA.

3. The package form of the power diode according to claim 1 or 2, characterized in that: An upwardly bent arc-shaped stress relief area is also provided between the lower pin and the lower electrode area of ​​the lower frame.

4. A packaging process for implementing the power diode package form of claim 1, characterized in that: First, the upper frame and lower frame are soldered to the chip. The lower surface of the upper electrode area of ​​the upper frame is soldered to the upper surface of the chip, and the upper surface of the lower electrode area of ​​the lower frame is soldered to the lower surface of the chip. Then, an ultra-thin encapsulation layer is formed on the outer periphery of the chip using a flexible encapsulation material. The ultra-thin encapsulation layer is controlled to be located only on the outer periphery of the chip, or the ultra-thin encapsulation layer is controlled to be located on the outer periphery of the chip and the upper surface of the upper electrode area, thus completing the encapsulation.

5. The packaging process for the power diode according to claim 4, characterized in that: The flexible encapsulation material is a UV insulating protective adhesive or silicone. During encapsulation, a scraper is used to apply the liquid UV insulating protective adhesive or silicone only to the outer peripheral surface of the chip or simultaneously to the outer peripheral surface of the chip and the upper surface of the upper electrode area, ensuring that the chip is evenly coated with UV insulating protective adhesive or silicone around its perimeter. Then, the liquid UV insulating protective adhesive or silicone is cured to form the required ultra-thin encapsulation layer.

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