Display panel, display device and manufacturing method

Abstract

The display panel, the display device and the manufacturing method are provided. The display panel comprises an array substrate, an opposite substrate and a liquid crystal layer between the array substrate and the opposite substrate. The array substrate comprises a substrate and a plurality of sub-pixel electrodes on one side of the substrate. At least one of the plurality of sub-pixel electrodes comprises a first pixel electrode part and a second pixel electrode part. The brightness of the first pixel electrode part when powered is greater than the brightness of the second pixel electrode part when powered. The first pixel electrode part is a block electrode, and at least part of the second pixel electrode part has a plurality of slits.

Description

Display panel, display device and manufacturing method Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel, a display device, and a manufacturing method. Background Technology

[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays.

[0003] Summary of the Invention

[0004] This disclosure provides a display panel, a display device, and a method for manufacturing them. The display panel includes:

[0005] The display panel includes:

[0006] An array substrate, a counter substrate, and a liquid crystal layer located between the array substrate and the counter substrate are disposed opposite to each other.

[0007] The array substrate includes a substrate and a plurality of sub-pixel electrodes located on one side of the substrate; at least one of the plurality of sub-pixel electrodes includes a first pixel electrode portion and a second pixel electrode portion; wherein, in the same sub-pixel electrode, the brightness of the first pixel electrode portion when energized is greater than the brightness of the second pixel electrode portion when energized; the first pixel electrode portion is a block electrode, and at least a portion of the second pixel electrode portion has a plurality of slits.

[0008] In one possible implementation, the display panel further includes: a first alignment film layer located on the array substrate, and a second alignment film layer located on the opposing substrate; the alignment pretilt angle of the second alignment film layer is smaller than the alignment pretilt angle of the first alignment film layer.

[0009] In one possible implementation, the difference between the alignment pretilt angle of the first alignment film layer and the alignment pretilt angle of the second alignment film layer ranges from 0.3° to 1.5°.

[0010] In one possible implementation, the second alignment film layer includes: a first alignment portion and a second alignment portion; the orthographic projection of the first alignment portion on the substrate overlaps with the orthographic projection of the first pixel electrode portion on the substrate; the orthographic projection of the second alignment portion on the substrate overlaps with the orthographic projection of the second pixel electrode portion on the substrate.

[0011] The alignment pretilt angle of the first alignment portion is less than the alignment pretilt angle of at least a portion of the second alignment portion.

[0012] In one possible implementation, the alignment pretilt angles of each region within the second alignment section are the same.

[0013] In one possible implementation, the second alignment portion includes: two first sub-alignment portions and a second sub-alignment portion; the two first sub-alignment portions are respectively located on both sides of the second sub-alignment portion along a first direction;

[0014] The alignment pretilt angle of the first sub-alignment is less than the alignment pretilt angle of the second sub-alignment.

[0015] In one possible implementation, the alignment pretilt angle of the first sub-alignment is the same as that of the first alignment portion.

[0016] In one possible implementation, the difference between the alignment pretilt angle of the first alignment portion and the alignment pretilt angle of the second alignment portion ranges from 0.1° to 0.7°.

[0017] In one possible implementation, the liquid crystal layer includes: a first liquid crystal portion and a second liquid crystal portion; the orthographic projection of the first liquid crystal portion onto the substrate coincides with the orthographic projection of the first pixel electrode portion onto the substrate; the orthographic projection of the second liquid crystal portion onto the substrate coincides with the orthographic projection of the second pixel electrode portion onto the substrate.

[0018] Both the first liquid crystal unit and the second liquid crystal unit include: n rows and n columns of sub-liquid crystal units; the azimuth angle of the liquid crystal in each sub-liquid crystal unit is greater than zero and less than 45°, where n is a positive integer greater than or equal to 2.

[0019] In one possible implementation, the second pixel electrode portion includes: a first sub-electrode unit and a second sub-electrode unit; the first sub-electrode unit and the second sub-electrode unit extend along a second direction and are arranged along a first direction;

[0020] The first sub-electrode unit includes: a first sub-part and a second sub-part arranged sequentially along the second direction; the second sub-electrode unit includes: a third sub-part and a fourth sub-part arranged sequentially along the second direction;

[0021] The first sub-part, the second sub-part, the third sub-part, and the fourth sub-part all have the slit, and the extension direction of the slit in the first sub-part is the same as the extension direction of the slit in the fourth sub-part; the extension direction of the slit in the second sub-part is the same as the extension direction of the slit in the third sub-part.

[0022] In one possible implementation, the second pixel electrode portion further includes: a third sub-electrode unit and a fourth sub-electrode unit; the third sub-electrode unit and the fourth sub-electrode unit extend along the second direction and are arranged sequentially along the first direction;

[0023] The third sub-electrode unit is a planar electrode, and the fourth sub-electrode unit is a planar electrode.

[0024] In one possible implementation, the first sub-electrode unit, the third sub-electrode unit, the fourth sub-electrode unit, and the second sub-electrode unit are arranged sequentially along the first direction.

[0025] In one possible implementation, the third sub-electrode unit, the first sub-electrode unit, the second sub-electrode unit, and the fourth sub-electrode unit are arranged sequentially along the first direction.

[0026] In one possible implementation, the area of ​​the first sub-pixel electrode portion projected onto the substrate is smaller than the area of ​​the second sub-pixel electrode portion projected onto the substrate.

[0027] In one possible implementation, the display panel further includes: a plurality of gate lines extending along a second direction, a plurality of data lines extending along a first direction, a plurality of pixel circuits, and a plurality of first traces;

[0028] The first pixel electrode portion and the second pixel electrode portion are located on different sides of the gate line, respectively;

[0029] The pixel circuit includes a first transistor, a second transistor, and a third transistor; a first electrode of the first transistor is electrically connected to the data line, and a second electrode of the first transistor is electrically connected to the first pixel electrode; the first electrode of the second transistor is multiplexed with the first electrode of the first transistor, and the second electrode of the second transistor is electrically connected to the second pixel electrode; the first electrode of the third transistor is multiplexed with the second electrode of the second transistor, and the second electrode of the third transistor is electrically connected to the first trace; the pixel circuit is configured to release a portion of the electrical signal loaded onto the second pixel electrode to the first trace, so that the brightness of the second pixel electrode is less than the brightness of the first pixel electrode.

[0030] This disclosure also provides a display panel, which includes:

[0031] An array substrate, a counter substrate, and a liquid crystal layer located between the array substrate and the counter substrate are disposed opposite to each other.

[0032] A first alignment film layer is located on the array substrate;

[0033] The second alignment film layer is located on the opposing substrate;

[0034] Wherein, the alignment pretilt angle of the second alignment film is less than the alignment pretilt angle of the first alignment film.

[0035] In one possible implementation, the difference between the alignment pretilt angle of the first alignment film layer and the alignment pretilt angle of the second alignment film layer ranges from 0.3° to 1.5°.

[0036] In one possible implementation, the second alignment film layer includes: a first alignment portion and a second alignment portion; the orthographic projection of the first alignment portion on the substrate overlaps with the orthographic projection of the first pixel electrode portion on the substrate; the orthographic projection of the second alignment portion on the substrate overlaps with the orthographic projection of the second pixel electrode portion on the substrate.

[0037] The alignment pretilt angle of the first alignment portion is less than the alignment pretilt angle of at least a portion of the second alignment portion.

[0038] In one possible implementation, the alignment pretilt angles of each region within the second alignment section are the same.

[0039] In one possible implementation, the second alignment portion includes: two first sub-alignment portions and a second sub-alignment portion; the two first sub-alignment portions are respectively located on both sides of the second sub-alignment portion along a first direction;

[0040] The alignment pretilt angle of the first sub-alignment is less than the alignment pretilt angle of the second sub-alignment.

[0041] In one possible implementation, the alignment pretilt angle of the first sub-alignment is the same as that of the first alignment portion.

[0042] In one possible implementation, the difference between the alignment pretilt angle of the first alignment portion and the alignment pretilt angle of the second alignment portion is in the range of 0.1° to 0.7°.

[0043] In one possible implementation, the liquid crystal layer includes: a first liquid crystal portion and a second liquid crystal portion; the orthographic projection of the first liquid crystal portion onto the substrate coincides with the orthographic projection of the first pixel electrode portion onto the substrate; the orthographic projection of the second liquid crystal portion onto the substrate coincides with the orthographic projection of the second pixel electrode portion onto the substrate.

[0044] Both the first liquid crystal unit and the second liquid crystal unit include: n rows and n columns of sub-liquid crystal units; the azimuth angle of the liquid crystal in each sub-liquid crystal unit is greater than zero and less than 45°, where n is a positive integer greater than or equal to 2.

[0045] In one possible implementation, the material of the first alignment film layer is different from the material of the second alignment film layer.

[0046] This disclosure also provides a display device, which includes the display panel as described in this disclosure.

[0047] This disclosure also provides a method for manufacturing a display panel, used to manufacture the display panel as provided in this disclosure, wherein the manufacturing method includes:

[0048] An array substrate comprising a plurality of sub-pixel electrodes is formed; wherein at least one of the plurality of sub-pixel electrodes comprises: a first pixel electrode portion and a second pixel electrode portion; wherein, in the same sub-pixel electrode, the brightness of the first pixel electrode portion when energized is greater than the brightness of the second pixel electrode portion when energized; the first pixel electrode portion is a block electrode, and at least a portion of the second pixel electrode portion has a plurality of slits;

[0049] Forming opposing substrates;

[0050] Liquid crystal is formed between the array substrate and the opposing substrate, and the array substrate and the opposing substrate are aligned.

[0051] In one possible implementation, forming the opposing substrate includes:

[0052] A second alignment film layer is formed on the side of the opposing substrate facing the array substrate;

[0053] The second alignment film layer is photo-aligned using a first mask, wherein the first mask includes a light-transmitting area and a light-blocking area; wherein at least a portion of the light-transmitting area has a light transmittance of less than 100%.

[0054] In one possible implementation, the first mask has a first mask portion and a second mask portion; wherein the orthographic projection of the first mask portion onto the substrate overlaps with the orthographic projection of the first pixel electrode portion onto the substrate; and the orthographic projection of the second mask portion onto the substrate overlaps with the orthographic projection of the second pixel electrode portion onto the substrate.

[0055] The first mask portion and the second mask portion have the light-transmitting area and the light-blocking area, and the light transmittance of at least part of the light-transmitting area of ​​the second mask portion is 40% to 60% of the light transmittance of the light-transmitting area of ​​the first mask portion. Attached Figure Description

[0056] Figure 1 is a schematic cross-sectional view of the display panel provided in an embodiment of this disclosure;

[0057] Figure 2A is one of the top views provided in the embodiments of this disclosure;

[0058] Figure 2B is a schematic diagram of a single film layer in the sub-pixel electrode layer in Figure 2A;

[0059] Figure 2C is a schematic diagram of the display panel shown in Figure 2A when the light is aligned;

[0060] Figure 2D is a schematic diagram comparing the parameters of the display panel and reference example corresponding to Figure 2C;

[0061] Figure 2E is a schematic diagram comparing the gamma curves of the display panel and the reference example corresponding to Figure 2C;

[0062] Figure 2F is a schematic diagram of a single film layer containing the gate lines in Figure 2A;

[0063] Figure 2G is a schematic diagram of a single film layer containing the data line in Figure 2A;

[0064] Figure 3A is a second top view schematic diagram provided in the embodiment of this disclosure;

[0065] Figure 3B is a schematic diagram of a single film layer in the sub-pixel electrode layer in Figure 3A;

[0066] Figure 3C is a schematic diagram of the display panel shown in Figure 3A when the light is aligned;

[0067] Figure 3D is a schematic diagram comparing the parameters of the display panel and reference example corresponding to Figure 3C;

[0068] Figure 3E is a schematic diagram comparing the gamma curves of the display panel and the reference example corresponding to Figure 3C;

[0069] Figure 4A is a third top view schematic diagram showing an embodiment of this disclosure;

[0070] Figure 4B is a schematic diagram of a single film layer in the sub-pixel electrode layer in Figure 4A;

[0071] Figure 4C is a schematic diagram of the display panel shown in Figure 4A when the light is aligned;

[0072] Figure 4D is a schematic diagram comparing the parameters of the display panel and reference example corresponding to Figure 4C.

[0073] Figure 4E is a schematic diagram comparing the gamma curves of the display panel and the reference example corresponding to Figure 4C;

[0074] Figure 5 is a schematic diagram of the equivalent circuit provided in the embodiment of this disclosure;

[0075] Figure 6 is a schematic diagram of the display of sub-pixels of different display panels;

[0076] Figure 7A is a fourth top view schematic diagram showing an embodiment of this disclosure;

[0077] Figure 7B is a schematic diagram of a single film layer in the sub-pixel electrode layer in Figure 7A;

[0078] Figure 7C is a schematic diagram of the display panel shown in Figure 7A when the light is aligned;

[0079] Figure 7D is a schematic diagram comparing the parameter values ​​of the display panel and the reference example corresponding to Figure 7C;

[0080] Figure 7E is a schematic diagram comparing the gamma curves of the display panel and the reference example corresponding to Figure 7C;

[0081] Figure 8A is a fifth top view schematic diagram showing an embodiment of this disclosure;

[0082] Figure 8B is a schematic diagram of a single film layer in the sub-pixel electrode layer in Figure 8A;

[0083] Figure 8C is a schematic diagram of the display panel shown in Figure 8A when the light is aligned;

[0084] Figure 8D is a schematic diagram comparing the display panel and reference example parameters corresponding to Figure 8C;

[0085] Figure 8E is a schematic diagram comparing the gamma curves of the display panel and the reference example corresponding to Figure 8C;

[0086] Figure 9A is a top view diagram of an embodiment of this disclosure;

[0087] Figure 9B is a schematic diagram of a single film layer in the sub-pixel electrode layer in Figure 9A;

[0088] Figure 10A is a top view diagram (seventh) showing an embodiment of this disclosure;

[0089] Figure 10B is a schematic diagram of a single film layer in the sub-pixel electrode layer in Figure 10A;

[0090] Figure 10C is a schematic diagram of the display panel shown in Figure 10A when the light is aligned;

[0091] Figure 10D is a schematic diagram comparing the display panel and reference example parameters corresponding to Figure 10C;

[0092] Figure 10E is a schematic diagram comparing the gamma curves of the display panel and the reference example corresponding to Figure 10C;

[0093] Figure 11 is a schematic diagram of the display panel manufacturing process provided in the embodiments of this disclosure. Detailed Implementation

[0094] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0095] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0096] As used herein, “approximately” or “substantially the same” includes the stated value and means within an acceptable range of deviations from the specific value, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “substantially the same” may mean a difference relative to the stated value within one or more standard deviations, or within ±30%, 20%, 10%, or 5%.

[0097] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, deviations from the shapes shown in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, sharp corners illustrated may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0098] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0099] Vertical alignment (VA) liquid crystal display panels are prone to color shift or insufficient color saturation due to the inherent characteristics of their display mode. They often utilize a multi-domain design, which allows the liquid crystal molecules in a single pixel to be divided into multiple different alignment domains to achieve a wide viewing angle. This is known as a multi-domain vertical alignment liquid crystal display panel. However, due to the limitations of the optical properties of the liquid crystal molecules themselves, this type of liquid crystal display panel still has color shift and insufficient color saturation problems when viewed from different angles, and there is still a significant difference in image quality when viewed from the front and the side.

[0100] In view of the above, referring to Figures 1, 2A-2G, 3A-3E, and 4A-4E, this disclosure provides a display panel, which includes:

[0101] An array substrate 1, a counter substrate 2, and a liquid crystal layer 3 located between the array substrate 1 and the counter substrate 2 are arranged opposite to each other.

[0102] The array substrate 1 includes a substrate 11 and a plurality of sub-pixel electrodes 14 located on one side of the substrate 11. At least one of the plurality of sub-pixel electrodes 14 includes a first pixel electrode portion 141 and a second pixel electrode portion 142. Referring to FIG2A, optionally, the first pixel electrode portion 141 and the second pixel electrode portion 142 of the same sub-pixel electrode 14 are arranged along a first direction X, and the first pixel electrode portion 141 and the second pixel electrode portion 142 are located on different sides of the gate line 12. In the same sub-pixel electrode 14, the brightness of the first pixel electrode portion 141 when energized is greater than the brightness of the second pixel electrode portion 142 when energized. The first pixel electrode portion 141 is a block electrode, and at least a portion of the second pixel electrode portion 142 has a plurality of slits F.

[0103] In this embodiment, the sub-pixel electrode 14 includes a first pixel electrode portion 141 and a second pixel electrode portion 142. The brightness of the first pixel electrode portion 141 when energized is greater than that of the second pixel electrode portion 142 when energized. The first pixel electrode portion 141 can serve as a bright pixel (or main pixel), and the second pixel electrode portion 142 can serve as a dark pixel (or secondary pixel). By forming different bright and dark regions within a sub-pixel, color shift and insufficient color saturation can be improved. Furthermore, the first pixel electrode portion 141 is a block electrode, and at least a portion of the second pixel electrode portion 142 has multiple slits F. That is, by setting slits F in the region where the dark pixel is located, the electric field between the second pixel electrode portion 142 and the common electrode layer of the opposing substrate 2 can be adjusted through the setting of slits F, thereby adjusting the pretilt angle and / or azimuth angle of the liquid crystal, further improving the color shift and insufficient color saturation, and making the gamma curve of the display panel closer to the standard curve when viewed from the side.

[0104] In one possible implementation, referring to Figures 2A, 2B, 3A, 3B, 4A, and 4B, the second pixel electrode portion 142 includes: a first sub-electrode unit P1 and a second sub-electrode unit P2; the first sub-electrode unit P1 and the second sub-electrode unit P2 extend along a second direction Y and are arranged along a first direction X; the first sub-electrode unit P1 includes: a first sub-part P11 and a second sub-part P12 arranged sequentially along the second direction Y; the second sub-electrode unit P2 includes: a third sub-part P21 and a fourth sub-part P22 arranged sequentially along the second direction Y; optionally, referring to Figure 2B, the second pixel electrode portion 142 includes The upper sub-electrode unit P1 and the lower sub-electrode unit P2 are distributed vertically. The upper sub-electrode unit P1 further includes a lower sub-part P11 and a lower sub-part P12 distributed horizontally. The lower sub-electrode unit P2 further includes a lower sub-part P21 and a lower sub-part P22 distributed horizontally. The lower sub-part P11, the lower sub-part P12, the lower sub-part P21, and the lower sub-part P22 all have slits F. The extension direction of the slit F of the lower sub-part P11 is the same as the extension direction of the slit F of the lower sub-part P22. The extension direction of the slit F of the lower sub-part P12 is the same as the extension direction of the slit F of the lower sub-part P21. Optionally, for example, the angle formed between the extension direction of the slit F of the first sub-part P11 and the second direction Y can be 30° to 60°; for example, the angle formed between the extension direction of the slit F of the first sub-part P11 and the second direction Y can be 30°, 35°, 40°, 45°, 50°, 55°, or 60°; optionally, for example, the angle formed between the extension direction of the slit F of the second sub-part P12 and the second direction Y can be 120° to 150°; for example, the angle formed between the extension direction of the slit F of the second sub-part P12 and the second direction Y can be 120°, 125°, 130°, 135°, 140°, 145°, or 150°.

[0105] In this embodiment of the present disclosure, the second pixel electrode portion 142 includes a first sub-portion P11, a second sub-portion P12, a third sub-portion P21, and a fourth sub-portion P22, which can form a four-domain display in the dark pixel area to improve the problems of color shift and insufficient color saturation.

[0106] In one possible implementation, as shown in Figures 2A and 2B, the entire area of ​​the second pixel electrode portion 142 may be an area with a slit F.

[0107] In another possible implementation, the second pixel electrode portion 142 may have a slit F in some areas and a planar electrode in other areas. For example, referring to Figures 3A, 3B, 4A, and 4B, the second pixel electrode portion 142 further includes a third sub-electrode unit P3 and a fourth sub-electrode unit P4; the third sub-electrode unit P3 and the fourth sub-electrode unit P4 extend along the second direction Y and are arranged sequentially along the first direction X; the third sub-electrode unit P3 is a planar electrode, and the fourth sub-electrode unit P4 is a planar electrode. In this embodiment, the second pixel electrode portion 142 further includes a planar electrode, which can further adjust the electric field in the dark pixel area to form a multi-domain display, thereby improving the problems of color shift and insufficient color saturation.

[0108] In one possible implementation, as shown in Figures 3A and 3B, the first sub-electrode unit P1, the third sub-electrode unit P3, the fourth sub-electrode unit P4, and the second sub-electrode unit P2 are arranged sequentially along the first direction X. That is, in the second pixel electrode portion 142, the planar electrode is located in the middle region, and the electrode with slits is located in the two end regions.

[0109] In one possible implementation, referring to Figures 4A and 4B, the third sub-electrode unit P3, the first sub-electrode unit P1, the second sub-electrode unit P2, and the fourth sub-electrode unit P4 are arranged sequentially along the first direction X. That is, in the second pixel electrode portion 142, the planar electrode is located in the two end regions, and the electrode with the slit is located in the middle region.

[0110] In one possible implementation, referring to Figures 2A, 2B, 3A, 3B, 4A, and 4B, the area of ​​the first sub-pixel electrode portion 141 projected onto the substrate is smaller than the area of ​​the second sub-pixel electrode portion 142 projected onto the substrate. Optionally, the ratio of the area of ​​the first pixel electrode portion 141 projected onto the substrate 11 to the area of ​​the second pixel electrode portion 142 projected onto the substrate 11 is greater than or equal to 1:2.3 and less than or equal to 1:1.8, for example, 1:1.8, 1:1.9, 1:2, 1:2.1, 1:2.2, 1:2.3, etc. The smaller the area of ​​the first pixel electrode portion 141 projected onto the substrate 11, the flatter the liquid crystal in the area where the first pixel electrode portion 141 is located, the earlier the bright spots appear, and the better the color shift in low gray levels. However, the color shift in medium and high gray levels will deteriorate. Among them, when the area ratio is 1:2, the uniformity of the change in Gamma shift in low, medium and high gray levels compared with the standard curve gamma 2.2 is better. That is, the low, medium and high gray level balance of the 1:2 area ratio scheme is better and there is no abrupt change, which has a better effect on improving color shift. Therefore, the present disclosure can set the ratio of the area of ​​the first pixel electrode portion 141 projected onto the substrate 11 to the area of ​​the second pixel electrode portion 142 projected onto the substrate 11 to 1:1.8 to 1:2.3, preferably 1:2.

[0111] In one possible implementation, as shown in Figures 2A, 2B, 3A, 3B, 4A, and 4B, the display panel further includes: a plurality of gate lines 12 extending along the second direction Y, a plurality of data lines 13 extending along the first direction X, a plurality of pixel circuits, and a plurality of first traces 15.

[0112] The first pixel electrode portion 141 and the second pixel electrode portion 142 are located on different sides of the gate line 12, respectively.

[0113] The pixel circuit includes: a first transistor T1, a second transistor T2, and a third transistor T3; the first terminal (e.g., the source) of the first transistor T1 is electrically connected to the data line 13, and the second terminal (e.g., the drain) of the first transistor T1 is electrically connected to the first pixel electrode 141. Referring to Figure 2A, the second terminal of the first transistor T1 and the first pixel electrode 141 can be electrically connected through a first via K1; the first terminal (e.g., the source) of the second transistor T2 is multiplexed from the first terminal of the first transistor T1, and the second terminal (e.g., the drain) of the second transistor T2 is connected to the second... The pixel electrode portion 142 is electrically connected. Referring to FIG. 2A, the second electrode of the second transistor T2 is electrically connected to the second pixel electrode portion 142 via the second via K2. The first electrode (e.g., the source electrode) of the third transistor T3 multiplexes the second electrode of the second transistor T2, and the second electrode (e.g., the drain electrode) of the third transistor T3 is electrically connected to the first trace 15. The pixel circuit is configured to release a portion of the electrical signal loaded onto the second pixel electrode portion 142 to the first trace 15, so that the brightness of the second pixel electrode portion 142 is less than the brightness of the first pixel electrode portion 141. Optionally, the electrical signal may include charge and / or voltage.

[0114] In one possible implementation, referring to FIG2F, the array substrate 1 may further include a first common trace 121 disposed on the same layer as the gate line 12. The first common trace 121 may include a portion extending along the second direction Y and two portions extending along the first direction X. The orthographic projection of the portion of the first common trace 121 extending along the second direction Y on the substrate 11 can pass through the central region of the first pixel electrode portion 141. The two portions of the first common trace 121 extending along the first direction X can be located respectively at the first common trace 121 extending along the second direction Y. On both sides of the extension portion, the orthographic projection of the two portions of the first common trace 121 extending along the first direction X onto the substrate 11 can overlap with the orthographic projection of the two side regions of the first pixel electrode portion 141 onto the substrate 11; the orthographic projection of the first common trace 121 onto the substrate can coincide with the dark pattern in the area of ​​the first pixel electrode portion 141, thus avoiding the problem that the display panel has a low aperture ratio if there is a dark pattern in the area where the first pixel electrode portion 141 is located, and there is also a first common trace 121 that does not overlap with the dark pattern projection.

[0115] In VA display products, after ultraviolet-induced multi-domain vertical alignment (UV2A), for the liquid crystal molecules at the central horizontal dark lines and the branch dark lines on both sides of the horizontal dark lines, when viewed from the side, the liquid crystal molecules are viewed from the side along the long axis direction. Due to the birefringence of the liquid crystal, light leakage occurs in the UV2A alignment display mode. In this embodiment, the setting of the first common trace 121 can block the light leakage in the middle and side areas of the first pixel electrode portion 141.

[0116] In one possible implementation, referring to FIG2F, the array substrate 1 may further include a second common trace group disposed on the same layer as the gate line 12. The second common trace group may extend along the first direction X and be disconnected at the position where it intersects with the gate line 12. The second common trace group may include two second common traces 122 extending along the first direction X, and a portion of the second common traces 122 and a portion of the first common traces 121 extending in the same direction and adjacent to each other are integrally connected.

[0117] In one possible implementation, referring to FIG2F, the array substrate 1 may further include a third common trace 123 and a fourth common trace 124 disposed on the same layer as the gate line 12; the third common trace 123 extends along the second direction Y, and the third common trace 123 in the same extension direction is disconnected at the position where it intersects with the projection of the data line 13 and the first trace 15; the fourth common trace 124 extends along the second direction Y, and at least a portion of the orthographic projection of the fourth common trace 124 onto the substrate 11 may be located in the edge region of the orthographic projection of the sub-pixel electrode 14 onto the substrate 11.

[0118] In one possible implementation, as shown in Figures 2A and 2F, the orthographic projection of at least one of the first common trace 121, the second common trace 122, the third common trace 123, and the fourth common trace 124 onto the substrate 11 overlaps with the orthographic projection of the sub-pixel electrode 14 onto the substrate 11, forming an overlapping capacitor.

[0119] In one possible implementation, referring to Figures 2A and 2F, the first pixel electrode portion 141 overlaps with the first common line 121 and / or the second common line 122 and / or the third common line 123 and / or the fourth common line 124 in a direction perpendicular to the substrate 11 to form a first storage capacitor Cst1, and the first pixel electrode portion 141 may overlap with the common electrode of the opposing substrate in a direction perpendicular to the substrate 1 to form a first liquid crystal capacitor Cpx1; the second pixel electrode portion 142 overlaps with the second common line 122 and / or the third common line 123 and / or the fourth common line 124 in a direction perpendicular to the substrate 1 to form a second storage capacitor Cst2, and the second pixel electrode portion 142 may overlap with the common electrode of the opposing substrate in a direction perpendicular to the substrate 1 to form a second liquid crystal capacitor Cpx2.

[0120] In one possible implementation, referring to FIG5, the pixel circuit may further include: a first storage capacitor Cst1, a first liquid crystal capacitor Cpx1, a second storage capacitor Cst2, and a second liquid crystal capacitor Cpx2. In this embodiment of the present disclosure, the first pixel electrode 141 can be electrically connected to the gate line 12 and the data line 13 through the first transistor T1, and the second pixel electrode 142 can be electrically connected to the gate line 12 and the data line 13 through the second transistor T2. The third transistor T3 is electrically connected to the first trace 15, which can release the stored charge in the second storage capacitor Cst2 corresponding to the second pixel electrode 142 to the first trace 15 through the third transistor T3. This can make the brightness of the first pixel electrode 141 greater than the brightness of the second pixel electrode 142, thereby enabling the first pixel electrode 141 and the second pixel electrode 142 to have different bright and dark areas.

[0121] In one possible implementation, referring to Figures 2A-2B, the array substrate may further include: a second wiring group; the second wiring group includes: two second wirings 144 extending along the second direction Y; the second wirings 144 may be disposed on the same layer as the sub-pixel electrode 14 and spaced apart, and the orthographic projection of the second wirings 144 on the substrate, the region between the first pixel electrode portion 141 and the second pixel electrode portion 142, is within the orthographic projection of the substrate; optionally, two second wirings 144 may be disposed between the first pixel electrode portion 141 and the second pixel electrode portion 142; the orthographic projection of the second wirings 144 on the substrate overlaps with the orthographic projection of the edge of the gate line 12 on the substrate, so that the signal of the gate line 12 can be effectively shielded by the second wirings 144, so that the first pixel electrode portion 141 and the second pixel electrode portion 142 will no longer be interfered with by the gate line 12, but will form a coupling capacitance with the second wirings 144. Optionally, the voltage of the second trace 144 is about 7V (e.g., 8V), and the voltage difference between the second trace 144 and the first pixel electrode 141 and the second pixel electrode 142 is about 0 to 7V, which is less than the voltage difference of 16V to 30V between the gate line 12 and the first pixel electrode 141 and the second pixel electrode 142 in the related art. This can effectively improve the phenomenon that the liquid crystal molecules rotate abnormally and brighten due to the electric field formed by the large voltage difference. Furthermore, in the same second wiring group, the orthographic projection of the gap region between the two second wirings 144 onto the substrate overlaps with the orthographic projection of the middle region of the gate line 12 onto the substrate. That is, the orthographic projection of the middle part of the gate line 12 onto the substrate does not overlap with the orthographic projection of the second wiring 144 onto the substrate, which helps to reduce the load on the gate line 12. Optionally, at least a portion of the shape of the second wiring 144 and the first pixel electrode portion, and / or the second pixel electrode portion cooperate with each other. For example, if the first pixel electrode portion is a protruding structure, then at least a portion of the second wiring 144 is a recessed structure.

[0122] In one possible implementation, referring to Figures 2A-2B, in the same second wiring group, the orthographic projection of the second wiring 144 adjacent to the second pixel electrode 142 onto the substrate is interrupted at the location where it intersects with the orthographic projection of the second electrode of the second transistor T2 onto the substrate. This is to avoid overlapping with the second transistor T2 and / or the third transistor T3, thus preventing interference with the normal display of the display panel.

[0123] In one possible implementation, as shown in Figures 2A-2B, the array substrate may further include a third trace 143 extending along the first direction X on the same layer as the sub-pixel electrodes 14 and located between two adjacent sub-pixel electrodes 14. The third trace 143 may be integrally disposed with the second trace 144 so that the third trace 143 and the second trace 144 form a mesh structure to improve the uniformity of the common voltage signal.

[0124] In one possible implementation, referring to Figures 2A-2B, the orthographic projection of data line 13 on substrate 11 lies within the orthographic projection of third trace 143 on substrate 1. This allows third trace 143 to shield the signal of data line 13, preventing interference between data line 13 and adjacent, uncoupled first pixel electrode portion 141 or second pixel electrode portion 142. Since the linewidth of data line 13 is relatively narrow (e.g., 8 μm), even if third trace 143 completely covers data line 13, it will not cause a significant load on data line 13. However, complete coverage of data line 13 by third trace 143 ensures that its linewidth is greater than or equal to the linewidth of data line 13, reducing the risk of breakage of third trace 143.

[0125] In one possible implementation, referring to Figures 2A, 2B, and 2F, the array substrate may further include a connection portion 145 on the same layer as the sub-pixel electrode 14. The connection portion 145 may be integrally connected with the second trace 144. Optionally, the connection portion 145 may be electrically connected to the third common trace 123 on the layer where the gate line 12 is located via a third via K3. To ensure a good connection, the second trace 144 is widened at the location of the connection portion 145. By electrically connecting the second trace 144 to the third common trace 123, the overall resistance of the second trace 144 and the third common trace 123 can be reduced, thereby decreasing the voltage drop (IR drop) of the common voltage signal and improving the uniformity and anti-interference capability of the common voltage signal.

[0126] In one possible implementation, referring to FIG2C, the display panel further includes: a first alignment film layer 10 located on the array substrate 1, and a second alignment film layer 20 located on the opposing substrate 2; the alignment pretilt angle direction of the first alignment film intersects the alignment pretilt angle direction of the second alignment film, and optionally, the first alignment film 10 may be located on the side of the sub-pixel electrode 14 facing the liquid crystal layer 3; the alignment pretilt angle of the second alignment film layer 20 is smaller than the alignment pretilt angle of the first alignment film layer 10. For example, the orientation pretilt angle of the second alignment film layer 20 can range from 87.1° to 89.1°; optionally, the orientation pretilt angle range can be from 87.6° to 88.6°; optionally, the orientation pretilt angle range can be from 88.0° to 88.6°; optionally, the orientation pretilt angle can be 88.0°, 88.1°, 88.2°, 88.4°, 88.5°, or 88.6°. °; for example, the orientation pretilt angle of the first alignment membrane 10 can be in the range of 87.9° to 89.9°, optionally, the orientation pretilt angle of the first alignment membrane 10 can be in the range of 88.4° to 89.4°; optionally, the orientation pretilt angle of the first alignment membrane 10 can be in the range of 88.7° to 89.2°; optionally, the orientation pretilt angle of the first alignment membrane 10 can be 88.7°, 88.8°, 88.9°, 89.0°, 89.1°, or 89.2°.

[0127] In this embodiment of the present disclosure, by making the alignment pretilt angle on the opposing substrate 2 side smaller than the alignment pretilt angle on the array substrate 1 side, the orientation angle of the liquid crystal can be reduced. The smaller the orientation angle of the liquid crystal, the smaller the gamma shift, which can improve the problems of color shift and insufficient color saturation.

[0128] Optionally, the direction of the alignment pretilt angle on the array substrate 1 side can be different from the direction of the alignment pretilt angle on the opposing substrate 2 side; for example, it can be perpendicular. Optionally, on the array substrate 1 side, the first alignment film 10 can be divided into two regions along the extension direction of the gate line 12, and the alignment pretilt angle directions of the two regions can be opposite. For example, as shown in FIG. 2C, in the first alignment film 10, the alignment pretilt angle direction of the left region can be downward, and the alignment pretilt angle direction of the right region can be upward. On the opposing substrate 2 side, the second alignment film 20 in the bright pixel region can be divided into two regions along the extension direction of the data line 13, and the alignment pretilt angle directions of the two regions are opposite. For example, in the bright pixel, the alignment pretilt angle direction of the upper region is to the right, and the alignment pretilt angle direction of the lower region is to the left. Similarly, the dark pixel region can also be divided into two regions along the extension direction of the data line 13, and the alignment pretilt angle directions of the two regions are opposite. For example, in the dark pixel, the alignment pretilt angle direction of the upper region is to the right, and the alignment pretilt angle direction of the lower region is to the left.

[0129] Referring to Figure 6, the inventors of this disclosure studied and measured the images and color shifts of the first, second, and third display panel structures under different viewing angles, voltages, pretilt angles, and azimuth angles. In the first display panel (REF), the alignment pretilt angle on the array substrate side is the same as that on the opposing substrate side; for example, both the array substrate side and the opposing substrate side are 88.9°. In the second display panel (T>C), the alignment pretilt angle on the array substrate side is greater than that on the opposing substrate side; for example, the array substrate side alignment pretilt angle is 88.9°, and both the opposing substrate side alignment pretilt angles are 88.1°. ° In the third type of display panel (T < C), the alignment pretilt angle on the array substrate side is smaller than the alignment pretilt angle on the opposing substrate side. For example, the alignment pretilt angle on the array substrate side is 88.9°. ° The alignment pretilt angle on the opposite substrate side is 89.2. ° According to the research results, for the UV2A mode, when the alignment pretilt angle of the array substrate is greater than that of the opposing substrate, the liquid crystal orientation angle decreases; when the alignment pretilt angle of the array substrate is less than that of the opposing substrate, the liquid crystal orientation angle increases; and the smaller the liquid crystal orientation angle, the smaller the gamma shift.

[0130] In this embodiment, by controlling the alignment pretilt angle of the array substrate 1 side to be greater than the alignment pretilt angle of the opposing substrate 2 side, the orientation angle of the liquid crystal can be reduced, thereby reducing the gamma shift and improving the problems of color shift and insufficient color saturation. Moreover, as shown in Figure 6, reducing the orientation angle of the liquid crystal can make the gamma curve of the display panel closer to the standard gamma curve (Gamma 2.2). However, at high gray levels, there is a problem that the actual gamma curve of the display panel deviates too much from the standard gamma curve. In the display panel, the bright pixel area mainly controls the display at low gray levels, and the dark pixel area mainly controls the display at high gray levels. By setting a slit F in the dark pixel area, the electric field of the dark pixel area can be adjusted through the slit F. This can improve the problem that the actual gamma curve of the display panel deviates too much from the standard gamma curve at high gray levels, thereby making the overall actual gamma curve of the display panel closer to the standard gamma curve.

[0131] In practical implementation, the alignment pretilt angle of the second alignment film layer 20 can be made smaller than that of the first alignment film layer 10 through various methods. For example, the alignment pretilt angle of the second alignment film layer 20 can be made smaller than that of the first alignment film layer 10 by selecting the alignment film material. For example, the second alignment film layer 20 can use an alignment film material with a low pretilt angle, such as polyimide film (PI), for example, the first type of PI; the first alignment film layer 10 can use an alignment film material with a high pretilt angle, for example, the material of the first alignment film layer 10 can be polyimide film (PI). Film (PI), such as the second type of PI; or, for example, by different exposure rates of the alignment film, the alignment pretilt angle of the second alignment film layer 20 can be made smaller than that of the first alignment film layer 10. For example, when performing ultraviolet light alignment on the first alignment film layer 10, the transmittance of the corresponding mask opening area can be reduced, thereby reducing the exposure energy of the first alignment film layer 10 and increasing the pretilt angle, thus making the alignment pretilt angle of the second alignment film layer 20 smaller than that of the first alignment film layer 10.

[0132] In one possible implementation, the difference between the alignment pretilt angle of the first alignment film layer 10 and the alignment pretilt angle of the second alignment film layer 20 ranges from 0.3° to 1.5°. In another possible implementation, the difference between the alignment pretilt angle of the first alignment film layer and the alignment pretilt angle of the second alignment film layer ranges from 0.5° to 1.1°; the difference between the alignment pretilt angle of the first alignment film layer 10 and the alignment pretilt angle of the second alignment film layer 20 is 0.5°, 0.6°, 0.7°, 0.8°, 0.9°, 1.0°, or 1.1°.

[0133] In one possible implementation, referring to FIG2C, the second alignment film layer 20 includes: a first alignment portion 201 and a second alignment portion 202; the orthographic projection of the first alignment portion 201 on the substrate 11 overlaps with the orthographic projection of the first pixel electrode portion 141 on the substrate 11; the orthographic projection of the second alignment portion 202 on the substrate 11 overlaps with the orthographic projection of the second pixel electrode portion 142 on the substrate 11; the alignment pretilt angle of the first alignment portion 201 is smaller than the alignment pretilt angle of at least a portion of the second alignment portion 202. For example, the orientation pretilt angle of the first alignment portion 201 can be in the range of 87.9° to 88.4°, or optionally, in the range of 88.0° to 88.3°; or optionally, in the range of 88.0°, 88.1°, 88.2°, or 88.3°. For example, the orientation pretilt angle of the second alignment portion 202 can be in the range of 88.2° to 89.8°, or optionally, in the range of 88.3° to 88.7°; or optionally, in the range of 88.3°, 88.4°, 88.5°, 88.6°, or 88.7°.

[0134] In this embodiment of the disclosure, by making the alignment pretilt angle of the first alignment portion 201 smaller than the alignment pretilt angle of at least a portion of the second alignment portion 202, the problem that the actual gamma curve of the display panel is too low compared to the standard gamma curve can be improved at high grayscale, thereby making the actual gamma curve of the display panel closer to the standard gamma curve as a whole.

[0135] In specific implementation, the alignment pretilt angle of the first alignment portion 201 can be made smaller than the alignment pretilt angle of at least a portion of the second alignment portion 202 in various ways. For example, as shown in FIG2C, when the material of the second alignment film layer 20 is determined (e.g., an alignment film material with a low pretilt angle), a halftone mask can be applied to the second alignment portion 202 of the second alignment film layer 20, while a normal mask is applied to the first alignment portion 201. This reduces the exposure energy of the second alignment portion 202 region, thereby increasing the pretilt angle of the second alignment portion 202.

[0136] In one possible implementation, as shown in FIG2C, the alignment pretilt angles of each region within the second alignment section 202 are the same.

[0137] Specifically, taking the display panel shown in FIG2C as Example 1, a reference example display panel is fabricated. Referring to FIGS2D and 2E, in the reference example display panel, the alignment layers on both the TFT side of the array substrate and the CF side of the opposing substrate use materials with high pretilt angles, and normal exposure alignment processes are performed on the alignment layers on both the TFT side of the array substrate and the CF side of the opposing substrate. In Example 1, the first alignment layer 10 on the TFT side of the array substrate uses a material with a high pretilt angle, and the second alignment layer 20 on the CF side of the opposing substrate uses a material with a low pretilt angle. Furthermore, in the second alignment portion 20 of the second alignment layer 20… 2 (i.e., the area where the dark pixel (subpixel) is located) uses a halftone mask process to make the alignment pretilt angle of the first alignment portion 201 smaller than the alignment pretilt angle of the second alignment portion 202, and a slit F is provided in the second pixel electrode portion 142 (i.e., the area where the dark pixel (subpixel) is located) on the TFT side of the array substrate; the obtained gamma curves corresponding to the reference example and embodiment 1 are shown in FIG2E. As can be seen from FIG2E, compared with the display panel of the reference example, the gamma curve of embodiment 1 provided by this disclosure is closer to the standard gamma curve, and has a better color shift and color saturation improvement effect.

[0138] In one possible implementation, referring to FIG3C, the second alignment portion 202 includes: two first sub-alignment portions 2021 and a second sub-alignment portion 2022; the two first sub-alignment portions 2021 are respectively located on both sides of the second sub-alignment portion 2022 along the first direction X; the alignment pretilt angle of the first sub-alignment portion 2021 is smaller than the alignment pretilt angle of the second sub-alignment portion 2022.

[0139] As shown in Figure 6, when the pretilt angle of the alignment film layer on the array substrate side is greater than that on the opposing substrate side (T > C), there will be a problem of reduced brightness in the central region of the dark pixel. The display panel shown in Figure 3C provided in this embodiment of the present disclosure increases the pretilt angle of the central region of the dark pixel by setting a block electrode in the central region of the dark pixel (that is, the region where the second pixel electrode portion 142 is located), setting slits in the end regions on both sides of the dark pixel, and using a halftone mask in the central region. This improves the problem of low brightness in the central region of the dark pixel at high grayscale (providing higher voltage) and lower brightness than the normal gamma curve at high grayscale.

[0140] In one possible implementation, as shown in Figures 3A-3C, the orthographic projection of a first sub-alignment 2021 onto the substrate 11 may overlap with the orthographic projection of a first sub-electrode unit P1 onto the substrate 11; the orthographic projection of another first sub-alignment 2021 onto the substrate 11 may overlap with the orthographic projection of a second sub-electrode unit P2 onto the substrate 11; and the orthographic projection of a second sub-alignment 2022 onto the substrate 11 may overlap with the orthographic projections of a third sub-electrode unit P3 and a fourth sub-electrode unit P4 onto the substrate 11.

[0141] Specifically, taking the display panel shown in FIG3C as Example 2, a reference example display panel is fabricated. Referring to FIG3D and FIG3E, in the reference example display panel, the alignment layers on both the TFT side of the array substrate and the CF side of the opposing substrate use materials with high pretilt angles, and normal exposure alignment processes are performed on the alignment layers on both the TFT side of the array substrate and the CF side of the opposing substrate. In Example 2, the first alignment layer 10 on the TFT side of the array substrate uses a material with a high pretilt angle, and the second alignment layer 20 on the CF side of the opposing substrate uses a material with a low pretilt angle. The second sub-alignment 2022 of the second alignment portion 202 (i.e., the region where the dark pixel (sub-pixel) is located) in layer 20 uses a halftone mask process, and slits F are provided at both ends of the second pixel electrode portion 142 (i.e., the region where the dark pixel (sub-pixel) is located) on the TFT side of the array substrate; the gamma curves corresponding to the reference example and embodiment 2 are shown in FIG3E. As can be seen from FIG3E, compared with the display panel of the reference example, the gamma curve of embodiment 2 provided by this disclosure is closer to the standard gamma curve, and has a better color shift and color saturation improvement effect.

[0142] In one possible implementation, as shown in Figures 4A-4C, the orthographic projection of a first sub-alignment 2021 onto the substrate 11 may overlap with the orthographic projection of a third sub-electrode unit P3 onto the substrate 11; the orthographic projection of another first sub-alignment 2021 onto the substrate 11 may overlap with the orthographic projection of a fourth sub-electrode unit P4 onto the substrate 11; and the orthographic projection of a second sub-alignment 2022 onto the substrate 11 may overlap with the orthographic projections of the first sub-electrode unit P1 and the second sub-electrode unit P2 onto the substrate 11.

[0143] Specifically, taking the display panel shown in Figure 4C as Example 3, a reference example display panel was fabricated. Referring to Figures 4D and 4E, in the reference example display panel, the alignment layers on both the TFT side of the array substrate and the CF side of the opposing substrate use materials with high pretilt angles, and normal exposure alignment processes are performed on both the TFT side of the array substrate and the CF side of the opposing substrate. In Example 3, the first alignment layer 10 on the TFT side of the array substrate uses a material with a high pretilt angle, and the second alignment layer 20 on the CF side of the opposing substrate uses a material with a low pretilt angle. The second sub-alignment 2022 of the second alignment portion 202 (i.e., the region where the dark pixel (sub-pixel) is located) in layer 20 uses a halftone mask process, and a slit F is provided in the middle region of the second pixel electrode portion 142 (i.e., the region where the dark pixel (sub-pixel) is located) on the TFT side of the array substrate; the obtained gamma curves corresponding to the reference example and embodiment 3 are shown in FIG4E. As can be seen from FIG4E, compared with the display panel of the reference example, the gamma curve of embodiment 3 provided by this disclosure is closer to the standard gamma curve, and has a better color shift and color saturation improvement effect.

[0144] In one possible implementation, as shown in Figures 3C and 4C, the alignment pretilt angle of the first sub-alignment 2021 is the same as that of the first alignment part 201.

[0145] In one possible embodiment, the difference between the alignment pretilt angle of the first alignment portion 201 and the alignment pretilt angle of the second alignment portion 202 ranges from 0.1° to 0.7°. In one possible embodiment, the difference between the alignment pretilt angle of the first alignment portion and the alignment pretilt angle of the second alignment portion ranges from 0.2° to 0.6°. In one possible embodiment, the difference between the alignment pretilt angle of the first alignment portion and the alignment pretilt angle of the second alignment portion ranges from 0.3° to 0.5°. In one possible embodiment, the difference between the alignment pretilt angle of the first alignment portion and the alignment pretilt angle of the second alignment portion is 0.3°, 0.4°, or 0.5°.

[0146] In one possible implementation, as shown in Figures 2C, 3C, and 4C, the liquid crystal layer 3 includes: a first liquid crystal portion 31 and a second liquid crystal portion 32; the orthographic projection of the first liquid crystal portion 31 onto the substrate 11 coincides with the orthographic projection of the first pixel electrode portion 141 onto the substrate 11; the orthographic projection of the second liquid crystal portion 32 onto the substrate 11 coincides with the orthographic projection of the second pixel electrode portion 142 onto the substrate 11; both the first liquid crystal portion 31 and the second liquid crystal portion 32 include: n rows and n columns of sub-liquid crystal portions 30; the orientation angle of the liquid crystal in the sub-liquid crystal portion 30 is greater than zero and less than 45°, where n is a positive integer greater than or equal to 2.

[0147] In one possible implementation, as shown in Figures 2C, 3C, and 4C, in the same first liquid crystal unit 31, the azimuth directions of the liquid crystals in each sub-liquid crystal unit 30 may be different; in the same second liquid crystal unit 32, the azimuth directions of the liquid crystals in each sub-liquid crystal unit 30 may be different.

[0148] In one possible implementation, as shown in Figures 7A-7E, a slit F can be provided only in the dark pixels (second pixel electrode portion 142) to improve the problem that the actual gamma curve of the display panel is too low compared to the standard gamma curve at high gray levels, so that the actual gamma curve of the display panel is close to the standard gamma curve overall. The display panel structure shown in Figures 7A-7E differs from the display panel structure shown in Figures 2A-2E in that no grayscale mask is applied to the dark pixels (second pixel electrode portion 142).

[0149] Specifically, taking the display panel shown in FIG7C as Example 4, a reference example display panel was fabricated. Referring to FIG7D and FIG7E, in the reference example display panel, the alignment layers on both the TFT side of the array substrate and the CF side of the opposing substrate use materials with high pretilt angles, and normal exposure alignment processes are performed on both the TFT side of the array substrate and the CF side of the opposing substrate. In Example 4, the first alignment layer 10 on the TFT side of the array substrate uses a material with a high pretilt angle, and the second alignment layer 20 on the CF side of the opposing substrate uses a material with a low pretilt angle. A slit F is provided in the second pixel electrode portion 142 (i.e., the area where the dark pixel (sub-pixel) is located) on the TFT side of the array substrate. The obtained gamma curves corresponding to the reference example and Example 4 are shown in FIG7E. As can be seen from FIG7E, compared to the display panel of the reference example, the gamma curve of Example 4 provided by this disclosure is closer to the standard gamma curve, exhibiting better color shift and color saturation improvement effects.

[0150] In specific implementations, the problems of color shift and insufficient color saturation in the display panel can also be improved simply by adjusting the pretilt angle of the alignment film layer. Optionally, based on the same inventive concept, this disclosure also provides a display panel, as shown in Figures 1, 8A, and 8B, comprising:

[0151] An array substrate 1, a counter substrate 2, and a liquid crystal layer 3 located between the array substrate 1 and the counter substrate 2 are arranged opposite to each other.

[0152] The first alignment film layer 10 is located on the array substrate 1;

[0153] The second alignment film layer 20 is located on the opposing substrate 2;

[0154] The orientation pretilt angle of the second alignment film layer 20 is smaller than that of the first alignment film layer 10.

[0155] In this embodiment of the present disclosure, by making the alignment pretilt angle on the opposing substrate 2 side smaller than the alignment pretilt angle on the array substrate 1 side, the orientation angle of the liquid crystal can be reduced. The smaller the orientation angle of the liquid crystal, the smaller the gamma shift, which can improve the problems of color shift and insufficient color saturation.

[0156] In one possible implementation, referring to Figures 8A-8B, the array substrate may include: a substrate 11, and a plurality of sub-pixel electrodes 14 located on one side of the substrate 11; at least one of the plurality of sub-pixel electrodes 14 includes: a first pixel electrode portion 141 and a second pixel electrode portion 142; wherein, among the same sub-pixel electrodes 14, the brightness of the first pixel electrode portion 141 when energized is greater than the brightness of the second pixel electrode portion 142 when energized. Optionally, the first alignment film 10 may be located on the side of the sub-pixel electrode 14 facing the liquid crystal layer 3.

[0157] Optionally, the orientation pretilt angle of the second alignment film layer 20 can be in the range of 87.1° to 89.1°; optionally, the orientation pretilt angle of the second alignment film layer 20 can be in the range of 87.6° to 88.6°; optionally, the orientation pretilt angle of the second alignment film layer 20 can be in the range of 88.0° to 88.6°; optionally, the orientation pretilt angle of the second alignment film layer 20 can be 88.0°, 88.1°, 88.2°, 88.4°, 88.5°, or 88. 6°; for example, the orientation pretilt angle of the first alignment membrane 10 can be in the range of 87.9° to 89.9°, optionally, the orientation pretilt angle of the first alignment membrane 10 can be in the range of 88.4° to 89.4°; optionally, the orientation pretilt angle of the first alignment membrane 10 can be in the range of 88.7° to 89.2°; optionally, the orientation pretilt angle of the first alignment membrane 10 can be 88.7°, 88.8°, 88.9°, 89.0°, 89.1°, or 89.2°.

[0158] Referring to Figure 6, the inventors of this disclosure have studied and measured the images and color shifts of the first, second, and third display panel structures under different viewing angles, voltages, pretilt angles, and azimuth angles. In the first display panel (REF), the alignment pretilt angle on the array substrate side is the same as that on the opposing substrate side; for example, both the alignment pretilt angles on the array substrate side and the opposing substrate side are 88.9°. In the second display panel (T>C), the alignment pretilt angle on the array substrate side is greater than that on the opposing substrate side; for example, the alignment pretilt angle on the array substrate side is... The alignment pretilt angles on the opposing substrate side are all 88.1°. In the third type of display panel (T < C), the alignment pretilt angle on the array substrate side is smaller than that on the opposing substrate side. For example, the alignment pretilt angle on the array substrate side is 88.9°, and the alignment pretilt angle on the opposing substrate side is 89.2°. According to the research results, for the UV2A mode, when the alignment pretilt angle of the array substrate is greater than that of the opposing substrate, the liquid crystal orientation angle decreases; when the alignment pretilt angle of the array substrate is less than that of the opposing substrate, the liquid crystal orientation angle increases. The smaller the liquid crystal orientation angle, the smaller the gamma shift.

[0159] In this embodiment of the present disclosure, by controlling the alignment pretilt angle of the array substrate 1 side to be greater than the alignment pretilt angle of the opposing substrate 2 side, the orientation angle of the liquid crystal can be reduced, thereby reducing the gamma shift and improving the problems of color shift and insufficient color saturation. Moreover, as shown in Figure 6, reducing the orientation angle of the liquid crystal can make the gamma curve of the display panel closer to the standard gamma curve (Gamma 2.2).

[0160] In practical implementation, the alignment pretilt angle of the second alignment film layer 20 can be made smaller than that of the first alignment film layer 10 through various methods. For example, as shown in Figure 8C, the alignment pretilt angle of the second alignment film layer 20 can be made smaller than that of the first alignment film layer 10 by selecting the alignment film material. For example, the second alignment film layer 20 can use an alignment film material with a low pretilt angle, such as a polyimide film (PI), for example, the first type of PI; the first alignment film layer 10 can use an alignment film material with a high pretilt angle, such as a polyimide film (PI). Film (PI), such as the second type of PI; or, as shown in Figure 9A, the alignment pretilt angle of the second alignment film layer 20 can be made smaller than that of the first alignment film layer 10 by different exposure rates of the alignment film. For example, when performing ultraviolet light alignment on the first alignment film layer 10, the transmittance of the corresponding mask opening area can be reduced, thereby reducing the exposure energy of the first alignment film layer 10 and increasing the pretilt angle, thus making the alignment pretilt angle of the second alignment film layer 20 smaller than that of the first alignment film layer 10.

[0161] Specifically, taking the display panel shown in Figure 8C as Example 5, a reference example display panel was fabricated. Referring to Figures 8D and 8E, in the reference example display panel, the alignment layers on both the TFT side of the array substrate and the CF side of the opposing substrate use materials with high pretilt angles, and both the TFT side of the array substrate and the CF side of the opposing substrate undergo normal exposure alignment processes. In Example 5, the first alignment layer 10 on the TFT side of the array substrate uses a material with a high pretilt angle, and the second alignment layer 20 on the CF side of the opposing substrate uses a material with a low pretilt angle. The obtained gamma curves corresponding to the reference example and Example 5 are shown in Figure 8E. As can be seen from Figure 8E, compared to the display panel of the reference example, the gamma curve of Example 5 provided by this disclosure is closer to the standard gamma curve, exhibiting better color shift and color saturation improvement effects.

[0162] Specifically, taking the display panel shown in Figure 9A as Example 6, a reference example display panel is fabricated. Referring to Figures 9A and 9B, in the reference example display panel, the alignment layers on both the TFT side of the array substrate and the CF side of the opposing substrate use materials with high pretilt angles. Normal exposure alignment processes are performed on the alignment layers on both the TFT side of the array substrate and the CF side of the opposing substrate (i.e., the mask used includes a light-shielding area and a light-transmitting area, wherein the light transmittance of the light-transmitting area is 100%, and the light transmittance of the light-shielding area is 0%). In Example 6... In embodiment 6, the first alignment layer 10 on the TFT side of the array substrate uses a material with a high pretilt angle, and the second alignment layer 20 on the CF side of the substrate uses a material with a high pretilt angle. A halftone mask process is used on the second alignment layer 20 (as shown in FIG. 9A, the transmittance of the opening region can be <100%, for example, the transmittance of the opening region can be 45% to 55%, for example, it can be 50%), so that the gamma curve of embodiment 6 provided in this disclosure is closer to the standard gamma curve, and has a better color shift and color saturation improvement effect.

[0163] In one possible implementation, the difference between the orientation pretilt angle of the first alignment film layer 10 and the orientation pretilt angle of the second alignment film layer 20 ranges from 0.3° to 1.3°. In another possible implementation, the difference between the orientation pretilt angle of the first alignment film layer and the orientation pretilt angle of the second alignment film layer ranges from 0.5° to 1.1°; the difference between the orientation pretilt angle of the first alignment film layer 10 and the orientation pretilt angle of the second alignment film layer 20 is 0.5°, 0.6°, 0.7°, 0.8°, 0.9°, 1.0°, or 1.1°.

[0164] In one possible implementation, referring to Figures 10A-10B, the second alignment film layer 20 includes: a first alignment portion 201 and a second alignment portion 202; the orthographic projection of the first alignment portion 201 onto the substrate 11 overlaps with the orthographic projection of the first pixel electrode portion 141 onto the substrate 11; the orthographic projection of the second alignment portion 202 onto the substrate 11 overlaps with the orthographic projection of the second pixel electrode portion 142 onto the substrate 11; the alignment pretilt angle of the first alignment portion 201 is smaller than the alignment pretilt angle of at least a portion of the second alignment portion 202. For example, the orientation pretilt angle of the first alignment portion 201 can range from 87.9° to 88.4°, or optionally from 88.0° to 88.3°; or optionally from 88.0°, 88.1°, 88.2°, or 88.3°. Similarly, the orientation pretilt angle of the second alignment portion 202 can range from 88.2° to 89.8°, or optionally from 88.3° to 88.7°; or optionally from 88.3°, 88.4°, 88.5°, 88.6°, or 88.7°.

[0165] In this embodiment of the disclosure, by making the alignment pretilt angle of the first alignment portion 201 smaller than the alignment pretilt angle of at least a portion of the second alignment portion 202, the problem that the actual gamma curve of the display panel is too low compared to the standard gamma curve can be improved at high grayscale, thereby making the actual gamma curve of the display panel closer to the standard gamma curve as a whole.

[0166] In specific implementation, the alignment pretilt angle of the first alignment portion 201 can be made smaller than the alignment pretilt angle of at least a portion of the second alignment portion 202 in various ways. For example, as shown in FIG10C, when the material of the second alignment film layer 20 is determined (e.g., an alignment film material with a low pretilt angle), the second alignment portion 202 of the second alignment film layer 20 can be halftone masked, while the first alignment portion 201 can be masked normally. This reduces the exposure energy of the second alignment portion 202 region, thereby increasing the pretilt angle of the second alignment portion 202.

[0167] In one possible implementation, as shown in FIG10C, the alignment pretilt angles of each region within the second alignment section 202 are the same.

[0168] In one possible implementation, referring to FIG10C, the second alignment portion 202 includes: two first sub-alignment portions 2021 and a second sub-alignment portion 2022; the two first sub-alignment portions 2021 are respectively located on both sides of the second sub-alignment portion 2022 along the first direction X; the alignment pretilt angle of the first sub-alignment portion 2021 is smaller than the alignment pretilt angle of the second sub-alignment portion 2022.

[0169] As shown in Figure 6, when the pretilt angle of the alignment film layer on the array substrate side is greater than that on the opposing substrate side (T > C), there will be a problem of reduced brightness in the central region of the dark pixel. The display panel shown in Figure 10C provided in this embodiment of the present disclosure can increase the pretilt angle of the central region of the dark pixel by using a halftone mask in the central region of the dark pixel (that is, the region where the second pixel electrode portion 142 is located), thereby improving the problem of low brightness in the central region of the dark pixel at high grayscale (providing higher voltage) and the problem of lower gamma curve than normal at high grayscale.

[0170] In one possible implementation, as shown in FIG10C, the alignment pretilt angle of the first sub-alignment 2021 is the same as that of the first alignment pretilt angle of the first alignment 201.

[0171] In one possible embodiment, the difference between the alignment pretilt angle of the first alignment portion 201 and the alignment pretilt angle of the second alignment portion 202 ranges from 0.1° to 0.7°. In one possible embodiment, the difference between the alignment pretilt angle of the first alignment portion and the alignment pretilt angle of the second alignment portion ranges from 0.2° to 0.6°. In one possible embodiment, the difference between the alignment pretilt angle of the first alignment portion and the alignment pretilt angle of the second alignment portion ranges from 0.3° to 0.5°. In one possible embodiment, the difference between the alignment pretilt angle of the first alignment portion and the alignment pretilt angle of the second alignment portion is 0.3°, 0.4°, or 0.5°.

[0172] In one possible implementation, as shown in FIG10C, the liquid crystal layer 3 includes: a first liquid crystal portion 31 and a second liquid crystal portion 32; the orthographic projection of the first liquid crystal portion 31 onto the substrate 11 coincides with the orthographic projection of the first pixel electrode portion 141 onto the substrate 11; the orthographic projection of the second liquid crystal portion 32 onto the substrate 11 coincides with the orthographic projection of the second pixel electrode portion 142 onto the substrate 11; both the first liquid crystal portion 31 and the second liquid crystal portion 32 include: n rows and n columns of sub-liquid crystal portions 30; the orientation angle of the liquid crystal in the sub-liquid crystal portion 30 is greater than zero and less than 45°, where n is a positive integer greater than or equal to 2.

[0173] In one possible implementation, as shown in FIG10C, in the same first liquid crystal unit 31, the azimuth directions of the liquid crystals in each sub-liquid crystal unit 30 may be different; in the same second liquid crystal unit 32, the azimuth directions of the liquid crystals in each sub-liquid crystal unit 30 may be different.

[0174] Specifically, taking the display panel shown in FIG10A as Example 7, a reference example display panel is fabricated. In the reference example display panel, as shown in FIG10D and FIG10E, the alignment film layers on the TFT side of the array substrate and the CF side of the opposing substrate both use materials with high pretilt angles, and the alignment film layers on the TFT side of the array substrate and the CF side of the opposing substrate are subjected to normal exposure alignment processes. In Example 7, the first alignment film layer 10 on the TFT side of the array substrate uses a material with high pretilt angles, and the second alignment film layer 20 on the CF side of the opposing substrate uses a material with low pretilt angles. A halftone mask process is used on the second alignment film layer 20 to make the gamma curve of Example 7 provided in this disclosure closer to the standard gamma curve, and to have better color shift and color saturation improvement effects.

[0175] Based on the same inventive concept, embodiments of this disclosure also provide a display device, which includes a display panel as provided in embodiments of this disclosure.

[0176] Based on the same inventive concept, this disclosure also provides a method for manufacturing a display panel, as shown in Figure 11, for manufacturing a display panel as provided in this disclosure, wherein the manufacturing method includes:

[0177] Step S100: Form an array substrate including a plurality of sub-pixel electrodes; wherein, at least one of the plurality of sub-pixel electrodes includes: a first pixel electrode portion and a second pixel electrode portion; wherein, in the same sub-pixel electrode, the brightness of the first pixel electrode portion when powered on is greater than the brightness of the second pixel electrode portion when powered on; the first pixel electrode portion is a block electrode, and at least a portion of the second pixel electrode portion has a plurality of slits.

[0178] Step S200: Forming opposing substrates;

[0179] Step S300: Form liquid crystal between the array substrate and the opposing substrate, and align the array substrate and the opposing substrate.

[0180] In one possible implementation, referring to Figures 2C, 3C, 4C, 9A, and 10C, step S200, forming the opposing substrate, includes:

[0181] Step S210: Form a second alignment film layer on the side of the opposing substrate facing the array substrate;

[0182] Step S220: Photo-align the second alignment film layer using a first mask, wherein the first mask includes a light-transmitting area and a light-blocking area; wherein at least a portion of the light-transmitting area has a transmittance of less than 100%. Optionally, referring to Figures 2C, 3C, 4C, 9A, and 10C, the mask used for UV 2A photo-alignment of the second alignment film layer 20 of the opposing substrate can be used as the first mask. For example, for the first mask used for UV 2A photo-alignment of the second alignment film layer 20 in Figure 2C, the transmittance of the opening area of ​​the first mask corresponding to the second alignment portion 202 can be set to less than 100%.

[0183] In one possible implementation, the first mask has a first mask portion and a second mask portion; wherein the orthographic projection of the first mask portion onto the substrate overlaps with the orthographic projection of the first pixel electrode portion onto the substrate; the orthographic projection of the second mask portion onto the substrate overlaps with the orthographic projection of the second pixel electrode portion onto the substrate; that is, the area in the first mask that corresponds to the first pixel electrode portion 141 can be used as the first mask portion, and the area that corresponds to the second pixel electrode portion 142 can be used as the second mask portion.

[0184] The first mask portion and the second mask portion have a light-transmitting area and a light-blocking area, and the light transmittance of at least a portion of the light-transmitting area of ​​the second mask portion is 40% to 60% of the light transmittance of the light-transmitting area of ​​the first mask portion. Optionally, the light transmittance of at least a portion of the light-transmitting area of ​​the second mask portion is 50% of the light transmittance of the light-transmitting area of ​​the first mask portion. For example, as shown in FIG2C, the light transmittance of the entire light-transmitting area of ​​the second mask portion can be set to 50% of the light transmittance of the light-transmitting area of ​​the first mask portion to achieve halftone masking of the entire dark pixel portion; as another example, as shown in FIG3C, the light transmittance of the middle area of ​​the second mask portion can be set to 50% of the light transmittance of the light-transmitting area of ​​the first mask portion to achieve halftone masking of the middle area of ​​the dark pixel portion.

[0185] In some embodiments, the display panel provided in this disclosure may further include a liquid crystal layer between an array substrate and a counter substrate, a first polarizer on the side of the array substrate away from the counter substrate, and a second polarizer on the side of the counter substrate away from the array substrate, wherein the polarization direction of the first polarizer and the polarization direction of the second polarizer are perpendicular to each other. Other essential components of the display panel are those which should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the scope of this disclosure.

[0186] Based on the same inventive concept, this disclosure also provides a display device, comprising the display panel described above and a backlight module located on the light-incident side of the display panel. The backlight module can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting diodes (LEDs), such as miniature LEDs (Mini LEDs, Micro LEDs, etc.).

[0187] Micro-LEDs, at the sub-millimeter or even micrometer scale, are self-emissive devices, just like organic light-emitting diodes (OLEDs). Like OLEDs, they offer a range of advantages, including high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic LEDs emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic LEDs, such as lower power consumption, better resistance to high and low temperatures, and longer lifespan. When used as backlights, micro-LEDs can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while eliminating glare caused by traditional dynamic backlighting between bright and dark areas, thus optimizing the visual experience.

[0188] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or have different component arrangements.

[0189] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0190] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Therefore, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A display panel, wherein, include: An array substrate, a counter substrate, and a liquid crystal layer located between the array substrate and the counter substrate are disposed opposite to each other. The array substrate includes a substrate and a plurality of sub-pixel electrodes located on one side of the substrate; at least one of the plurality of sub-pixel electrodes includes a first pixel electrode portion and a second pixel electrode portion; wherein, in the same sub-pixel electrode, the brightness of the first pixel electrode portion when energized is greater than the brightness of the second pixel electrode portion when energized; the first pixel electrode portion is a block electrode, and at least a portion of the second pixel electrode portion has a plurality of slits.

2. The display panel as claimed in claim 1, wherein, The display panel further includes: a first alignment film layer located on the array substrate, and a second alignment film layer located on the opposing substrate; the alignment pretilt angle of the second alignment film layer is smaller than the alignment pretilt angle of the first alignment film layer.

3. The display panel as described in claim 2, wherein, The difference between the alignment pretilt angle of the first alignment film layer and the alignment pretilt angle of the second alignment film layer ranges from 0.3° to 1.5°.

4. The display panel as described in claim 2 or 3, wherein, The second alignment film layer includes: a first alignment portion and a second alignment portion; the orthographic projection of the first alignment portion on the substrate overlaps with the orthographic projection of the first pixel electrode portion on the substrate; the orthographic projection of the second alignment portion on the substrate overlaps with the orthographic projection of the second pixel electrode portion on the substrate. The alignment pretilt angle of the first alignment portion is less than the alignment pretilt angle of at least a portion of the second alignment portion.

5. The display panel as claimed in claim 4, wherein, The orientation pretilt angles are the same in each region of the second orientation section.

6. The display panel as claimed in claim 5, wherein, The second alignment portion includes: two first sub-alignment portions and a second sub-alignment portion; the two first sub-alignment portions are respectively located on both sides of the second sub-alignment portion along a first direction; The alignment pretilt angle of the first sub-alignment is smaller than the alignment pretilt angle of the second sub-alignment. Inclination angle.

7. The display panel as claimed in claim 6, wherein, The alignment pretilt angle of the first sub-alignment is the same as that of the first alignment part.

8. The display panel according to any one of claims 4-7, wherein, The difference between the alignment pretilt angle of the first alignment part and the alignment pretilt angle of the second alignment part is in the range of 0.1° to 0.7°.

9. The display panel according to any one of claims 2-8, wherein, The liquid crystal layer includes: a first liquid crystal portion and a second liquid crystal portion; the orthographic projection of the first liquid crystal portion onto the substrate coincides with the orthographic projection of the first pixel electrode portion onto the substrate; the orthographic projection of the second liquid crystal portion onto the substrate coincides with the orthographic projection of the second pixel electrode portion onto the substrate. Both the first liquid crystal unit and the second liquid crystal unit include: n rows and n columns of sub-liquid crystal units; the azimuth angle of the liquid crystal in each sub-liquid crystal unit is greater than zero and less than 45°, where n is a positive integer greater than or equal to 2.

10. The display panel according to any one of claims 1-9, wherein, The second pixel electrode portion includes: a first sub-electrode unit and a second sub-electrode unit; the first sub-electrode unit and the second sub-electrode unit extend along a second direction and are arranged along a first direction; The first sub-electrode unit includes: a first sub-part and a second sub-part arranged sequentially along the second direction; the second sub-electrode unit includes: a third sub-part and a fourth sub-part arranged sequentially along the second direction; The first sub-part, the second sub-part, the third sub-part, and the fourth sub-part all have the slit, and the extension direction of the slit in the first sub-part is the same as the extension direction of the slit in the fourth sub-part; the extension direction of the slit in the second sub-part is the same as the extension direction of the slit in the third sub-part.

11. The display panel as claimed in claim 10, wherein, The second pixel electrode portion further includes: a third sub-electrode unit and a fourth sub-electrode unit; the third sub-electrode unit and the fourth sub-electrode unit extend along the second direction and are arranged sequentially along the first direction; The third sub-electrode unit is a planar electrode, and the fourth sub-electrode unit is a planar electrode.

12. The display panel as claimed in claim 11, wherein, The first sub-electrode unit, the third sub-electrode unit, the fourth sub-electrode unit, and the second sub-electrode unit are arranged sequentially along the first direction.

13. The display panel as claimed in claim 11, wherein, The third sub-electrode unit, the first sub-electrode unit, the second sub-electrode unit, and the fourth sub-electrode unit are arranged sequentially along the first direction.

14. The display panel according to any one of claims 1-13, wherein, The area of ​​the first sub-pixel electrode portion projected onto the substrate is smaller than the area of ​​the second sub-pixel electrode portion projected onto the substrate.

15. The display panel as claimed in claim 14, wherein, The display panel further includes: multiple gate lines extending along a second direction, multiple data lines extending along a first direction, multiple pixel circuits, and multiple first traces; The first pixel electrode portion and the second pixel electrode portion are located on different sides of the gate line, respectively; The pixel circuit includes a first transistor, a second transistor, and a third transistor; a first electrode of the first transistor is electrically connected to the data line, and a second electrode of the first transistor is electrically connected to the first pixel electrode; the first electrode of the second transistor is multiplexed with the first electrode of the first transistor, and the second electrode of the second transistor is electrically connected to the second pixel electrode; the first electrode of the third transistor is multiplexed with the second electrode of the second transistor, and the second electrode of the third transistor is electrically connected to the first trace; the pixel circuit is configured to release a portion of the electrical signal loaded onto the second pixel electrode to the first trace, so that the brightness of the second pixel electrode is less than the brightness of the first pixel electrode.

16. A display panel, wherein, include: An array substrate, a counter substrate, and a liquid crystal layer located between the array substrate and the counter substrate are disposed opposite to each other. A first alignment film layer is located on the array substrate; The second alignment film layer is located on the opposing substrate; Wherein, the alignment pretilt angle of the second alignment film is less than the alignment pretilt angle of the first alignment film.

17. The display panel as claimed in claim 16, wherein, The difference between the alignment pretilt angle of the first alignment film layer and the alignment pretilt angle of the second alignment film layer ranges from 0.3° to 1.5°.

18. The display panel as claimed in claim 16 or 17, wherein, The second alignment film layer includes: a first alignment portion and a second alignment portion; the orthographic projection of the first alignment portion on the substrate overlaps with the orthographic projection of the first pixel electrode portion on the substrate; the orthographic projection of the second alignment portion on the substrate overlaps with the orthographic projection of the second pixel electrode portion on the substrate. The alignment pretilt angle of the first alignment portion is less than the alignment pretilt angle of at least a portion of the second alignment portion.

19. The display panel as claimed in claim 18, wherein, The orientation pretilt angles are the same in each region of the second orientation section.

20. The display panel of claim 18, wherein, The second alignment portion includes: two first sub-alignment portions and a second sub-alignment portion; the two first sub-alignment portions are respectively located on both sides of the second sub-alignment portion along a first direction; The alignment pretilt angle of the first sub-alignment is less than the alignment pretilt angle of the second sub-alignment.

21. The display panel as claimed in claim 20, wherein, The alignment pretilt angle of the first sub-alignment is the same as that of the first alignment part.

22. The display panel as claimed in any one of claims 18-21, wherein, The difference between the alignment pretilt angle of the first alignment part and the alignment pretilt angle of the second alignment part is in the range of 0.1° to 0.7°.

23. The display panel according to any one of claims 16-22, wherein, The liquid crystal layer includes: a first liquid crystal portion and a second liquid crystal portion; the orthographic projection of the first liquid crystal portion onto the substrate coincides with the orthographic projection of the first pixel electrode portion onto the substrate; the orthographic projection of the second liquid crystal portion onto the substrate coincides with the orthographic projection of the second pixel electrode portion onto the substrate. Both the first liquid crystal unit and the second liquid crystal unit include: n rows and n columns of sub-liquid crystal units; the azimuth angle of the liquid crystal in each sub-liquid crystal unit is greater than zero and less than 45°, where n is a positive integer greater than or equal to 2.

24. The display panel according to any one of claims 16-23, wherein, The material of the first alignment film layer is different from the material of the second alignment film layer.

25. A display device, wherein, Includes the display panel as described in any one of claims 1-24.

26. A method for manufacturing a display panel, used to manufacture the display panel as described in any one of claims 1-24, wherein, The manufacturing method includes: An array substrate comprising a plurality of sub-pixel electrodes is formed; wherein at least one of the plurality of sub-pixel electrodes comprises: a first pixel electrode portion and a second pixel electrode portion; wherein, in the same sub-pixel electrode, the brightness of the first pixel electrode portion when energized is greater than the brightness of the second pixel electrode portion when energized; the first pixel electrode portion is a block electrode, and at least a portion of the second pixel electrode portion has a plurality of slits; Forming opposing substrates; Liquid crystal is formed between the array substrate and the opposing substrate, and the array substrate and the opposing substrate are aligned.

27. The manufacturing method as described in claim 26, wherein, The formation of the opposing substrate includes: A second alignment film layer is formed on the side of the opposing substrate facing the array substrate; The second alignment film layer is photo-aligned using a first mask, wherein the first mask includes a light-transmitting area and a light-blocking area; wherein at least a portion of the light-transmitting area has a light transmittance of less than 100%.

28. The manufacturing method as described in claim 27, wherein, The first mask has a first mask portion and a second mask portion; wherein the orthographic projection of the first mask portion onto the substrate overlaps with the orthographic projection of the first pixel electrode portion onto the substrate; and the orthographic projection of the second mask portion onto the substrate overlaps with the orthographic projection of the second pixel electrode portion onto the substrate. The first mask portion and the second mask portion have the light-transmitting area and the light-blocking area, and the light transmittance of at least part of the light-transmitting area of ​​the second mask portion is 40% to 60% of the light transmittance of the light-transmitting area of ​​the first mask portion.

Images