Array substrate, display panel and display device

Abstract

An array substrate. The array substrate comprises a first substrate, a plurality of first electrodes, a plurality of signal line groups, a plurality of third signal lines, a plurality of first transistors and a second electrode layer. The plurality of first electrodes and the plurality of signal line groups are disposed on one side of the first substrate, each signal line group comprising a first signal line and a second signal line. The plurality of third signal lines and the plurality of signal line groups intersect each other in orthographic projection on the first substrate to form a grid structure, one grid defining one pixel region. The first electrode is located in the pixel region. One pixel region is provided with one first transistor. The second electrode layer is disposed on the side of the third signal line away from the first substrate and is electrically connected with the second signal line. The orthographic projection of the second electrode layer on the first substrate does not overlap with the orthographic projection of the first transistor on the first substrate, and at least partially overlaps with the orthographic projection of the plurality of third signal lines on the first substrate, and covers at least part of the edge of the orthographic projection of the first signal line on the first substrate.

Description

Array substrate, display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] With the continuous development of display technology, display devices have been widely used, and people's requirements for display devices are becoming increasingly higher. Among them, high pixel density (Pixels Per Inch; PPI) is an important development direction for display devices. Common display devices can include liquid crystal displays (LCDs) and organic light-emitting diode displays (OLEDs). Thanks to the simpler pixel circuit structure of LCDs (which can contain fewer thin-film transistors and capacitors), LCDs have an advantage in ultra-high pixel densities (such as greater than or equal to 1000 PPI). As pixel density increases, the aperture ratio of display devices gradually decreases, leading to a decrease in transmittance (light transmittance / transmission rate). How to improve the aperture ratio and light transmittance of display devices is a crucial technical problem facing LCD devices.

[0003] Summary of the Invention

[0004] On one hand, an array substrate is provided. The array substrate includes a first substrate, a plurality of first electrodes, a plurality of signal line groups, a plurality of third signal lines, a plurality of first transistors, and a second electrode layer. The plurality of first electrodes and the plurality of signal line groups are disposed on one side of the first substrate. The plurality of signal line groups are spaced apart along a first direction, and each signal line group includes a first signal line and a second signal line, both of which extend along a second direction. The plurality of third signal lines are spaced apart along the second direction, and each third signal line extends along the first direction. The orthographic projections of the plurality of third signal lines and the plurality of signal line groups onto the first substrate intersect to form a grid structure, with each grid defining a pixel region. The first electrodes are located within the pixel regions. The first signal lines are configured to be electrically connected to the gate of the first transistor. The second electrode layer is disposed on the side of the first signal line away from the first substrate, and the second electrode layer is electrically connected to the second signal line. The orthographic projection of the second electrode layer onto the first substrate does not coincide with the orthographic projection of the first transistor onto the first substrate, but at least partially coincides with the orthographic projections of the plurality of third signal lines onto the first substrate, and covers at least a portion of the edge of the orthographic projection of the first signal lines onto the first substrate. The first direction intersects with the second direction.

[0005] In some embodiments, the first signal line includes an integrally formed main body and a plurality of protrusions. The main body extends along a second direction, and at least a portion of the plurality of protrusions is located on the side of the main body away from the second signal line, and the plurality of protrusions are spaced apart along the second direction. The orthographic projection of the second electrode layer on the first substrate covers the orthographic projection of at least a portion of the edges of the plurality of protrusions away from the second signal line on the first substrate, and does not coincide with the orthographic projection of the portion of the main body away from the second signal line on the first substrate.

[0006] In some embodiments, the orthographic projection of the second electrode layer on the first substrate covers the orthographic projection of at least a portion of the edge of the first signal line near the second signal line on the first substrate.

[0007] In some embodiments, the portion of the first signal line whose orthographic projection on the first substrate coincides with the second electrode layer's orthographic projection on the first substrate has a dimension greater than or equal to 1.9 μm along a direction perpendicular to the boundary of the first signal line.

[0008] In some embodiments, the first signal line includes an integrally formed body portion and a plurality of protrusions, the body portion extending along the second direction, the protrusions including a gate region and a base region; the gate region is disposed on the side of the body portion away from the second signal line and is configured to form the gate of the first transistor; at least a portion of the base region is disposed on the side of the body portion away from the second signal line and is configured to support a spacer.

[0009] In some embodiments, the spacer includes a primary spacer and a secondary spacer. The plurality of protrusions include a plurality of base regions, including a first base region and a second base region. The first base region is located on the side of the body portion away from the second signal line and is configured to support the secondary spacer. The second base region is partially located on the side of the body portion away from the second signal line and partially located on the side of the body portion closer to the second signal line, and the second base region is configured to support the primary spacer.

[0010] In some embodiments, the dimension of the portion of the second base plate region located on the side of the main body away from the second signal line along the first direction is greater than the dimension of the portion of the main body located on the side of the main body closer to the second signal line along the first direction.

[0011] In some embodiments, the portion of the second signal line disposed opposite to the second base region protrudes away from the first signal line to form a winding portion. The spacing between the winding portion and the second base region is equal to the spacing between the second signal line and the main body portion.

[0012] In some embodiments, the plurality of pixel regions includes a red pixel region, a green pixel region, and a blue pixel region. The first base region is adjacent to the red pixel region or the green pixel region, and the second base region is adjacent to the blue pixel region.

[0013] In some embodiments, the gate region and the base region are arranged side-by-side along the second direction, with at least a portion of the gate region and at least a portion of the base region belonging to the same protrusion located on opposite sides of a third signal line. The pixel region is adjacent to one gate region and one base region belonging to two protrusions, respectively, and a first gap exists between the gate region and the base region adjacent to the same pixel region. The first transistor includes a source pattern and a drain pattern, the source pattern being electrically connected to the third signal line, and the drain pattern being electrically connected to the first electrode. The drain pattern extends along the second direction, and in the orthographic projection of the drain pattern and the first signal line onto the first substrate, the drain pattern is partially located within the gate region and partially within the first gap.

[0014] In some embodiments, the signal line group and the first electrode are disposed on the same film layer. The array substrate further includes a first insulating layer, a second insulating layer, a first via, and a transition electrode. The first insulating layer is located between the signal line group and the third signal line, and the second insulating layer is located between the third signal line and the second electrode layer. The first via penetrates the first insulating layer and the second insulating layer, and exposes a first region of the first electrode and a second region of the drain pattern. The transition electrode and the second electrode layer are made of the same material and disposed in the same layer, and at least a portion of the transition electrode is located within the first via, electrically connected to the first region and the second region, respectively.

[0015] In some embodiments, the first region and the second region are arranged along the first direction.

[0016] In some embodiments, the first electrode includes a connection portion extending along the first direction. The orthographic projection of the connection portion onto the first substrate lies within the first interval and coincides with the orthographic projection portion of the drain pattern onto the first substrate.

[0017] In some embodiments, the size of the first region in the first direction is greater than or equal to 1.9 μm; and / or, the size of the second region in the first direction is greater than or equal to 2.1 μm.

[0018] In some embodiments, the signal line group and the first electrode are disposed on the same film layer. The array substrate further includes a first insulating layer, a second insulating layer, and a second via. The first insulating layer is located between the signal line group and the third signal line. The second insulating layer is located between the third signal line and the second electrode layer. The second via penetrates the first insulating layer and the second insulating layer, exposing a portion of the second signal line, and at least a portion of the orthographic projection of the second via onto the first substrate is located outside the range of the orthographic projection of the second signal line onto the first substrate. A portion of the second electrode layer is located within the second via and is electrically connected to the second signal line through the second via.

[0019] In some embodiments, the portion of the orthogonal projection of the second via on the first substrate is located in the region between the second signal line and the first signal line, and has a second spacing between them.

[0020] In some embodiments, the second signal line is recessed at the location of the second via to form a first groove on the side away from the first signal line, and the second via exposes at least a portion of the first groove.

[0021] In some embodiments, the portion of the second via that is located outside the range of the second signal line's orthogonal projection on the first substrate has a dimension greater than or equal to 1.9 μm along the first direction; and / or, the portion of the second via that overlaps with the orthogonal projection of the second signal line on the first substrate has a dimension greater than or equal to 2.1 μm along the first direction.

[0022] In some embodiments, the first signal line includes an integrally formed body portion and a plurality of protrusions, at least a portion of which is located on the side of the body portion away from the second signal line. The body portion extends along the second direction, and the protrusions include a gate region and a base region. The second via is offset from the base region in the second direction.

[0023] In some embodiments, the second via and the gate region are disposed opposite to each other in the first direction.

[0024] In some embodiments, the third signal line includes alternately connected first and second extension segments. In the orthographic projection of the third signal line and the signal line group onto the first substrate, the first extension segment partially overlaps with the signal line group, and both ends of the first extension segment penetrate the signal line group. The second extension segment does not overlap with the signal line group. The linewidth of the first extension segment is greater than or equal to the linewidth of the second extension segment.

[0025] In some embodiments, the linewidth of the first extension is greater than or equal to 4.5 μm; and / or, the linewidth of the second extension is 2.5 μm to 8 μm.

[0026] In some embodiments, the second signal line includes alternating third and fourth extension segments, wherein in the orthographic projection of the second signal line and the third signal line onto the first substrate, the third extension segment at least partially overlaps with the third signal line, and the fourth extension segment does not overlap with the third signal line. The linewidth of the third extension segment is less than or equal to the linewidth of the fourth extension segment.

[0027] In some embodiments, the orthographic projection of the third extension on the first substrate extends through the orthographic projection of the third signal line on the first substrate, and there is a third gap between the end of the third extension and the third signal line.

[0028] In some embodiments, the linewidth of the third extension segment is 2.5 μm to 4 μm; and / or, the linewidth of the fourth extension segment is greater than or equal to 4 μm; and / or, the third interval is greater than or equal to 1.9 μm.

[0029] On the other hand, a display panel is provided, comprising the array substrate, color filter substrate, and liquid crystal layer as described in any of the above embodiments. The color filter substrate is disposed opposite to the array substrate, and the liquid crystal layer is disposed between the array substrate and the color filter substrate.

[0030] In some embodiments, the first signal line includes an integrally formed main body and a plurality of protrusions. The main body extends along the second direction. The protrusions include a gate region and a base region, and the plurality of base regions included in the plurality of protrusions include a plurality of first base regions and a plurality of second base regions. The color filter substrate includes a second substrate and a plurality of main spacers and a plurality of sub-spacers disposed on one side of the second substrate. The ends of the main spacers away from the second substrate abut against the array substrate, and the ends of the sub-spacers away from the second substrate abut against the array substrate or have a gap. The end face of the sub-spacer away from the second substrate is a first end face, and the end face of the main spacer away from the second substrate is a second end face. The orthographic projection of the first end face on the array substrate at least partially coincides with the first base region, and the orthographic projection of the second end face on the array substrate at least partially coincides with the second base region.

[0031] In some embodiments, the boundary of the orthographic projection of the first end face on the array substrate is greater than or equal to 2 μm between the boundary of the first base plate region and the boundary of the first base plate region; and / or, the boundary of the orthographic projection of the second end face on the array substrate is greater than or equal to 4.5 μm between the boundary of the second base plate region and the boundary of the second base plate region.

[0032] In some embodiments, the color filter substrate further includes a black matrix disposed on the side of the plurality of primary spacers and the plurality of secondary spacers near the second substrate. The distance between the boundary of the orthographic projection of the first end face on the array substrate and the boundary of the orthographic projection of the black matrix on the array substrate is greater than or equal to 18 μm; and / or, the distance between the boundary of the orthographic projection of the second end face on the array substrate and the boundary of the orthographic projection of the black matrix on the array substrate is greater than or equal to 25 μm.

[0033] In another aspect, a display device is provided, comprising the array substrate described in any of the above embodiments, or comprising the display panel described in any of the above embodiments. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0035] Figure 1 is a structural diagram of a display device according to some embodiments;

[0036] Figure 2 is a structural diagram of a display device according to some embodiments;

[0037] Figure 3 is a partial planar structural diagram of the array substrate according to some embodiments;

[0038] Figure 4 is a magnified view of a portion of region A in Figure 3;

[0039] Figure 5 is a cross-sectional view along section line BB in Figure 4;

[0040] Figure 6 is a planar structural diagram of an array substrate when the second electrode layer covers one edge of the first signal line according to some embodiments;

[0041] Figure 7 is another planar structure diagram of the array substrate when the second electrode layer covers one edge of the first signal line according to some embodiments;

[0042] Figure 8 is a planar structural diagram of the array substrate after the second electrode layer has been removed according to some embodiments;

[0043] Figure 9 is a structural diagram of a display panel according to some embodiments;

[0044] Figure 10 is a projection structure diagram of the sub-spacer and black matrix on the array substrate according to some embodiments;

[0045] Figure 11 is a projection structure diagram of the main spacer and the black matrix on the array substrate according to some embodiments;

[0046] Figure 12 is a structural diagram of a first transistor according to some embodiments;

[0047] Figure 13 is a magnified view of region C in Figure 4;

[0048] Figure 14 is a cross-sectional view along section line DD in Figure 13;

[0049] Figure 15 is a structural diagram of a signal line group and a third signal line according to some embodiments;

[0050] Figures 16 to 20 are process steps of fabrication of array substrates according to some embodiments. Detailed Implementation

[0051] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0052] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0053] In this disclosure, terms such as “down,” “below,” “above,” and “up” are used to explain the relationships between components shown in the accompanying drawings. The terms may be relative concepts and described based on the directions shown in the drawings, or based on the sequence of process steps, but are not limited thereto.

[0054] The term "relative" means that the first element can be directly or indirectly relative to the second element. In the case where the third element is between the first and second elements, although they are still relative to each other, the first and second elements can be understood as being indirectly relative to each other.

[0055] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0056] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0057] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0058] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0059] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0060] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0061] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0062] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0063] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0064] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0065] Referring to FIG1, an embodiment of the present disclosure provides a display device, the display device 1000 being a product having image display functionality. Exemplarily, the display device 1000 can be any device that displays either moving (e.g., video) or fixed (e.g., still image) content, and whether it is text or an image.

[0066] For example, the aforementioned display device 1000 can be any product or component with display function, such as a television, laptop computer, tablet computer, personal digital assistant (PDA), mobile phone, watch, clock, calculator, GPS receiver / navigator, camera, display of camera view (e.g., display of a rearview camera in a vehicle), wearable device, augmented reality (AR) device, virtual reality (VR) device, mixed reality (MR) device, in-vehicle display, flying display, etc.

[0067] In some embodiments, from the perspective of the light emission type of the display device 1000, the display device 1000 can be a liquid crystal display (LCD). From the perspective of the shape of the display device 1000, the display device 1000 can be a flat panel display device or a curved panel display device, etc. From the perspective of the shape of the display device 1000, the display device 1000 can be rectangular or circular, etc. The following uses a rectangular and flat liquid crystal display device as an example to illustrate some embodiments of this disclosure. However, the embodiments of this disclosure are not limited to this, and any other display device can be considered as long as the same technical concept is applied.

[0068] In some embodiments, referring to FIG2, the display device 1000 includes a display panel 1100 and a driving circuit board (not shown in the figure). The driving circuit board may include, for example, a timing controller (TCON), a power management chip (DC / DC), and an adjustable resistor voltage divider circuit (generating Vcom), etc. The driving circuit board may also include other circuit structures, which will not be listed here. The driving circuit board is electrically connected to the display panel 1100 and is used to transmit control signals to the display panel 1100, thereby driving the display panel 1100 to display images. In addition, the display device 1000 may also include a touch structure, an under-display camera, and an under-display fingerprint sensor, enabling the display device 1000 to perform various functions such as touch control, photography, video recording, or fingerprint recognition, which will not be listed here.

[0069] Referring again to Figure 2, when the display device 1000 is a liquid crystal display device, the display device 1000 may further include a backlight module 1200 disposed on the backlight side of the display panel 1100. For example, the backlight module 1200 may be a direct-lit backlight module or an edge-lit backlight module, etc. The backlight module 1200 is used to provide a light source for the display panel 1100. The display panel 1100 includes a plurality of sub-pixels, each of which can adjust the amount of light passing through the display panel 1100, thereby enabling each sub-pixel to display the same or different gray levels to achieve the purpose of image display.

[0070] Referring again to Figure 2, when the display panel 1100 is a liquid crystal display panel, it may include an array substrate 100 and a color filter substrate 200 disposed opposite each other, as well as a liquid crystal layer 300 and a spacer PS disposed between the array substrate 100 and the color filter substrate 200. The color filter substrate 200 may also be referred to as an opposing substrate or a packaging substrate. The spacer PS supports the cell thickness between the array substrate 100 and the color filter substrate 200, ensuring a stable and relatively uniform thickness space between them to support the liquid crystal layer 300. Of course, the structure of the display panel 1100 is not limited to this; it may include other structures, as long as the same technical concept is adopted. For example, the display panel 1100 may also include a first alignment film (not shown in the figure) disposed on the side of the array substrate 100 near the liquid crystal layer 300, and a second alignment film (not shown in the figure) disposed on the side of the color filter substrate 200 near the liquid crystal layer 300, etc.

[0071] The array substrate 100 can be an Advanced Super Dimension Switch (ADS) type or a High-Advanced Dimension Switch (HADS) type with a high aperture ratio. ADS technology places both the common electrode and pixel electrode on the array substrate. A multi-dimensional electric field is formed by the electric field generated at the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer. This allows all oriented liquid crystal molecules within the liquid crystal cell, between the slit electrodes and directly above the electrodes, to rotate, thereby improving the liquid crystal's working efficiency and increasing light transmittance. It also offers advantages such as high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no push murmur. HADS technology is an important implementation of ADS technology, with an even higher aperture ratio.

[0072] The color filter substrate 200 may include a light filter section and a black matrix. The light filter section is used to filter the light incident on the color filter substrate 200 so that each sub-pixel emits light of a certain color (such as red, green, or blue). Different sub-pixels can emit light of the same or different colors, thereby enabling the display panel 1100 to achieve color display. The black matrix is ​​used to cover the first transistor and signal lines on the array substrate to improve the contrast of the display panel (see below for the specific structure of the color filter substrate 200).

[0073] In liquid crystal display devices, the transmittance of the display panel 1100 is a crucial indicator. Improving the transmittance of the display panel 1100 not only enhances the brightness of the display device but also reduces the power consumption of the backlight module 1200, thereby lowering the overall power consumption of the display device. A conventional ADS liquid crystal display panel includes multiple signal lines on an array substrate and a black matrix on a color filter substrate. The orthographic projection of the black matrix onto the array substrate covers the multiple signal lines. However, voltage fluctuations on the signal lines can disturb the liquid crystal layer and potentially cause light leakage in areas of the display panel near the signal lines. To avoid this problem, a larger black matrix is ​​typically required to block the signal lines on the array substrate. This makes it difficult to reduce the size of the black matrix and also hinders improvements in the aperture ratio and transmittance of the display panel.

[0074] To address at least one of the aforementioned technical problems and improve the aperture ratio and transmittance of the display panel, referring to Figures 3, 4, and 5, embodiments of this disclosure provide an array substrate 100. The array substrate 100 includes a first substrate 10, a plurality of first electrodes 11 disposed on one side of the first substrate 10, a plurality of signal line groups 20, a plurality of third signal lines 30, a plurality of first transistors T1, and a second electrode layer 40.

[0075] For example, the first substrate 10 can be a rigid substrate. Rigid substrates may include, but are not limited to, glass substrates or polymethyl methacrylate (PMMA) substrates. Alternatively, the first substrate 10 can also be a flexible substrate. Flexible substrates may include, but are not limited to, polyethylene terephthalate (PET) substrates, polyimide (PI) substrates, or polyethylene naphthalate (PEN) substrates. Furthermore, the first substrate 10 can also be a transparent substrate, allowing light emitted from the backlight module to pass through it, which helps improve the transmittance of the array substrate 100.

[0076] Multiple signal line groups 20 are disposed on one side of the first substrate 10, and the multiple signal line groups 20 are spaced apart along the first direction Y. Multiple third signal lines 30 are spaced apart along the second direction X, and each third signal line 30 extends along the first direction Y. The orthographic projections of the multiple third signal lines 30 and the multiple signal line groups 20 on the first substrate 10 intersect to form a grid structure, and each grid defines a pixel area 101. The first direction Y intersects the second direction X, for example, the first direction Y and the second direction X are perpendicular to each other.

[0077] For example, pixel region 101 can be red pixel region 102, green pixel region 103, or blue pixel region 104. Correspondingly, the color filter substrate can include a red filter, a green filter, and a blue filter. The orthographic projection of a red filter onto the array substrate 100 can at least partially overlap with a red pixel region to form a red sub-pixel, and the light passing through the red sub-pixel is red. The orthographic projection of a green filter onto the array substrate can at least partially overlap with a green pixel region to form a green sub-pixel, and the light passing through the green sub-pixel is green. The orthographic projection of a blue filter onto the array substrate can at least partially overlap with a blue pixel region to form a blue sub-pixel, and the light passing through the blue sub-pixel is blue.

[0078] Each of the plurality of first electrodes 11 is disposed within a pixel region 101. For example, the first electrode 11 may be a pixel electrode.

[0079] In some embodiments, the signal line group 20 and the first electrode 11 can be disposed on the same film layer. In other words, the signal line group 20 and the first electrode 11 are in contact with the same layer of material located on the side of both near the first substrate 10. The spacing between the two and the first substrate 10 can be equal or unequal, but this does not mean that they are formed in the same patterning process. Exemplarily, the signal line group 20 and the first electrode 11 are formed on the same film layer (such as the first substrate 10) through two different processes. Based on this, their materials can also be different. For example, the material of the signal line group 20 may include a metallic conductive material to improve the conductivity of the signal line group 20 and reduce the power consumption of the array substrate, while the material of the first electrode 11 may include a transparent conductive material to improve the transmittance of the first electrode 11 and thus improve the transmittance of the array substrate.

[0080] Each signal line group 20 includes a first signal line 21 and a second signal line 22. For example, each signal line group 20 includes one first signal line 21 and one second signal line 22. Both the first signal line 21 and the second signal line 22 extend along a second direction X. A pixel region 101 is also correspondingly provided with a first transistor T1. The first signal line 21 is configured to be electrically connected to the gate of the first transistor T1, or is configured to form the gate of the first transistor T1.

[0081] For example, the first transistor T1 may be a bottom-gate transistor, that is, the semiconductor layer ACT of the first transistor T1 is disposed on the side of the gate (gate region 25) of the first transistor T1 away from the first substrate 10. For example, the first transistor T1 includes a gate disposed on the same layer as the first signal line 21, a semiconductor layer ACT located on the side of the first signal line 21 away from the first substrate 10, and a source pattern 31 and a drain pattern 32 located on the side of the semiconductor layer ACT away from the first substrate 10.

[0082] A pixel region 101 can be jointly controlled by a first signal line 21 and a third signal line 30 surrounding the pixel region 101. Exemplarily, the first signal line 21 is used to transmit a scan signal, which controls the first transistor T1 to be turned on or off; the third signal line 30 can be a data signal line, configured to transmit a data signal. The gate of the first transistor T1 is electrically connected to the first signal line 21. Furthermore, the first transistor T1 can also be electrically connected to the third signal line 30 and the first electrode 11. For example, the source pattern 31 and drain pattern 32 of the first transistor T1 are electrically connected to the third signal line 30 and the first electrode 11, respectively. The first transistor T1 is configured to be turned on or off under the control of the first signal line 21, and when the first transistor T1 is on, the electrical signal (data signal) transmitted on the third signal line 30 is transmitted to the first electrode 11. At this time, an electric field can be formed between the first electrode 11 and the second electrode layer 40. This electric field can drive the liquid crystal molecules of the liquid crystal layer to deflect. The deflection angle of the liquid crystal molecules is used to control the polarization direction of the light passing through the pixel area 101, and different gray levels can be displayed in conjunction with the polarizer.

[0083] The second electrode layer 40 is disposed on the side of the first signal line 21 away from the first substrate 10, and the second electrode layer 40 is electrically connected to the second signal line 22. For example, the second signal line 22 can be a common voltage signal line used to transmit a constant voltage signal; in this case, the second electrode layer 40 can also be referred to as the common electrode layer. The parallel arrangement of the second signal line 22 and the second electrode layer 40 can reduce the voltage drop across the second electrode layer 40, which is beneficial for improving the voltage stability of the second electrode layer 40.

[0084] For example, the materials of the first electrode 11 and the second electrode layer 40 may both include transparent conductive materials, so that light emitted from the backlight module can pass through the first electrode 11 and the second electrode layer 40. The transparent conductive materials include, but are not limited to, at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and IGZO. The materials of the first electrode 11 and the second electrode layer 40 may be the same, or the materials of the first electrode 11 and the second electrode layer 40 may be different.

[0085] In some embodiments, within the same pixel region 101, one of the first electrode 11 and the second electrode layer 40 can be a continuous block structure, and the other can be a comb-like structure. Thus, the array substrate 100 can form an ADS-type or HADS-type array substrate. For example, the array substrate 100 provided in the embodiments of this disclosure can be used to form a HADS-type array substrate with a high aperture ratio.

[0086] For example, as shown in Figures 3 and 4, the first electrode 11 is a continuous block structure within the pixel area 101, and the portion of the second electrode layer 40 within the pixel area 101 includes multiple elongated electrode strips with slit-shaped openings between adjacent electrode strips.

[0087] The orthographic projection of the second electrode layer 40 on the first substrate 10 does not coincide with the orthographic projection of the first transistor T1 on the first substrate 10. For example, the orthographic projection of the second electrode layer 40 on the first substrate 10 may not coincide with the orthographic projection of the channel layer of the first transistor T1 on the first substrate 10. In this way, the influence of the voltage on the second electrode layer 40 on the first transistor T1 can be reduced, and it is also beneficial to reduce the leakage current of the first transistor T1.

[0088] For example, as shown in FIG4, the second electrode layer 40 may include a clearance opening 42, and the first transistor T1 is disposed within the range of the clearance opening 42.

[0089] The orthographic projection of the second electrode layer 40 onto the first substrate 10 at least partially overlaps with the orthographic projections of the multiple third signal lines 30 onto the first substrate 10. The second electrode layer 40 can effectively shield the electric field generated by the third signal lines 30, reducing the impact of the electric field on the liquid crystal layer, thereby reducing the risk of light leakage near the third signal lines 30. Based on this, it is beneficial to reduce the size of the black matrix used to block the third signal lines 30 on the color filter substrate, which is beneficial to improving the aperture ratio of the array substrate and improving the light extraction efficiency of the array substrate. In addition, the display panel can be set to a normally black mode, that is, when the array substrate is not working, even if the backlight module emits light, the light will not pass through the display panel, which is beneficial to further reduce the light leakage problem of the display panel near the third signal lines 30.

[0090] For example, as shown in Figures 3 and 4, the orthographic projection of the second electrode layer 40 onto the first substrate 10 can cover the portion of the third signal line 30 other than the source pattern used to form the first transistor T1. For instance, in the orthographic projection of the second electrode layer 40, the third signal line 30, and the first signal line 21 onto the first substrate 10, at least the portion where the third signal line 30 and the first signal line 21 overlap is not covered by the second electrode layer 40. Thus, the second electrode layer 40 can cover the third signal line 30 to a great extent without covering the first transistor T1.

[0091] The second electrode layer 40, when projected onto the first substrate 10, also covers at least a portion of the edge of the first signal line 21 projected onto the first substrate 10. Thus, the second electrode layer 40 can also shield the electric field generated at the edge of the first signal line 21, reducing the impact of the electric field generated by signal fluctuations in the first signal line 21 on the liquid crystal molecules in the liquid crystal layer. This reduces the disturbance of the first signal line 21 to the liquid crystal layer. Furthermore, since the HADS array substrate is in a normally black mode, the edge of the first signal line is a dark area, preventing light leakage. This helps to reduce the size of the portion of the black matrix on the color filter substrate covering the first signal line 21, thereby improving the aperture ratio and transmittance of the display panel. Furthermore, compared to covering the entire area of ​​the first signal line 21 with the second electrode layer 40, by covering at least a portion of the edge of the first signal line 21 with the second electrode layer 40, the second electrode layer 40 can shield the electric field generated by the first signal line 21 while significantly reducing the facing area between the second electrode layer 40 and the first signal line 21. This reduces the parasitic capacitance formed between the second electrode layer 40 and the first signal line 21, thereby reducing the load on the first signal line 21 and its power consumption, which in turn helps to reduce the power consumption of the power array substrate 100. In other words, the array substrate provided by the embodiments of this disclosure can balance the aperture ratio and power consumption of the array substrate.

[0092] In some embodiments, referring to FIG. 5, the array substrate 100 further includes a first insulating layer GI and a second insulating layer PVX. The first insulating layer GI is located between the signal line group 20 and the first electrode 11 and the semiconductor layer ACT, to prevent the signal line group 20 from directly short-circuiting with the first electrode 11 and the semiconductor layer ACT. The second insulating layer PVX is located between the third signal line 30 and the second electrode layer 40. As shown in FIG. 5, there may be no insulating layer between the third signal line 30 and the semiconductor layer ACT, for example, the third signal line 30 may be in direct contact with the semiconductor layer ACT (the fabrication method of the array substrate 100 is described below).

[0093] In some embodiments, referring to FIG6, the first signal line 21 includes an integrally formed main body portion 23 and a plurality of protrusions 24. The main body portion 23 extends along a second direction X, and at least a portion of the plurality of protrusions 24 is located on the side of the main body portion 23 away from the second signal line 22, and the plurality of protrusions 24 are spaced apart along the second direction X. Exemplarily, the protrusions 24 may include a gate region 25 and a base region 26; the gate region 25 is used to form the gate of the first transistor T1, and the base region 26 can be used to support the spacer between the array substrate 100 and the color filter substrate.

[0094] The second electrode layer 40 is projected onto the first substrate 10 and covers at least a portion of the edges of the protrusions 24 away from the second signal line 22. The edges of the protrusions 24 away from the second signal line 22 are adjacent to the pixel area 101 (the pixel area 101 located on the upper side of the protrusions 24) and are relatively close to the pixel area 101. The second electrode layer 40 covering at least a portion of the edges of the protrusions 24 away from the second signal line 22 can greatly reduce the influence of the first signal line 21 on the liquid crystal layer in the pixel area 101, thereby reducing the light leakage problem of the first signal line 21 on the side close to the pixel area 101. This is beneficial to reducing the size of the portion of the black matrix on the color filter substrate that covers the protrusions 24, thereby improving the aperture ratio and transmittance of the display panel.

[0095] Furthermore, the orthographic projection of the second electrode layer 40 onto the first substrate 10 does not coincide with the orthographic projection of the edge of the portion of the main body 23 away from the second signal line 22 onto the first substrate 10. As shown in FIG6, on the one hand, the distance between the edge of the portion of the main body 23 located between two adjacent protrusions 24 and the pixel area 101 is large, and it is completely blocked by the black matrix on the color filter substrate. Even if the electric field generated by the first signal line 21 at this location causes some disturbance to the liquid crystal molecules in the liquid crystal layer, there will be no risk of light leakage at the edge of the pixel area 101, so it will not have an adverse effect on the aperture ratio and transmittance of the display panel. On the other hand, it is advantageous to set other structures (transfer electrodes 41) on the second electrode layer 40 in the area between two adjacent protrusions 24, without the need to add a special film layer to set the transfer electrodes 41. The second electrode layer 40 avoids the above-mentioned area, which helps to simplify the structure of the array substrate 100 and reduce the fabrication difficulty of the array substrate 100.

[0096] For example, as shown in FIG6, the orthographic projection of the second electrode layer 40 on the first substrate 10 does not coincide with the orthographic projection of the edge of the portion of the main body 23 located between two adjacent protrusions 24 away from the second signal line 22 on the first substrate 10, and does not coincide with the orthographic projection of the edges of the protrusions 24 located on both sides of the second direction X on the first substrate 10.

[0097] In some embodiments, referring to FIG7, the orthographic projection of the second electrode layer 40 on the first substrate 10 can also cover the orthographic projection of the edge of the first signal line 21 near the second signal line 22 (the lower edge of the first signal line 21 in FIG7) on the first substrate 10. In this way, the second electrode layer 40 shields the electric field generated by the first signal line 21 near the edge of the second signal line 22, reducing the disturbance caused by the first signal line 21 to the liquid crystal molecules in the pixel area 101 (the pixel area 101 below the first signal line 21) located on its side near the second signal line 22, reducing the risk of light leakage in the pixel area 101 below the first signal line 21. This reduces the size of the portion of the black matrix covering the first signal line 21 near the second signal line 22, which is beneficial for improving the aperture ratio and transmittance of the display panel.

[0098] In some embodiments, referring to FIG4, the orthographic projection of the second electrode layer 40 on the first substrate 10 can simultaneously cover the orthographic projection of the edge of the first signal line 21 near the second signal line 22 on the first substrate 10, and cover the orthographic projection of the edges of the plurality of protrusions 24 away from the second signal line 22 on the first substrate 10.

[0099] In the actual fabrication of the array substrate, the second electrode layer 40 can be configured in the manner shown in Figures 4, 6, or 7, or other structures can be used, as long as the same technical concept is adopted (i.e., the orthogonal projection of the second electrode layer 40 on the first substrate 10 covers the orthogonal projection of a portion of the edge of the first signal line 21 on the first substrate 10). The following embodiments of this disclosure are exemplified by using the structure shown in Figure 4 for the second electrode layer 40. It is understood that the embodiments of this disclosure are not limited to this, and other suitable embodiments can be considered.

[0100] As shown in Figure 4, in some embodiments, the portion where the orthographic projection of the first signal line 21 on the first substrate 10 coincides with the orthographic projection of the second electrode layer 40 on the first substrate 10 has a dimension D1 greater than or equal to 1.9 μm along the direction perpendicular to the boundary of the first signal line 21. That is, the edge width D1 of the first signal line 21 covered by the second electrode layer 40 is ≥ 1.9 μm. Thus, the second electrode layer 40 can significantly reduce the disturbance of the liquid crystal molecules in the liquid crystal layer caused by the electric field generated by the first signal line 21, reducing the risk of light leakage at the edge of the first signal line 21 in the display panel. This, in turn, reduces the size of the portion of the black matrix used to cover the first signal line 21, which is beneficial for improving the aperture ratio and transmittance of the display panel.

[0101] For example, the portion where the orthographic projection of the first signal line 21 on the first substrate 10 coincides with the orthographic projection of the second electrode layer 40 on the first substrate 10, along the direction perpendicular to the boundary of the first signal line 21, can have a size D1 of 1.9μm, 2.0μm, 2.2μm, or 2.3μm, etc. The embodiments of this disclosure will not be listed one by one.

[0102] In some embodiments, referring to Figures 4 and 8, the first signal line 21 includes an integrally formed body portion 23 and a plurality of protrusions 24. The body portion 23 extends along a second direction X, and the protrusions 24 include a gate region 25 and a base region 26. The gate region 25 is disposed on the side of the body portion 23 away from the second signal line 22 and is configured to form the gate of the first transistor T1; at least a portion of the base region 26 is disposed on the side of the body portion 23 away from the second signal line 22, and the base region 26 is configured to support a spacer.

[0103] In the embodiments of this disclosure, the gate region 25 and the base region 26 are disposed on the same side of the main body 23, and both are disposed on the side of the main body 23 away from the second signal line 22. In this way, the maximum span of the first signal line 21 in the first direction Y (the distance between the outermost endpoints of the first signal line 21 in the first direction Y) can be greatly reduced. Furthermore, the gate region 25 and the base region 26 can be disposed at least partially side by side in the second direction X, which is beneficial to reduce the space occupied by the first signal line 21, thereby reducing the space of the signal line group 20 in the first direction Y. It can also improve the regularity of the edges of the first signal line 21 and the second signal line 22, that is, reduce the unevenness of the edges of the first signal line 21 and the second signal line 22 in the first direction Y, which can improve the aperture ratio of the array substrate and is beneficial to reduce the size of the black matrix used to block the signal line group 20 in the first direction Y, thereby improving the aperture ratio and transmittance of the display panel.

[0104] It should be noted that in existing array substrate structure designs, the gate region and the base region on the first signal line are typically located on opposite sides of the main body in the first direction Y. This results in raised structures on both sides of the first signal line, occupying a relatively large width. Furthermore, the electric field generated at the raised locations has a significant impact on the liquid crystal layer, requiring a larger black matrix to block potential light leakage areas at the raised locations, thus limiting the improvement of the display panel's aperture ratio. This application, through the aforementioned design, can significantly improve the problems existing in the prior art, which is beneficial for improving the aperture ratio and transmittance of the display panel.

[0105] In some embodiments, referring to FIG9, the color filter substrate 200 may include a second substrate 210 and a black matrix 220 and spacers PS sequentially disposed on the second substrate 210. The spacers PS may include a main spacer PS1 and a secondary spacer PS2. The end of the main spacer PS1 that is away from the second substrate 210 abuts against the array substrate 100, and the end of the secondary spacer PS2 that is away from the second substrate 210 abuts against the array substrate 100 or has a gap.

[0106] For example, when the color filter substrate 200 and the array substrate 100 are not subjected to pressure that brings them closer together, the end of the secondary spacer PS2 away from the second substrate 210 has a gap with the array substrate 100. When the color filter substrate 200 and / or the array substrate 100 are subjected to pressure that brings them closer together, the primary spacer PS1 is compressed and deformed, and the secondary spacer PS2 can also abut against the array substrate 100, serving to support the cell thickness between the color filter substrate 200 and the array substrate 100.

[0107] For example, when the display panel is in its normal state, the main spacer PS1 provides support for the liquid crystal cell thickness. When the display panel is pressed, the color filter substrate 200 is squeezed towards the array substrate 100, the main spacer PS1 is deformed by the compression, and the secondary spacer PS2 participates in supporting the liquid crystal cell thickness, that is, the secondary spacer PS2 contacts the upper surface of the array substrate 100 (the surface near the color filter substrate). The main spacer PS1 and the secondary spacer PS2 together provide support for the liquid crystal cell thickness.

[0108] In one example, the end face of the secondary spacer PS2 furthest from the second substrate 210 is designated as the first end face S1, and the end face of the primary spacer PS1 furthest from the second substrate 210 is designated as the second end face S2. In its natural state (when the display panel is not under pressure), the height difference between the first end face S1 and the second end face S2 can be 0.4 μm to 0.6 μm. Exemplarily, the height difference between the first end face S1 and the second end face S2 can be 0.4 μm, 0.5 μm, or 0.6 μm, etc., and these will not be listed individually in the embodiments of this disclosure.

[0109] Referring to Figures 8 and 9, the plurality of protrusions 24 include a plurality of base regions 26, including a first base region 261 and a second base region 262. The first base region 261 is configured to support the secondary spacer PS2; for example, the orthographic projection of the first end face S1 on the array substrate 100 at least partially coincides with the first base region 261. The second base region 262 is configured to support the primary spacer PS1; for example, the orthographic projection of the second end face S2 on the array substrate 100 at least partially coincides with the second base region 262. Exemplarily, a portion of the orthographic projection of the first end face S1 on the array substrate 100 is located within the first base region 261, and another portion is located within the main body 23; a portion of the orthographic projection of the second end face S2 on the array substrate 100 is located within the second base region 262, and another portion is located within the main body 23.

[0110] In this configuration, the first base area 261 is located on the side of the main body 23 away from the second signal line 22. That is, the first signal line 21 is located at the first base area 261, and there is no protruding structure on the side closest to the second signal line 22. This arrangement helps to reduce the width of the first signal line 21 at the first base area 261 and improves the edge regularity at that location. It also helps to reduce the size of the black matrix along the first direction Y at the first base area 261, thereby improving the aperture ratio and transmittance of the display panel.

[0111] Part of the second base area 262 is located on the side of the main body 23 away from the second signal line 22, and part is located on the side of the main body 23 closer to the second signal line 22. That is, at the location of the second base area 262, the first signal line 21 has protruding structures on both sides in the first direction Y. This increases the area of ​​the second base area 262, thereby ensuring that the main spacer PS1 can always be in contact with the location of the second base area 262, ensuring the supporting effect of the second base area 262 on the main spacer PS1.

[0112] Referring to Figure 8, in some embodiments, the dimension D2 of the portion of the second base plate region 262 located on the side of the main body 23 away from the second signal line 22 along the first direction Y is greater than the dimension D3 of the portion of the main body 23 located on the side closer to the second signal line 22 along the first direction Y. That is, most of the second base plate region 262 is located on the upper side of the main body 23. This helps to reduce the size of the first signal line 21 protruding towards the second signal line 22, i.e., reducing the degree of unevenness of the edges of the first signal line 21 and the second signal line 22 in the first direction Y. This also helps to reduce the size of the black matrix used to block the signal line group 20 in the first direction Y, thereby improving the aperture ratio and transmittance of the display panel.

[0113] Referring again to Figure 8, in some embodiments, the portion of the second signal line 22 that is disposed opposite to the second base region 262 protrudes away from the first signal line 21 to form a winding portion 221. The spacing between the winding portion 221 and the second base region 262 is equal to the spacing between the second signal line 22 and the main body portion 23. This avoids the spacing between the second signal line 22 and the second base region 262 being too small, reducing the risk of a short circuit between the second signal line 22 and the second base region 262.

[0114] In some embodiments, the first base station region 261 is adjacent to the red pixel region 102 or the green pixel region 103; the second base station region 262 is adjacent to the blue pixel region 104. Exemplarily, the first base station region 261 is adjacent to the red pixel region 102 or the green pixel region 103 located on its side away from the second signal line 22 in the first direction Y; for example, a portion of the first base station region 261 is adjacent to the red pixel region 102 located on its side away from the second signal line 22 in the first direction Y, and a portion of the first base station region 261 is adjacent to the green pixel region 103 located on its side away from the second signal line 22 in the first direction Y. Studies have found that, under the same aperture ratio and conditions (such as the same grayscale), the luminous efficiency of the blue pixel area 104 is lower than that of the red pixel area 102 and the green pixel area 103. Based on this, in the embodiments of this disclosure, the first base area 261 is adjacent to the red pixel area 102 or the green pixel area 103; the second base area 262 is adjacent to the blue pixel area 104, which is beneficial to improving the overall transmittance of the display panel.

[0115] In some embodiments, referring to FIG10, the distance D12 between the boundary of the orthographic projection of the first end face S1 of the sub-spacer PS2 onto the array substrate 100 and the boundary of the first sill region 261 is greater than or equal to 2 μm. On the one hand, this ensures that even if a certain alignment error occurs between the array substrate 100 and the color filter substrate, the sub-spacer PS2 can still be supported on the first sill region 261. On the other hand, the flatness requirement for the first sill region 261 on the array substrate 100 used to support the sub-spacer PS2 is relatively low. When the distance D12 is greater than or equal to 2 μm, not only can the design requirements be met, but it is also beneficial to reduce the area of ​​the first sill region 261 and improve the aperture ratio of the array substrate. Exemplarily, the distance D12 between the boundary of the first end face S1 and the boundary of the first sill region 261 can be 2 μm, 2.2 μm, 2.5 μm, or 3 μm, etc., and the embodiments of this disclosure will not be listed one by one.

[0116] In some embodiments, continuing to refer to FIG10, the distance D14 between the boundary of the orthographic projection of the first end face S1 on the array substrate 100 and the boundary of the orthographic projection of the black matrix 220 on the array substrate 100 is greater than or equal to 18 μm. In this way, even if the sub-spacer PS2 slides to a certain extent, the black matrix 220 can still block the location of the sub-spacer PS2, reducing the risk of light leakage around the sub-spacer PS2. Exemplarily, the distance D14 can be 18 μm, 19 μm, 20 μm, or 21 μm, etc., and will not be listed individually in the embodiments of this disclosure. It should be noted that the orthographic projection of the black matrix 220 on the array substrate 100 is not limited to the shape and size shown in Figures 10 and 11. Figures 10 and 11 only illustrate the corresponding size and dimensions of the black matrix 220 required to cover the main spacer PS1 and the secondary spacer PS2. In order to cover other structures (such as signal line group 20 and third signal line 30), the black matrix 220 may also include other parts, and the embodiments of this disclosure do not limit this.

[0117] Referring to Figure 11, the distance D13 between the boundary of the orthographic projection of the second end face S2 of the main spacer PS1 onto the array substrate 100 and the boundary of the second sill region 262 is greater than or equal to 4.5 μm. On one hand, this ensures that even if a certain alignment error occurs between the array substrate 100 and the color filter substrate, the main spacer PS1 can still be supported on the second sill region 262, ensuring the support effect of the main spacer PS1. On the other hand, the flatness requirement for the second sill region 262 on the array substrate 100 used to support the main spacer PS1 is high. When the distance D13 is greater than or equal to 2 μm, the main spacer PS1 can be supported on a relatively flat surface, reducing the risk of slippage. For example, the distance D13 between the boundary of the second end face S2 and the boundary of the second sill region 262 can be 4.5 μm, 5 μm, 6 μm, or 6.5 μm, etc., and will not be listed individually in the embodiments of this disclosure.

[0118] In some embodiments, continuing to refer to FIG10, the interval D15 between the boundary of the orthographic projection of the second end face S2 on the array substrate 100 and the boundary of the orthographic projection of the black matrix 220 on the array substrate 100 is greater than or equal to 25 μm. Thus, even if the main spacer PS1 slides a large distance (e.g., into the pixel area 101), the black matrix can still shield the scratched area on the array substrate 100, reducing the risk of light leakage in the display panel. Exemplarily, the interval D15 can be 25 μm, 27 μm, 28.5 μm, or 30 μm, etc., and will not be listed individually in the embodiments of this disclosure.

[0119] It should be noted that the orthographic projection of the black matrix 220 on the array substrate 100 includes not only the shape and size shown in Figures 10 and 11. Figures 10 and 11 only illustrate the corresponding size and dimensions of the black matrix 220 required to cover the main spacer PS1 and the secondary spacer PS2. In order to cover other structures (such as signal line group 20 and third signal line 30), the black matrix 220 may also include other parts.

[0120] In some embodiments, as shown in FIG8, the gate region 25 and the base region 26 belonging to the same protrusion 24 are respectively located on both sides of a third signal line 30. This not only separates the gate region 25 and the base region 26 on the same protrusion 24 from each other, avoiding the spacer PS from abutting against the first transistor T1 and reducing the risk of the first transistor T1 being damaged by pressure, but also simplifies the pattern of the gate region 25 and the base region 26, reducing the fabrication difficulty of the first signal line 21. The pixel region 101 is adjacent to a gate region 25 and a base region 26 belonging to two protrusions 24 respectively, and there is a first gap L1 between the gate region 25 and the base region 26 adjacent to the same pixel region 101. In this way, the structure of the first transistor T1 can be set within the first gap L1 so that the boundary of the first transistor T1 in the first direction Y does not exceed the edge of the protrusion 24, reducing the space occupied by the first signal line 21 and the first transistor T1 in the first direction Y, thereby improving the aperture ratio of the array substrate.

[0121] In some embodiments, as shown in FIG12, the first transistor T1 includes a source pattern 31 and a drain pattern 32. The source pattern 31 is electrically connected to the third signal line 30, and the drain pattern 32 is electrically connected to the first electrode 11. Exemplarily, the source pattern 31 and the third signal line 30 are integrally disposed, that is, the source pattern 31 and the third signal line 30 are a whole, and the two are different regions artificially divided on the same physical structure, or in other words, the two may not have obvious boundaries in the actual structure. The drain pattern 32 extends along the second direction X, and in the orthogonal projection of the drain pattern 32 and the first signal line 21 on the first substrate 10, part of the drain pattern 32 is located within the gate region 25, and part is located within the first interval L1. That is, part of the drain pattern 32 is located on the gate region 25, and part extends into the first interval L1, and the part of the drain pattern 32 extending into the first interval L1 is electrically connected to the first electrode 11. In this way, the space occupied by the first transistor T1 in the first direction Y can be reduced, which is beneficial to improving the aperture ratio of the array substrate.

[0122] In some embodiments, referring to Figures 5 and 12, the orthographic projection of the drain pattern 32 on the first substrate 10 partially coincides with the orthographic projection of the first electrode 11 on the first substrate 10. The array substrate 100 also includes a first via V1 and a transition electrode 41. The first via V1 penetrates the first insulating layer GI and the second insulating layer PVX, and exposes a first region 111 of the first electrode 11 and a second region 321 of the drain pattern 32. The transition electrode 41 and the second electrode layer 40 are made of the same material and are disposed in the same layer. The transition electrode 41 is at least partially located within the first via V1 and is electrically connected to the first region 111 and the second region 321, respectively. Compared to connecting the electrodes to the first electrode and the drain pattern through two vias respectively, in the embodiments of this disclosure, the first electrode 11 and the drain pattern 32 can be exposed simultaneously through a single via (first via V1). This not only reduces the number of vias but also allows the bottom morphology of the first via V1 to have certain undulations, which can reduce the step difference formed on the array substrate at the first via V1. In this way, the PI liquid (used to prepare the alignment film) flows and diffuses within the first via V1, avoiding uneven diffusion of the PI liquid within the first via V1, thereby reducing Mura-type defects caused by uneven diffusion of the PI liquid.

[0123] In some embodiments, as shown in FIG12, the first region 111 and the second region 321 are arranged along the first direction Y, that is, the first via V1 extends along the first direction Y. In this way, the size of the first via V1 and the transition electrode 41 in the second direction X can be reduced, thereby increasing the space for setting the base region 26. This is beneficial for setting the base region 26 of the first signal line 21 on the side of the main body 23 away from the second signal line 22, thereby improving the aperture ratio and transmittance of the array substrate 100.

[0124] In some embodiments, continuing to refer to FIG12, the first electrode 11 includes a connection portion 112, which extends along a first direction Y. The orthographic projection of the connection portion 112 on the first substrate 10 is located within a first interval L1 and coincides with the orthographic projection portion of the drain pattern 32 on the first substrate 10.

[0125] Referring again to Figure 12, in some embodiments, the dimension D4 of the first region 111 in the first direction Y is greater than or equal to 1.9 μm. This ensures that the first via V1 can expose the first electrode 11 and guarantees the contact area between the adapter electrode 41 and the first electrode 11, reducing the contact resistance between them. Exemplarily, the dimension D4 of the first region 111 in the first direction Y can be 1.9 μm, 2.0 μm, 2.2 μm, or 2.3 μm, etc., and these will not be listed individually in the embodiments of this disclosure.

[0126] Referring again to Figure 12, the dimension D5 of the second region 321 in the first direction Y is greater than or equal to 2.1 μm. This ensures that the first via V1 can expose the drain pattern 32, and also helps to increase the contact area between the transition electrode and the drain pattern 32, thereby reducing the contact resistance between them. For example, the dimension D5 of the second region 321 in the first direction Y can be 2.1 μm, 2.2 μm, 2.3 μm, or 2.5 μm, etc., and these will not be listed individually in the embodiments of this disclosure.

[0127] Referring to Figures 13 and 14, in some embodiments, the array substrate 100 further includes a second via V2. The second via V2 penetrates the first insulating layer GI and the second insulating layer PVX, and exposes a portion of the second signal line 22. A portion of the second electrode layer 40 is located within the second via V2 and is electrically connected to the second signal line 22 through the second via V2. Furthermore, at least a portion of the orthographic projection of the second via V2 onto the first substrate 10 lies outside the range of the orthographic projection of the second signal line 22 onto the first substrate 10. Similar to the first via V1, the design of the second via V2 can create a certain undulating morphology at its bottom. This facilitates the diffusion of the PI liquid within the second via V2, avoiding uneven diffusion of the PI liquid within the first via V1, and thus reducing Mura-type defects caused by uneven PI liquid diffusion.

[0128] Referring again to Figures 13 and 14, in some embodiments, the portion of the orthographic projection of the second via V2 onto the first substrate 10 is located in the region between the second signal line 22 and the first signal line 21. That is, the second via V2 is disposed on the side of the second signal line 22 closer to the first signal line 21. This increases the distance between the pixel region 101 adjacent to the second signal line 22 and the second via V2. A greater distance exists between the boundary of the orthographic projection of the black matrix on the color filter substrate onto the array substrate 100 and the boundary of the second via V2, avoiding light leakage caused by Mura-type defects due to the second via V2, and thus increasing the aperture ratio of the array substrate 100. The portion of the orthographic projection of the second via V2 onto the first substrate 10 located between the second signal line 22 and the first signal line 21 has a second gap L2 with the first signal line 21. This prevents short circuits between the second electrode layer 40 and the first signal line 21.

[0129] As shown in Figures 8 and 13, the second signal line 22 is recessed (downward) at the location of the second via V2, forming a first groove 222 away from the first signal line 21. The second via V2 exposes at least a portion of the first groove 222. This increases the spacing between the second via V2 and the first signal line 21, and reduces the distance between the second electrode layer 40 and the first signal line 21, thus preventing a short circuit between the second electrode layer 40 and the first signal line 21 at the location of the second via V2.

[0130] Referring again to Figures 8 and 13, the portion of the second via V2 located outside the orthographic projection of the second signal line 22 onto the first substrate 10 has a dimension D6 greater than or equal to 1.9 μm along the first direction Y. This ensures that the second via V2 is partially located outside the second signal line 22, forming a step at the bottom of the second via V2, thus improving the flow and diffusion of the PI liquid within the second via V2. Exemplarily, the dimension D6 of the portion of the second via V2 outside the second signal line 22 along the first direction Y can be 1.9 μm, 2.1 μm, 2.3 μm, or 2.5 μm, etc., and these will not be listed individually in the embodiments of this disclosure.

[0131] The portion of the second via V2 that overlaps with the orthographic projection of the second signal line 22 on the first substrate 10 has a dimension D7 along the first direction Y greater than or equal to 2.1 μm. This ensures that the second via V2 exposes sufficient space for the second signal line 22, which helps increase the contact area between the second electrode layer 40 and the second signal line 22, and reduces the contact resistance between them. Exemplarily, the dimension D7 of the portion of the second via V2 exposing the second signal line 22 along the first direction Y can be 2.1 μm, 2.2 μm, 2.3 μm, or 2.5 μm, etc., and these will not be listed individually in the embodiments of this disclosure.

[0132] In some embodiments, as shown in FIG8, when the first signal line 21 includes a main body portion 23 and a protrusion portion 24, the protrusion portion 24 includes a gate region 25 and a base region 26, and the array substrate 100 includes a second via V2, the second via V2 and the base region 26 are offset in the second direction X. This avoids the second via V2 and the base region 26 being aligned in the first direction Y, reducing the possibility of a protrusion forming on the side of the second signal line 22 away from the first signal line 21, and thus improving the aperture ratio of the array substrate 100.

[0133] Referring again to Figure 8, the second via V2 can be disposed opposite to the gate region 25 in the first direction Y. Since there is no protrusion structure on the side of the gate region 25 near the second signal line 22, the second via V2 being disposed opposite to the gate region 25 in the first direction Y will not cause the second signal line 22 to form a protrusion at the second via V2, which is beneficial to improving the aperture ratio of the array substrate 100.

[0134] In some embodiments, referring to FIG15, the third signal line 30 includes alternating first extension segments 33 and second extension segments 34. In the orthographic projection of the third signal line 30 and the signal line group 20 onto the first substrate 10, the first extension segment 33 partially overlaps with the signal line group 20, while the second extension segment 34 does not overlap with the signal line group 20. The linewidth (dimension along the direction perpendicular to the first extension segment 33) D8 of the first extension segment 33 is greater than or equal to the linewidth (dimension along the direction perpendicular to the second extension segment 34) D9 of the second extension segment 34. Thus, since the signal line group 20 is located on the side of the third signal line 30 closer to the first substrate 10, and the signal line group 20 has a certain thickness, the surface of the first insulating layer GI1 away from the first substrate 10 will form an undulating morphology at the location of the signal line group 20. The fact that the linewidth of the first extension segment 33 is greater than or equal to the linewidth of the second extension segment 34 can reduce the risk of the third signal line 30 breaking or experiencing excessive local resistance at the ramp point.

[0135] In some embodiments, the linewidth D8 of the first extension segment 33 is greater than or equal to 4.5 μm, which ensures that the first extension segment 33 is continuous at the climbing position and that the resistance does not increase significantly. Exemplarily, the linewidth D8 of the first extension segment 33 can be 4.5 μm, 5.0 μm, 5.2 μm, 7 μm, or 8 μm, etc., and the embodiments of this disclosure will not be listed one by one.

[0136] The linewidth D9 of the second extension segment 34 can be 2.5μm to 8μm. For example, the linewidth D9 of the second extension segment 34 can be 2.5μm to 4.5μm, or 4.5μm to 8μm. When the linewidth D9 of the second extension segment 34 is 2.5μm to 4.5μm, the linewidth D8 of the first extension segment 33 can be greater than the linewidth of the second extension segment 34. In this case, the linewidth D9 of the second extension segment 34 can be, for example, 2.5μm, 3μm, 4μm, or 4.5μm. When the linewidth D9 of the second extension segment 34 is 4.5μm to 8μm, the size of the first extension segment D8 can be equal to the size of the second extension segment 34. In this case, the linewidth D9 of the second extension segment 34 can be, for example, 4.5μm, 6μm, 7μm, or 8μm, etc., and the embodiments of this disclosure will not be listed one by one.

[0137] In some embodiments, continuing to refer to FIG15, the second signal line 22 includes alternating third extensions 27 and fourth extensions 28. In the orthographic projection of the second signal line 22 and the third signal line 30 onto the first substrate 10, the third extension 27 at least partially overlaps with the third signal line 30, while the fourth extension 28 does not overlap with the third signal line 30. The linewidth (dimension along the direction perpendicular to the third extension 27) D10 of the third extension 27 is smaller than the linewidth D11 of the fourth extension 28. This reduces the facing area between the third signal line 30 and the second signal line 22, reduces the parasitic capacitance formed between the third signal line 30 and the second signal line 22, thereby reducing the load on the third signal line 30 and facilitating a reduction in the power consumption of the array substrate.

[0138] In some embodiments, as shown in FIG15, the orthographic projection of the third extension 27 on the first substrate 10 passes through the orthographic projection of the third signal line 30 on the first substrate 10, and there is a third gap L3 between the end of the third extension 27 and the third signal line 30. In this way, it is possible to avoid the third extension 27 not being able to be positioned opposite to the third signal line 30 due to manufacturing errors. That is, it is possible to ensure that the third signal line 30 can be positioned opposite to the third extension 27, thereby reducing the parasitic capacitance formed between the third signal line 30 and the second signal line 22, thereby reducing the load on the third signal line 30 and helping to reduce the power consumption of the array substrate.

[0139] In some embodiments, the linewidth D11 of the fourth extension 28 of the second signal line 22 can be greater than or equal to 4.5 μm. This allows the second signal line 22 to have lower resistance, which is beneficial for reducing the voltage across the second signal line 22 and the second electrode layer 40. Exemplarily, the linewidth D11 of the fourth extension 28 can be 4.5 μm, 5.0 μm, 5.5 μm, or 6 μm, etc., and these embodiments will not be listed individually in this disclosure.

[0140] The linewidth D10 of the third extension segment 27 can be 2.5μm to 4μm. For example, the linewidth D10 of the third extension segment 27 can be 2.5μm, 3.0μm, 3.5μm, or 4.5μm, etc., and the aforementioned third interval L3 can be greater than or equal to 1.9μm. For example, the third interval L3 can be 1.9μm, 2.0μm, 2.3μm, or 2.5μm, etc. The embodiments of this disclosure will not be listed one by one.

[0141] Some embodiments of this disclosure also provide a method for fabricating an array substrate. Referring to Figures 16-20, the method may include steps S100-S400. Figures 16-20 illustrate the fabrication process of the array substrate in the cross-section shown in Figure 8.

[0142] S100, referring to FIG16, a plurality of first electrodes 11 are formed on the first substrate 10. FIG16 only schematically shows one first electrode 11.

[0143] For example, step S100 may include: forming a full-layer first transparent electrode layer on the first substrate 10, and then patterning the first transparent electrode layer using a photolithography process to form a plurality of first electrodes 11. The portion of each first electrode 11 within a pixel region is a continuous block structure; in other words, the portion of the first electrode 11 within the pixel region is not patterned during the photolithography process. Furthermore, the material of the first electrode 11 may include a transparent conductive material, such as ITO, and the thickness of the first electrode 11 may be [missing information].

[0144] S200, referring to FIG17, a signal line group 20 is formed on the first substrate 10. FIG17 only schematically shows the first signal line 21 of the signal line group 20.

[0145] For example, step S200 may include: forming a full-layer first conductive layer on the first substrate 10 and the first electrode 11, then patterning the first conductive layer by photolithography, removing the portion of the first conductive layer located in the pixel area, and forming a patterned first signal line 21 and a second signal line (not shown in the figure). The structure of the first signal line 21 and the second signal line may be the structure described in any of the above embodiments.

[0146] Furthermore, the material of the first conductive layer may include metallic conductive materials, such as one or more of titanium, aluminum, copper, molybdenum, niobium, nickel, and their alloys, or the first conductive layer may also be a metallic multilayer structure. Exemplarily, the first conductive layer may include one or a combination of the following structures: titanium-aluminum-titanium (Ti / Al / Ti) multilayer structure, molybdenum-aluminum (Mo / Al) multilayer structure, molybdenum-aluminum-molybdenum (Mo / Al / Mo) multilayer structure, molybdenum-niobium-titanium (MoNb / Ti) multilayer structure, molybdenum-niobium-titanium-copper (MoNb / Ti / Cu) multilayer structure, molybdenum-niobium-copper (MoNb / Cu) multilayer structure, molybdenum-nickel-titanium-copper (MTD / Cu) multilayer structure, molybdenum-niobium-copper-molybdenum-titanium-nickel (MoNb / Cu / MTD) multilayer structure, molybdenum-nickel-titanium-copper-molybdenum-nickel-titanium (MTD / Cu / MTD) multilayer structure, molybdenum-neodymium-copper multilayer structure, MoNb-copper-MoNb multilayer structure, and AlNb-molybdenum-AlNd multilayer structure.

[0147] In a specific example, the first conductive layer comprises a molybdenum-aluminum-molybdenum stacked structure, and along the direction away from the first substrate, the thicknesses of the three molybdenum-aluminum-molybdenum films are respectively: and

[0148] S300, referring to Figure 18, prepares and forms the first insulating layer GI.

[0149] For example, the first insulating layer described above can be formed by a thin film deposition process. The material of the first insulating layer may include at least one of silicon nitride and silicon oxide. The first insulating layer can be a single-layer structure or a multilayer structure, which will not be listed here.

[0150] S400, continuing to refer to Figure 18, the semiconductor layer ACT and the third signal line 30 are fabricated.

[0151] For example, step S400 may include: firstly, forming a semiconductor layer and a second conductive layer sequentially through a film deposition process, wherein both the semiconductor layer and the second conductive layer are integral layer structures. A mask layer material is coated onto the second conductive layer, and a semi-transparent mask (HTM) is used to expose the mask layer material, wherein partial exposure is performed on the portion of the mask layer material located in the channel region, and then a mask layer is formed. A dry etching process is used to first pattern the second conductive layer, forming a third signal line 30 and a drain pattern 32 of the first transistor, retaining the portion of the second conductive layer located between the third signal line 31 and the drain pattern 32 (the portion located in the channel region). Then, a wet etching process is used to pattern the semiconductor layer, etching away the areas of the semiconductor layer not covered by the second conductive layer, retaining the portion located in the channel region. Then, the mask layer is removed by ashing exposure, and a second dry etching process is used to remove the portion of the second conductive layer located in the channel region, exposing the channel region of the semiconductor layer. The above-described process for fabricating the semiconductor layer and the third signal line can reduce the use of a mask, which helps to simplify the fabrication process of the array substrate and reduce the fabrication cost of the array substrate.

[0152] The semiconductor layer material includes semiconductor materials, such as metal oxide materials. Metal oxide materials include, but are not limited to: indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxides (In-free OS), rare earth-doped oxides (Ln-OS, such as rare earth element-doped IGZO / IZO), zinc oxide (ZnO), gallium oxide (GaO), and indium oxide (InO).

[0153] The material of the second conductive layer may include a metallic conductive material. For reference on the materials of the signal line group above, the metallic conductive material will not be repeated here. The materials of the second conductive layer and the signal line group may be the same or different.

[0154] S500, referring to Figure 19, a second insulating layer PVX is formed, and a first via V1 and a second via are formed (not shown in the figure).

[0155] For example, a solid-state second insulating layer PVX can be formed using a thin-film deposition process. The material of the second insulating layer PVX may include silicon nitride and / or silicon oxide, and the thickness of the second insulating layer PVX can be [missing information]. Then, the first via V1 and the second via can be formed by photolithography. The position and structure of the first via V1 and the second via can be the position and structure described in any of the above embodiments, and will not be repeated here.

[0156] S600, referring to Figure 20, forms the second electrode layer 40.

[0157] Step S600 above may include: forming a solid second transparent conductive layer, and then patterning the second transparent conductive layer using a photolithography process to form a second electrode layer 40 and a connecting electrode 41. Furthermore, the material of the second transparent conductive layer may include a transparent conductive material, such as ITO, and the thickness of the second transparent conductive layer may be [missing information - likely a value or specification].

[0158] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, comprising: A first substrate, a plurality of first electrodes disposed on one side of the first substrate, and a plurality of signal line groups, wherein the plurality of signal line groups are spaced apart along a first direction, and each of the signal line groups includes a first signal line and a second signal line, wherein both the first signal line and the second signal line extend along a second direction; the first direction intersects the second direction. as well as, Multiple third signal lines are distributed at intervals along the second direction, and each of the third signal lines extends along the first direction; The orthogonal projections of the plurality of third signal lines and the plurality of signal line groups on the first substrate intersect to form a grid structure, with each grid defining a pixel area; The first electrode is located within the pixel area; A plurality of first transistors, wherein the first signal line is configured to be electrically connected to the gate of the first transistor; The second electrode layer is disposed on the side of the first signal line away from the first substrate. The second electrode layer is electrically connected to the second signal line. The orthographic projection of the second electrode layer on the first substrate does not coincide with the orthographic projection of the first transistor on the first substrate, and at least partially coincides with the orthographic projections of the plurality of third signal lines on the first substrate, and covers at least a portion of the edge of the orthographic projection of the first signal line on the first substrate.

2. The array substrate according to claim 1, wherein, The first signal line includes an integrally formed main body and a plurality of protrusions. The main body extends along the second direction, and at least a portion of the plurality of protrusions is located on the side of the main body away from the second signal line, and the plurality of protrusions are spaced apart along the second direction. The orthographic projection of the second electrode layer on the first substrate covers the orthographic projection of at least a portion of the edges of the plurality of protrusions away from the second signal line on the first substrate, and does not coincide with the orthographic projection of the portion of the main body away from the second signal line on the first substrate.

3. The array substrate according to claim 1 or 2, wherein, The orthographic projection of the second electrode layer onto the first substrate covers the orthographic projection of at least a portion of the edge of the first signal line near the second signal line onto the first substrate.

4. The array substrate according to any one of claims 1 to 3, wherein, The portion of the first signal line projected onto the first substrate and the second electrode layer projected onto the first substrate that overlaps has a dimension greater than or equal to 1.9 μm along the direction perpendicular to the boundary of the first signal line.

5. The array substrate according to any one of claims 1 to 4, wherein, The first signal line includes an integrally formed main body and a plurality of protrusions. The main body extends along the second direction. At least a portion of the plurality of protrusions is located on the side of the main body away from the second signal line. The protrusions include a gate region and a base region. The gate region is disposed on the side of the main body away from the second signal line and is configured to form the gate of the first transistor. At least a portion of the base region is disposed on the side of the main body away from the second signal line and is configured to support a spacer.

6. The array substrate according to claim 5, wherein, The septum includes a primary septum and a secondary septum; The plurality of protrusions include the plurality of base regions comprising: The first base area, located on the side of the main body away from the second signal line, is configured to support the sub-septum; The second base plate area is located partly on the side of the main body away from the second signal line and partly on the side of the main body closer to the second signal line. The second base plate area is configured to support the main spacer.

7. The array substrate according to claim 6, wherein, The dimension of the portion of the second base plate region located on the side of the main body away from the second signal line along the first direction is greater than the dimension of the portion of the main body located on the side of the main body closer to the second signal line along the first direction.

8. The array substrate according to claim 6 or 7, wherein, The portion of the second signal line that is disposed opposite to the second base plate area protrudes away from the first signal line to form a winding portion; the interval between the winding portion and the second base plate area is equal to the interval between the second signal line and the main body portion.

9. The array substrate according to any one of claims 6 to 8, wherein, The plurality of pixel regions includes red pixel regions, green pixel regions, and blue pixel regions; The first base plate area is adjacent to the red pixel area or the green pixel area, and the second base plate area is adjacent to the blue pixel area.

10. The array substrate according to any one of claims 5 to 9, wherein, The gate region and the base region are arranged side by side along the second direction. At least a portion of the gate region and at least a portion of the base region belonging to the same protrusion are located on both sides of a third signal line. The pixel region is adjacent to a gate region and a base region belonging to two protrusions respectively, and there is a first interval between the gate region and the base region adjacent to the same pixel region. The first transistor includes a source pattern and a drain pattern, the source pattern being electrically connected to the third signal line, and the drain pattern being electrically connected to the first electrode; The drain pattern extends along the second direction, and in the orthographic projection of the drain pattern and the first signal line on the first substrate, the drain pattern is partially located within the range of the gate region and partially located within the first interval.

11. The array substrate according to claim 10, wherein, The signal line group and the first electrode are disposed on the same film layer; The array substrate further includes: A first insulating layer is located between the signal line group and the third signal line; The second insulating layer is located between the third signal line and the second electrode layer; A first via penetrates the first insulating layer and the second insulating layer, and exposes a first region of the first electrode and a second region of the drain pattern; The adapter electrode, which is made of the same material as the second electrode layer and is disposed in the same layer, is at least partially located in the first via. It is located inside and electrically connected to the first region and the second region, respectively.

12. The array substrate according to claim 11, wherein, The first region and the second region are arranged along the first direction.

13. The array substrate according to claim 12, wherein, The first electrode includes a connection portion that extends along the first direction. The orthographic projection of the connection portion on the first substrate is located within the first interval and coincides with the orthographic projection portion of the drain pattern on the first substrate.

14. The array substrate according to claim 12 or 13, wherein, The size of the first region in the first direction is greater than or equal to 1.9 μm; and / or, The second region has a size greater than or equal to 2.1 μm in the first direction.

15. The array substrate according to any one of claims 1 to 14, wherein, The signal line group and the first electrode are disposed on the same film layer; the array substrate further includes: A first insulating layer is located between the signal line group and the third signal line; The second insulating layer is located between the third signal line and the second electrode layer; The second via penetrates the first insulating layer and the second insulating layer, exposing a portion of the second signal line. At least a portion of the orthographic projection of the second via on the first substrate is located outside the range of the orthographic projection of the second signal line on the first substrate. The second electrode layer is located within the second via and is electrically connected to the second signal line through the second via.

16. The array substrate according to claim 15, wherein, The portion of the second via projected onto the first substrate is located in the region between the second signal line and the first signal line, and has a second gap with the first signal line.

17. The array substrate according to claim 16, wherein, The second signal line is recessed at the location of the second via to the side away from the first signal line to form a first groove, and the second via exposes at least a portion of the first groove.

18. The array substrate according to any one of claims 15 to 17, wherein, The portion of the second via located outside the range of the second signal line's orthogonal projection on the first substrate in the orthogonal projection of the second via on the first substrate has a dimension greater than or equal to 1.9 μm along the first direction; And / or, The portion of the second via that overlaps with the second signal line in the orthographic projection on the first substrate has a dimension greater than or equal to 2.1 μm along the first direction.

19. The array substrate according to any one of claims 15 to 18, wherein, The first signal line includes an integrally formed main body and a plurality of protrusions, at least a portion of which is located on the side of the main body away from the second signal line. The main body extends along the second direction, and the protrusions... Including the gate region and the base region; The second via is offset from the base area in the second direction.

20. The array substrate according to claim 19, wherein, The second via is disposed opposite to the gate region in the first direction.

21. The array substrate according to any one of claims 1 to 20, wherein, The third signal line includes alternating first extension segments and second extension segments. In the orthographic projection of the third signal line and the signal line group on the first substrate, the first extension segment partially overlaps with the signal line group, and both ends of the first extension segment pass through the signal line group. The second extension segment does not overlap with the signal line group. The line width of the first extension segment is greater than or equal to the line width of the second extension segment.

22. The array substrate according to claim 21, wherein, The linewidth of the first extension segment is greater than or equal to 4.5 μm; and / or, The linewidth of the second extension segment is 2.5μm to 8μm.

23. The array substrate according to any one of claims 1 to 22, wherein, The second signal line includes an alternately connected third extension and a fourth extension. In the orthographic projection of the second signal line and the third signal line onto the first substrate, the third extension at least partially overlaps with the third signal line, and the fourth extension does not overlap with the third signal line. The line width of the third extension segment is less than or equal to the line width of the fourth extension segment.

24. The array substrate according to claim 23, wherein, The orthographic projection of the third extension on the first substrate passes through the orthographic projection of the third signal line on the first substrate, and there is a third gap between the end of the third extension and the third signal line.

25. The array substrate according to claim 24, wherein, The linewidth of the third extension segment is 2.5 μm to 4 μm; and / or, The linewidth of the fourth extension segment is greater than or equal to 4 μm; and / or, The third interval is greater than or equal to 1.9 μm.

26. A display panel, comprising: The array substrate as described in any one of claims 1 to 25; A color filter substrate is disposed opposite to the array substrate; A liquid crystal layer is disposed between the array substrate and the color filter substrate.

27. The display panel according to claim 26, wherein, The first signal line of the array substrate includes an integrally formed main body and a plurality of protrusions. The main body extends along a second direction. The protrusions include a gate region and a base region. The plurality of base regions included in the plurality of protrusions include a plurality of first base regions and a plurality of second base regions. The color filter substrate includes a second substrate and a plurality of main spacers and a plurality of secondary spacers disposed on one side of the second substrate. The primary spacer abuts against the array substrate at its end away from the second substrate, and the secondary spacer abuts against the array substrate at its end away from the second substrate or has a gap therebetween; Wherein, the end face of the secondary spacer away from the second substrate is the first end face, and the end face of the main spacer away from the second substrate is the second end face. The orthographic projection of the first end face on the array substrate at least partially coincides with the first sill region, and the orthographic projection of the second end face on the array substrate at least partially coincides with the second sill region.

28. The display panel according to claim 27, wherein, The distance between the boundary of the orthographic projection of the first end face onto the array substrate and the boundary of the first sill region is greater than or equal to 2 μm; and / or, The distance between the boundary of the orthographic projection of the second end face onto the array substrate and the boundary of the second sill region is greater than or equal to 4.5 μm.

29. The display panel according to claim 27 or 28, wherein, The color filter substrate also includes a black matrix disposed on the side of the plurality of main spacers and the plurality of sub spacers near the second substrate; The distance between the boundary of the orthographic projection of the first end face on the array substrate and the boundary of the orthographic projection of the black matrix on the array substrate is greater than or equal to 18 μm. And / or, The distance between the boundary of the orthographic projection of the second end face on the array substrate and the orthographic projection of the black matrix on the array substrate is greater than or equal to 25 μm.

30. A display device, comprising: The array substrate as described in any one of claims 1 to 25; Or, the display panel as described in any one of claims 26 to 29.

Images