Array substrate, display panel and display device

Abstract

An array substrate, a display panel and a display device. The array substrate comprises: a substrate (1); a plurality of gate lines (2); a plurality of data lines (3); a plurality of sub-pixel electrodes (4), the sub-pixel electrode (4) comprising: a first pixel electrode part (41), and a second pixel electrode part (42); a plurality of first traces (5), the first trace (5) comprising: a first sub-trace (51); the first sub-trace (51) is in a bent shape, and in the orthographic projection of the substrate (1), is located in the orthographic projection of the sub-pixel electrode (4) in the substrate (1); a pixel circuit (6), the pixel circuit (6) is configured to release part of the electrical signal loaded to the second pixel electrode part (42) to the first trace (5), so that the brightness of the first pixel electrode part (41) is greater than the brightness of the second pixel electrode part (42).

Description

Array substrate, display panel and display device Technical Field

[0001] This invention relates to the field of display technology, and more particularly to an array substrate, a display panel, and a display device. Background Technology

[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays.

[0003] Summary of the Invention

[0004] This disclosure provides an array substrate, a display panel, and a display device. The array substrate includes:

[0005] Substrate;

[0006] Multiple grid lines extend along the first direction;

[0007] Multiple data cables extend along the second direction;

[0008] Multiple sub-pixel electrodes, each sub-pixel electrode comprising: a first pixel electrode portion and a second pixel electrode portion; the first pixel electrode portion and the second pixel electrode portion of the same sub-pixel electrode are arranged along the second direction;

[0009] Multiple first traces, each first trace including a first sub-trace; the first sub-trace is bent and its orthographic projection on the substrate is located within the orthographic projection of the sub-pixel electrode on the substrate; the first sub-trace includes a first sub-section and a second sub-section; the first sub-section extends along a first direction; one end of the second sub-section is connected to one end of the first sub-section and extends along a second direction, and the orthographic projection of the second sub-section on the substrate overlaps with the orthographic projection of the edge region of the sub-pixel electrode near the data line on the substrate;

[0010] A pixel circuit is electrically connected to the first pixel electrode portion, the second pixel electrode portion, and the first trace. The pixel circuit is configured to release a portion of the electrical signal loaded onto the second pixel electrode portion to the first trace, so that the brightness of the first pixel electrode portion is greater than the brightness of the second pixel electrode portion.

[0011] In one possible implementation, the first sub-trace further includes: the third sub-part located on the side of the first sub-part away from the gate line, one end of which is connected to the other end of the first sub-part, and extending along the second direction;

[0012] The first sub-part's orthographic projection on the substrate passes through the central region of the first pixel electrode's orthographic projection on the substrate; the second sub-part's orthographic projection on the substrate is located at the edge region on one side of the first pixel electrode's orthographic projection on the substrate; the third sub-part's orthographic projection on the substrate is located at the edge region on the other side of the first pixel electrode's orthographic projection on the substrate.

[0013] In one possible implementation, the orthographic projection of the first sub-trace onto the substrate is located within the orthographic projection of the first pixel electrode portion onto the substrate.

[0014] The array substrate further includes: a plurality of common traces; the plurality of common traces include: a first common trace; the orthographic projection of the first common trace on the substrate covers the orthographic projection of the first sub-trace on the substrate.

[0015] In one possible implementation, the first trace further includes: a second sub-trace; the second sub-trace is located on the side of the first sub-part away from the gate line, one end of which is connected to the other end of the third sub-part, and extends along the first direction;

[0016] The multiple common routes also include: a second route extending along the first direction;

[0017] At least a portion of the second sub-trace's orthographic projection on the substrate overlaps with at least a portion of the second trace's orthographic projection on the substrate, and is electrically connected via a via at the overlap location.

[0018] In one possible implementation, the second sub-trace includes: a second sub-trace main portion and a first transition portion; the first transition portion is connected to the end of the second sub-trace main portion; the width of the first transition portion in the second direction is greater than the width of the second sub-trace main portion in the second direction.

[0019] The second trace includes: a second trace main portion extending along the first direction, and a second transition portion connected to the second trace main portion; the width of the second transition portion in the second direction is greater than the width of the second trace main portion in the second direction.

[0020] The orthographic projection of the first adapter portion onto the substrate overlaps with the orthographic projection of the second adapter portion onto the substrate.

[0021] In one possible implementation, the layer containing the first transition portion is located on the side of the layer containing the second transition portion away from the substrate; the array substrate further includes: a third transition portion located on the side of the layer containing the first transition portion away from the layer containing the second transition portion, and an insulating layer located between the layer containing the third transition portion and the layer containing the second transition portion.

[0022] The insulating layer has a first through hole, which partially exposes the first adapter portion and partially exposes the second adapter portion. The third adapter portion covers the first through hole and partially contacts the first adapter portion and partially contacts the second adapter portion through the first through hole.

[0023] In one possible implementation, the first common trace, the second trace, and the gate line are on the same layer and made of the same material; the first trace and the data line are on the same layer and made of the same material; the third adapter is on the same layer and made of the same material as the sub-pixel electrode.

[0024] In one possible implementation, the first pixel electrode portion has a first recess at the location of the third transition portion; a portion of the third transition portion is located within the first recess.

[0025] The second pixel electrode portion has a second recess at the position of the third transition portion; a portion of the third transition portion is located within the second recess.

[0026] In one possible implementation, the first trace further includes a third sub-trace and a fourth sub-trace; the third sub-trace is located on the side of the first sub-part facing the gate line, one end of which is connected to the other end of the second sub-part and extends along the first direction; one end of the fourth sub-trace is connected to the other end of the third sub-trace, extends along the second direction, and its orthographic projection on the substrate intersects with the orthographic projection of the gate line on the substrate.

[0027] In one possible implementation, the first trace further includes a fifth sub-trace; the fifth sub-trace extends along the first direction, and the other end of the fourth trace is connected to the middle position of the fifth sub-trace.

[0028] In one possible implementation, the first trace further includes a sixth sub-trace; the sixth sub-trace is connected to one end of the fifth sub-trace, and the orthographic projection of the sixth sub-trace onto the substrate is located within the orthographic projection of the second pixel electrode portion onto the substrate.

[0029] In one possible implementation, the array substrate further includes: a second common trace group; the second common trace group extends along the second direction and is disconnected at the location of the gate line; the second common trace group includes: two second common traces located on different sides of the data line;

[0030] The orthographic projection of the second common trace on the substrate overlaps with the orthographic projection of the sub-pixel electrode on the substrate.

[0031] In one possible implementation, the array substrate further includes: a third common trace; the third common trace extends along the first direction and is disconnected at a location where it intersects with the data line and the first trace.

[0032] In one possible implementation, the fifth sub-trace's orthographic projection onto the substrate is located within the orthographic projection of the substrate at the point where the third common trace is disconnected.

[0033] In one possible implementation, the orthographic projection of the first trace onto the substrate does not overlap with the orthographic projection of the central region of the second pixel electrode onto the substrate.

[0034] In one possible implementation, the first pixel electrode portion and the second pixel electrode portion of the same sub-pixel electrode are located on different sides of the gate line; and the area of ​​the first pixel electrode portion projected onto the substrate is smaller than the area of ​​the second pixel electrode portion projected onto the substrate.

[0035] In one possible implementation, the pixel circuit includes: a first transistor, a second transistor, and a third transistor;

[0036] The first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first pixel electrode portion through a via.

[0037] The first electrode of the second transistor is multiplexed with the first electrode of the first transistor, and the second electrode of the second transistor is electrically connected to the second pixel electrode portion through a via.

[0038] The first terminal of the third transistor is multiplexed with the second terminal of the second transistor, and the second terminal of the third transistor is electrically connected to the first trace.

[0039] In one possible implementation, the array substrate further includes: a third wiring group; the third wiring group includes: two third wirings extending along the first direction; and the region of the third wiring group located between the first pixel electrode portion and the second pixel electrode portion in the orthographic projection of the substrate is within the orthographic projection of the substrate.

[0040] The orthographic projection of the third trace onto the substrate overlaps with the orthographic projection of at least a portion of the edge of the gate line onto the substrate; in the same group of third traces, the orthographic projection of the gap region between two third traces onto the substrate overlaps with the orthographic projection of the middle region of the gate line onto the substrate.

[0041] In one possible implementation, in the same third trace group, the orthographic projection of the third trace adjacent to the second pixel electrode portion onto the substrate is broken at the position where it intersects with the orthographic projection of the second electrode of the second transistor onto the substrate.

[0042] In one possible implementation, the array substrate further includes: a fourth trace; the fourth trace extends along the second direction, and the region of the fourth trace located between two adjacent sub-pixel electrodes in the first direction is within the orthographic projection of the substrate.

[0043] The orthographic projection of the fourth trace on the substrate overlaps with the orthographic projection of the data line on the substrate.

[0044] In one possible implementation, the fourth trace and the third trace are on the same layer and interconnected; the fourth trace and the third trace are on the same layer as the sub-pixel electrode and spaced apart from each other.

[0045] This disclosure also provides a display panel, which includes the array substrate as provided in this disclosure, and a counter substrate disposed opposite to the array substrate, the counter substrate including a common electrode layer.

[0046] In one possible implementation, the opposing substrate includes: a black matrix layer; the black matrix layer includes: a first black matrix portion; the orthographic projection of the first black matrix portion onto the substrate covers the orthographic projection of the first common trace onto the substrate.

[0047] In one possible implementation, the first common trace includes: a first sub-common portion, a second sub-common portion, and a third sub-common portion; the first sub-common portion extends along the first direction; the orthographic projection of the second sub-common portion on the substrate is located on the side of the orthographic projection of the first sub-common portion on the substrate facing the gate line, and the second sub-common portion extends along the second direction, with one end connected to one end of the first sub-common portion; the orthographic projection of the third sub-common portion on the substrate is located on the side of the orthographic projection of the first sub-common portion on the substrate away from the gate line, and the third sub-common portion extends along the second direction, with one end connected to the other end of the first sub-common portion;

[0048] The first black matrix portion includes: a first sub-black matrix portion, a second sub-black matrix portion, and a third sub-black matrix portion; the first sub-black matrix portion extends along the first direction; the second sub-black matrix portion and the third sub-black matrix portion extend along the second direction and are respectively located on different sides of the first sub-black matrix portion;

[0049] The orthographic projection of the first sub-black matrix portion onto the substrate covers the orthographic projection of the first sub-common portion onto the substrate; the orthographic projection of the second sub-black matrix portion onto the substrate covers the orthographic projection of the second sub-common portion onto the substrate; the orthographic projection of the third sub-black matrix portion onto the substrate covers the orthographic projection of the third sub-common portion onto the substrate.

[0050] In one possible implementation, the orthographic projection of the first sub-common portion onto the substrate covers the orthographic projection of the first sub-part onto the substrate; the orthographic projection of the second sub-common portion onto the substrate covers the orthographic projection of the second sub-part onto the substrate; and the orthographic projection of the third sub-common portion onto the substrate covers the orthographic projection of the third sub-part onto the substrate.

[0051] In one possible implementation, the black matrix layer further includes: a second black matrix portion and a third black matrix portion; the orthographic projection of the second black matrix portion onto the substrate covers the orthographic projection of the gate line onto the substrate; the orthographic projection of the third black matrix portion onto the substrate covers the orthographic projection of the data line onto the substrate.

[0052] The second sub-black matrix section is integrally connected to the third black matrix section, and the third sub-black matrix section is integrally connected to another third black matrix section.

[0053] In one possible implementation, the display panel has a first dark pattern when powered on; the orthographic projection of the first dark pattern onto the substrate overlaps with the orthographic projection of at least a portion of the first common trace onto the substrate.

[0054] Based on the same inventive concept, embodiments of this disclosure also provide a display device, which includes the display panel as described in embodiments of this disclosure. Attached Figure Description

[0055] Figure 1A is one of the top views of the array substrate provided in the embodiments of this disclosure;

[0056] Figure 1B is a schematic diagram of a single film layer containing the gate lines in Figure 1A;

[0057] Figure 1C is a schematic diagram of a single film layer containing the data line in Figure 1A;

[0058] Figure 1D is a schematic diagram of a single film layer in the layer containing the sub-pixel electrode in Figure 1A;

[0059] Figure 1E is a schematic diagram of a single film layer of the black matrix layer corresponding to Figure 1A;

[0060] Figure 1F is a cross-sectional schematic diagram of the display panel corresponding to the one in Figure 1A at the dashed line e1;

[0061] Figure 2A is a second top view of the array substrate provided in an embodiment of this disclosure;

[0062] Figure 2B is a schematic diagram of a single film layer in the layer containing the gate lines in Figure 2A;

[0063] Figure 2C is a schematic diagram of a single film layer containing the data line in Figure 2A;

[0064] Figure 2D is a schematic diagram of a single film layer in the layer containing the sub-pixel electrode in Figure 2A;

[0065] Figure 2E is a cross-sectional view corresponding to the dashed line e2 in Figure 2A;

[0066] Figure 3 is a schematic diagram of the pixel circuit corresponding to Figure 1A;

[0067] Figure 4A is a third top view of the array substrate provided in the embodiment of this disclosure;

[0068] Figure 4B is a schematic diagram of a single film layer of the black matrix layer corresponding to Figure 4A;

[0069] Figure 5 is a schematic diagram of the dark pattern of the sub-pixel provided in an embodiment of this disclosure. Detailed Implementation

[0070] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0071] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0072] As used herein, “approximately” or “substantially the same” includes the stated value and means within an acceptable range of deviations from the specific value, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “substantially the same” may mean a difference relative to the stated value within one or more standard deviations, or within ±30%, 20%, 10%, or 5%.

[0073] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, deviations from the shapes shown in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, sharp corners illustrated may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0074] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0075] With the development of display technology, consumers have increasingly stringent requirements for the image quality of LCD screens. As screen sizes increase, color shift becomes more pronounced at wider viewing angles. Therefore, color shift at different viewing angles has become a crucial indicator for evaluating panel performance. Multi-domain displays divide a sub-pixel into different regions, each with varying degrees of liquid crystal deflection. When viewing an LCD screen from different angles, the overall effect of the deflection of liquid crystals in each region is observed. This reduces contrast differences at different angles caused by uniform liquid crystal deflection within a pixel, thereby reducing color shift and increasing viewing angle. For example, in achieving an 8-domain effect, the color shift can be improved by adjusting the brightness ratio of the top four domains to the bottom four domains. Brighter pixels are called bright pixels, and darker pixels are called dark pixels. In some embodiments, pixels can be discharged by transistors connected to discharge lines to make the pixels darker. However, in this scheme, the discharge line usually passes through the pixel opening area. Due to the angle (taper angle) between the sidewall of the etched metal layer and the lower surface, the discharge line can cause metal reflection, which in turn leads to a decrease in the contrast of the display panel.

[0076] In view of the above, this disclosure provides an array substrate, as shown in Figures 1A-1F and 2A-2E, comprising:

[0077] Substrate 1;

[0078] Multiple grid lines 2 extend along the first direction X;

[0079] Multiple data lines 3 extend along the second direction Y;

[0080] Multiple sub-pixel electrodes 4, each sub-pixel electrode 4 including a first pixel electrode portion 41 and a second pixel electrode portion 42; the first pixel electrode portion 41 and the second pixel electrode portion 42 of the same sub-pixel electrode 4 are arranged along the second direction Y, referring to FIG1A. Optionally, the first pixel electrode portion 41 and the second pixel electrode portion 42 are located on different sides of the gate line 2.

[0081] Multiple first traces 5, each first trace 5 including: a first sub-trace 51; the first sub-trace 51 is bent and its orthographic projection on the substrate 1 is located within the orthographic projection of the sub-pixel electrode 4 on the substrate 1; the first sub-trace 51 includes: a first sub-part 511 and a second sub-part 512; the first sub-part 511 extends along a first direction X; one end of the second sub-part 512 is connected to one end of the first sub-part 511 and extends along a second direction Y, and the orthographic projection of the second sub-part 512 on the substrate 1 overlaps with the orthographic projection of the edge region of the sub-pixel electrode 4 near the data line 3 on the substrate 1;

[0082] Pixel circuit 6 is electrically connected to first pixel electrode 41, second pixel electrode 42, and first trace 5. Pixel circuit 6 is configured to release a portion of the electrical signal loaded onto second pixel electrode 42 to first trace 5 so that the brightness of first pixel electrode 41 is greater than the brightness of second pixel electrode 42. Optionally, the electrical signal may include charge and / or voltage.

[0083] In this embodiment, the pixel circuit 6 can release a portion of the electrical signal loaded onto the second pixel electrode 42 to the first trace 5, so that the brightness of the first pixel electrode 41 is greater than the brightness of the second pixel electrode 42. The first trace 5 can serve as a discharge line. By designing the first sub-trace 51 of the first trace 5 in a bent shape, that is, including a first sub-section 511 extending along the first direction X and a second sub-section 512 extending along the second direction Y, the orthographic projection of the second sub-section 512 on the substrate 1 overlaps with the orthographic projection of the edge region of the sub-pixel electrode 4 near the data line 3 on the substrate 1. Since the area where the first sub-pixel electrode 41 is located usually has a relatively coarse dark ridge extending through its central region along the first direction X and located in the side region along the second direction Y (as shown by the dashed box D in FIG5), by bending the first trace 5 and setting it in the area where the relatively coarse dark ridge is located, the metallic reflection generated by the first trace 5 in the pixel opening area can be reduced, thereby improving the problem of the display panel contrast reduction caused by the reflection of the first trace 5.

[0084] Optionally, the area of ​​the sub-pixel electrode 4 near the edge of the data line 3 can be the area between the edge of the sub-pixel electrode 4 near the data line 3 and the data line 3, or it can be the area of ​​the sub-pixel electrode 4 near the edge of the data line 3. That is, the second sub-part 512 can overlap with the edge of the sub-pixel electrode 4 near the data line 3.

[0085] Optionally, the area where the first pixel electrode portion 41 is located can be a bright pixel area, and the area where the second pixel electrode portion 42 is located can be a dark pixel area. The bright pixel area and the dark pixel area can each be displayed in 4 domains, so that each sub-pixel can be displayed in 8 domains. The 4 domains can be aligned by an alignment film and / or by a slit on the pixel electrode. In this case, the electrodes of the bright pixel area and the dark pixel area can be block-shaped or have slits. This case illustrates the block shape.

[0086] In one possible implementation, referring to Figures 1A-1D and 2A-2E, the second sub-part 512 is located on the side of the first sub-part 511 facing the gate line 2; the first sub-line 51 further includes a third sub-part 513; the third sub-part 513 is located on the side of the first sub-part 511 away from the gate line 2, one end of which is connected to the other end of the first sub-part 511, and extends along the second direction Y. The orthographic projection of the first sub-part 511 onto the substrate 1 passes through the central region O of the orthographic projection of the first pixel electrode portion 41 onto the substrate 1; the orthographic projection of the second sub-part 512 onto the substrate 1 is located on the edge region of the first pixel electrode portion 41 on the side of the orthographic projection onto the substrate 1; the orthographic projection of the third sub-part 513 onto the substrate 1 is located on the edge region of the first pixel electrode portion 41 on the other side of the orthographic projection onto the substrate 1. For example, as shown in FIG1A, the orthographic projection of the second sub-part 512 onto the substrate 1 is located on the right edge region of the first pixel electrode part 41 on the side of the orthographic projection onto the substrate 1; the orthographic projection of the third sub-part 513 onto the substrate 1 is located on the left edge region of the first pixel electrode part 41 on the other side of the orthographic projection onto the substrate 1.

[0087] In one possible implementation, referring to Figures 1A-1D and 2A-2E, the orthographic projection of the first sub-line 51 onto the substrate 1 is located within the orthographic projection of the first pixel electrode portion 41 onto the substrate 1; the array substrate further includes: a plurality of common lines 7, including: a first common line 71; the orthographic projection of the first common line 71 onto the substrate 1 covers the orthographic projection of the first sub-line 51 onto the substrate 1.

[0088] In this embodiment, the first sub-line 51 is located in the area where the first pixel electrode portion 41 is located, that is, the first sub-line 51 is located in the area where the bright pixel is located. Since a bent first common line 71 is provided in the area where the first pixel electrode portion 41 is located, by placing the first sub-line 51 in the area where the existing first common line 71 is located and overlapping with the first common line 71, optionally, the width of the first common line 71 is greater than the width of the first sub-line 51. The first common line 71 covers the first sub-line 51, which can reduce the problem of decreased display panel contrast caused by reflection of the first sub-line 51. It avoids the problem of low contrast caused by the simultaneous presence of two non-overlapping orthographic projection metal lines, the first common line 71 and the first sub-line 51, in the area where the first pixel electrode portion 41 is located.

[0089] In one possible implementation, referring to Figures 1A-1D and 2A-2E, the first common trace 71 includes: a first sub-common portion 711, a second sub-common portion 712, and a third sub-common portion 713; the first sub-common portion 711 extends along a first direction X; the orthographic projection of the second sub-common portion 712 onto the substrate 1 is located on the side of the orthographic projection of the first sub-common portion 711 onto the substrate 1 facing the gate line 2, and the second sub-common portion 712 extends along a second direction Y, with one end connected to one end of the first sub-common portion 711; the orthographic projection of the third sub-common portion 713 onto the substrate 1 is located on the side of the orthographic projection of the first sub-common portion 711 onto the substrate 1 away from the gate line 2, and the third sub-common portion 713 extends along the second direction Y, with one end connected to the other end of the first sub-common portion 711; the orthographic projection of the first sub-common portion 711 onto the substrate 1 covers the orthographic projection of the first sub-portion 511 onto the substrate 1; the orthographic projection of the second sub-common portion 712 onto the substrate 1... The orthographic projection of the second sub-part 512 onto the substrate; the orthographic projection of the third sub-common part 713 onto the substrate 1, covering the orthographic projection of the third sub-part 513 onto the substrate 1.

[0090] In VA display products, after ultraviolet-induced multi-domain vertical alignment (UV2A), when viewing the liquid crystal molecules under the dark lines in the center and branches of the pixel from the side, the human eye is looking at the liquid crystal molecules from the side along the long axis direction. Due to the birefringence of the liquid crystal, light leakage occurs in the UV2A alignment display mode. In this embodiment, the first common trace 71 includes a first sub-common part 711, a second sub-common part 712, and a third sub-common part 713, which can block the light leakage in the middle and side areas of the first pixel electrode part 41.

[0091] In one possible implementation, referring to Figures 1A-1D and 2A-2E, the multiple common traces 7 further include a second common trace group 73 extending along the second direction Y, which is interrupted at the gate line 2. The second common trace group 73 includes two second common traces 730 extending along the second direction Y on different sides of the data line 3. The second common traces 730 are integrally connected with the adjacent second sub-common portion 712 and / or third sub-common portion 713. Therefore, referring to Figure 1B, the widths of the common traces on both sides of the first sub-common portion 711 are different, and the wider common trace includes the second common trace 730 and the third sub-common portion 713. The orthographic projection of the second common trace 730 onto the substrate overlaps with the orthographic projection of the sub-pixel electrode 4 onto the substrate to form an overlapping capacitance.

[0092] In one possible implementation, as shown in Figures 1A and 1B, the plurality of common traces 7 further include: a fourth common trace 75 extending along the first direction X; a gap between the third sub-common portion 713 and the fourth common trace 75; and the second common trace 730, the fourth common trace 75, and the third sub-common portion 713 forming a first notch Q1 with the opening facing the first pixel electrode portion 41. Specifically, when a short circuit occurs at the junction of data line 3 and the fourth common trace 75 due to foreign objects or a broken gate insulation layer, the fourth common trace 75 below the junction and both ends of data line 3 need to be cut off. The fourth common trace 75 below the junction is then floated to prevent direct contact between data line 3 and the fourth common trace 75, which could cause a short circuit. Subsequently, the two ends of the cut data line 3 are connected by bridging. In this embodiment, the second common trace 730, the fourth common trace 75, and the third sub-common part 713 form a first notch Q1 with the opening facing the first pixel electrode part 41. This makes the cutting position (as shown by the thick black line in Figure 2B) narrower in the first direction X, avoiding the problem that laser cutting repair may not be able to cut the light in one go when the third sub-common part 713 is set to improve light leakage.

[0093] In one possible implementation, referring to Figures 1A and 1B, the multiple common traces 7 further include: a third common trace 74 extending in the first direction X; the third common trace 74 in the same extending direction is broken at the position where it intersects with the data line 3 and the first trace 5; a gap exists between the second sub-common portion 712 and the third common trace 74; the second common trace 730, the third common trace 74, and the second sub-common portion 712 form a second recess Q2 with the opening facing the pixel electrode 4. In this embodiment, the second common trace 730, the third common trace 74, and the second sub-common portion 712 form a second recess Q2 with the opening facing the pixel electrode 4, making the cutting position narrower in the first direction X. This avoids the possibility that the laser cutting repair could not be completed in one cut when the second sub-common portion 712 is used for light shielding and light leakage improvement.

[0094] In one possible implementation, referring to Figures 1A-1D, Figure 3, the first pixel electrode portion 41 overlaps with the first common line 71 and / or the second common line 730 and / or the fourth common line 75 and / or the third common line 74 in a direction perpendicular to the substrate 1 to form a first storage capacitor Cst1, and the first pixel electrode portion 41 may overlap with the common electrode of the opposing substrate in a direction perpendicular to the substrate 1 to form a first liquid crystal capacitor Cpx1; the second pixel electrode portion 42 overlaps with the first common line 71 and / or the second common line 730 and / or the fourth common line 75 and / or the third common line 74 in a direction perpendicular to the substrate 1 to form a second storage capacitor Cst2, and the second pixel electrode portion 42 may overlap with the common electrode of the opposing substrate in a direction perpendicular to the substrate 1 to form a second liquid crystal capacitor Cpx2.

[0095] In one possible implementation, referring to FIG3, the pixel circuit 6 includes: a first transistor T1, a second transistor T2, and a third transistor T3; it may also include: a first storage capacitor Cst1, a first liquid crystal capacitor Cpx1, a second storage capacitor Cst2, and a second liquid crystal capacitor Cpx2.

[0096] The first electrode TA of the first transistor T1 is electrically connected to the data line 3, and the second electrode TB of the first transistor T1 is electrically connected to the first pixel electrode 41 through a via; optionally, the second electrode TB of the first transistor T1 can be electrically connected to the first pixel electrode 41 through the second via K2.

[0097] The first electrode TA of the second transistor T2 is multiplexed with the first electrode TA of the first transistor T1, and the second electrode TB of the second transistor T2 is electrically connected to the second pixel electrode 42 through a via; optionally, the second electrode TB of the second transistor T2 is electrically connected to the second pixel electrode 42 through a third via K3.

[0098] The first terminal TA of the third transistor T3 is multiplexed with the second terminal TB of the second transistor T2, and the second terminal TB of the third transistor T3 is electrically connected to the first trace 5.

[0099] In this embodiment, the first pixel electrode 41 can be electrically connected to the gate line 2 and the data line 3 through the first transistor T1, the second pixel electrode 42 can be electrically connected to the gate line 2 and the data line 3 through the second transistor T2, and the third transistor T3 can be electrically connected to the first trace 5. The stored charge in the second storage capacitor Cst2 corresponding to the second pixel electrode 42 can be released to the first trace 5 through the third transistor T3, thereby making the brightness of the first pixel electrode 41 greater than the brightness of the second pixel electrode 42, so that the first pixel electrode 41 and the second pixel electrode 42 have different bright and dark areas.

[0100] In one possible implementation, referring to Figures 1A-1D, the first trace 5 further includes a second sub-trace 52. The second sub-trace 52 is located on the side of the first sub-part 511 away from the gate line 2, with one end connected to the other end of the third sub-part 513, and extends along the first direction X. The orthographic projection of the second sub-trace 52 onto the substrate 1 overlaps with the orthographic projection of a portion of the fourth common trace 75 onto the substrate 1. In this way, by hiding the second sub-trace 52 in the area where the fourth common trace 75 is located, the problem of decreased contrast of the display panel due to reflection from the second sub-trace 52 can be reduced. This avoids the problem of a large number of reflective metal areas in the area where the first pixel electrode part 41 is located due to the simultaneous presence of two non-overlapping orthographic projections of the fourth common trace 75 and the second sub-trace 52, which would lead to a lower contrast.

[0101] Unlike the array substrates shown in Figures 2A-2D, in the array substrate structure shown in Figures 1A-1D, the second sub-trace 52 and the fourth common trace 75 can be electrically connected at their overlapping positions without vias. The second sub-trace 52 can be bent (bent upwards as shown in Figure 1C) to extend to the peripheral area for electrical signal release.

[0102] In one possible implementation, referring to Figures 1A-1D, the first trace 5 further includes: a third sub-trace 53 and a fourth sub-trace 54; the third sub-trace 53 is located on the side of the first sub-part 511 facing the gate line 2, one end of which is connected to the other end of the second sub-part 512 and extends along the first direction X; the fourth sub-trace 54 is connected to the other end of the third sub-trace 53, extends along the second direction Y, and its orthographic projection on the substrate 1 intersects with the orthographic projection of the gate line 2 on the substrate 1.

[0103] In one possible implementation, referring to Figures 1A-1D, the first trace 5 further includes a fifth sub-trace 55; the fifth sub-trace 55 extends along a first direction X, and the other end of the fourth sub-trace 54 is connected to the middle position of the fifth sub-trace 55.

[0104] Optionally, the orthographic projection of the fifth sub-line 55 onto the substrate may be located at the point where the third common line 74, which overlaps with the second pixel electrode portion 42, is disconnected, so as to avoid forming an overlapping capacitance with the second common line 730; Optionally, as shown in FIG1C, the fifth sub-line 55 may include an external protrusion 550, which is located on the side of the extension line of the fourth sub-line 54 away from the sixth sub-line 56.

[0105] In this embodiment, the fifth sub-line 55 can serve as a film layer alignment pattern for aligning the common wiring layer with other wiring layers and for measuring alignment accuracy. For example, the alignment accuracy can be determined by measuring the overlap between the fifth sub-line 55 and the second pixel electrode portion 42 (or the third common wiring 74) in the second direction Y and / or the first direction X, thus avoiding excessive alignment errors between the common wiring layer and other wiring layers, which could affect the normal display of the display panel. Furthermore, the fifth sub-line 55 has an outward protrusion 550, ensuring that the alignment pattern has a certain length in the first direction X (e.g., 0.1 micrometer to 20 micrometers, optionally, such as 1 micrometer to 6 micrometers). This prevents the actual edge at the end from being non-right-angled and potentially arc-shaped during film fabrication. If there is no outward protrusion 550 or the outward protrusion 550 is too short, it could affect accurate measurement.

[0106] Optionally, the orthographic projection of the fifth sub-line 55 onto the substrate may overlap with the orthographic projection of the second pixel electrode portion 42 onto the substrate.

[0107] In one possible implementation, referring to Figures 1A-1D, the first trace 5 further includes a sixth sub-trace 56; the sixth sub-trace 56 is connected to one end of the fifth sub-trace 55, and the orthographic projection of the sixth sub-trace 56 onto the substrate is located within the orthographic projection of the second pixel electrode portion 42 onto the substrate. In this embodiment of the present disclosure, the first trace 5 further includes the sixth sub-trace 56, so that the first trace 5 can be extended to the peripheral area in the second direction Y to release electrical signals.

[0108] In one possible implementation, referring to Figures 2A-2D, the orthographic projection of the first trace 5 onto the substrate 1 does not overlap with the orthographic projection of the central region of the second pixel electrode portion 42 onto the substrate 1. That is, the first trace 5 may not be provided in the region where the second pixel electrode portion 42 is located. Optionally, the orthographic projection of the first trace 5 onto the substrate 1 does not overlap with the orthographic projection of the portion of the second pixel electrode portion 42 located in the pixel opening region onto the substrate 1, wherein the pixel opening region can be the opening region of the black matrix.

[0109] In one possible implementation, referring to Figures 2A-2D, the first trace 5 further includes: a second sub-trace 52; the second sub-trace 52 is located on the side of the first sub-part 511 away from the gate line 2, one end of which is connected to the other end of the third sub-part 513, and extends along the first direction X; the array substrate further includes: a second trace 72 extending along the first direction X; at least a portion of the orthographic projection of the second sub-trace 52 onto the substrate 1 overlaps with at least a portion of the orthographic projection of the second trace 72 onto the substrate 1, and is electrically connected at the overlapping position through a via.

[0110] In this embodiment, the first trace 5 is electrically connected to the second trace 72 via a via through the second sub-trace 52. That is, the first trace 5 is transferred to the layer where the common trace 7 is located via a jump layer and electrically connected to the second trace 72 of the common trace 7. The first trace 5 is then led to the periphery through the second trace 72 to release the electrical signal. Compared with the display panel shown in FIG1A, which has a sixth sub-trace 56 extending along the second direction in the second pixel electrode part 42 to extend the first trace 5 to the periphery area in the second direction Y to release the electrical signal, the embodiment shown in FIG2A can avoid the problem of low contrast in the pixel opening area when the display panel is provided with both the second trace 72 and the sixth sub-trace 56. While ensuring that the first trace 5 can meet the requirements for releasing the electrical signal, the long trace segment of the first trace 5 in the dark pixel area (i.e., the sixth sub-trace 56) can be eliminated, which can greatly reduce the problem of low contrast in the pixel opening area caused by light leakage and / or reflection of the first trace 5.

[0111] In one possible implementation, referring to Figures 2A-2D, the second sub-trace 52 includes: a second sub-trace main portion 521 and a first transition portion 520; the second sub-trace main portion 521 is located on the side of the first sub-trace 511 away from the gate line 2, one end of which is connected to the other end of the third sub-trace 513 and extends along the first direction X; the first transition portion 520 is connected to the other end of the second sub-trace main portion 521; the second trace 72 includes: a second trace main portion 721 and a second transition portion 720 connected to the second trace main portion 721; the orthographic projection of the first transition portion 520 on the substrate 1 overlaps with the orthographic projection of the second transition portion 720 on the substrate 1, and they are electrically connected through vias at the overlapping position.

[0112] In one possible implementation, referring to Figures 2A-2D, the width d1 of the first adapter 520 in the second direction Y is greater than the width d2 of the second sub-trace 52 in the second direction Y; the width d3 of the second adapter 720 in the second direction Y is greater than the width d4 of the second trace 72 in the second direction Y. This ensures a better electrical connection between the second sub-trace 52 and the second trace 72, avoiding the situation where, if the second sub-trace 52 and the second trace 72 are relatively thin, directly drilling holes above them would result in small vias, hindering proper conductivity.

[0113] In one possible implementation, as shown in Figures 2A-2D, the second trace 72 may not be connected to other traces on the same layer as the common trace 7. In some embodiments, the lower the voltage of the discharge line (including the second trace 72), the more leakage current in the dark pixel, the greater the voltage difference between the bright and dark areas, the lower the transmittance (Tr%), and the greater the contrast difference between the dark pixel area and the bright pixel area, which has a certain impact on color shift. Optionally, the voltage applied to the second trace 72 may be greater than or equal to 7V and less than or equal to 10V, such as 7V, 8V, 9V, 10V, etc.

[0114] In one possible implementation, as shown in Figures 2A-2D, when the second trace 72 and other traces in the layer where the common trace 7 are located can be unconnected, the third common trace 74 in the same extension direction can be connected to each other at the position where it intersects with the data line 3, so that the third common trace 74 and the second common trace 730 in the same sub-pixel row are connected to each other as a whole; while the third common trace 74 and the second common trace 730 in different sub-pixel rows can be electrically connected through the connection portion 47 in the layer where the sub-pixel electrode 4 is located and through the fourth via K4.

[0115] In one possible implementation, referring to FIG2E, the layer where the first transition portion 520 is located is on the side of the layer where the second transition portion 720 is located away from the substrate 1; the array substrate further includes: a third transition portion 40 located on the side of the layer where the first transition portion 520 is located away from the layer where the second transition portion 720 is located, and an insulating layer 91 located between the layer where the third transition portion 40 is located and the layer where the second transition portion 720 is located; the insulating layer 91 has a first via K1, the first via K1 partially exposes the first transition portion 520 and partially exposes the second transition portion 720, the third transition portion 40 covers the first via K1, and partially contacts the first transition portion 520 and partially contacts the second transition portion 720 through the first via K1.

[0116] In this embodiment, the first via K1 partially exposes the first transition portion 520 and partially exposes the second transition portion 720, so that the first via K forms a stepped structure inside, which plays a role in guiding the alignment liquid, preventing the alignment liquid from sticking, and improving the uniformity of the alignment liquid on the array substrate, avoiding the appearance of moiré patterns on the screen, thereby improving the display quality.

[0117] In one possible implementation, referring to FIG2E, the insulating layer 91 may include: a gate insulating layer 911, a passivation layer 912 located on the side of the gate insulating layer 911 facing away from the substrate 1, and a planarization layer 913 located on the side of the passivation layer 912 facing away from the gate insulating layer 911; optionally, the planarization layer 913 may be an organic film layer, and optionally, the passivation layer 912 may be a silicon nitride material layer.

[0118] Optionally, the second sub-line 52 is on the same layer and made of the same material as the first adapter 520, and the two are in direct contact and connected; the second line 72 is on the same layer and made of the same material as the second adapter 720, and the two are in direct contact and connected.

[0119] In one possible implementation, as shown in Figures 2A-2D, the first common trace 71, the second trace 72, and the gate line 2 are on the same layer and made of the same material; the first trace 5 and the data line 3 are on the same layer and made of the same material; and the third transition portion 40 and the sub-pixel electrode 4 are on the same layer and made of the same material. Thus, the first common trace 71 and the second trace 72 can be formed simultaneously with the gate line 2; the first trace 5 can be formed simultaneously with the data line 3; and the third transition portion 40 can be formed simultaneously with the sub-pixel electrode 4. This simplifies the fabrication process of the array substrate and reduces the manufacturing cost of the display panel.

[0120] In one possible implementation, referring to Figures 2A-2D, the first pixel electrode portion 41 has a first recess 410 at the position of the third transition portion 40; a portion of the third transition portion 40 is located within the first recess 410; the second pixel electrode portion 42 has a second recess 420 at the position of the third transition portion 40; a portion of the third transition portion 40 is located within the second recess 420. In this embodiment, the first pixel electrode portion 41 has a first recess 410 at the position of the third transition portion 40 to prevent the third transition portion 40 from making contact with the first pixel electrode portion 41 and affecting the normal display of the display panel; similarly, the second pixel electrode portion 42 has a second recess 420 at the position of the third transition portion 40 to prevent the third transition portion 40 from making contact with the second pixel electrode portion 42 and affecting the normal display of the display panel.

[0121] In one possible implementation, referring to Figures 1A-2D and 2A-2D, the area of ​​the first pixel electrode portion 41 projected onto the substrate 1 is smaller than the area of ​​the second pixel electrode portion 42 projected onto the substrate 1. Optionally, the ratio of the area of ​​the first pixel electrode portion 41 projected onto the substrate 1 to the area of ​​the second pixel electrode portion 42 projected onto the substrate 1 is greater than or equal to 1:2.3 and less than or equal to 1:1.8, for example, 1:1.8, 1:1.9, 1:2, 1:2.1, 1:2.2, 1:2.3, etc. The smaller the area of ​​the first pixel electrode portion 41 projected onto the substrate 1, the flatter the liquid crystal in the area where the first pixel electrode portion 41 is located, the earlier the bright spots appear, and the better the color shift in low grayscale. However, the color shift in medium and high grayscale will deteriorate. Among them, when the area ratio is 1:2, the uniformity of the change in Gamma shift in low, medium and high grayscale compared with the standard curve gamma 2.2 is better. That is, the low, medium and high grayscale balance of the 1:2 area ratio scheme is better and there is no abrupt change, which has a better effect on improving color shift. Therefore, the present disclosure can set the ratio of the area of ​​the first pixel electrode portion 41 projected onto the substrate 1 to the area of ​​the second pixel electrode portion 42 projected onto the substrate 1 to 1:1.8 to 1:2.3, preferably 1:2.

[0122] In one possible implementation, referring to Figures 1A-2D and 2A-2D, the array substrate may further include: a third wiring group; the third wiring group includes: two third wirings 45 extending along the first direction X; the third wirings 45 may be disposed on the same layer as the sub-pixel electrode 4 and spaced apart, and the orthographic projection of the third wirings 45 on the substrate, the area between the first pixel electrode portion 41 and the second pixel electrode portion 42, is within the orthographic projection of the substrate; optionally, two third wirings 45 may be disposed between the first pixel electrode portion 41 and the second pixel electrode portion 42; the orthographic projection of the third wirings 45 on the substrate 1 overlaps with the orthographic projection of the edge of the gate line 2 on the substrate 1, so that the signal of the gate line 2 can be effectively shielded by the third wirings 45, so that the first pixel electrode portion 41 and the second pixel electrode portion 42 will no longer be interfered with by the gate line 2, but will form a coupling capacitance with the third wirings 45. Optionally, the voltage of the third trace 45 is approximately 7V (e.g., 8V), and the voltage difference between the third trace 45 and the first pixel electrode portion 41 and the second pixel electrode portion 42 is approximately 0-7V, which is less than the 16V-30V voltage difference between the gate line 2 and the first pixel electrode portion 41 and the second pixel electrode portion 42 in the related art. This effectively improves the phenomenon of abnormal brightening of liquid crystal molecules due to the electric field formed by the large voltage difference. Furthermore, in the same group of third traces, the orthographic projection of the gap region between the two third traces 45 onto the substrate overlaps with the orthographic projection of the middle region of the gate line onto the substrate. That is, the orthographic projection of the middle part of the gate line 2 onto the substrate 1 and the orthographic projection of the third trace 45 onto the substrate 1 do not overlap, which helps to reduce the load on the gate line 2. Optionally, the shape of at least some of the third traces is compatible with the first pixel electrode portion and / or the second pixel electrode portion. For example, if the first pixel electrode portion is a protruding structure, then at least some of the third traces are recessed structures.

[0123] In one possible implementation, referring to Figures 1A-2D and 2A-2D, in the same third trace group, the orthographic projection of the third trace 45 adjacent to the second pixel electrode 42 onto the substrate is broken at the position where it intersects with the orthographic projection of the second electrode of the second transistor T2 onto the substrate. This is to avoid overlapping with the second transistor T2 and / or the third transistor T3, thus preventing interference with the normal display of the display panel.

[0124] In one possible implementation, as shown in Figures 1A-2D and 2A-2D, the array substrate may further include a fourth trace 46 extending along the second direction Y on the same layer as the sub-pixel electrode 4 and located between two adjacent sub-pixel electrodes 4. The fourth trace 46 may be integrally disposed with the third trace 45 so that the fourth trace 46 and the third trace 45 form a mesh structure to improve the uniformity of the common voltage signal.

[0125] In one possible implementation, referring to Figures 1A-2D and 2A-2D, the orthogonal projection of the data line 3 on the substrate 1 lies within the orthogonal projection of the fourth trace 46 on the substrate 1. This allows the fourth trace 46 to shield the signal of the data line 3, preventing interference between the data line 3 and adjacent, uncoupled first pixel electrode portion 41 or second pixel electrode portion 42. Since the linewidth of the data line 3 is relatively narrow (e.g., 8 μm), even if the fourth trace 46 completely covers the data line 3, it will not cause a significant load on the data line 3. However, the complete coverage of the data line 3 by the fourth trace 46 ensures that its linewidth is greater than or equal to the linewidth of the data line 3, reducing the risk of breakage of the fourth trace 46.

[0126] In one possible implementation, referring to Figures 1A-2D and 2A-2D, the array substrate may further include a connection portion 47 on the same layer as the sub-pixel electrode 4. The connection portion 47 may be integrally connected to the third trace 45. Optionally, the connection portion 47 may be electrically connected through a third common trace 74 on the layer where the fourth via K4 gate line 2 is located. To ensure a good connection, the third trace 45 is widened at the location of the connection portion 47. By electrically connecting the third trace 45 to the third common trace 74, the overall resistance of the third trace 45 and the third common trace 74 can be reduced, thereby reducing the voltage drop (IR drop) of the common voltage signal and improving the uniformity and anti-interference capability of the common voltage signal.

[0127] Based on the same inventive concept, this disclosure also provides a display panel, as shown in FIG1G, which includes an array substrate as provided in the embodiments of this disclosure, and also includes a counter substrate 002 disposed opposite to the array substrate.

[0128] In one possible implementation, as shown in FIG4A and FIG4B, the opposing substrate 002 includes: a black matrix layer 8; the black matrix layer 8 includes: a first black matrix portion 81; the orthographic projection of the first black matrix portion 81 onto the substrate 1 covers the orthographic projection of the first common trace 71 onto the substrate 1.

[0129] In one possible implementation, referring to Figures 4A and 4B, the first black matrix portion 81 includes: a first sub-black matrix portion 811, a second sub-black matrix portion 812, and a third sub-black matrix portion 813; the first sub-black matrix portion 811 extends along a first direction X; the second sub-black matrix portion 812 and the third sub-black matrix portion 813 extend along a second direction Y and are respectively located on different sides of the first sub-black matrix portion 811;

[0130] The orthographic projection of the first sub-black matrix portion 811 onto the substrate 1 covers the orthographic projection of the first sub-common portion 711 onto the substrate 1; the orthographic projection of the second sub-black matrix portion 812 onto the substrate 1 covers the orthographic projection of the second sub-common portion 812 onto the substrate 1; the orthographic projection of the third sub-black matrix portion 813 onto the substrate 1 covers the orthographic projection of the third sub-common portion 713 onto the substrate.

[0131] In this embodiment, in addition to the metal light leakage caused by the discharge line (first trace 5), the edge of the first common trace 71 will also have metal edge light leakage due to the Taper angle. By adding a first black matrix portion 81 at the corresponding position on the opposite substrate side to block the light leakage of the metal side of the first common trace 71, and without loss of aperture ratio, the contrast of the display panel can be improved.

[0132] In one possible implementation, referring to Figures 4A and 4B, the black matrix layer 8 further includes: a second black matrix portion 82 and a third black matrix portion 83; the orthographic projection of the second black matrix portion 82 onto the substrate 1 covers the orthographic projection of the gate line 2 onto the substrate 1; the orthographic projection of the third black matrix portion 83 onto the substrate 1 covers the orthographic projection of the data line 3 onto the substrate 1; the second sub-black matrix portion 812 is integrally connected to the third black matrix portion 83, and the third sub-black matrix portion 813 is integrally connected to another third black matrix 83.

[0133] In one possible implementation, as shown in FIG1G, the opposing substrate 002 may further include: an opposing substrate 202, a color resist 204 located on the side of the black matrix layer 8 opposite to the opposing substrate 202, and a common electrode layer 201 located on the side of the color resist 204 opposite to the black matrix layer 8. Optionally, this embodiment may also be a COA structure, in which the color resist layer is disposed on one side of the array substrate, and the pixel electrode layer is disposed on the side of the color resist layer away from the substrate.

[0134] In one possible implementation, the display panel has a first dark ripple when powered on (as shown by the dashed box D in FIG5); the orthographic projection of the first dark ripple onto the substrate overlaps with the orthographic projection of at least a portion of the first common trace 71 onto the substrate 1. In this embodiment of the present disclosure, by placing the first trace 51 and the first common trace 71 at the location of the first dark ripple, the problem of a small effective display area and a low aperture ratio of the display panel is avoided when they are placed at other locations, where the display panel would simultaneously have the first dark ripple and the first common trace 71 and / or the first trace that do not overlap with the first dark ripple.

[0135] In some embodiments, the display panel provided in this disclosure may further include a liquid crystal layer between an array substrate and a counter substrate, a first polarizer on the side of the array substrate away from the counter substrate, and a second polarizer on the side of the counter substrate away from the array substrate, wherein the polarization direction of the first polarizer and the polarization direction of the second polarizer are perpendicular to each other. Other essential components of the display panel are those which should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the scope of this disclosure.

[0136] Based on the same inventive concept, this disclosure also provides a display device, comprising the display panel described above and a backlight module located on the light-incident side of the display panel. The backlight module can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting diodes (LEDs), such as miniature LEDs (Mini LEDs, Micro LEDs, etc.).

[0137] Micro-LEDs, at the sub-millimeter or even micrometer scale, are self-emissive devices, just like organic light-emitting diodes (OLEDs). Like OLEDs, they offer a range of advantages, including high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic LEDs emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic LEDs, such as lower power consumption, better resistance to high and low temperatures, and longer lifespan. When used as backlights, micro-LEDs can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while eliminating glare caused by traditional dynamic backlighting between bright and dark areas, thus optimizing the visual experience.

[0138] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include memory, a power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or have different component arrangements.

[0139] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0140] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Therefore, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. An array substrate, wherein, include: Substrate; Multiple grid lines extend along the first direction; Multiple data cables extend along the second direction; Multiple sub-pixel electrodes, each sub-pixel electrode comprising: a first pixel electrode portion and a second pixel electrode portion; the first pixel electrode portion and the second pixel electrode portion of the same sub-pixel electrode are arranged along the second direction; Multiple first traces, each first trace including: a first sub-trace; the first sub-trace is bent and its orthographic projection on the substrate is located within the orthographic projection of the sub-pixel electrode on the substrate; the first sub-trace includes: a first sub-section and a second sub-section; the first sub-section extends along a first direction; one end of the second sub-section is connected to one end of the first sub-section and extends along a second direction, and the orthographic projection of the second sub-section on the substrate overlaps with the orthographic projection of the edge region of the sub-pixel electrode near the data line on the substrate; A pixel circuit is electrically connected to the first pixel electrode portion, the second pixel electrode portion, and the first trace. The pixel circuit is configured to release a portion of the electrical signal loaded onto the second pixel electrode portion to the first trace, so that the brightness of the first pixel electrode portion is greater than the brightness of the second pixel electrode portion.

2. The array substrate as claimed in claim 1, wherein, The first sub-trace further includes: the third sub-section is located on the side of the first sub-section away from the gate line, one end of which is connected to the other end of the first sub-section, and extends along the second direction; The first sub-part's orthographic projection on the substrate passes through the central region of the first pixel electrode's orthographic projection on the substrate; the second sub-part's orthographic projection on the substrate is located at the edge region on one side of the first pixel electrode's orthographic projection on the substrate; the third sub-part's orthographic projection on the substrate is located at the edge region on the other side of the first pixel electrode's orthographic projection on the substrate.

3. The array substrate as described in claim 1 or 2, wherein, The first sub-trace's orthographic projection onto the substrate is located within the orthographic projection of the first pixel electrode portion onto the substrate; The array substrate further includes: a plurality of common traces; the plurality of common traces include: a first common trace; the orthographic projection of the first common trace on the substrate covers the orthographic projection of the first sub-trace on the substrate.

4. The array substrate according to any one of claims 1-3, wherein, The first trace further includes: a second sub-trace; the second sub-trace is located on the side of the first sub-part away from the gate line, one end of which is connected to the other end of the third sub-part, and extends along the first direction; The array substrate further includes: a second trace extending along the first direction; At least a portion of the second sub-trace's orthographic projection on the substrate overlaps with at least a portion of the second trace's orthographic projection on the substrate, and is electrically connected via a via at the overlap location.

5. The array substrate as claimed in claim 4, wherein, The second sub-trace includes: a second sub-trace main portion and a first transition portion; the first transition portion is connected to the end of the second sub-trace main portion; the width of the first transition portion in the second direction is greater than the width of the second sub-trace main portion in the second direction; The second trace includes: a second trace main portion extending along the first direction, and a second transition portion connected to the second trace main portion; the width of the second transition portion in the second direction is greater than the width of the second trace main portion in the second direction. The orthographic projection of the first adapter portion onto the substrate overlaps with the orthographic projection of the second adapter portion onto the substrate.

6. The array substrate as claimed in claim 5, wherein, The first transition portion is located on the side of the second transition portion located away from the substrate; the array substrate further includes: a third transition portion located on the side of the first transition portion located away from the second transition portion located, and an insulating layer located between the third transition portion located and the second transition portion located. The insulating layer has a first through hole, which partially exposes the first adapter portion and partially exposes the second adapter portion. The third adapter portion covers the first through hole and partially contacts the first adapter portion and partially contacts the second adapter portion through the first through hole.

7. The array substrate as claimed in claim 6, wherein, The first common trace, the second trace, and the gate line are on the same layer and made of the same material; the first trace and the data line are on the same layer and made of the same material; the third adapter is on the same layer and made of the same material as the sub-pixel electrode.

8. The array substrate as claimed in claim 7, wherein, The first pixel electrode portion has a first recess at the position of the third transition portion; a portion of the third transition portion is located within the first recess. The second pixel electrode portion has a second recess at the position of the third transition portion; a portion of the third transition portion is located within the second recess.

9. The array substrate according to any one of claims 4-8, wherein, The first trace further includes: a third sub-trace and a fourth sub-trace; the third sub-trace is located on the side of the first sub-part facing the gate line, one end of which is connected to the other end of the second sub-part and extends along the first direction; one end of the fourth sub-trace is connected to the other end of the third sub-trace, extends along the second direction, and its orthographic projection on the substrate intersects with the orthographic projection of the gate line on the substrate.

10. The array substrate as claimed in claim 9, wherein, The first trace further includes a fifth sub-trace; the fifth sub-trace extends along the first direction, and the other end of the fourth trace is connected to the middle position of the fifth sub-trace.

11. The array substrate according to any one of claims 2-10, wherein, The first trace further includes a sixth sub-trace; the sixth sub-trace is connected to one end of the fifth sub-trace, and the orthographic projection of the sixth sub-trace on the substrate is located within the orthographic projection of the second pixel electrode portion on the substrate.

12. The array substrate as claimed in claim 10 or 11, wherein, The array substrate further includes: a second common trace group; the second common trace group extends along the second direction and is disconnected at the location of the gate line; the second common trace group includes: two second common traces located on different sides of the data line; The orthographic projection of the second common trace on the substrate overlaps with the orthographic projection of the sub-pixel electrode on the substrate.

13. The array substrate as claimed in claim 12, wherein, The array substrate further includes: a third common trace; the third common trace extends along the first direction and is broken at the position where it intersects with the data line and the first trace.

14. The array substrate as claimed in claim 13, wherein, The fifth sub-trace's orthographic projection onto the substrate is located within the orthographic projection of the substrate at the point where the third common trace is disconnected.

15. The array substrate according to any one of claims 4-10, 12-14, wherein, The orthographic projection of the first trace onto the substrate does not overlap with the orthographic projection of the central region of the second pixel electrode onto the substrate.

16. The array substrate according to any one of claims 1-15, wherein, The first pixel electrode portion and the second pixel electrode portion of the same sub-pixel electrode are located on different sides of the gate line; and the area of ​​the first pixel electrode portion projected onto the substrate is smaller than the area of ​​the second pixel electrode portion projected onto the substrate.

17. The array substrate according to any one of claims 1-16, wherein, The pixel circuit includes: a first transistor, a second transistor, and a third transistor; The first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first pixel electrode portion through a via. The first electrode of the second transistor is multiplexed with the first electrode of the first transistor, and the second electrode of the second transistor is electrically connected to the second pixel electrode portion through a via. The first terminal of the third transistor is multiplexed with the second terminal of the second transistor, and the second terminal of the third transistor is electrically connected to the first trace.

18. The array substrate as claimed in claim 17, wherein, The array substrate further includes: a third wiring group; the third wiring group includes: two third wirings extending along the first direction; and the region of the third wiring group located between the first pixel electrode portion and the second pixel electrode portion in the orthographic projection of the substrate is within the orthographic projection of the substrate. The orthographic projection of the third trace onto the substrate overlaps with the orthographic projection of at least a portion of the edge of the gate line onto the substrate; in the same group of third traces, the orthographic projection of the gap region between two third traces onto the substrate overlaps with the orthographic projection of the middle region of the gate line onto the substrate.

19. The array substrate as claimed in claim 18, wherein, In the same third trace group, the orthographic projection of the third trace adjacent to the second pixel electrode portion onto the substrate is broken at the position where it intersects with the orthographic projection of the second electrode of the second transistor onto the substrate.

20. The array substrate as claimed in claim 18 or 19, wherein, The array substrate further includes: a fourth trace; the fourth trace extends along the second direction, and the region of the fourth trace located between two adjacent sub-pixel electrodes in the first direction is within the orthogonal projection of the substrate. The orthographic projection of the fourth trace on the substrate overlaps with the orthographic projection of the data line on the substrate.

21. The array substrate as claimed in claim 20, wherein, The fourth and third traces are on the same layer and connected to each other; the fourth and third traces are on the same layer as the sub-pixel electrode and are spaced apart from each other.

22. A display panel, wherein, The array substrate as described in any one of claims 1-21 is further comprising a counter substrate disposed opposite to the array substrate, the counter substrate comprising a common electrode layer.

23. The display panel as claimed in claim 22, wherein, The opposing substrate includes a black matrix layer; the black matrix layer includes a first black matrix portion; the orthographic projection of the first black matrix portion onto the substrate covers the orthographic projection of the first common trace onto the substrate.

24. The display panel as claimed in claim 23, wherein, The first common trace includes: a first sub-common portion, a second sub-common portion, and a third sub-common portion; the first sub-common portion extends along the first direction; the orthographic projection of the second sub-common portion on the substrate is located on the side of the orthographic projection of the first sub-common portion on the substrate facing the gate line, and the second sub-common portion extends along the second direction, with one end connected to one end of the first sub-common portion; the orthographic projection of the third sub-common portion on the substrate is located on the side of the orthographic projection of the first sub-common portion on the substrate away from the gate line, and the third sub-common portion extends along the second direction, with one end connected to the other end of the first sub-common portion; The first black matrix portion includes: a first sub-black matrix portion, a second sub-black matrix portion, and a third sub-black matrix portion; the first sub-black matrix portion extends along the first direction; the second sub-black matrix portion and the third sub-black matrix portion extend along the second direction and are respectively located on different sides of the first sub-black matrix portion; The orthographic projection of the first sub-black matrix portion onto the substrate covers the orthographic projection of the first sub-common portion onto the substrate; the orthographic projection of the second sub-black matrix portion onto the substrate covers the orthographic projection of the second sub-common portion onto the substrate; the orthographic projection of the third sub-black matrix portion onto the substrate covers the orthographic projection of the third sub-common portion onto the substrate.

25. The display panel as claimed in claim 24, wherein, The orthographic projection of the first sub-common portion onto the substrate covers the orthographic projection of the first sub-part onto the substrate; The orthographic projection of the second sub-common portion onto the substrate covers the orthographic projection of the second sub-part onto the substrate; The orthographic projection of the third sub-common part onto the substrate covers the orthographic projection of the third sub-part onto the substrate.

26. The display panel of claim 24 or 25, wherein the black matrix layer further comprises: The second black matrix section, and the third black matrix section; The orthographic projection of the second black matrix portion onto the substrate covers the orthographic projection of the gate line onto the substrate; The orthographic projection of the third black matrix onto the substrate covers the orthographic projection of the data line onto the substrate; The second sub-black matrix section is integrally connected to the third black matrix section, and the third sub-black matrix section is integrally connected to another third black matrix section.

27. The display panel according to any one of claims 22-26, wherein, When the display panel is powered on, it has a first dark pattern; the orthographic projection of the first dark pattern on the substrate overlaps with the orthographic projection of at least a portion of the first common trace on the substrate.

28. A display device, wherein, Includes the display panel as described in any one of claims 22-27.

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