Array substrate, display panel and display device

Abstract

The present disclosure provides an array substrate, a display panel and a display device. The array substrate comprises a frame start signal line, a gate driving unit and a second transistor. The gate driving unit comprises a first input module, and the first input module comprises a first transistor. The end of the frame start signal line is electrically connected to the first transistor of at least one gate driving unit. The second transistor comprises at least two poles of a gate, a source and a drain, and at least one pole of the second transistor is electrically connected to the signal transmission section before the end of the frame start signal line. The adverse effects caused by electrostatic discharge can be reduced.

Description

Array substrate, display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to an array substrate, a display panel, and a display device. Background Technology

[0002] Gate On Array (GOA) technology integrates the gate driving circuitry onto the array substrate. The gate driving circuitry comprises multiple gate driving units (GOAs), each of which acts as a shift register, sequentially transmitting the scan signal to the next GOA, thus activating the transistor switches of the pixel units row by row and completing the data signal input for each pixel unit. A frame start signal line (STV) is provided in the array substrate and connected to the input module of the GOA to input the frame start signal. Because the STV is relatively long, it is prone to accumulating static electricity during array substrate fabrication. Excessive static electricity can easily burn out the display substrate circuitry.

[0003] Summary of the Invention

[0004] This disclosure provides an array substrate, a display panel, and a display device to reduce the defect rate caused by electrostatic discharge.

[0005] A first aspect of this disclosure provides an array substrate, comprising:

[0006] A display area and a first non-display area, a second non-display area, and a third non-display area arranged around the display area. The first non-display area and the third non-display area are arranged relative to each other. The second non-display area connects the first non-display area and the third non-display area. The first non-display area includes a binding area.

[0007] Frame start signal line; the frame start signal line is led out from the binding area, and the end of the frame start signal line extends along the second non-display area to the side of the second non-display area away from the first non-display area;

[0008] Gate driving unit; the gate driving unit includes a first input module, the first input module includes a first transistor; the end of the frame start signal line is electrically connected to the first transistor of at least one gate driving unit;

[0009] At least one second transistor; the second transistor includes at least two terminals: a gate, a source, and a drain, and at least one terminal of the second transistor is electrically connected to a signal transmission segment preceding the end of the frame start signal line.

[0010] In some embodiments, the channel length of the second transistor is less than or equal to the channel length of the first transistor.

[0011] In some embodiments, the number of second transistors is multiple, and the multiple second transistors are electrically connected to the signal transmission segment at different locations; the different locations include a first non-display area, and / or a second non-display area, and / or a third non-display area.

[0012] In some embodiments, multiple second transistors are alternately distributed on both sides of the signal transmission segment along the extension direction of the frame start signal line.

[0013] In some embodiments, the drain of the second transistor is electrically connected to the drain of the first transistor.

[0014] In some embodiments, the array substrate further includes a backup driving unit, which includes a second input module and a third transistor; the frame start signal line is also electrically connected to the third transistor.

[0015] In some embodiments, the frame start signal line is connected to a third transistor via a spare lead;

[0016] The array substrate also includes at least one fourth transistor, which includes a gate, a source, and a drain, and at least one of the terminals of the fourth transistor is electrically connected to a spare lead.

[0017] In some embodiments, the array substrate further includes:

[0018] Substrate;

[0019] A first conductive layer is located on one side of the substrate; the signal transmission segment includes a first part and a second part located in the first conductive layer, the first part and the second part being adjacent to each other along the extension direction of the frame start signal line and disconnected from each other;

[0020] The second conductive layer is located on the side of the first conductive layer away from the substrate. The second conductive layer includes a first bridging structure and a second bridging structure. The first bridging structure and the second bridging structure are arranged in pairs and are located at positions corresponding to the disconnection positions of the first part and the second part. The paired first bridging structure and the second bridging structure are arranged side by side along the width direction of the frame start signal line, and the width direction is perpendicular to the extension direction of the frame start signal line.

[0021] The first part and the second part are electrically connected by at least one of the first bridging structure and the second bridging structure.

[0022] In some embodiments, the array substrate further includes a third conductive layer located on the side of the second conductive layer away from the substrate; the third conductive layer includes a third bridging structure and a fourth bridging structure;

[0023] The number of frame start signal lines in the array substrate is greater than or equal to one; for at least one frame start signal line, the first part is electrically connected to the first bridging structure through the third bridging structure, and the second part is electrically connected to the first bridging structure through the fourth bridging structure.

[0024] In some embodiments, the array substrate further includes:

[0025] The first insulating layer is located between the first conductive layer and the second conductive layer;

[0026] The second insulating layer is located between the second conductive layer and the third conductive layer;

[0027] For at least one frame start signal line, the array substrate has a first via that penetrates the first insulating layer and the second insulating layer and exposes a first portion, and a second via that penetrates the second insulating layer and exposes a first bridging structure. The third bridging structure is electrically connected to the first portion through the first via and to the first bridging structure through the second via. The array substrate also has a third via that penetrates the first insulating layer and the second insulating layer and exposes a second portion, and a fourth via that penetrates the second insulating layer and exposes the first bridging structure. The fourth bridging structure is electrically connected to the second portion through the third via and to the first bridging structure through the fourth via.

[0028] The orthographic projection of the second via on the substrate and the orthographic projection of the first via on the substrate are arranged in multiple rows and columns, and the second via and the first via are arranged alternately along the row direction and / or column direction;

[0029] The orthographic projection of the fourth via on the substrate and the orthographic projection of the third via on the substrate are arranged in multiple rows and columns, and the fourth via and the third via are arranged alternately along the row direction and / or column direction.

[0030] In some embodiments, the array substrate further includes:

[0031] The first insulating layer is located between the first conductive layer and the second conductive layer;

[0032] The number of frame start signal lines in the array substrate is greater than or equal to one; for at least one frame start signal line, the second bridging structure is directly electrically connected to the first part through a fifth via penetrating the first insulating layer, and the second bridging structure is directly electrically connected to the second part through a sixth via penetrating the first insulating layer.

[0033] In some embodiments, the array substrate further includes:

[0034] Substrate;

[0035] The first conductive layer is located on one side of the substrate; the signal transmission segment further includes a third part and a fourth part located in the first conductive layer, the third part and the fourth part being adjacent to each other along the extension direction of the signal transmission segment and disconnected from each other.

[0036] The top film layer is located on the side of the first conductive layer that is away from the substrate, and among all the film layers located on the side of the first conductive layer that is away from the substrate, the top film layer is the farthest from the first conductive layer.

[0037] The array substrate has a first connection hole and a second connection hole. Both the first connection hole and the second connection hole penetrate the top film layer and other film layers between the top film layer and the first conductive layer. The first connection hole exposes a third part, and the second connection hole exposes a fourth part.

[0038] In some embodiments, the bonding area includes bonding pads, and the signal transmission segment is led out from the bonding pads; the bonding pads include a plurality of bonding leads extending along a first direction and arranged along a second direction; the first direction is the extension direction of the frame start signal line, and the second direction is perpendicular to the first direction.

[0039] The bonding pads also include parallel structures, in which at least some of the bonding leads are interconnected.

[0040] In some embodiments, the array substrate further includes a first test terminal and a first test lead; the first test terminal is electrically connected to the frame start signal line via the first test lead;

[0041] The array substrate also includes:

[0042] Substrate;

[0043] A first conductive layer is located on one side of the substrate. The first test terminal includes a fifth part and a sixth part located on the first conductive layer. The fifth part and the sixth part are disconnected from each other, and the first test lead is connected to the sixth part.

[0044] An insulating layer is located on the side of the first conductive layer that faces away from the substrate; the insulating layer has a plurality of seventh vias that expose the fifth portion and eighth vias that expose the sixth portion;

[0045] The third conductive layer is located on the side of the first conductive layer away from the substrate; the third conductive layer includes at least one fifth bridging structure, which is electrically connected to the fifth part and the sixth part through the seventh via and the eighth via, respectively.

[0046] In some embodiments, the array substrate further includes a second conductive layer located between the first conductive layer and the second conductive layer; the insulating layer includes a first insulating layer and a second insulating layer, the first insulating layer being located between the first conductive layer and the second conductive layer, and the second insulating layer being located between the second conductive layer and the third conductive layer.

[0047] The second conductive layer includes a first electrostatic discharge structure. The orthographic projection of the first electrostatic discharge structure onto the plane of the substrate is located between the orthographic projections of the fifth part onto the plane of the substrate and the orthographic projection of the sixth part onto the plane of the substrate. The orthographic projection of the first electrostatic discharge structure onto the plane of the substrate at least partially overlaps with the orthographic projection of the fifth bridging structure onto the plane of the substrate.

[0048] In some embodiments, the array substrate further includes a second test terminal and a second test lead; the first test lead is electrically connected to the second test terminal, the second test terminal is electrically connected to the second test lead, and the second test lead is electrically connected to the frame start signal line;

[0049] The second test terminal includes a seventh part and an eighth part located in the first conductive layer. The seventh part and the eighth part are disconnected from each other, and the first test lead is connected to the seventh part and the second test lead is connected to the eighth part.

[0050] The insulating layer also has multiple ninth vias exposing the seventh part and tenth vias exposing the eighth part;

[0051] The third conductive layer also includes at least one sixth bridging structure, which is electrically connected to the seventh and eighth portions via the ninth and tenth vias, respectively.

[0052] In some embodiments, the array substrate further includes a second conductive layer located between the first conductive layer and the second conductive layer; the insulating layer includes a first insulating layer and a second insulating layer, the first insulating layer being located between the first conductive layer and the second conductive layer, and the second insulating layer being located between the second conductive layer and the third conductive layer.

[0053] The second conductive layer includes a second electrostatic discharge structure. The orthographic projection of the second electrostatic discharge structure onto the plane of the substrate is located between the orthographic projections of the seventh part onto the plane of the substrate and the orthographic projections of the eighth part onto the plane of the substrate. The orthographic projection of the second electrostatic discharge structure onto the plane of the substrate at least partially overlaps with the orthographic projection of the fifth bridging structure onto the plane of the substrate.

[0054] A second aspect of this disclosure provides an array substrate, the array substrate comprising:

[0055] A display area and a first non-display area, a second non-display area, and a third non-display area arranged around the display area. The first non-display area and the third non-display area are arranged relative to each other. The second non-display area connects the first non-display area and the third non-display area. The first non-display area includes a binding area.

[0056] Frame start signal line; the frame start signal line is led out from the binding area, and the end of the frame start signal line extends along the second non-display area to the side of the second non-display area away from the first non-display area;

[0057] Gate driving unit; the frame start signal line is electrically connected to at least one gate driving unit;

[0058] The array substrate also includes:

[0059] Substrate;

[0060] A first conductive layer is located on one side of the substrate; the frame start signal line includes a first part and a second part located in the first conductive layer, the first part and the second part are arranged adjacent to each other along the extension direction of the frame start signal line and are disconnected from each other.

[0061] The second conductive layer is located on the side of the first conductive layer away from the substrate. The second conductive layer includes a first bridging structure and a second bridging structure. The first bridging structure and the second bridging structure are arranged in pairs and are located at positions corresponding to the disconnection positions of the first part and the second part. The paired first bridging structure and the second bridging structure are arranged side by side along the width direction of the frame start signal line, and the width direction is perpendicular to the extension direction of the frame start signal line.

[0062] The first part and the second part are electrically connected by at least one of the first bridging structure and the second bridging structure.

[0063] In some embodiments, the frame start signal line further includes a third portion and a fourth portion located in the first conductive layer, wherein the third portion and the fourth portion are disposed adjacent to each other along the extension direction of the frame start signal line and are disconnected from each other.

[0064] The array substrate also includes:

[0065] The top film layer is located on the side of the first conductive layer that is away from the substrate, and among all the film layers located on the side of the first conductive layer that is away from the substrate, the top film layer is the farthest from the first conductive layer.

[0066] The array substrate has a first connection hole and a second connection hole. Both the first connection hole and the second connection hole penetrate the top film layer and other film layers between the top film layer and the first conductive layer. The first connection hole exposes a third part, and the second connection hole exposes a fourth part.

[0067] In some embodiments, the bonding area includes bonding pads, and the frame start signal line is led out from the bonding pads; the bonding pads include a plurality of bonding leads extending along a first direction and arranged along a second direction; the first direction is the extension direction of the frame start signal line, and the second direction is perpendicular to the first direction.

[0068] The bonding pads also include parallel structures, in which at least some of the bonding leads are interconnected.

[0069] In some embodiments, the array substrate further includes a first test terminal and a first test lead; the first test terminal is electrically connected to the frame start signal line via the first test lead;

[0070] The first test terminal includes a fifth part and a sixth part located in the first conductive layer. The fifth part and the sixth part are disconnected from each other, and the first test lead is connected to the sixth part.

[0071] The array substrate also includes:

[0072] The third conductive layer is located on the side of the second conductive layer that faces away from the substrate;

[0073] The first insulating layer is located between the first conductive layer and the second conductive layer;

[0074] The second insulating layer is located between the second conductive layer and the third conductive layer;

[0075] The array substrate has multiple seventh vias that penetrate the first insulating layer and the second insulating layer and expose the fifth portion, and multiple eighth vias that penetrate the first insulating layer and the second insulating layer and expose the sixth portion; the third conductive layer includes at least one fifth bridging structure, which is electrically connected to the fifth portion and the sixth portion through the seventh vias and the eighth vias, respectively.

[0076] In some embodiments, the array substrate further includes a second test terminal and a second test lead; the first test lead is electrically connected to the second test terminal, the second test terminal is electrically connected to the second test lead, and the second test lead is electrically connected to the frame start signal line;

[0077] The second test terminal includes a seventh part and an eighth part located in the first conductive layer. The seventh part and the eighth part are disconnected from each other, and the first test lead is connected to the seventh part and the second test lead is connected to the eighth part.

[0078] The array substrate also has multiple ninth vias that penetrate the first insulating layer and the second insulating layer and expose the seventh portion, and multiple tenth vias that penetrate the first insulating layer and the second insulating layer and expose the eighth portion;

[0079] The third conductive layer also includes at least one sixth bridging structure, which is electrically connected to the seventh and eighth portions via the ninth and tenth vias, respectively.

[0080] A third aspect of this disclosure provides a display panel, wherein an array substrate comprising any of the above-mentioned components is provided.

[0081] In some embodiments, the array substrate includes:

[0082] Substrate;

[0083] The first conductive layer is located on one side of the substrate; the signal transmission segment also includes a third part and a fourth part located in the first conductive layer, the third part and the fourth part being arranged adjacent to each other along the extension direction of the frame start signal line and disconnected from each other;

[0084] The top film layer is located on the side of the first conductive layer that is away from the substrate, and among all the film layers located on the side of the first conductive layer that is away from the substrate, the top film layer is the farthest from the first conductive layer.

[0085] The array substrate has a first connection hole and a second connection hole. Both the first connection hole and the second connection hole penetrate the top film layer and other film layers between the top film layer and the first conductive layer. The first connection hole exposes a third part, and the second connection hole exposes a fourth part.

[0086] The display panel also includes:

[0087] The opposing substrate is positioned opposite to the array substrate;

[0088] The liquid crystal layer is located between the opposing substrate and the array substrate;

[0089] A conductive structure is located between the opposing substrate and the array substrate; the third part is electrically connected to the fourth part through the first connecting hole, the conductive structure, and the second connecting hole.

[0090] A fourth aspect of this disclosure provides a display device, wherein a display panel comprising any one of the foregoing claims is provided.

[0091] The beneficial effects of this disclosure are as follows:

[0092] This disclosure provides an array substrate, a display panel, and a display device. The array substrate includes a display area and a first non-display area, a second non-display area, and a third non-display area disposed around the display area. The first and third non-display areas are disposed opposite to each other, and the second non-display area connects the first and third non-display areas. The first non-display area includes a bonding area. The array substrate also includes a frame start signal line, a gate driving unit, and a second transistor. The frame start signal line is led out from the bonding area, and its end extends along the second non-display area to the side of the second non-display area away from the first non-display area. The gate driving unit includes a first input module, which includes a first transistor. The end of the frame start signal line is electrically connected to the first transistor of at least one gate driving unit. The second transistor includes at least two terminals: a gate, a source, and a drain. At least one terminal of the second transistor is electrically connected to a signal transmission segment before the end of the frame start signal line. Before the static electricity accumulated on the frame start signal line is transmitted to the end, most of the static electricity can be released through the second transistor, thereby reducing or completely eliminating the static electricity transmitted to the gate driving unit through the end of the frame start signal line, protecting the gate driving unit, and reducing the adverse effects caused by electrostatic discharge. Attached Figure Description

[0093] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments of this disclosure will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0094] Figure 1 is a schematic diagram of the structure of the array substrate in the related technology;

[0095] Figure 2 is one of the structural schematic diagrams of the array substrate provided in the embodiments of this disclosure;

[0096] Figure 3A is one of the schematic diagrams of the connection structure of the first transistor provided in an embodiment of this disclosure;

[0097] Figure 3B is a second schematic diagram of the connection structure of the first transistor provided in an embodiment of this disclosure;

[0098] Figure 4 is a schematic diagram of one of the gate drive circuits provided in the embodiments of this disclosure;

[0099] Figure 5 is one of the schematic diagrams of the second transistor connection provided in the embodiments of this disclosure;

[0100] Figure 6 is a second schematic diagram of the second transistor connection provided in an embodiment of this disclosure;

[0101] Figure 7A is a third schematic diagram of the second transistor connection provided in an embodiment of this disclosure;

[0102] Figure 7B is a fourth schematic diagram of the second transistor connection provided in an embodiment of this disclosure;

[0103] Figure 7C is the fifth schematic diagram of the second transistor connection provided in the embodiments of this disclosure;

[0104] Figure 8 is a second schematic diagram of the structure of the array substrate provided in the embodiment of this disclosure;

[0105] Figure 9 is a partially enlarged schematic diagram of the backup drive unit provided in an embodiment of this disclosure;

[0106] Figure 10 is one of the enlarged schematic diagrams of a frame start signal line provided in an embodiment of this disclosure;

[0107] Figure 11 is a second enlarged schematic diagram of a frame start signal line provided in an embodiment of this disclosure;

[0108] Figure 12 is one of the cross-sectional structural schematic diagrams of the array substrate provided in the embodiments of this disclosure;

[0109] Figure 13 is a third schematic diagram of the structure of the array substrate provided in the embodiment of this disclosure;

[0110] Figure 14 is a third enlarged schematic diagram of a frame start signal line provided in an embodiment of this disclosure;

[0111] Figure 15 is a fourth enlarged schematic diagram of a frame start signal line provided in an embodiment of this disclosure;

[0112] Figure 16 is a second schematic diagram of the cross-sectional structure of the array substrate provided in the embodiment of this disclosure;

[0113] Figure 17 is a partial enlarged schematic diagram of the frame start signal line provided in an embodiment of this disclosure;

[0114] Figure 18 is a third schematic diagram of the cross-sectional structure of the array substrate provided in the embodiments of this disclosure;

[0115] Figure 19 is a partial enlarged schematic diagram of the frame start signal line provided in an embodiment of this disclosure;

[0116] Figure 20 is a fourth schematic cross-sectional view of the array substrate provided in the embodiments of this disclosure;

[0117] Figure 21 is a partially enlarged schematic diagram of the array substrate provided in an embodiment of this disclosure;

[0118] Figure 22A is one of the enlarged schematic diagrams of the binding area provided in an embodiment of this disclosure;

[0119] Figure 22B is a second enlarged schematic diagram of the binding area provided in an embodiment of this disclosure;

[0120] Figure 23 is a fourth schematic diagram of the structure of the array substrate provided in the embodiment of this disclosure;

[0121] Figure 24 is one of the enlarged schematic diagrams of the first test terminal provided in the embodiments of this disclosure;

[0122] Figure 25 is a fifth schematic cross-sectional view of the array substrate provided in the embodiments of this disclosure;

[0123] Figure 26 is a second enlarged schematic diagram of the first test terminal provided in an embodiment of this disclosure;

[0124] Figure 27 is a third enlarged schematic diagram of the first test terminal provided in an embodiment of this disclosure;

[0125] Figure 28 is a sixth schematic diagram of the cross-sectional structure of the array substrate provided in the embodiments of this disclosure;

[0126] Figure 29 is a fifth schematic diagram of the structure of the array substrate provided in the embodiment of this disclosure;

[0127] Figure 30 is an enlarged schematic diagram of the second test terminal provided in an embodiment of this disclosure;

[0128] Figure 31 is a schematic diagram of the cross-sectional structure of the display panel provided in an embodiment of this disclosure. Detailed Implementation

[0129] To make the above-described objects, features, and advantages of this disclosure more apparent and understandable, the disclosure will be further described below in conjunction with the accompanying drawings and embodiments. However, the exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make the disclosure more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the figures denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms describing position and direction as described in this disclosure are illustrative of the accompanying drawings, but changes may be made as needed, and all such changes are included within the scope of protection of this disclosure. The accompanying drawings of this disclosure are for illustrative purposes only and do not represent actual scale.

[0130] Figure 1 is a schematic diagram of the array substrate structure in the related art. As shown in Figure 1, the array substrate in the related art includes multiple cascaded gate driving units (GOAs). In the cascaded multiple gate driving units (GOAs), the input module of the first-stage gate driving unit (GOA1) is connected to the frame start signal line (STV), and the output module of the previous-stage gate driving unit (GOA) is connected to the input module of the next-stage gate driving unit (GOA). Furthermore, the output module of each stage of the gate driving unit (GOA) is connected to a gate line g, thereby realizing the line-by-line transmission of the scan signal. The specific connection method between the cascaded multiple gate driving units (GOAs) can be found in the related art and will not be elaborated here.

[0131] The array substrate includes a display area AA (the area within the dashed line in Figure 1) and a non-display area surrounding the display area AA. The non-display area surrounding the display area AA may include a first non-display area NA1, a second non-display area NA2, and a third non-display area NA3 located on different sides of the display area AA. The first non-display area NA1 and the third non-display area NA3 are positioned opposite each other, and the second non-display area NA2 is connected to both the first and second non-display areas NA1 and NA3. The first non-display area NA1 includes a bonding area BD. The starting end of the frame start signal line STV is electrically connected to a driving element located in the bonding area, and the end of the frame start signal line STV is led out from the bonding area BD and extends to the side of the second non-display area NA2 away from the first non-display area NA1, connecting to the first-stage gate driving unit GOA1 in a cascaded plurality of gate driving units GOA. The side where the binding region BD (first non-display region NA1) is located is called the data binding side (Data Pad, abbreviated as DP). The side where the third non-display region NA3, which is opposite to the first non-display region NA1, is located is called the data binding opposite side (Data Pad Opposite, abbreviated as DPO). Among the multiple cascaded gate drive units GOA, the first-stage gate drive unit GOA1, which is directly connected to the frame start signal line STV, is usually far away from the data binding DP and close to the data binding opposite side DPO. Therefore, after the frame start signal line STV is led out from the binding region BD, it needs to be extended a long distance in the second non-display region NA2 before connecting to the first-stage gate drive unit GOA1. Furthermore, due to the numerous circuit structures on the array substrate, the frame start signal line (STV) often requires complex winding, resulting in a relatively long length. During the array substrate manufacturing process, the frame start signal line (STV) is prone to accumulating static electricity. Excessive static electricity can easily cause the display substrate circuitry to burn out. In particular, the first transistor T1 in the input module of the gate drive unit (GOA) is directly connected to the frame start signal line (STV) and is easily burned out by the static electricity transmitted from the frame start signal line (STV).

[0132] A first aspect of this disclosure provides an array substrate for solving the aforementioned problems.

[0133] Figure 2 is a schematic diagram of one of the structures of the array substrate provided in this embodiment of the present disclosure. In this embodiment, as shown in Figure 2, the array substrate includes a display area AA and a first non-display area NA1, a second non-display area NA2, and a third non-display area NA3 disposed around the display area AA. The first non-display area NA1 and the third non-display area NA3 are disposed opposite to each other, and the second non-display area NA2 connects the first non-display area NA1 and the third non-display area NA3. The first non-display area NA1 includes a bonding area BD, which is used to bond a driving circuit, such as a flexible circuit board or COF (chip on film).

[0134] The array substrate also includes a frame start signal line STV, a gate drive unit GOA, and at least one second transistor T2.

[0135] The frame start signal line STV is led out from the binding area BD, and the end E of the frame start signal line STV extends along the second non-display area NA2 to the side of the second non-display area NA2 away from the first non-display area NA1.

[0136] The gate driving unit GOA includes a first input module, which includes a first transistor T1. The end E of the frame start signal line STV is electrically connected to at least one first transistor T1 of the gate driving unit GOA.

[0137] Figure 3A is one of the schematic diagrams of the connection structure of the first transistor provided in the embodiment of this disclosure; Figure 3B is another schematic diagram of the connection structure of the first transistor provided in the embodiment of this disclosure.

[0138] In some embodiments, as shown in FIG3A, the source S1 and gate G1 of the first transistor T1 are connected together and electrically connected to the end E of the frame start signal line STV, and the drain D1 of the first transistor T1 is connected to the pull-up node PU of the gate drive unit GOA.

[0139] In some embodiments, as shown in FIG3B, the end E of the frame start signal line STV is electrically connected to the gate G1 of the first transistor T1, the source of the first transistor T1 is connected to a power supply signal, such as the VGH signal or the VGL signal, which is not limited here, and the drain D1 of the first transistor T1 is connected to the pull-up node PU of the gate drive unit GOA.

[0140] In a specific implementation, the end E of the frame start signal line STV is used to lead out at least one frame start signal line lead 11. The frame start signal line lead 11 is used to connect the end E of the frame start signal line STV to the gate driving unit GOA, thereby transmitting the frame start signal to the gate driving unit GOA. It should be noted that the end E of the frame start signal line STV may specifically include the end point of the frame start signal line STV and a portion of the area adjacent to the end point, in order to facilitate the setting of the frame start signal line lead 11, but this is not limited here.

[0141] In some embodiments, a frame start signal line STV can be electrically connected to the first transistor T1 of only one gate drive unit GOA. For example, in the embodiment shown in FIG2, all gate drive units GOA controlled by the same frame start signal line STV are connected end to end in a cascaded manner, and the end E of the frame start signal line STV is only connected to the first-stage gate drive unit GOA1. Specifically, the end E of the frame start signal line STV can be connected to the first transistor T1 through the frame start signal line lead 11; in some embodiments, the end E of the frame start signal line STV can also be directly connected to the first transistor T1, which is not limited here.

[0142] In some embodiments, a frame start signal line STV can be electrically connected to the first transistor T1 of multiple gate drive units GOA, that is, the frame start signal line is connected to the preceding multiple gate drive units, such as the preceding 2nd, 3rd, 4th, 5th, and 6th stage gate drive circuits. Figure 4 is a schematic diagram of one of the gate drive circuit structures provided in the embodiments of this disclosure. For example, as shown in Figure 4, in an 8CLK gate drive circuit, the multiple gate drive units GOA can be divided into 4 gate drive unit groups, each gate drive unit group including multiple gate drive units GOA. The multiple gate drive units GOA in each gate drive unit group are connected to each other in a cascaded manner, and the frame start signal line STV is connected to the first stage gate drive unit GOA in each gate drive unit group. Specifically, the end E of the frame start signal line STV can be connected to the first stage gate drive unit GOA in the 4 gate drive unit groups through 4 frame start signal line leads 11, which is not limited here. In specific implementations, the gate drive circuit can also be a 4CLK, 6CLK, 12CLK, 16CLK, or other structures. The connection methods between the gate drive circuits of different structures and the frame start signal line STV will not be elaborated here.

[0143] It should be noted that this case uses the example of setting one frame start signal line STV, but multiple lines can also be set, such as setting two frame start signal lines, STVA and STVB. STVA can be electrically connected to the previous odd-numbered gate drive circuit, and STVB can be electrically connected to the previous even-numbered gate drive circuit. For example, STVA can be electrically connected to the first stage GOA or the first and third stage GOA, and STVB can be electrically connected to the second stage or the second and fourth stage GOA, etc.

[0144] The second transistor T2 includes at least two terminals: a gate, a source, and a drain. At least one terminal of the second transistor T2 is electrically connected to the signal transmission segment C before the end E of the frame start signal line STV. The signal transmission segment C of the frame start signal line STV is the portion of the frame start signal line STV located between its start end and its end E, wherein the start end of the frame start signal line STV is located in the bonding region BD. In specific implementations, in addition to being connected to the signal transmission segment C, the second transistor T2 may also be connected to the end E of the frame start signal line STV and / or the frame start signal line lead 11; this is not limited here.

[0145] The second transistor T2 can release static electricity and protect the gate driving unit GOA. Specifically, since at least one of the electrodes of the second transistor T2 is electrically connected to the signal transmission segment C of the frame start signal line STV, most of the static electricity accumulated on the frame start signal line STV can be released through the second transistor T2 before it is transmitted to the end E. This reduces or completely eliminates the static electricity transmitted to the gate driving unit GOA through the end of the frame start signal line STV, thus protecting the gate driving unit GOA.

[0146] In some embodiments, the source, gate, and drain of the second transistor T2 are all electrically connected to the signal transmission segment C. Figure 5 is one of the schematic diagrams of the second transistor connection provided in an embodiment of this disclosure. For example, as shown in Figure 5, the source S2, gate G2, and drain G2 of the second transistor T2 are all electrically connected to the signal transmission segment C. When the electrostatic charge on the frame start signal line STV accumulates to a certain level, the voltage generated by the electrostatic charge on the gate G2 of the second transistor T2 controls the second transistor T2 to turn on, so that the electrostatic charge can be propagated through the second transistor T2. When the electrostatic charge is too large, the second transistor T2 is electrostatically broken down, thereby releasing the electrostatic charge and preventing all the electrostatic charge from being transmitted to the first transistor T1 of the gate drive circuit unit, thereby protecting the first transistor T1.

[0147] In some embodiments, the source and gate of the second transistor T2 are electrically connected to the signal transmission segment, and the drain of the second transistor T2 is electrically connected to the drain of the first transistor T1. Figure 6 is a second schematic diagram of the second transistor connection provided in an embodiment of this disclosure. For example, as shown in Figure 6, the source S2 and gate G2 of the second transistor T2 are electrically connected to the signal transmission segment C. When the electrostatic charge on the frame start signal line STV accumulates to a certain level, the voltage generated by the electrostatic charge controls the second transistor T2 to conduct, thereby allowing the electrostatic charge to propagate through the second transistor T2. When the electrostatic charge is too large, the second transistor T2 is electrostatically broken down, thereby releasing the electrostatic charge and preventing all the electrostatic charge from being transmitted to the first transistor T1 of the gate drive circuit unit, thus protecting the first transistor T1. On the other hand, the drain D2 of the second transistor T2 is electrically connected to the drain D1 of the first transistor T1, and the source S1 of the first transistor T1 is electrically connected to the end E of the frame start signal line STV. During the normal transmission of the frame start signal line STV, the second transistor T2, which is not damaged by electrostatic charge, can also transmit the frame start signal to the gate drive unit GOA, improving the signal strength.

[0148] In some embodiments, some electrodes of the second transistor T2 may be electrically connected to the signal transmission segment, while the remaining electrodes may be floating. Floating can be understood as not being connected to any other signal lines.

[0149] Figure 7A is a third schematic diagram of the second transistor connection provided in an embodiment of this disclosure; Figure 7B is a fourth schematic diagram of the second transistor connection provided in an embodiment of this disclosure; Figure 7C is a fifth schematic diagram of the second transistor connection provided in an embodiment of this disclosure.

[0150] For example, as shown in Figure 7A, the source S2 (or drain D2) and gate G2 of the second transistor T2 can be electrically connected to the frame start signal line STV, and the drain D2 (or source S2) of the second transistor T2 can be floating. As shown in Figure 7B, the source S2 (or drain D2) of the second transistor T2 can be electrically connected to the frame start signal line STV, and the drain D2 (or source S2) and gate G2 of the second transistor T2 can be floating. As shown in Figure 7C, the gate G2 of the second transistor T2 can be electrically connected to the frame start signal line STV, and the drain D2 and source S2 of the second transistor T2 can be floating. The second transistor may also include a semiconductor layer. Optionally, the second transistor in this case can be configured as any two of the gate, source, and drain, with one of the two terminals connected to the frame start signal line and the other terminal floating, or the other terminal also electrically connected to the frame start signal line, or the other terminal grounded; no limitation is made here.

[0151] In some embodiments, the floating electrodes shown in Figures 7A to 7C can also be connected to the grounding wire GND or other dedicated electrostatic discharge lines, which are not limited here.

[0152] In some embodiments, the channel length of the second transistor T2 can be set to be less than or equal to the channel length of the first transistor T2. Specifically, the length of the transistor channel refers to the length of the semiconductor between the source and drain. Generally, the resistance of a transistor is positively correlated with the channel length; under the same conditions, a longer channel results in a longer transistor with a higher resistance. In this disclosure, the channel length of the second transistor T2 is set to be no greater than the channel length of the first transistor T2. By controlling the channel length of the second transistor T2 within a certain range, the resistance of the second transistor T2 is reduced, thereby improving the static electricity shunting capability of the second transistor T2. This allows more static electricity to be released through the second transistor T2, improving the protection capability of the first transistor.

[0153] In some embodiments, the channel length of the second transistor T2 can be set to be less than the channel length of the first transistor T2. For example, when the material and channel width are the same, if the channel length of the second transistor T2 is smaller than that of the first transistor T1, then the resistance of the second transistor T2 is lower, which is more conducive to the conduction of static electricity, reduces the amount of static charge flowing through the first transistor T1, and prevents the first transistor T1 from undergoing electrostatic breakdown due to excessive static energy. Optionally, when the channel width of the second transistor T2 is smaller than the channel width of the first transistor T1, by setting the second transistor T2 to have a smaller channel length, it can also play a better role in shunting static electricity compared to setting the second transistor T2 to have a longer channel. In specific implementations, the channel width of the second transistor T2 can be set according to the actual situation. For example, the channel width of the second transistor T2 can be adapted to the available space around the frame start signal line STV. When the space is sufficient, the channel width of the second transistor T2 can be set to be as large as possible to reduce the resistance of the second transistor T2. This is not limited here.

[0154] In some embodiments, the channel length of the second transistor T2 can be set to be equal to the channel length of the first transistor T1 to improve process stability. For some second transistors T2, the resistance can be reduced by increasing the channel width. In specific implementations, the width of the second transistor T2 can be adjusted according to the actual space reserved for each second transistor T2, and no limitation is made here.

[0155] In some embodiments, as shown in FIG2, the number of second transistors T2 can be multiple. For example, the number of second transistors T2 connected to the same frame start signal line STV can be 2, 4, 8 or more. In specific implementation, the number can be set according to the space size around the frame start signal line STV, and is not limited here.

[0156] In some embodiments, as shown in FIG2, a plurality of second transistors T2 are electrically connected to the signal transmission segment C of the frame start signal line STV at different locations. On the one hand, the plurality of second transistors T2 can be uniformly distributed at different locations of the signal transmission segment C along the extension direction of the frame start signal line STV, thereby improving the electrostatic discharge capability. On the other hand, the plurality of second transistors T2 can be disposed in the first non-display area NA1, and / or the second non-display area NA2, and / or the third non-display area NA3, without limitation.

[0157] In some embodiments, as shown in FIG2, multiple second transistors T2 are alternately distributed on both sides of the signal transmission segment C along the extension direction of the frame start signal line STV, thereby providing more space on both sides of the signal transmission segment C for setting the second transistors T2, which is beneficial to increasing the number of second transistors T2. In specific implementations, several consecutive second transistors T2 may also be set on the same side of the signal transmission segment C, which can be set according to the actual situation and is not limited here.

[0158] In some embodiments, the second transistor T2 and the first transistor T1 can be disposed in the same film layer to simplify the process flow. It is important to note that "the second transistor T2 and the first transistor T1 are disposed in the same film layer" specifically means that any component structure in the second transistor T2 is located in the same film layer as the corresponding structure in the first transistor T1. For example, the semiconductor layer of the first transistor T1 and the semiconductor layer of the second transistor T2 can be located in the same film layer; the gate G1 of the first transistor T1 and the gate G2 of the second transistor T2 can be located in the same film layer; the source S1 of the first transistor T1 and the source S2 of the second transistor T2 can be located in the same film layer; and the drain D1 of the first transistor T1 and the drain D2 of the second transistor T2 can be located in the same film layer. It should be noted that the two structures are located in the same film layer. Specifically, the two structures can be formed by patterning the same film layer using the same mask. For example, the semiconductor layer A1 of the first transistor T1 and the semiconductor layer A2 of the second transistor T2 can be formed by patterning the same semiconductor layer using the same mask. This will not be elaborated on here.

[0159] Figure 8 is a second schematic diagram of the array substrate provided in the embodiment of this disclosure; Figure 9 is a partially enlarged schematic diagram of the spare drive unit provided in the embodiment of this disclosure.

[0160] In some embodiments, as shown in Figures 8 and 9, the array substrate further includes a backup driving unit DM. The structure of the backup driving unit DM is basically the same as that of the gate driving unit GOA, except that the output module of the backup driving unit DM is not connected to the gate line g. The backup driving unit DM is used to improve the performance and reliability of the circuit and enhance signal stability. Specifically, the backup driving unit DM includes a second input module, which includes a third transistor T3. The structure of the third transistor T3 in the backup driving unit DM is the same as that of the first transistor T1 in the gate driving unit GOA. Optionally, the same structure may refer to the same channel aspect ratio and morphology of the first transistor T1 and the third transistor T3. The frame start signal line STV is also electrically connected to the third transistor T3. Specifically, as shown in Figures 8 and 9, the third transistor T3 can be connected to the end E of the frame start signal line STV through the backup lead 12, which is not limited here.

[0161] In some embodiments, as shown in Figures 8 and 9, the array substrate further includes at least one fourth transistor T4. The fourth transistor T4 includes at least two electrodes: a gate, a source, and a drain. At least one electrode of the fourth transistor T4 is electrically connected to the spare lead 12. Specifically, the fourth transistor T4 may have the same structure as the second transistor T2. Optionally, having the same structure may mean that the fourth transistor T4 and the second transistor T2 have the same channel aspect ratio and morphology. The fourth transistor T4 may also serve to release static electricity, which will not be elaborated upon here.

[0162] In some embodiments, the third transistor T3 and the fourth transistor T4 may be located in the same film layer as the first transistor T1 and the second transistor T2 to reduce the film layer structure of the array substrate and simplify the fabrication process, which is not limited herein.

[0163] Figure 10 is one of the partially enlarged schematic diagrams of the frame start signal line provided in an embodiment of this disclosure. In some embodiments, as shown in Figure 10, the array substrate includes multiple stacked film layers along the cross-sectional direction. Specifically, the array substrate includes: a substrate 200, a first conductive layer 300, and a second conductive layer 400.

[0164] The first conductive layer 300 is located on one side of the substrate 200. The signal transmission segment C includes a first portion 301 and a second portion 302 located in the first conductive layer 300. In the first conductive layer 300, the first portion 301 and the second portion 302 are adjacent to each other and disconnected from each other along the extension direction Y of the frame start signal line STV. In specific implementations, the first conductive layer 300 can be made of a metal material with good conductivity, such as aluminum (Al), copper (Cu), molybdenum (Mo), or titanium (Ti), which are commonly used metals in the art and are not limited here. In some embodiments, the first conductive layer 300 can be a single-layer structure, such as a single-layer aluminum metal layer. In some embodiments, the first conductive layer 300 can be a stacked structure of multiple metal layers, such as a Ti / Al / Ti stack stacked sequentially, and is not limited here. The first conductive layer 300 can be a gate metal layer, and the first conductive layer 300 can also include the gate of a transistor. In specific implementations, it can be set according to the specific structure of the transistor in the array substrate and is not limited here.

[0165] The second conductive layer 400 is located on the side of the first conductive layer 300 facing away from the substrate 200. The second conductive layer 400 includes a first bridging structure 401 and a second bridging structure 402, which are arranged in pairs and positioned corresponding to the disconnection points of the first portion 301 and the second portion 302. The paired first bridging structures 401 and 402 are arranged side-by-side along the width direction W of the frame start signal line STV, and the width direction W of the frame start signal line STV is perpendicular to the extension direction Y of the frame start signal line STV. In specific implementations, the second conductive layer 400 can be made of a metal material with good conductivity, such as aluminum (Al), copper (Cu), molybdenum (Mo), or titanium (Ti), which are commonly used metals in the art and are not limited herein. In some embodiments, the second conductive layer 400 can be a single-layer structure, such as a single layer of aluminum. In some embodiments, the second conductive layer 400 can be a stacked structure of multiple metal layers, such as a Ti / Al / Ti stack stacked sequentially, and is not limited herein. The second conductive layer 400 can be a source / drain metal layer (SD layer). The second conductive layer 400 can also include the source and drain of the transistor. In specific implementation, it can be set according to the specific structure of the transistor in the array substrate, and is not limited here.

[0166] The first part 301 and the second part 302 are electrically connected through at least one of the first bridging structures 401 and 402. Specifically, one of the first bridging structure 401 and the second bridging structure 402 can be used as the main connection structure, and the other can be used as a backup connection structure. For example, the first bridging structure 401 can be used as the main connection structure, and the second bridging structure 402 can be used as the backup connection structure. During the fabrication of the array substrate, the first part 301 and the second part 302 can be electrically connected only through the first bridging structure 401, and the second bridging structure 402 can be unconnected to either the first part 301 or the second part 302. Since the linewidth of the first bridging structure 401 along the width direction W of the frame start signal line STV is small, its ability to withstand static electricity is weak. When the static electricity generated during the fabrication of the array substrate is too large, it will be released preferentially at the location of the first bridging structure 401, causing the first bridging structure 401 to burn out. This avoids the static electricity from being transmitted to the gate drive unit GOA during the fabrication of the array substrate, causing the GOA to burn out. After the array substrate is fabricated, the connection status of the first bridging structure 401 can be detected. If the electrical connection between the first part 301 and the second part 302 fails due to the burn-out of the first bridging structure 401, the array substrate can be repaired through the second bridging structure 402, allowing the first part 301 and the second part 302 to be electrically connected through the second bridging structure 402. If the first part 301 and the second part 302 are still in a conductive state through the first bridging structure 401, then repair through the second bridging structure 402 can be chosen not to be performed. Alternatively, in addition to the first part 301 and the second part 302 being conductive through the first bridging structure 401, it can be further made so that the first part 301 and the second part 302 are conductive through the second bridging structure 402; this is not limited here. Thus, through the above method, electrostatic discharge protection of the gate drive unit GOA can be achieved during the fabrication of the array substrate, and the conductive state of the frame start signal line STV can be ensured.

[0167] Figure 11 is a second partially enlarged schematic diagram of the frame start signal line provided in an embodiment of this disclosure; Figure 12 is a schematic diagram of the cross-sectional structure of the array substrate provided in an embodiment of this disclosure.

[0168] In some embodiments, as shown in Figures 11 and 12, where Figure 12 can be considered a cross-sectional view of Figure 11 along section line AA, the array substrate further includes a third conductive layer 500, which is located on the side of the second conductive layer 400 facing away from the substrate 200. The third conductive layer 500 includes a third bridging structure 501 and a fourth bridging structure 502. The third conductive layer 500 can be a transparent conductive layer, and the material of the third conductive layer 500 can be a transparent conductive material such as indium tin oxide (ITO), which is not limited here. In specific implementations, depending on the specific structure of the array substrate, the third conductive layer 500 may also include a pixel electrode or a common electrode. For example, when applied to a vertical alignment (VA) type liquid crystal display panel, the pixel electrode and the common electrode are located on the array substrate and the opposing substrate, respectively, and in this case, the third conductive layer 500 may include a pixel electrode. For example, when applied to an in-plane switching (IPS) type liquid crystal display panel, the pixel electrode and the common electrode can both be disposed on the array substrate. In this case, the third conductive layer 500 can include either the pixel electrode or the common electrode, without limitation.

[0169] The number of frame start signal lines in the array substrate is greater than or equal to one. For example, as shown in Figure 2, a gate driving circuit can be provided on only one side of the array substrate, and driving can be performed in a single-sided driving manner. The array substrate is connected to the gate driving circuit through a single frame start signal line STV. Figure 13 is a third schematic diagram of the structure of the array substrate provided in this embodiment. As another example, as shown in Figure 13, gate driving circuits can be provided on opposite sides of the array substrate, and driving can be performed in a double-sided driving manner. The second non-display area NA2 includes a first sub-region NA21 and a second sub-region NA22 located on opposite sides of the display area AA. Both the first sub-region NA21 and the second sub-region NA22 are provided with gate driving circuits. The array substrate can include two frame start signal lines STV. One frame start signal line STV extends along the first sub-region NA21 and is connected to the gate driving circuit located in the first sub-region NA21. The other frame start signal line STV extends along the second sub-region NA22 and is connected to the gate driving circuit located in the second sub-region NA22. Depending on the specific structure of the array substrate, the array substrate may also include two or more frame start signal lines (STVs), which are not limited here.

[0170] In specific implementation, as shown in Figures 11 and 12, for at least one Frame Start Signal Line (STV), the first part 301 is electrically connected to the first bridging structure 401 via the third bridging structure 501, and the second part 302 is electrically connected to the first bridging structure 401 via the fourth bridging structure 502. Since the material of the third conductive layer 500, where the third bridging structure 501 and the fourth bridging structure 502 are located, is a metal oxide such as indium tin oxide, compared to metal materials, indium tin oxide and other metal oxides have a weaker ability to withstand instantaneous high-voltage electrostatic discharge. Therefore, connecting the first part 301 and the first bridging structure 401 via the third bridging structure 501, and connecting the second part 302 and the first bridging structure 401 via the fourth bridging structure 502, can reduce the electrostatic conductivity and further prevent electrostatic conduction to the gate drive unit (GOA). On the other hand, during the fabrication of the array substrate, if the first bridging structure 401, the third bridging structure 501, and the fourth bridging structure 502 between the first part 301 and the second part 302 of each frame start signal line STV in the array substrate are not broken due to electrostatic breakdown, then for each frame start signal line STV in the array substrate, the first part 301 can still be electrically connected to the first bridging structure 401 through the third bridging structure 501, and the second part 302 can still be electrically connected to the first bridging structure 401 through the fourth bridging structure 502. If, for a certain frame start signal line STV in the array substrate, the first bridging structure 301, the third bridging structure 501, and / or the fourth bridging structure 502 are broken due to electrostatic breakdown, then the frame start signal line STV can be repaired through the second bridging structure 402, and the remaining frame start signal lines STV can still be connected through the first bridging structure 301, the third bridging structure 501, and the fourth bridging structure 501.

[0171] In some embodiments, as shown in Figures 11 and 12, the array substrate further includes a first insulating layer 600 and a second insulating layer 700. The first insulating layer 600 is located between the first conductive layer 300 and the second conductive layer 400. The second insulating layer 700 is located between the second conductive layer 400 and the third conductive layer 500.

[0172] For at least one frame start signal line (STV), the array substrate has a first via H1 that penetrates the first insulating layer 600 and the second insulating layer 700 and exposes the first portion 301 of the frame start signal line STV, and a second via H2 that penetrates the second insulating layer 700 and exposes the first bridging structure 401. The third bridging structure 501 is electrically connected to the first portion 301 through the first via H1 and to the first bridging structure 401 through the second via H2. The array substrate also has a third via H3 that penetrates the first insulating layer 600 and the second insulating layer 700 and exposes the second portion 302, and a fourth via H4 that penetrates the second insulating layer 700 and exposes the first bridging structure 401. The fourth bridging structure 502 is electrically connected to the second portion 302 through the third via H3 and to the first bridging structure 401 through the fourth via H3. It should be noted that the different shapes of the first via H1 and the second via H2 shown in the figure are only for easy distinction and do not represent the actual shapes of the first via H1 and the second via H2. In specific implementation, the shapes of the first via H1 and the second via H2 shall be based on the actual shapes and are not limited here.

[0173] Figure 14 is a third enlarged schematic diagram of the frame start signal line provided in an embodiment of this disclosure.

[0174] In some embodiments, as shown in FIG14, the orthographic projections of the second via H2 on the substrate 200 and the first via H1 on the substrate 200 are arranged in multiple rows and columns, and the third via H3 and the first via H1 are alternately arranged along the row direction and / or column direction; the orthographic projections of the fourth via H4 on the substrate 200 and the third via H3 on the substrate 200 are arranged in multiple rows and columns, and the fourth via H4 and the third via H3 are alternately arranged along the row direction and / or column direction. The row direction can be parallel to the extension direction Y of the frame start signal line STV, and the column direction can be parallel to the width direction of the frame start signal line STV, which is not limited here. Alternating the second via H2 and the first via H1, and alternating the third via H3 and the fourth via H4, is beneficial for improving signal transmission efficiency and stability. In specific implementation, for the same frame start signal line STV, in the multiple rows and columns formed by the arrangement of the second via H2 and the first via H1, optionally, the total number of the second via H2 and the first via H1 can be set to be less than or equal to 6, and / or in the multiple rows and columns formed by the arrangement of the fourth via H4 and the first three via H3, the total number of the third via H3 and the fourth via H4 can be set to be less than or equal to 6, without limitation here.

[0175] Figure 15 is a partial enlarged schematic diagram of the frame start signal line provided in an embodiment of this disclosure.

[0176] In some embodiments, the linewidth of the first bridging structure 401 along the width direction W of the frame start signal line STV can be set to be less than or equal to 60 μm. The smaller the linewidth of the first bridging structure 401, the higher its sensitivity to electrostatic discharge. That is, the first bridging structure 401 can break at a lower discharge voltage, thereby preventing electrostatic conduction to the gate drive unit GOA. It should be noted that the linewidth of the first bridging structure 401 along the width direction W of the frame start signal line STV specifically refers to the sum of the widths of the solid portions of the first bridging structure 401. Specifically, as shown in FIG15, when the overall width of the first bridging structure 401 is relatively wide, a cutout F can be made in the first bridging structure 401. For example, in FIG15, the central region of the first bridging structure 401 is set as a cutout area, forming two solid portions, one of which has a first width W1 and the other has a second width W2. Then, the linewidth of the first bridging structure 401 specifically refers to the sum of the first width W1 and the second width W2. When the first bridging structure 401 adopts other hollowing methods, they will not be described in detail here. In addition, for all the lines mentioned in the embodiments of this disclosure, depending on the overall width of a specific line, when its overall width is relatively wide, a hollowing design can be adopted, as shown in Figure 15. A hollowing F can also be set for the signal transmission segment C, which will not be described in detail here.

[0177] Figure 16 is a second schematic diagram of the cross-sectional structure of the array substrate provided in the embodiments of this disclosure.

[0178] In some embodiments, as shown in Figures 14 and 16, where Figure 16 can be considered a cross-sectional view of Figure 14 along section line AA, the third bridging structure 501 and the fourth bridging structure 502 can also be connected to form an integral structure. Combining Figures 11 and 14, it can be seen that in Figure 11, the third bridging structure 501 and the fourth bridging structure 502 are separately arranged, while in Figure 14, the third bridging structure 501 and the fourth bridging structure 502 can be connected to form an integral structure, thereby improving signal transmission efficiency; however, this is not limited to these embodiments.

[0179] Figure 17 is a partial enlarged schematic diagram of the frame start signal line provided in the embodiment of this disclosure (Part 5); Figure 18 is a cross-sectional schematic diagram of the array substrate provided in the embodiment of this disclosure (Part 3).

[0180] In some embodiments, as shown in Figures 17 and 18, where Figure 18 can be considered a cross-sectional view of Figure 17 along section line BB, a first insulating layer 600 is disposed between the first conductive layer 200 and the second conductive layer 400. The number of frame start signal lines (STVs) in the array substrate is greater than or equal to one. For at least one frame start signal line (STV), a second bridging structure 402 is electrically connected to the first portion 301 of the frame start signal line (STV) through a fifth via H5 penetrating the first insulating layer 600, and the second bridging structure 402 is electrically connected to the second portion 302 of the frame start signal line (STV) through a sixth via H6 penetrating the first insulating layer 600. Specifically, if during the fabrication of the array substrate, any one of the first bridging structure 401, the third bridging structure 501, and the fourth bridging structure 502 is electrostatically broken down, causing the electrical connection between the first part 301 and the second part 302 of the frame start signal line STV to be disconnected, then a fifth via H5 can be opened in the first insulating layer 600 between the second bridging structure 402 and the first part 301 through laser repair or other methods, so that the second bridging structure 402 is connected to the first part 301 through the fifth via H5. Furthermore, a sixth via H6 can be opened in the first insulating layer 600 between the second bridging structure 402 and the second part 302, so that the second bridging structure 402 is connected to the second part 302 through the sixth via H6. Thus, the first part 301 and the second part 302 of the frame start signal line STV can be electrically connected through the second bridging structure 402. During the fabrication of the array substrate, for frame start signal lines (STVs) where the first bridging structure 401, the third bridging structure 501, and the fourth bridging structure 502 are not disconnected, laser repair can be performed without using the second bridging structure 402. That is, the first part 301 and the second part 302 of this portion of the frame start signal line STV are still electrically connected through the first bridging structure 401, the third bridging structure 501, and the fourth bridging structure 502, but not through the second bridging structure 402. Of course, to further improve signal transmission efficiency and quality, the first part 301 and the second part 302 of the frame start signal line STV can also be electrically connected through the first bridging structure 401, the third bridging structure 501, and the fourth bridging structure 502, while simultaneously being electrically connected through the second bridging structure 402; this is not a limitation here.

[0181] In some embodiments, the linewidth of the second bridging structure 401 can be set to be greater than or equal to 10 μm along the width direction W of the frame start signal line STV. The larger the linewidth of the second bridging structure 401, the higher the signal transmission efficiency and quality after the frame start signal line STV is repaired by the second bridging structure 401. It should be noted that, referring to the first bridging structure 401, the second bridging structure 401 can also adopt a hollow design. When the second bridging structure 401 adopts a hollow design, the linewidth of the second bridging structure 401 along the width direction W of the frame start signal line STV specifically refers to the sum of the widths of the solid parts of the second bridging structure 401, which will not be elaborated here.

[0182] Figure 19 is a partial enlarged schematic diagram of the frame start signal line provided in the embodiment of this disclosure (the sixth one); Figure 20 is a cross-sectional schematic diagram of the array substrate provided in the embodiment of this disclosure (the fourth one).

[0183] In some embodiments, as shown in Figures 19 and 20, where Figure 20 can be considered a cross-sectional view of Figure 19 along section line CC, the array substrate further includes a top film layer 99. The top film layer 99 is located on the side of the first conductive layer 300 facing away from the substrate 200, and among all the film layers located on the side of the first conductive layer 300 facing away from the substrate 200, the top film layer 99 is the furthest from the first conductive layer 300. That is, on the side of the first conductive layer 300 facing away from the substrate 200, the top film layer 99 is the outermost film layer of the array substrate, and the first insulating layer, second conductive layer, second insulating layer, third conductive layer, and other film layers are all located between the first conductive layer 300 and the top film layer 99.

[0184] The signal transmission segment C also includes a third part 303 and a fourth part 304 located in the first conductive layer 300. The third part 303 and the fourth part 304 are arranged adjacent to each other along the extension direction Y of the frame start signal line STV and are disconnected from each other.

[0185] The array substrate also has a first connection hole K1 and a second connection hole K2. The first connection hole K1 penetrates the top film layer 99 and other film layers 98 located between the top film layer 99 and the first conductive layer 300, thereby exposing the third portion 303 of the signal transmission segment C. The first connection hole K1 penetrates the top film layer 99 and other film layers 98 located between the top film layer 99 and the first conductive layer 300, thereby exposing the fourth portion 304 of the signal transmission segment C. The other film layers 98 may include a first insulating layer, a second insulating layer, etc., and are not limited thereto.

[0186] In specific implementation, during the fabrication of the array substrate, the signal transmission segment C is disconnected at the break point between the third part 303 and the fourth part 304. This blocks the conduction path of static electricity during the fabrication of the array substrate, preventing a large amount of static electricity from being conducted to the gate driving unit and causing damage to the gate driving unit. When assembling the array substrate and the opposing substrate, conductive material can be used to fill the first connection hole K1 and the second connection hole K2 to form a conductive structure connecting the third part 303 and the fourth part 304, thereby creating a path for the signal transmission segment C to facilitate the transmission of the frame start signal. For example, during the assembly process of the array substrate and the opposing substrate, conductive sealant can be used to connect the third part 303 and the fourth part 304; this is not limited to this method.

[0187] Figure 21 is a partially enlarged schematic diagram of the array substrate provided in an embodiment of this disclosure.

[0188] In some embodiments, besides the frame start signal line STV, the gate drive unit GOA also needs to be connected to some other signal lines OTH to receive specific signals. These other signal lines OTH include the clock signal line (CLK), the gate turn-off signal line (VSS), and possibly the DC voltage line (VDD), etc., which are not limited here. In specific implementations, as shown in Figure 21, the signal line can be disconnected only for the frame start signal line STV. In some embodiments, this design can also be done on other signal lines OTH connected to the gate drive unit, such as the CLK signal line, VSS signal line, VDD signal line, etc. The STV signal line and other signal lines OTH in Figure 18 can each have multiple cutouts F, which are not limited here.

[0189] Figure 22A is one of the enlarged schematic diagrams of the binding area provided in the embodiments of this disclosure; Figure 22B is another enlarged schematic diagram of the binding area provided in the embodiments of this disclosure.

[0190] In some embodiments, as shown in Figures 22A and 22B, the bonding area BD of the array substrate includes bonding pads BP, which are used to bond driving components such as circuit boards. The starting end of the frame start signal line STV is connected to the bonding pad BP, and the signal transmission segment C is led out from the bonding pad BP. The bonding pad BP includes multiple bonding leads LD extending along a first direction and arranged along a second direction. The first direction is the extension direction Y of the frame start signal line STV, and the second direction is perpendicular to the first direction, that is, the width direction W of the frame start signal line STV.

[0191] In some embodiments, as shown in Figures 22A and 22B, the bonding pad BP further includes a parallel structure P. At least some of the bonding leads LD are interconnected via the parallel structure P. For example, two adjacent bonding leads LD are connected by the parallel structure P located between them. Specifically, because a single bonding lead LD has a narrow linewidth and weak voltage withstand capability, it is easily damaged by high voltage loss caused by electrostatic discharge. By setting the parallel structure P to reduce the resistance of the bonding pad BP, the electrostatic discharge withstand capability of the pad BP can be effectively improved, reducing the incidence of bonding pad BP defects caused by electrostatic discharge.

[0192] In some embodiments, the number of parallel structures P can be minimized to keep the total area of ​​the bonding pads BP within a small range, reducing the risk of arcing due to excessively large bonding pad BP areas. Specifically, as shown in Figures 22A and 22B, a bonding lead LD can be configured to connect only to another bonding lead LD located on its side via a parallel structure P. For example, a bonding lead LD can be connected only to the bonding lead LD located to its left via a parallel structure P, and not to the bonding lead LD located to its right via a parallel structure P, or a bonding lead LD can be connected only to the bonding lead LD located to its right via a parallel structure P, and not to the bonding lead LD located to its left via a parallel structure P; this is not a limitation. In specific embodiments, the number of parallel structures P between two adjacent bonding leads LD can also be less than or equal to two. For example, as shown in Figure 22A, the number of parallel structures P between two adjacent bonding leads LD is only one. The parallel structures P can be located in the middle part of the bonding lead BP along the direction of the bonding lead LD's extension, forming an "H"-shaped structure. For example, as shown in Figure 22B, the number of parallel structures P between two adjacent binding leads LD can be two. The two parallel structures P can be set at opposite ends of the binding leads LD to form an "O" type structure, which is not limited here.

[0193] In some embodiments, as shown in Figures 22A and 22B, the third conductive layer 500 further includes a bonding region bridging structure CS, which connects bonding leads LD to each other through bonding region vias H that penetrate the insulating layer. In specific implementations, the bonding leads LD may be located in the first conductive layer 300 to facilitate connection between the bonding leads LD and the frame start signal line STV, which is not limited here.

[0194] Figure 23 is a fourth schematic diagram of the structure of the array substrate provided in the embodiments of this disclosure.

[0195] In some embodiments, as shown in FIG23, the array substrate further includes a first test terminal AT and a first test lead TST1. The first test terminal AT is electrically connected to the frame start signal line via the first test lead TST1. Specifically, the first test terminal AT can be connected to the bonding pad of the bonding area BD via the first test lead TST1, and then connected to the frame start signal line STV via the bonding pad, which is not limited here.

[0196] Figure 24 is one of the enlarged schematic diagrams of the first test terminal provided in the embodiments of this disclosure; Figure 25 is another schematic diagram of the cross-sectional structure of the array substrate provided in the embodiments of this disclosure.

[0197] In some embodiments, as shown in Figures 24 and 25, where Figure 25 can be considered a cross-sectional view of Figure 24 along section line DD, the first test terminal AT includes a fifth portion AT1 and a sixth portion AT2 located in the first conductive layer 300. The fifth portion AT1 and the sixth portion AT2 are disconnected from each other, and the sixth portion AT2 is connected to the first test lead TST1. The third conductive layer includes at least one fifth bridging structure 503. The insulating layer 67 between the first conductive layer 300 and the third conductive layer 500 has multiple seventh vias H7 exposing the fifth portion AT1 and eighth vias H8 exposing the sixth portion AT2. The insulating layer 67 includes a first insulating layer and a second insulating layer, etc., which are not specifically shown in the figures and will not be described in detail here. The fifth bridging structure 503 is electrically connected to the fifth portion AT1 and the sixth portion AT2 through the seventh vias H7 and the eighth vias H8, respectively. That is to say, the fifth bridging structure 503 connects the fifth portion AT1 and the sixth portion AT2 through the seventh vias H7 and the eighth vias H8.

[0198] Specifically, the first test terminal AT is used to connect an external signal generator during array substrate testing. The external signal generator is inserted into the first test terminal AT through a connection terminal to input a frame start signal to the first test terminal AT. Static electricity is easily generated during the insertion and removal of the external signal generator's connection terminal from the first test terminal AT. In related technologies, the static electricity generated during the insertion and removal of the external signal generator's connection terminal from the first test terminal AT can be directly conducted to the gate drive unit GOA through the first test lead TST1 and the frame start signal line STV, increasing the risk of damage to the gate drive unit GOA due to electrostatic discharge.

[0199] In this embodiment, the first test terminal AT is designed as a fifth part AT1 and a sixth part AT2 that are disconnected from each other. During array substrate testing, the fifth part AT1 is connected to the connection terminal for connecting an external signal generator. The static electricity generated during the insertion and removal process between the connection terminal of the external signal generator and the fifth part AT1 will not be directly conducted to the sixth part AT2, but will be indirectly conducted to the sixth part AT2 through the fifth bridging structure 503. Since the third conductive layer 500 is made of metal oxides such as indium tin oxide, its ability to withstand electrostatic discharge is weaker than that of the first conductive layer 300. Therefore, when the static energy is too large, most of the energy can be released in advance in the fifth bridging structure 503, avoiding conduction to the rear end, thereby playing a role in electrostatic protection for structures such as the gate drive unit GOA. Furthermore, since the area covered by the fifth bridging structure 503 is relatively large (including the area directly above the fifth part AT1 and the sixth part AT2, the area between the fifth part AT1 and the sixth part AT2, and the surface of the fifth via H5 and the sixth via H6), even if the fifth bridging structure 503 is locally damaged due to electrostatic discharge, the area of ​​the damaged part is still smaller than the total area of ​​the fifth bridging structure 503. The fifth bridging structure 503 can still transmit signals by relying on the undamaged area, and will not affect the array substrate testing process.

[0200] Figure 26 is a second enlarged schematic diagram of the first test terminal provided in an embodiment of this disclosure.

[0201] In some embodiments, as shown in FIG26, the fifth part AT1 and the sixth part AT2 can be connected by multiple independent fifth jumper structures 503. When the fifth part AT1 and the sixth part AT2 are connected by multiple independent fifth jumper structures 503, the adjacent fifth jumper structures 503 are spaced apart by a certain distance, so that the width of each fifth jumper structure 503 is narrower, and its ability to withstand electrostatic discharge is weaker, thus providing better electrostatic protection. Furthermore, the multiple fifth jumper structures 503 are independent of each other. If one fifth jumper structure 503 is damaged by electrostatic discharge, it will not affect the remaining fifth jumper structures 503, thereby ensuring the stability of the circuit structure. In a specific implementation, as shown in FIG24, the fifth part AT1 and the sixth part AT2 can also be connected by only one fifth jumper structure 503, which is not limited here.

[0202] Figure 27 is a third enlarged schematic diagram of the first test terminal provided in the embodiments of this disclosure; Figure 28 is a sixth cross-sectional schematic diagram of the array substrate provided in the embodiments of this disclosure.

[0203] In some embodiments, as shown in Figures 27 and 28, where Figure 28 can be considered a cross-sectional view of Figure 27 along section line DD, the second conductive layer 400 further includes a first electrostatic discharge structure 403. The orthographic projection of the first electrostatic discharge structure 403 onto the plane of the substrate 200 lies between the orthographic projections of the fifth portion AT1 and the sixth portion AT2 onto the plane of the substrate 200, and the orthographic projection of the first electrostatic discharge structure 403 onto the plane of the substrate 200 at least partially overlaps with the orthographic projection of the fifth bridging structure 503 onto the plane of the substrate 200. Specifically, an electrostatic discharge capacitor is formed between the first electrostatic discharge structure 403 and the fifth bridging structure 503. When the electrostatic energy conducted on the fifth bridging structure 503 is too large, the fifth bridging structure 503 can discharge to the first electrostatic discharge structure 403 through methods such as tip discharge, thereby reducing the electrostatic charge conducted to the sixth portion AT2.

[0204] In some embodiments, as shown in FIG27, an electrostatic ring R and a shorting bar SB are further provided in the array substrate. The electrostatic ring R is connected to the shorting bar SB, and the first electrostatic discharge structure 403 is also connected to the electrostatic ring R. In specific implementations, the fifth bridging structure 503 may also be connected to the electrostatic ring R, which is not limited here. The electrostatic ring R is usually disposed in the third conductive layer 500, and the shorting bar SB is usually disposed in the first conductive layer 300. In specific implementations, the arrangement and function of the electrostatic ring R and the shorting bar SB can be referred to the relevant technology in the art, which will not be elaborated here.

[0205] Figure 29 is the fifth schematic diagram of the structure of the array substrate provided in the embodiments of this disclosure.

[0206] In some embodiments, as shown in FIG29, the array substrate further includes a second test terminal CT and a second test lead TST2. The first test lead TST2 is electrically connected to the second test terminal CT, the second test terminal CT is electrically connected to the second test lead TST2, and the second test lead TST2 is electrically connected to the frame start signal line (STV). Specifically, the first test terminal CT and the second test terminal CT can be used for testing the array substrate at different stages of its fabrication. For example, the first test terminal CT can be used to connect an external signal generator during array testing, and the second test terminal CT can be used to connect an external signal generator during cell testing; this is not limited to these specific applications. The array substrate may include both the first test terminal CT and the second test terminal CT simultaneously, or it may include only one of the first test terminal CT and the second test terminal CT. For example, the array substrate may retain only the second test terminal CT, and the first test terminal CT may be removed after testing; this is not limited to these specific applications.

[0207] Figure 30 is an enlarged schematic diagram of the second test terminal provided in an embodiment of this disclosure.

[0208] In some embodiments, as shown in FIG30, the second test terminal CT includes a seventh portion CT1 and an eighth portion CT2 located in the first conductive layer 300. The seventh portion CT1 and the eighth portion CT2 are disconnected from each other, and the first test lead TST1 is connected to the seventh portion CT1, and the second test lead TST2 is connected to the eighth portion CT2. The insulating layer also has a plurality of ninth vias H9 exposing the seventh portion CT1 and tenth vias H10 exposing the eighth portion CT2. The third conductive layer 500 also includes at least one sixth bridging structure 504, which is electrically connected to the seventh portion CT1 and the eighth portion CT2 through the ninth vias H9 and the tenth vias H10, respectively. By setting the second test terminal CT to be the mutually disconnected seventh portion CT1 and the eighth portion CT2, it is beneficial to improve the electrostatic discharge protection effect. For details, please refer to the relevant content of the first test terminal AT, which will not be elaborated here.

[0209] In some embodiments, the second conductive layer 400 further includes a second electrostatic discharge structure 404. The orthographic projection of the second electrostatic discharge structure 404 onto the plane of the substrate 200 lies between the orthographic projections of the seventh portion CT1 and the eighth portion CT2 onto the plane of the substrate 200, and the orthographic projection of the second electrostatic discharge structure 404 onto the plane of the substrate 200 at least partially overlaps with the orthographic projection of the fifth bridging structure 504 onto the plane of the substrate 200. For details, please refer to the description of the first electrostatic discharge structure 403, which will not be repeated here. In specific implementations, the second electrostatic discharge structure 404 can also be connected to the ground signal line GND to improve the electrostatic protection effect, which will not be elaborated here.

[0210] A second aspect of this disclosure also provides an array substrate. Referring to FIG1, the array substrate includes a display area AA and a first non-display area NA1, a second non-display area NA2, and a third non-display area NA3 disposed around the display area AA. The first non-display area NA1 and the third non-display area NA3 are disposed opposite to each other. The second non-display area NA2 connects the first non-display area NA1 and the third non-display area NA3. The first non-display area NA1 includes a bonding area BD.

[0211] The array substrate also includes a frame start signal line (STV) and a gate drive unit (GOA). The frame start signal line (STV) is led out from the bonding region (BD), and its end extends along the second non-display region (NA2) to the side of the second non-display region (NA2) away from the first non-display region. The frame start signal line (STV) is electrically connected to at least one gate drive unit (GOA). The specific connection method between the frame start signal line (STV) and the gate drive unit (GOA) can be referred to the relevant portion of the first aspect of this disclosure, and will not be repeated here.

[0212] Referring to Figure 10, the array substrate also includes:

[0213] Substrate 200;

[0214] The first conductive layer 300 is located on one side of the substrate 200; the frame start signal line STV includes a first part 301 and a second part 302 located in the first conductive layer 300, the first part 301 and the second part 302 are arranged adjacent to each other along the extension direction Y of the frame start signal line STV and are disconnected from each other.

[0215] The second conductive layer 400 is located on the side of the first conductive layer 300 facing away from the substrate 200. The second conductive layer 400 includes a first bridging structure 401 and a second bridging structure 402, which are arranged in pairs and positioned corresponding to the disconnection positions of the first portion 301 and the second portion 302. The paired first bridging structures 401 and 402 are arranged side by side along the width direction W of the frame start signal line STV, and the width direction W is perpendicular to the extension direction Y of the frame start signal line STV.

[0216] The first part 301 and the second part 302 are electrically connected through at least one of the first bridging structure 401 and the second bridging structure 402. The specific manner in which the first part 301 and the second part 302 are electrically connected through at least one of the first bridging structure 401 and the second bridging structure 402, and the resulting technical effects, can be referred to the relevant parts of the first aspect of this disclosure, and will not be repeated here.

[0217] In some embodiments, referring to Figures 19 and 20, the frame start signal line STV further includes a third portion 303 and a fourth portion 304 located in the first conductive layer 300, wherein the third portion 303 and the fourth portion 304 are disposed adjacent to each other along the extension direction Y of the frame start signal line STV and are disconnected from each other.

[0218] The array substrate further includes a top film layer 99. The top film layer 99 is located on the side of the first conductive layer 300 away from the substrate 200, and among the film layers located on the side of the first conductive layer 300 away from the substrate 200, the top film layer 99 is the farthest from the first conductive layer 300.

[0219] The array substrate also has a first connection hole K1 and a second connection hole K2, both of which penetrate the top film layer 99 and other film layers between the top film layer 99 and the first conductive layer 300. The first connection hole K1 exposes the third portion 303, and the second connection hole K2 exposes the fourth portion 304. For details regarding the first connection hole K1 and the second connection hole K2, please refer to the relevant part of the first aspect of this disclosure, which will not be repeated here.

[0220] In some embodiments, referring to Figures 22A and 22B, the bonding region BD includes a bonding pad BP. A frame start signal line STV is led out from the bonding pad BP. The bonding pad BP includes a plurality of bonding leads LD extending in a first direction and arranged in a second direction. The first direction is the extension direction Y of the frame start signal line, and the second direction is perpendicular to the first direction. The bonding pad BP also includes a parallel structure P, through which at least a portion of the plurality of bonding leads LD are interconnected. Further details regarding the bonding pad BP can be found in the relevant portions of the first aspect of this disclosure, and will not be repeated here.

[0221] In some embodiments, referring to Figures 23-25, the array substrate further includes a first test terminal AT and a first test lead TST1. The first test terminal AT is electrically connected to the frame start signal line STV via the first test lead TST1. The first test terminal AT includes a fifth portion AT1 and a sixth portion AT2 located in the first conductive layer 300. The fifth portion AT1 and the sixth portion AT2 are disconnected from each other, and the first test lead TST1 is connected to the sixth portion AT2.

[0222] The array substrate also includes:

[0223] The third conductive layer 500 is located on the side of the second conductive layer 400 that is away from the substrate 200;

[0224] The first insulating layer 600 is located between the first conductive layer 300 and the second conductive layer 400;

[0225] The second insulating layer 700 is located between the second conductive layer 400 and the third conductive layer 500;

[0226] The array substrate has multiple seventh vias H7 that penetrate the first insulating layer 600 and the second insulating layer 700 and expose the fifth portion AT1, and multiple eighth vias H8 that penetrate the first insulating layer 600 and the second insulating layer 700 and expose the sixth portion AT2. The third conductive layer 500 includes at least one fifth bridging structure 503, which is electrically connected to the fifth portion AT1 and the sixth portion AT2 through the seventh vias H7 and the eighth vias H8, respectively.

[0227] In specific implementation, the relevant content regarding the first test terminal AT can be found in the relevant part of the first aspect of this disclosure, and will not be repeated here.

[0228] In some embodiments, referring to Figures 29-30, the array substrate further includes a second test terminal CT and a second test lead TST2. A first test lead TST1 is electrically connected to the second test terminal CT, the second test terminal CT is electrically connected to the second test lead TST2, and the second test lead TST2 is electrically connected to the frame start signal line STV. The second test terminal CT includes a seventh portion CT1 and an eighth portion CT2 located in the first conductive layer 300. The seventh portion CT1 and the eighth portion CT2 are disconnected from each other, and the first test lead TST1 is connected to the seventh portion CT1, and the second test lead TST2 is connected to the eighth portion CT2.

[0229] The array substrate also has multiple ninth vias H9 that penetrate the first insulating layer 600 and the second insulating layer 700 and expose the seventh portion CT1, and multiple tenth vias H10 that penetrate the first insulating layer 600 and the second insulating layer 700 and expose the eighth portion CT2. The third conductive layer 500 also includes at least one sixth bridging structure 504, which is electrically connected to the seventh portion CT1 and the eighth portion CT2 through the ninth vias H9 and the tenth vias H10, respectively.

[0230] In specific implementation, the relevant content regarding the second test terminal CT can be referred to the relevant part of the first aspect of this disclosure, which will not be repeated here.

[0231] A third aspect of this disclosure provides a display panel. The display panel provided in the third aspect of this disclosure includes an array substrate provided in any embodiment of the first aspect of this disclosure, or includes an array substrate provided in any embodiment of the second aspect of this disclosure. Therefore, the display panel provided in the third aspect of this disclosure has the same or similar technical effects as the array substrate provided in any embodiment of the first aspect of this disclosure, or the same or similar technical effects as the array substrate provided in any embodiment of the second aspect of this disclosure, which will not be elaborated here.

[0232] Figure 31 is a schematic diagram of the cross-sectional structure of the display panel provided in an embodiment of this disclosure.

[0233] In some embodiments, referring to Figures 19 and 31, the array substrate 10 includes:

[0234] Substrate 200;

[0235] The first conductive layer 300 is located on one side of the substrate 200. The signal transmission segment C also includes a third portion 303 and a fourth portion 304 located in the first conductive layer 300. The third portion 303 and the fourth portion 304 are arranged adjacent to each other along the extension direction Y of the frame start signal line and are disconnected from each other.

[0236] The top film layer 99 is located on the side of the first conductive layer 300 away from the substrate 200, and among all the film layers located on the side of the first conductive layer 300 away from the substrate 200, the top film layer 99 is the farthest from the first conductive layer 300.

[0237] The array substrate has a first connection hole K1 and a second connection hole K2. Both the first connection hole K1 and the second connection hole K2 penetrate the top film layer 99 and other film layers 98 between the top film layer 99 and the first conductive layer 300. The first connection hole K1 exposes the third part 303, and the second connection hole K2 exposes the fourth part 304.

[0238] The display panel also includes:

[0239] The opposing substrate 20 is disposed opposite to the array substrate 10.

[0240] The liquid crystal layer LC is located between the opposing substrate 2 and the array substrate 10.

[0241] A conductive structure 30 is located between the opposing substrate 20 and the array substrate 10. The third part 303 is electrically connected to the fourth part 304 through the first connecting hole K1, the conductive structure 30, and the second connecting hole K2. In a specific implementation, the conductive structure 30 can be a conductive sealant, which can be made by doping conductive particles such as gold balls into the sealant. It has the functions of bonding and sealing the opposing substrate 20 and the array substrate 10, and electrically connecting the third part 303 and the fourth part 304. The conductive structure 30 can also be made of other materials, which are not limited here. Optionally, one end of the conductive structure 30 can be electrically connected to the third part 303, and the other end can be connected to the electrode layer of the opposing substrate. One end of the conductive structure 30 can be electrically connected to the fourth part, and the other end can be connected to the electrode layer of the opposing substrate. The electrical connection between the third part and the fourth part is achieved through the conductive layer of the opposing substrate, which is not limited here.

[0242] A fourth aspect of this disclosure also provides a display device, including the display panel provided in any of the foregoing embodiments.

[0243] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0244] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. An array substrate, wherein, The array substrate includes: A display area and a first non-display area, a second non-display area, and a third non-display area are arranged around the display area. The first non-display area and the third non-display area are arranged opposite to each other. The second non-display area connects the first non-display area and the third non-display area. The first non-display area includes a binding area. A frame start signal line; the frame start signal line is led out from the binding area, and the end of the frame start signal line extends along the second non-display area to the side of the second non-display area away from the first non-display area; A gate driving unit; the gate driving unit includes a first input module, the first input module including a first transistor; the end of the frame start signal line is electrically connected to at least one first transistor of the gate driving unit; At least one second transistor; the second transistor includes at least two terminals: a gate, a source, and a drain, and at least one terminal of the second transistor is electrically connected to a signal transmission segment preceding the end of the frame start signal line.

2. The array substrate as claimed in claim 1, wherein, The channel length of the second transistor is less than or equal to the channel length of the first transistor.

3. The array substrate as described in claim 1 or 2, wherein, The number of the second transistors is multiple, and the multiple second transistors are electrically connected to the signal transmission segment at different locations; the different locations include the first non-display area, and / or, the second non-display area, and / or, the third non-display area.

4. The array substrate as claimed in claim 3, wherein, Along the extension direction of the frame start signal line, a plurality of second transistors are alternately distributed on both sides of the signal transmission segment.

5. The array substrate according to any one of claims 1 to 4, wherein, The drain of the second transistor is electrically connected to the drain of the first transistor.

6. The array substrate according to any one of claims 1 to 5, wherein, The array substrate further includes a backup driving unit, which includes a second input module and a third transistor; the frame start signal line is also electrically connected to the third transistor.

7. The array substrate as claimed in claim 6, wherein, The frame start signal line is connected to the third transistor via a spare lead; The array substrate further includes at least one fourth transistor, which includes a gate, a source, and a drain, and at least one of the terminals of the fourth transistor is electrically connected to the spare lead.

8. The array substrate according to any one of claims 1 to 7, wherein, The array substrate further includes: Substrate; A first conductive layer is located on one side of the substrate; the signal transmission segment includes a first portion and a second portion located in the first conductive layer, the first portion and the second portion being adjacent to each other along the extension direction of the frame start signal line and disconnected from each other; The second conductive layer is located on the side of the first conductive layer away from the substrate; the second conductive layer includes a first bridging structure and a second bridging structure, the first bridging structure and the second bridging structure are arranged in pairs and are located at positions corresponding to the disconnection positions of the first portion and the second portion; the paired first bridging structure and the second bridging structure are arranged side by side along the width direction of the frame start signal line, and the width direction is perpendicular to the extension direction of the frame start signal line; The first part and the second part are electrically connected through at least one of the first bridging structure and the second bridging structure.

9. The array substrate as claimed in claim 8, wherein, The array substrate further includes a third conductive layer, which is located on the side of the second conductive layer away from the substrate; the third conductive layer includes a third bridging structure and a fourth bridging structure; The number of frame start signal lines in the array substrate is greater than or equal to one; for at least one frame start signal line, the first part is electrically connected to the first bridging structure through the third bridging structure, and the second part is electrically connected to the first bridging structure through the fourth bridging structure.

10. The array substrate as claimed in claim 9, wherein, The array substrate further includes: A first insulating layer is located between the first conductive layer and the second conductive layer; The second insulating layer is located between the second conductive layer and the third conductive layer; For at least one frame start signal line, the array substrate has a first via penetrating the first insulating layer and the second insulating layer and exposing the first portion, and a second via penetrating the second insulating layer and exposing the first bridging structure. The third bridging structure is electrically connected to the first portion through the first via and to the first bridging structure through the second via. The array substrate also has a third via penetrating the first insulating layer and the second insulating layer and exposing the second portion, and a fourth via penetrating the second insulating layer and exposing the first bridging structure. The fourth bridging structure is electrically connected to the second portion through the third via and to the first bridging structure through the fourth via. The orthographic projection of the second via on the substrate and the orthographic projection of the first via on the substrate are arranged in multiple rows and columns, and the second via and the first via are alternately arranged along the row direction and / or column direction; The orthographic projection of the fourth via on the substrate and the orthographic projection of the third via on the substrate are arranged in multiple rows and columns, and the fourth via and the third via are alternately arranged along the row direction and / or column direction.

11. The array substrate according to any one of claims 8 to 10, wherein, The array substrate further includes: A first insulating layer is located between the first conductive layer and the second conductive layer; The number of frame start signal lines in the array substrate is greater than or equal to one; for at least one frame start signal line, the second bridging structure is directly electrically connected to the first part through a fifth via penetrating the first insulating layer, and the second bridging structure is directly electrically connected to the second part through a sixth via penetrating the first insulating layer.

12. The array substrate according to any one of claims 1 to 11, wherein, The array substrate further includes: Substrate; A first conductive layer is located on one side of the substrate; the signal transmission segment further includes a third portion and a fourth portion located in the first conductive layer, the third portion and the fourth portion being adjacent to each other along the extension direction of the signal transmission segment and disconnected from each other; The top film layer is located on the side of the first conductive layer opposite to the substrate, and among all the film layers located on the side of the first conductive layer opposite to the substrate, the top film layer is the farthest from the first conductive layer; The array substrate has a first connection hole and a second connection hole. Both the first connection hole and the second connection hole penetrate the top film layer and other film layers between the top film layer and the first conductive layer. The first connection hole exposes the third part, and the second connection hole exposes the fourth part.

13. The array substrate according to any one of claims 1 to 12, wherein, The bonding area includes bonding pads, and the signal transmission segment is led out from the bonding pads; the bonding pads include multiple bonding leads extending along a first direction and arranged along a second direction; the first direction is the extension direction of the frame start signal line, and the second direction is perpendicular to the first direction. The bonding pads also include a parallel structure, through which at least a portion of the multiple bonding leads are interconnected.

14. The array substrate according to any one of claims 1 to 13, wherein, The array substrate further includes a first test terminal and a first test lead; the first test terminal is electrically connected to the frame start signal line through the first test lead. The array substrate further includes: Substrate; A first conductive layer is located on one side of the substrate. The first test terminal includes a fifth portion and a sixth portion located on the first conductive layer. The fifth portion and the sixth portion are disconnected from each other, and the first test lead is connected to the sixth portion. An insulating layer is located on the side of the first conductive layer opposite to the substrate; the insulating layer has a plurality of seventh vias exposing the fifth portion and eighth vias exposing the sixth portion; A third conductive layer is located on the side of the first conductive layer facing away from the substrate; the third conductive layer includes at least one fifth bridging structure, which is electrically connected to the fifth portion and the sixth portion through the seventh via and the eighth via, respectively.

15. The array substrate as claimed in claim 14, wherein, The array substrate further includes a second conductive layer located between the first conductive layer and the second conductive layer; the insulating layer includes a first insulating layer and a second insulating layer, wherein the first insulating layer is located between the first conductive layer and the second conductive layer, and the second insulating layer is located between the second conductive layer and the third conductive layer. The second conductive layer includes a first electrostatic discharge structure, the orthographic projection of the first electrostatic discharge structure on the plane of the substrate is located between the orthographic projections of the fifth part on the plane of the substrate and the orthographic projection of the sixth part on the plane of the substrate, and the orthographic projection of the first electrostatic discharge structure on the plane of the substrate at least partially overlaps with the orthographic projection of the fifth bridging structure on the plane of the substrate.

16. The array substrate as claimed in claim 14 or 15, wherein, The array substrate further includes a second test terminal and a second test lead; the first test lead is electrically connected to the second test terminal, the second test terminal is electrically connected to the second test lead, and the second test lead is electrically connected to the frame start signal line; The second test terminal includes a seventh part and an eighth part located in the first conductive layer. The seventh part and the eighth part are disconnected from each other, and the first test lead is connected to the seventh part and the second test lead is connected to the eighth part. The insulating layer also has a plurality of ninth vias exposing the seventh part and tenth vias exposing the eighth part; The third conductive layer further includes at least one sixth bridging structure, which is electrically connected to the seventh part and the eighth part through the ninth via and the tenth via, respectively.

17. The array substrate as claimed in claim 16, wherein, The array substrate further includes a second conductive layer located between the first conductive layer and the second conductive layer; the insulating layer includes a first insulating layer and a second insulating layer, wherein the first insulating layer is located between the first conductive layer and the second conductive layer, and the second insulating layer is located between the second conductive layer and the third conductive layer. The second conductive layer includes a second electrostatic discharge structure. The orthographic projection of the second electrostatic discharge structure onto the plane of the substrate is located between the orthographic projections of the seventh portion and the eighth portion onto the plane of the substrate. Furthermore, the orthographic projection of the second electrostatic discharge structure onto the plane of the substrate intersects with the orthographic projection of the fifth bridging structure onto the plane of the substrate. The orthographic projections on the plane overlap at least partially.

18. An array substrate, wherein, The array substrate includes: A display area and a first non-display area, a second non-display area, and a third non-display area are arranged around the display area. The first non-display area and the third non-display area are arranged opposite to each other. The second non-display area connects the first non-display area and the third non-display area. The first non-display area includes a binding area. A frame start signal line; the frame start signal line is led out from the binding area, and the end of the frame start signal line extends along the second non-display area to the side of the second non-display area away from the first non-display area; Gate driving unit; the frame start signal line is electrically connected to at least one of the gate driving units; The array substrate further includes: Substrate; A first conductive layer is located on one side of the substrate; the frame start signal line includes a first portion and a second portion located in the first conductive layer, the first portion and the second portion being adjacent to each other along the extension direction of the frame start signal line and disconnected from each other; The second conductive layer is located on the side of the first conductive layer away from the substrate; the second conductive layer includes a first bridging structure and a second bridging structure, the first bridging structure and the second bridging structure are arranged in pairs and are located at positions corresponding to the disconnection positions of the first portion and the second portion; the paired first bridging structure and the second bridging structure are arranged side by side along the width direction of the frame start signal line, and the width direction is perpendicular to the extension direction of the frame start signal line; The first part and the second part are electrically connected through at least one of the first bridging structure and the second bridging structure.

19. The array substrate as claimed in claim 18, wherein, The frame start signal line further includes a third part and a fourth part located in the first conductive layer, wherein the third part and the fourth part are arranged adjacent to each other along the extension direction of the frame start signal line and are disconnected from each other; The array substrate further includes: The top film layer is located on the side of the first conductive layer opposite to the substrate, and is located in the first conductive layer. Of all the films on the side of a conductive layer that faces away from the substrate, the top film is the furthest from the first conductive layer; The array substrate has a first connection hole and a second connection hole. Both the first connection hole and the second connection hole penetrate the top film layer and other film layers between the top film layer and the first conductive layer. The first connection hole exposes the third part, and the second connection hole exposes the fourth part.

20. The array substrate as claimed in claim 18 or 19, wherein, The bonding area includes bonding pads, and the frame start signal line is led out from the bonding pads; the bonding pads include multiple bonding leads extending along a first direction and arranged along a second direction; the first direction is the extension direction of the frame start signal line, and the second direction is perpendicular to the first direction. The bonding pads also include a parallel structure, through which at least a portion of the multiple bonding leads are interconnected.

21. The array substrate according to any one of claims 18 to 20, wherein, The array substrate further includes a first test terminal and a first test lead; the first test terminal is electrically connected to the frame start signal line through the first test lead. The first test terminal includes a fifth portion and a sixth portion located in the first conductive layer, the fifth portion and the sixth portion being disconnected from each other, and the first test lead being connected to the sixth portion; The array substrate further includes: The third conductive layer is located on the side of the second conductive layer that is away from the substrate; A first insulating layer is located between the first conductive layer and the second conductive layer; The second insulating layer is located between the second conductive layer and the third conductive layer; The array substrate has multiple seventh vias that penetrate the first insulating layer and the second insulating layer and expose the fifth portion, and multiple eighth vias that penetrate the first insulating layer and the second insulating layer and expose the sixth portion; the third conductive layer includes at least one fifth bridging structure, which is electrically connected to the fifth portion and the sixth portion through the seventh vias and the eighth vias, respectively.

22. The array substrate as claimed in claim 21, wherein, The array substrate further includes a second test terminal and a second test lead; the first test lead is electrically connected to the second test terminal, the second test terminal is electrically connected to the second test lead, and the second test lead is electrically connected to the frame start signal line; The second test terminal includes a seventh part and an eighth part located in the first conductive layer. The seventh part and the eighth part are disconnected from each other, and the first test lead is connected to the seventh part and the second test lead is connected to the eighth part. The array substrate also has a plurality of ninth vias that penetrate the first insulating layer and the second insulating layer and expose the seventh portion, and a plurality of tenth vias that penetrate the first insulating layer and the second insulating layer and expose the eighth portion; The third conductive layer further includes at least one sixth bridging structure, which is electrically connected to the seventh part and the eighth part through the ninth via and the tenth via, respectively.

23. A display panel, wherein, Includes the array substrate as described in any one of claims 1 to 22.

24. The display panel as claimed in claim 23, wherein, The array substrate includes: Substrate; A first conductive layer is located on one side of the substrate; the signal transmission segment further includes a third part and a fourth part located in the first conductive layer, the third part and the fourth part being arranged adjacent to each other along the extension direction of the frame start signal line and disconnected from each other; The top film layer is located on the side of the first conductive layer opposite to the substrate, and among all the film layers located on the side of the first conductive layer opposite to the substrate, the top film layer is the farthest from the first conductive layer; The array substrate has a first connection hole and a second connection hole. Both the first connection hole and the second connection hole penetrate the top film layer and other film layers between the top film layer and the first conductive layer. The first connection hole exposes the third part, and the second connection hole exposes the fourth part. The display panel also includes: An opposing substrate is disposed opposite to the array substrate; A liquid crystal layer is located between the opposing substrate and the array substrate; A conductive structure is located between the opposing substrate and the array substrate; the third part is electrically connected to the fourth part through the first connecting hole, the conductive structure, and the second connecting hole.

25. A display device, wherein, Includes the display panel as described in claim 23 or 24.

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