Address space support for point-to-point cache coherency

Abstract

A system comprising: a plurality of cores, wherein each core is associated with a cache; a cache coherency subsystem comprising a data processing apparatus configured to perform operations comprising: receiving an address from a first core of the plurality of cores; determining that a reservation field of the address specifies a core pair of a region of shared memory in the plurality of cores; and in response, performing a reduced cache coherency procedure between the core pair of the plurality of cores.

Description

Background Technology

[0001] This specification relates to systems having integrated circuit devices.

[0002] A cache is a device that stores data retrieved from or written to memory for one or more different hardware devices in a system. The hardware devices can be different components integrated into a system-on-a-chip (SoC) or a system comprising several cores on different chips. In this specification, the device that provides read and write requests through the cache will be referred to as a client device.

[0003] A multiprocessor system can have multiple processing units, each with its own cache. A multiprocessor system can have multiple copies of any shared data—that is, multiple copies in shared memory and multiple copies in memory used by each cache. To maintain cache coherence, when one copy of data is modified, other copies in other caches sharing the same data must also be modified or invalidated.

[0004] Cache coherence systems maintain data consistency across caches in a multiprocessor system by communicating with various caches that may have access to specific data segments as data is updated. However, performing cache coherence processes can be expensive in several ways. For example, it can introduce more complex hardware, higher latency, and wasteful operations, such as when a cache does not have access to the specific data segment that is the object of the coherence process. Summary of the Invention

[0005] This specification describes techniques for modifying addresses in a manner that triggers a reduced cache coherence process in the cache coherence system. For example, when the data to be updated is shared only between two of multiple cores, this allows the cache coherence system to communicate only with the caches associated with those two cores. Additionally, when the data to be updated is accessed only by a single core, this allows the cache coherence system to communicate only with the cache associated with that core.

[0006] According to the first method, a system is provided, comprising: a plurality of cores, each core associated with a cache; a cache coherence subsystem including a data processing device configured to perform operations including: receiving an address from a first core among the plurality of cores; determining a core pair whose reserved field of the address specifies a region of shared memory among the plurality of cores; and, in response, performing a reduced cache coherence process between the core pair among the plurality of cores.

[0007] In some implementations, the operation also includes: receiving a second address from one of the multiple cores; determining that the reserved field of the address does not specify a core pair; and, in response, performing a full cache coherence process across the multiple cores.

[0008] In some implementations, a reduced cache coherence process checks cache coherence on fewer cores compared to a full cache coherence process.

[0009] In some implementations, one or more cores are configured to execute instructions to implement an operating system, and the operating system is configured to perform operations including: mapping between a maintenance program, a core on which the program executes, and a corresponding region of memory shared by the program; and filling reserved fields of addresses with core identifiers whenever a physical address must be computed for use by a program identified in the mapping as running on one or two cores.

[0010] In some implementations, the operation also includes: receiving a request to move the program from the first and second cores to the third and fourth cores; and recalculating the reserved field address using the core identifier associated with the third and fourth cores.

[0011] In some implementations, the address is a physical address, and the reserved fields of the address occupy fewer bits than all the bits of the physical address.

[0012] In some implementations, each program shares one or more regions of memory with one or more other programs.

[0013] In some implementations, cores in a multi-core architecture are divided into core pairs, where each core shares one or more regions of memory with its paired core.

[0014] In some implementations, this operation also includes assigning shared memory programs to each core pair in the core pair.

[0015] In some implementations, the operation further includes: receiving a second address from one of the multiple cores; determining a core cluster pair whose reserved field of the address specifies a region of shared memory in the multiple cores; and, in response, performing a reduced cache coherence process among the cores in the core cluster pair of the multiple cores.

[0016] In some implementations, the operation also includes: receiving a second address from one of the multiple cores; determining that the reserved field of the address specifies a single core; and, in response, bypassing the cache coherence process for the multiple cores.

[0017] Specific embodiments of the subject matter described in this specification can be implemented to achieve one or more of the following advantages. Cache coherence can be a complex process requiring significant circuitry and latency. Cache coherence systems can reduce coherence traffic for multiprocessor systems. In a multiprocessor system with multiple cores, when data is not shared across all cores, the system can use an address with a reserved field as an indication that the cache coherence system should only perform a reduced cache coherence process. Compared to a full cache coherence process, a reduced cache coherence process checks cache coherence on fewer cores and therefore executes faster, requires less complex operations, and involves less inter-core communication traffic.

[0018] For example, to specify which cores to check cache coherence against during a cache coherence process, a conventional cache coherence system might broadcast every data access to all caches. This approach has scalability issues because it has N^2 complexity. The technique described in this specification also avoids the problems of another conventional solution, which is to maintain a directory storing the cache in which each data element is stored. This can become very complex, may require additional silicon area, and may suffer from latency. In contrast, the cache coherence system described in this specification uses reserved space in addresses to map regions of memory to specify the core against which a scaled cache coherence process should be performed.

[0019] Details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of this subject matter will become apparent from the description, drawings, and claims. Attached Figure Description

[0020] Figure 1 This is a diagram of the example system.

[0021] Figure 2 This is a diagram illustrating an example address with reserved fields for a specified core pair.

[0022] Figure 3 This is a flowchart illustrating an example procedure used to determine the type of cache coherence process to be performed.

[0023] Figure 4 This is a flowchart illustrating an example procedure for filling addresses based on memory requests.

[0024] Similar reference numerals and names in the various figures indicate similar elements. Detailed Implementation

[0025] Figure 1This is a diagram of example system 100. System 100 includes a system-on-chip (SOC) 102 communicatively coupled to a memory device 118. SOC 102 has a plurality of client devices 110a-n, each having an associated local cache 112a-n, and a cache coherence subsystem 114. Each local cache 112a-n serves memory requests from its associated client devices 110a-n. Cache coherence subsystem 114 is a communication subsystem that performs a cache coherence process whenever data in any local cache 112a-n is updated or data is requested from the cache. The techniques described in this specification can also be used in systems with additional cache layers.

[0026] To improve the performance of maintaining a consistent cache, system 100 can modify some addresses by triggering a reduced cache coherence process by cache coherence subsystem 114. For example, cache coherence subsystem 114 can use reserved spaces in addresses to identify the client device for which a reduced cache coherence process should be performed. For instance, when the data to be updated is shared only between two of the multiple client devices 112a-n, the system can indicate this by filling a reserved field in the address used by the client device, which signals the cache coherence system to communicate only with the caches associated with those two client devices when performing cache coherence maintenance. Additionally, when the data to be updated is accessed only by a single client device, this allows the cache coherence system to communicate only with the cache associated with that client device or bypass communication with any cache. These mechanisms improve system performance because a reduced cache coherence process is significantly cheaper in terms of time and resources compared to a full cache coherence process considering a larger subset or all caches in the system.

[0027] SOC 102 is an example of a device that can be installed on or integrated into any suitable computing device, which may be referred to as a host device. For example, SOC 102 can be installed on a mobile host device, such as a smartphone, smartwatch, or other wearable computing device, tablet computer, or laptop computer, to name just a few.

[0028] SOC 102 has multiple client devices 110a-n. Each client device 110a-n may have one or more cores, which are implemented as any suitable module, device, or functional component configured to read or store data in a memory device. For example, a client device may be a CPU, a DMA controller, or a lower-level component of the SOC itself.

[0029] System 100 may include an operating system configured to modify addresses in a manner that indicates regions of shared memory shared by one or more client devices. Client devices 110a-n may be configured to execute instructions to implement the operating system. The operating system may be configured to maintain a mapping between programs or client devices 110an-n of the respective regions of shared memory, for example, maintaining a mapping between regions accessible to one or more client devices for each region of memory. Shared regions of memory may be distinguished from each other, for example, using memory region identifiers. A memory region identifier may be an abstraction of contiguous data that can be mapped to a region of address space. A memory region identifier may represent data in a memory storage device such as memory storage device 118.

[0030] The operating system can be configured to populate page tables with addresses that have reserved fields set using kernel identifiers. A kernel identifier can be a set of values ​​used to identify one or more devices using a particular cache. For example, each client device 110a-n may have multiple compute cores. However, if a particular client device uses only one local cache, a single kernel identifier can be used for that client device. Alternatively or additionally, each client device may have a single compute core, in which case each client device may have a separate and distinct kernel identifier. In cases where a client device has multiple cores that use multiple caches respectively, a single client device may be associated with multiple kernel identifiers to distinguish between cores using multiple caches respectively. Reserved fields for addresses may be allowed within otherwise unused bit fields within the address.

[0031] The cache coherence subsystem 114 is the communication subsystem of the SOC 102 that ensures consistency of all data stored in local caches 112a-n. In other words, the cache coherence subsystem 114 strives to give each cache the same view of the value in memory 118. The value in the cache may differ from the corresponding value in memory—for example, if a cached write has not yet been flushed—but the cache itself should have the same view of such unflushed values. Whenever data is updated in a local cache 112a-n, the cache coherence subsystem can perform a cache coherence process to ensure that any other cache accessing that data does not contain a different version of that data. The cache coherence subsystem 114 includes communication paths that allow client devices 110a-n to communicate with each other and make requests to read and write data using memory device 140. The cache coherence subsystem 114 may include any suitable combination of communication hardware, such as a bus or dedicated interconnect circuitry system.

[0032] As described above, programs running on client devices 112a-n or client devices 112a-n themselves can share regions of memory. For example, two processes running on different cores can read from and write to a shared region of memory. The cache coherence subsystem 118 can be configured to receive an address from a first client device and determine whether a reserved field of the address specifies a client device pair or subset of client devices sharing a region of memory that is not shared with any other client device. If the reserved field of the address specifies a client device pair, the cache coherence subsystem 118 can perform a reduced cache coherence process between the client device pair without communicating with any other client devices in the SOC 102. Compared to a full cache coherence process that checks cache coherence in all local caches 112-an, the reduced cache coherence process checks cache coherence on fewer client devices.

[0033] When the operating system has already populated the reserved address field to specify a client device pair, the cache coherence subsystem 118 can perform a reduced cache coherence process that checks cache coherence only for that client device pair. The reserved field can also specify a client device. When the reserved field specifies a client device, the cache coherence subsystem bypasses the execution of the cache coherence process.

[0034] When the reserved field does not specify a pair of client devices or a single client device, the cache consistency subsystem 118 can perform a full cache consistency process that checks cache consistency for all client devices.

[0035] The address can be a physical address, and reserved fields of the address can occupy fewer bits than the physical address. For example, if the reserved field is not filled, the address can be read as 0x000.....ppppp___. Using the same format, the reserved field can be identified as being marked by filling the address with 0x0jk0.....ppppp___. j Client devices and those marked as k The client device. When this reserved field identifies, for example, the client device. j When dealing with a single client device, this address is read as 0x0jj0.....ppppp___.

[0036] This reserved field can also identify client device clusters. In some examples, the reserved address field specifies a pair of client device clusters representing regions of shared memory across multiple cores. The cache coherence subsystem 118 can perform a reduced cache coherence process among client devices in a core cluster pair without checking cache coherence for client devices that are not part of any cluster.

[0037] Caches 110a-n are located in the data path between client devices 112a-n and memory controller 130. Memory controller 130 can handle requests to and from memory device 140.

[0038] Figure 2 This is a diagram illustrating an example physical address 200 with reserved fields for a specified core pair. The address is the address space 202 of a 64-bit system. Address space 202 includes reserved fields for a first core identifier 204 and a second core identifier 206 for regions of shared memory, as well as fields for physical pages 208 and offset bits 210.

[0039] The field used for physical page 208 identifies a page shared only between the two cores, and the reserved field used for the first core identifier 204 can identify one core, while the second core identifier 206 can identify the second core. The reserved field for the address can have fewer bits than all the bits of the physical address. For example, if the reserved field is not filled, the address can be read as 0x000.....ppppp___. Using the same format, the reserved field can be identified by filling the address bits with 0x0jk0.....ppppp___. j The core and marked as k The core, of which the first core identifier 204 is composed of j Filled, and the second core identifier 206 is... k Fill. When only with, for example, the core. j When reading a core shared page, the address is 0x0jj0…..ppppp___, and the two core identifiers are... j filling.

[0040] Figure 3 This is a flowchart illustrating an example procedure for determining the type of cache coherence process to be performed. Example procedure 300 can be performed by a component of SOC 102—specifically, by cache coherence subsystem 114.

[0041] The cache coherence subsystem 114 receives an address from a first core among multiple cores (step 310). The core may be the core of a multiprocessor system, each core having an associated local cache.

[0042] The cache coherence subsystem 114 determines whether the reserved field of the address specifies a core pair of regions of shared memory across multiple cores (step 320). The address can be a physical address, where the reserved field of the address occupies fewer bits than the physical address, for example... Figure 2 Example address 200.

[0043] If the reserved field of the address specifies a core pair of regions in shared memory, the cache coherence subsystem 114 performs a reduced cache coherence process between the core pair (step 330). Compared to a full cache coherence process, the reduced cache coherence process checks cache coherence on fewer cores—for example, the two cores in a core pair.

[0044] If the reserved field of the address does not specify a core pair of the shared memory region, the cache coherence subsystem 114 performs a full cache coherence process (step 330) that checks cache coherence on all cores across the multiple cores.

[0045] The reserved field for an address can also specify a single core. In some implementations, the cache coherence subsystem can determine that the reserved field for an address specifies a single core and bypass the cache coherence process because the data does not need to be updated for other cores.

[0046] The operating system can delegate shared memory regions to which cores. Each program or core can share one or more regions of memory with one or more other programs or cores. In some implementations, each core can share memory region identifiers with a subset extracted from each of the other cores in the system. The operating system can select which cores to assign shared memory to based on which tasks are assigned to a particular core—e.g., based on task requirements.

[0047] Alternatively, the operating system can divide a core from multiple cores into core pairs. In some implementations, each core shares one or more regions of memory only with its paired core.

[0048] The reserved address field can also specify the core cluster. In some implementations, the reserved address field can specify a core cluster pair across multiple cores that share memory regions. For example, a cluster M It can represent the core. j and k And cluster N It can represent the core. h and iThe cache consistency subsystem 114 can perform a scaled-down cache consistency process between cores in a core cluster pair. For example, the cache consistency subsystem can target cores... j, k, h and i Check cache consistency.

[0049] Figure 4 This is a flowchart illustrating an example procedure for populating bit fields of an address based on a configuration of shared memory between programs running on the kernel. Example procedure 400 can be executed by the operating system.

[0050] The system maintains a mapping between programs for a shared memory region (step 410). Programs may share a memory region for various reasons. For example, a multi-process application may have multiple processes that read from and write to the same region of memory. As another example, a producer process and a consumer process may use a shared region of memory as a buffer between the two processes.

[0051] For example, a shared region of memory can be identified by a memory region identifier. A memory region identifier can be an abstraction of one or more regions of memory that are mapped into the address space. A memory region identifier can represent a portion of a memory storage device, such as memory storage device 118.

[0052] The system receives a request to update the program's page table (step 420). Updating the page table can be for various reasons, such as the first time memory is allocated to the program, or due to a page fault.

[0053] Typically, updating a page table requires implicitly or explicitly calculating the physical address from the virtual address belonging to the program. The mapping between physical addresses or pages and virtual addresses or pages can then be added to the page table. The operating system uses page tables to store the mapping from virtual addresses to physical addresses, where each mapping is a page table entry.

[0054] The system determines, in the mapping of programs in the shared memory region, whether the program is identified as running on one or two cores (step 430). If so, the system can modify the physical address in the page table by writing the core identifier into the reserved space of the physical address (branch to step 440). This modification then causes the cache coherent system to perform a reduced cache coherent process whenever those physical addresses are encountered during execution. Similar modifications can be made to other architectural structures, such as those maintaining address translation in one or more translation back buffers.

[0055] In some examples, the operating system may choose to maintain mappings of kernel pairs rather than mappings of programs. Each kernel may share one or more regions of memory with its paired kernel. The system may assign programs in shared memory to each kernel pair. In other examples, the operating system may choose to track and map shared memory regions individually. Each of a plurality of kernels may share one or more regions of memory with each of the other kernels in the plurality of kernels.

[0056] A program can use one or more memory region identifiers shared between more than two cores—for example, between five cores or between seven cores. When a program uses memory region identifiers shared with more than a specified number of cores—for example, two—the system does not modify the physical address, and the cache coherence subsystem performs a full cache coherence process. Conversely, a program can also use one or more memory region identifiers shared only between one core or core pair. When a program uses memory region identifiers shared with a specified number of cores—for example, two—the system does modify the physical address, and the cache coherence subsystem performs a full cache coherence process.

[0057] If the program is not identified in the mapping as running on one or two cores, the system can keep the reserved fields of the address unchanged (branch to step 440).

[0058] When generating a physical address from a virtual address, the system can determine whether the virtual address is part of a memory region identifier known to be accessible to only one or two cores (or a core group). If the virtual address is part of a memory region identifier known to be accessible to only one or two cores, the operating system can write the core identifier into a reserved field of the physical address in the page table. For example, a reserved field can be identified by filling the physical address bits in the page table with 0x0jk0.....ppppp___. j The core and marked as k The core. Other bit encodings are possible, some of which can reduce the number of bits required for encoding, perhaps through cooperation from the hardware. For example, as few as 1 bit can be used if the hardware applies a reduced coherence protocol only between core pairs with numbers that differ only in the least significant bit, and the operating system sets the bit only for programs that use memory only on those core pairs.

[0059] After the page tables are populated with entries mapping virtual addresses to physical addresses (including physical addresses with kernel identifiers), the system can receive requests for kernel access to specific addresses in memory. This can trigger a cache coherence process. When memory is accessed in a page that has a kernel identifier in the reserved field of the physical address, the cache coherence hardware will use a reduced cache coherence process.

[0060] The operating system can move a program from one core to another. When moving a program to a different core, the operating system can recalculate the corresponding physical addresses in the page table. Alternatively, the operating system can move programs running on the first and second cores to the second and third cores. In some implementations, the system can populate reserved fields in the physical address table with corresponding identifiers for the second and third cores. For example, the third core could be marked as... h The core. The first and second cores can be labeled as... j and k The system can change the address from 0x0jk0.....ppppp___ to 0x0hk0.....ppppp___.

[0061] The system can use an N-to-N crossbar switch (e.g., a butterfly circuit) to transfer cached data between any pair of cores. When using an N-to-N crossbar switch, some memory regions can be shared between cores 4 and 5, and other regions can be shared between cores 4 and 17. Each page in a memory region will have its own... j and k The set of bits, therefore, the N-to-N crossbar allows process A to have a memory region identifier shared with process B, and another memory region identifier shared with process C, and the crossbar will support AB link and BC link as needed.

[0062] In some examples, point-to-point links can exist between cores 0 and 1, 1 and 2, 2 and 3, 3 and 4, etc., which can support data pipelines, such as those that may occur in media-intensive products. Instead of using N-to-N crossbar switches for point-to-point traffic between different cores, system 100 can use simpler point-to-point connections between cores 0 and 1, 2 and 3, etc., and the operating system can assign shared memory programs to those appropriately paired cores.

[0063] In computer systems where most areas of memory are shared by programs running on more than two cores, there may not be enough bits to encode the cores sharing that area. If this is expected, the system can link small clusters of cores using a relatively simple (e.g., listening) coherence circuitry system, andj and k The identifier then refers to the cluster number rather than the individual core number. Clustering cores can provide more CPU power to each set of programs accessing memory segments.

[0064] This specification uses the term "configured" to combine system and computer program components. For a system of one or more computers to be configured to perform a specific operation or action, this means that the system has software, firmware, hardware, or a combination thereof installed thereon that causes the system to perform those operations or actions in operation. For one or more computer programs configured to perform a specific operation or action, this means that the one or more programs include instructions that, when executed by a data processing device, cause the device to perform that operation or action.

[0065] Embodiments of the subject matter and functional operation described in this specification may be implemented in digital electronic circuit systems, in tangibly embodied computer software or firmware, in computer hardware (including the structures disclosed in this specification and their equivalents), or in combinations thereof. Embodiments of the subject matter described in this specification may be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-transitory storage medium for execution by a data processing device or for controlling the operation of a data processing device. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination thereof. Alternatively or additionally, program instructions may be encoded on artificially generated propagation signals—e.g., machine-generated electrical, optical, or electromagnetic signals—to generate artificially generated propagation signals to encode information for transmission to a suitable receiver device for execution by the data processing device.

[0066] The term "data processing device" refers to data processing hardware and includes all kinds of devices, apparatuses, and machines for processing data, such as programmable processors, computers, or multiple processors or computers. The device may also be or further include special-purpose logic circuit systems, such as FPGAs (Field-Programmable Gate Arrays) or ASICs (Application-Specific Integrated Circuits). In addition to hardware, the device may optionally include code that creates an execution environment for computer programs, such as code constituting processor firmware, protocol stacks, database management systems, operating systems, or combinations thereof.

[0067] A computer program, which may also be referred to or described as a program, software, software application, app, module, software module, script, or code, can be written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages); and it can be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A program may, but does not need to, correspond to a file in a file system. A program may be stored as a part of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinating files (e.g., a file storing one or more modules, subroutines, or code portions). A computer program can be deployed to execute on a single computer or on multiple computers located at a site or distributed across multiple sites and interconnected via a data communication network.

[0068] The processes and logic flows described in this specification can be executed by one or more programmable computers, which execute one or more computer programs to perform functions by manipulating input data and generating outputs. The processes and logic flows can also be executed by a dedicated logic circuit system (e.g., an FPGA or ASIC) or by a combination of a dedicated logic circuit system and one or more programmable computers.

[0069] A computer suitable for executing computer programs can be based on a general-purpose or special-purpose microprocessor, or both, or any other type of central processing unit. Typically, the central processing unit receives instructions and data from read-only memory or random access memory, or both. The basic components of a computer are the central processing unit for executing instructions and one or more memory devices for storing instructions and data. The central processing unit and memory may be supplemented by or incorporated into a special-purpose logic circuit system. Typically, a computer will also include one or more mass storage devices for storing data, such as magnetic disks, magneto-optical disks, or optical disks, or operatively coupled to receive data from or transfer data to or from them, or both. However, a computer does not necessarily have to have such devices. Furthermore, a computer can be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device such as a universal serial bus (USB) flash drive, to name a few.

[0070] Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices), magnetic disks (e.g., internal hard disks or removable disks), magneto-optical disks, and CD-ROM and DVD-ROM disks.

[0071] In addition to the embodiments described above, the following embodiments are also innovative: Example 1 is a system comprising: Multiple cores, each associated with a cache; A cache consistency subsystem, comprising a data processing device configured to perform operations including: Receive the address from the first core among the plurality of cores; The reserved field of the address specifies the core pair that defines the shared memory region among the plurality of cores; and In response, a reduced cache coherence process is performed between the core pairs in the plurality of cores.

[0072] Example 2 is the system as described in Example 1, wherein the operation further includes: Receive the second address from one of the plurality of cores; It was determined that the reserved field of the address did not specify a core pair; and In response, a full cache coherence process is performed across the multiple cores.

[0073] Example 3 is a system as described in Example 2, wherein the reduced cache coherence process checks cache coherence on fewer cores compared to the full cache coherence process.

[0074] Example 4 is a system as described in any one of Examples 1 to 3, wherein one or more of the cores are configured to execute instructions to implement an operating system, and wherein the operating system is configured to perform operations including: The mapping between the maintenance program, the core on which the program executes, and the corresponding shared regions of memory of the program; and Whenever a physical address must be calculated for use by a program identified in the mapping as running on one or two cores, the reserved field of the address is populated with the core identifier.

[0075] Example 5 is the system as described in Example 4, wherein the operation further includes: Receive requests to move the program from the first and second cores to the third and fourth cores; and The reserved field addresses are recalculated using the core identifiers associated with the third and fourth cores.

[0076] Example 6 is a system as described in any one of Examples 1 to 5, wherein the address is a physical address, and the reserved field of the address occupies fewer bits than all bits of the physical address.

[0077] Example 7 is a system as described in Example 4, wherein each program shares one or more regions of memory with one or more other programs.

[0078] Example 8 is a system as described in Example 4, wherein the cores of the plurality of cores are divided into core pairs, wherein each core shares one or more regions of memory with its paired core.

[0079] Example 9 is a system as described in Example 8, wherein the operation further includes: assigning a program in the shared memory to each of the core pairs.

[0080] Example 10 is a system as described in any one of Examples 1 to 9, wherein the operation further includes: Receive the second address from one of the plurality of cores; The reserved field of the address specifies the core cluster pair that defines the shared memory region among the plurality of cores; and In response, a reduced cache coherence process is performed among the cores in the core cluster pair of the plurality of cores.

[0081] Example 11 is a system as described in any one of Examples 1 to 10, wherein the operation further includes: Receive the second address from one of the plurality of cores; The reserved field at the address specifies a single core; and In response, the cache coherency process for the multiple cores is bypassed.

[0082] Example 12 is a method comprising performing the operations described in any one of Examples 1 to 11.

[0083] Example 13 is a computer storage medium encoded with instructions that, when executed by a data processing device, are operable to cause the data processing device to perform the operations claimed in any one of claims 1 to 11.

[0084] While this specification contains numerous details of specific implementations, these details should not be construed as limiting the scope of any invention or the scope that may be claimed, but rather as descriptions of features that may be specific to particular embodiments of a particular invention. Certain features described in the context of individual embodiments in this specification may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed in this way, in some cases one or more features from that combination may be removed from the claimed combination, and the claimed combination may involve sub-combinations or variations thereof.

[0085] Similarly, although operations are depicted in the accompanying drawings and described in a specific order in the claims, this should not be construed as requiring such operations to be performed in the specific order shown or in a sequential order, or requiring all shown operations to be performed to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0086] Specific embodiments of this subject matter have been described. Other embodiments are within the scope of the appended claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired result. As an example, the processes depicted in the drawings do not necessarily require a specific order or sequence shown to achieve the desired result. In some cases, multitasking and parallel processing can be advantageous.

Claims

1. A system comprising: Multiple cores, each associated with a cache; A cache consistency subsystem, comprising a data processing device configured to perform operations including: Receive the address from the first core among the plurality of cores; The reserved field of the address specifies the core pair that defines the shared memory region among the plurality of cores; and In response, a reduced cache coherence process is performed between the core pairs in the plurality of cores.

2. The system of claim 1, wherein the operation further comprises: Receive the second address from one of the plurality of cores; It was determined that the reserved field of the address did not specify a core pair; as well as In response, a full cache coherence process is performed across the multiple cores.

3. The system of claim 2, wherein the reduced cache coherence process checks cache coherence on fewer cores compared to the full cache coherence process.

4. The system of any preceding claim, wherein one or more of the cores are configured to execute instructions to implement an operating system, and wherein the operating system is configured to perform operations, the operations comprising: A mapping between the maintenance program, the core on which the program executes, and the corresponding shared regions of memory of the program; as well as Whenever a physical address must be calculated for use by a program identified in the mapping as running on one or two cores, the reserved field of the address is populated with the core identifier.

5. The system of claim 4, wherein the operation further comprises: Receive requests to move the program from the first and second cores to the third and fourth cores; as well as The reserved field addresses are recalculated using the core identifiers associated with the third and fourth cores.

6. The system of any of the preceding claims, wherein the address is a physical address, and the reserved field of the address occupies fewer bits than all of the physical address.

7. The system of claim 4, wherein each program shares one or more regions of memory with one or more other programs.

8. The system of claim 4, wherein the cores of the plurality of cores are divided into core pairs, wherein each core shares one or more regions of memory with its paired core.

9. The system of claim 8, wherein the operation further comprises: The shared memory program is assigned to each of the core pairs.

10. The system as claimed in any of the preceding claims, wherein the operation further comprises: Receive the second address from one of the plurality of cores; The reserved field of the address specifies the core cluster pair that defines the region of shared memory in the plurality of cores; as well as In response, a reduced cache coherency process is performed among the cores in the core cluster pair of the multiple cores.

11. The system as claimed in any of the preceding claims, wherein the operation further comprises: Receive the second address from one of the plurality of cores; The reserved field at the address specifies a single core; as well as In response, the cache coherency process for the multiple cores is bypassed.

12. A method executed by a system comprising multiple cores, wherein each core is associated with a cache, the method comprising: Receive the address from the first core among the plurality of cores; The reserved field of the address specifies the core pair of the shared memory region among the plurality of cores; as well as In response, a reduced cache coherence process is performed between the core pairs in the plurality of cores.

13. The method of claim 12, further comprising: Receive the second address from one of the plurality of cores; It was determined that the reserved field of the address did not specify a core pair; as well as In response, a full cache coherence process is performed across the multiple cores.

14. The method of claim 13, wherein the reduced cache coherence process checks cache coherence on fewer cores compared to the full cache coherence process.

15. The method of any one of claims 12 to 14, wherein one or more of the cores are configured to execute instructions to implement an operating system, and further comprises operations performed by the operating system, the operations including: A mapping between the maintenance program, the core on which the program executes, and the corresponding shared regions of memory of the program; as well as Whenever a physical address must be calculated for use by a program identified in the mapping as running on one or two cores, the reserved field of the address is populated with the core identifier.

16. The method of claim 15, further comprising: Receive requests to move the program from the first and second cores to the third and fourth cores; as well as The reserved field addresses are recalculated using the core identifiers associated with the third and fourth cores.

17. The method of any one of claims 12 to 16, wherein the address is a physical address, and the reserved field of the address occupies fewer bits than all bits of the physical address.

18. The method of claim 15, wherein each program shares one or more regions of memory with one or more other programs.

19. The method of claim 15, wherein the cores of the plurality of cores are divided into core pairs, wherein each core shares one or more regions of memory with its paired core.

20. The method of claim 19, further comprising: The shared memory program is assigned to each of the core pairs.

21. The method of any one of claims 12 to 20, further comprising: Receive the second address from one of the plurality of cores; The reserved field of the address specifies the core cluster pair that defines the region of shared memory in the plurality of cores; as well as In response, a reduced cache coherence process is performed among the cores in the core cluster pair of the plurality of cores.

22. The method of any one of claims 12 to 21, further comprising: Receive the second address from one of the plurality of cores; The reserved field at the address specifies a single core; as well as In response, the cache coherency process for the multiple cores is bypassed.

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