Cache line reservation hint information for conditional write instructions

Abstract

In response to the instruction decode circuit decoding the conditional write instruction, the processing circuit determines whether a predetermined condition is satisfied for a target cache line corresponding to a target address specified by the conditional write instruction. If the predetermined condition is satisfied for the target cache line, a write request is issued to update the target cache line. If the predetermined condition is not satisfied for the target cache line, a failure indication is returned. Depending on whether the instruction sequence specifies cache line retention hint information applicable to the conditional write instruction, the processing circuit selects whether to prevent a unique coherency state of the target cache line from being abandoned by a local cache associated with the processing circuit for a retention period following processing of the conditional write instruction. The unique coherency state includes a coherency state in which the processing circuit has exclusive rights to update the target cache line.

Description

background Technical Field

[0001] This technology relates to the field of data processing. Background Technology

[0002] Conditional write instructions can be used to conditionally execute a write to a memory location depending on whether a predetermined condition is met. If the predetermined condition is not met, the write does not occur. Such conditional write instructions can be used, for example, in read / modify / write sequences that may need to be executed atomically when multiple threads or processors are competing for access to a shared variable. The predetermined condition associated with a conditional write instruction allows detection of whether a second thread has updated the variable between the first thread's read of the variable and its write, and can therefore be used to determine whether the write should continue to update the variable. Conditional write instructions can be included within a program loop that repeatedly attempts to execute a sequence including the conditional write instruction until the conditional write instruction succeeds. Summary of the Invention

[0003] At least some examples of the present technology provide an apparatus comprising: An instruction decoding circuit, used to decode instruction sequences; and Processing circuitry, the processing circuitry being configured to perform data processing in response to the decoding of the instruction sequence by the instruction decoding circuitry; wherein: In response to the instruction decoding circuit decoding the conditional write instruction, the processing circuit is configured as follows: Determine whether the predetermined conditions are met for the target cache line corresponding to the target address specified by the condition write instruction; In response to determining that the predetermined condition is met for the target cache line, a write request is issued to update the target cache line; and In response to determining that the predetermined condition is not met for the target cache line, a failure indication is returned; and Depending on whether the instruction sequence specifies cache line retention hints applicable to the conditional write instruction, it is selected whether to prevent the unique consistency state of the target cache line from being abandoned by the local cache associated with the processing circuit during a retention period after the processing of the conditional write instruction. The unique consistency state includes a consistency state in which the processing circuit has exclusive rights to update the target cache line.

[0004] At least some examples of this technology provide a non-transitory computer-readable medium for storing computer-readable code for manufacturing an apparatus, the apparatus comprising: An instruction decoding circuit, used to decode instruction sequences; and Processing circuitry, the processing circuitry being configured to perform data processing in response to the decoding of the instruction sequence by the instruction decoding circuitry; wherein: In response to the instruction decoding circuit decoding the conditional write instruction, the processing circuit is configured as follows: Determine whether the predetermined conditions are met for the target cache line corresponding to the target address specified by the condition write instruction; In response to determining that the predetermined condition is met for the target cache line, a write request is issued to update the target cache line; and In response to determining that the predetermined condition is not met for the target cache line, a failure indication is returned; and Depending on whether the instruction sequence specifies cache line retention hints applicable to the conditional write instruction, it is selected whether to prevent the unique consistency state of the target cache line from being abandoned by the local cache associated with the processing circuit during a retention period after the processing of the conditional write instruction. The unique consistency state includes a consistency state in which the processing circuit has exclusive rights to update the target cache line.

[0005] At least some examples of this technology provide a method comprising: Decoding the instruction sequence; and In response to the decoding of the instruction sequence, processing circuitry is used to perform data processing; wherein: In response to decoding a conditional write command, the data processing includes: Determine whether the predetermined conditions are met for the target cache line corresponding to the target address specified by the condition write instruction; In response to determining that the predetermined condition is met for the target cache line, a write request is issued to update the target cache line; and In response to determining that the predetermined condition is not met for the target cache line, a failure indication is returned; and Depending on whether the instruction sequence specifies cache line retention hints applicable to the conditional write instruction, it is selected whether to prevent the unique consistency state of the target cache line from being abandoned by the local cache associated with the processing circuit during a retention period after the processing of the conditional write instruction. The unique consistency state includes a consistency state in which the processing circuit has exclusive rights to update the target cache line.

[0006] Further aspects, features, and advantages of this technology will become apparent from the following description, which is taken in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 An example of a data processing device is shown;

[0008] Figure 2 An example of a cache is shown;

[0009] Figure 3 This is a flowchart illustrating a method for processing a conditional write instruction, wherein cache line retention hints are used to determine whether to prevent the unique consistency state of the target cache line from being discarded by the local cache during the retention period following the processing of the conditional write instruction.

[0010] Figure 4 This is a flowchart illustrating an example of determining whether cache line retention hints are applicable to a conditional write instruction; and

[0011] Figure 5 An example is shown of signaling the consistency control circuitry to indicate whether the local cache will abandon the unique consistency state of a given cache line. Detailed Implementation

[0012] An apparatus includes: an instruction decoding circuit for decoding an instruction sequence; and a processing circuit for performing data processing in response to the decoding of the instruction sequence by the instruction decoding circuit. In response to the instruction decoding circuit decoding a conditional write instruction, the processing circuit determines whether a predetermined condition is met for a target cache line corresponding to a target address specified by the conditional write instruction. If the predetermined condition is met for the target cache line, a write request is issued to update the target cache line. If the predetermined condition is not met for the target cache line, a failure indication is returned. Depending on whether the instruction sequence specifies a cache line retention hint message applicable to the conditional write instruction, the processing circuit selects whether to prevent the unique consistency state of the target cache line from being abandoned by a local cache associated with the processing circuit during a retention period after the processing of the conditional write instruction. The unique consistency state includes a consistency state in which the processing circuit has exclusive rights to update the target cache line.

[0013] Therefore, the processing circuitry has hardware that supports the use of hints provided by the software in the sequence of instructions being executed, allowing the processing circuitry to determine whether it might be beneficial to maintain a target cache line in a uniquely consistent state for a period of time after the processing of a conditional write instruction. This can be particularly useful after an attempt to execute a conditional write instruction on a target cache line has failed. This can be useful in scenarios where the conditional write instruction is used as part of a read / modify / write sequence, because preventing the target cache line from relinquishing its uniquely consistent state in its local cache for a period of time after a failed conditional write instruction makes subsequent attempts to execute the conditional write instruction more likely to succeed and reduces the chance that multiple competing threads (each executing a read / modify / write sequence associated with the same target cache line) will encounter significant delays before any of these threads can complete a write due to the ping-pong of uniquely consistent states between the corresponding local caches associated with the processors executing the respective threads. However, while preventing the relinquishment of the target cache line can be particularly useful after a failed conditional write instruction, the failure of the conditional write instruction is not a requirement for preventing the relinquishment of the target cache line, and some implementations may also apply a retention period after a successful conditional write instruction.

[0014] Without cache line retention hints, processing circuitry may struggle to determine whether retaining the target cache line in a uniquely consistent state after a conditional write instruction is useful, as similar instructions can be used in other software use cases that do not involve access to the same cache line. In those other software use cases, retaining the target cache line in a uniquely consistent state for too long after a conditional write instruction may degrade overall system performance (if it prevents other threads from accessing the target cache line) when the thread encountering the conditional write instruction does not actually need the cache line for a considerable period after the instruction. Therefore, providing processing circuitry that selects whether to prevent the uniquely consistent state of the target cache line from being abandoned for a certain period after the conditional write instruction is processed, based on whether cache line retention hints are included in the instruction sequence including the conditional write instruction, depends on the specific software use case where the conditional write instruction is being executed. This supports better system performance and provides more flexible control over how the target cache line is managed after a conditional write instruction.

[0015] Cache line retention hints can be used for various types of conditional write instructions, which typically perform a write to a target cache line in memory if a predetermined condition is met, and return a failure indication if the predetermined condition is not met (e.g., storing the failure indication in a register, or setting the condition status code to a specific value).

[0016] However, cache line retention hints can be particularly useful when the conditional write instruction itself involves a request to bring the target cache line into the local cache in a uniquely consistent state (or at least when the conditional write instruction is expected to be used in a sequence of software instructions, where a previous instruction preceding the conditional write instruction may have already caused the processing circuitry to bring the target cache line into the local cache in a uniquely consistent state).

[0017] A specific example of such conditional write instructions could be a Compare-and-Swap (CAS) instruction, which specifies a target address, a compare operand, and a swap operand. In response to a CAS instruction, the processing circuitry determines whether a predetermined condition is met based on a comparison of the compare operand with the value loaded for the target cache line corresponding to the target address. If the predetermined condition is met, the processing circuitry issues a write request to write the swap operand to the target cache line. Retaining cache line hints can be particularly useful for such CAS instructions because loading a value to be compared with the compare operand to evaluate the predetermined condition is relatively likely to result in the target cache line being brought into the local cache in a uniquely consistent state (preparing for subsequent writes to the target cache line if the comparison satisfies the predetermined condition), and because such CAS instructions are typically used for read / modify / write sequences, it may be necessary to observe these sequences executing atomically when multiple threads compete to apply such sequences to the same cache line in memory.

[0018] During the retention period, the processing circuitry can prevent the uniquely consistent state of a target cache line from being abandoned by delaying the response to a snoop request associated with that target cache line until after the retention period ends. If the response to such a snoop request is delayed until after the retention period ends, this prevents another thread executing on a different processor from completing a write to the target cache line during the retention period, thus giving threads executing on processors with local caches that prevent abandonment of the uniquely consistent state more time to perform their read / modify / write sequences while the line remains in a uniquely consistent state.

[0019] Cache line hold hints can be encoded in several different ways. Typically, the processing circuitry chooses whether to prevent the abandonment of the unique consistency state of the target cache line during the hold period following a failed conditional write instruction, based on whether the instruction sequence including the conditional write instruction specifies cache line hold hints applicable to that conditional write instruction.

[0020] In some implementations, the processing circuitry may choose to prevent the unique consistency state from being abandoned for a period of time after the conditional write instruction if the cache line retention hint information applicable to the conditional write instruction is not present in the instruction sequence, and allow the unique consistency state to be abandoned during that period of time after the conditional write instruction if the cache line retention hint information applicable to the conditional write instruction is present in the instruction sequence. In this case, the default behavior could be to resist abandoning the unique consistency state of the target cache line after a conditional write to the cache line unless an applicable hint information is detected in the instruction sequence. If a hint information is present, it may be permissible to abandon the unique consistency state of the target cache line earlier before the end of the retention period. This approach may be useful if, in most software usage scenarios, conditional write instructions (e.g., CAS instructions) are expected to be used in scenarios such as read / modify / write, where it may be useful to resist abandoning the unique consistency state for a period of time after the conditional write, where the hint information indicates a deviation from the default, and where allowing earlier abandonment of the unique consistency state is considered better if another processor requires the same cache line.

[0021] However, in other implementations, the default approach in the absence of a cue message can be the opposite. The processing circuitry can choose to prevent the uniquely consistent state from being abandoned for a certain period after the conditional write instruction if a cache line retention cue message applicable to the conditional write instruction exists in the instruction sequence, and allow the uniquely consistent state to be abandoned for that period after the conditional write instruction if a cache line retention cue message applicable to the conditional write instruction does not exist in the instruction sequence. This approach has the advantages of making it easier to trigger mandatory retention of the target cache line in a microarchitecture based on a cue message explicitly included in the instruction sequence, and also because it supports the option to define additional attributes in the cue message that can influence how the processing circuitry manages the period during which the uniquely consistent state is prevented from being abandoned.

[0022] The presence / absence of cache line retention hints may not be the only condition for determining whether processing circuitry should prevent the unique consistency state of the target cache line from being abandoned during the retention period after processing a conditional write instruction that causes it to return a failure. Other conditions may also be applied, such as whether the processing circuitry is executing in a specific mode, or microarchitecture-related conditions, such as whether one or more metrics determined based on the current utilization of the local cache meet certain criteria.

[0023] In some examples, cache line hold hints (if present) can be encoded by the conditional write instruction itself. Therefore, at least one of the instruction decoding circuitry and the processing circuitry can detect whether the instruction sequence specifies a cache line hold hint based on whether the conditional write instruction specifies one. For example, the conditional write instruction can specify a cache line hold hint using various parameters of the instruction. For example, the instruction's opcode can indicate the presence or absence of a cache line hold hint. Two or more variations of the conditional write instruction (e.g., distinguished by different opcodes) can be supported, where each variation triggers the same functional operation, but some of those variations are considered to encode the presence of a cache line hold hint, and others are considered to encode the absence of a cache line hold hint. Alternatively, another field encoded separately from the opcode can be used to signal whether a cache line hold hint is present or absent. Another option is that a register operand (a value stored in a register referenced by a register specifier encoded in the instruction) can specify whether a cache line hold hint is present or absent. The register operand can be a separate operand from any other operand that affects the architecture-defined functional operation of the conditional write instruction itself (e.g., for CAS instructions, the hint register operand can be separate from the register operand used to provide the comparison operand, swap operand, and / or define the destination address). Alternatively, one of the existing operands of the conditional write instruction can have some spare bits that are not currently used for a meaningful purpose, and these bits can be reused to encode whether a hint message is present or absent for cache lines. For example, the address operand of a conditional instruction can be specified as a register operand using a register with a given number of bits (e.g., 64 bits), but the actual memory space in use can span an address range that does not require the total number of bits in the register to encode every address in that range (e.g., less than 64 bits may be sufficient to encode all addresses in the actual memory space in use). Therefore, the address operand register may include spare bits that can be used to encode the presence / absence of cache line hold hints (and, if the hint is present, to encode any other information specified by the hint, such as managing the applicability of the hint to subsequent conditional write instructions, or indicating the duration of the hold period). Thus, various methods may exist in which the conditional write instruction itself can be encoded to specify cache line hold hints.

[0024] Alternatively, in other examples, the cache line hold hint can be encoded by an instruction separate from the conditional write instruction. Thus, at least one of the instruction decoding circuitry and the processing circuitry can detect whether an instruction sequence specifies a cache line hold hint based on whether an instruction earlier than the conditional write instruction specifies the cache line hold hint. This earlier instruction can be a dedicated hint instruction (e.g., an instruction that behaves as an architecture no-operation (NOP) instruction and therefore does not cause a change in the architecture state—the effect of the hint is to control the microarchitecture to determine whether to resist abandoning a uniquely consistent state). Alternatively, the earlier instruction can be an instruction that also triggers a specific architecture operation, such that it can cause a change in the architecture state (e.g., a change in the value associated with an architecture register of the processing circuitry). For example, a variant of an existing type of instruction (intended typically for sequences of types that might benefit from the hint) can be provided that, in addition to the normal function of the instruction, also signals the cache line hold hint. If there is not enough encoding space in the conditional write instruction to encode the cache line hold hint, it may be useful to provide a dedicated hint instruction or reuse an existing instruction other than the conditional write instruction itself.

[0025] While earlier instructions encoding cache line hold hints could be a wide variety of instructions (including dedicated software hint instructions without specific architectural functionality), one potentially useful option is to use a specific variant of the CAS (Compare and Swap) instruction to indicate hints. A CAS instruction specifies a given address, a compare operand, and a swap operand, and causes processing circuitry to compare the compare operand with the value loaded for a given cache line corresponding to the given address, and in response to determining that a comparison condition is met in the comparison between the compare operand and the loaded value, writes the swap operand to the given cache line corresponding to the given address. Instances of CAS instructions whose compare operand is equal to the swap operand can be considered earlier instructions encoding cache line hold hints. For simplicity, CAS instructions with a compare operand equal to the swap operand are referred to below as "identity CAS instructions." Using identity CAS instructions to deliver hints can be particularly useful because it means no additional instruction encoding space is required to support hints, as the existing instruction encoding format for CAS instructions can be used. Instead, the presence or absence of a hint can be detected based on the identifiers of the compare operand and the swap operand. Therefore, a conditional write instruction that benefits from the presence of a hint can be a "true" CAS instruction with a comparison operand equal to the swap operand, but the presence of a hint can be encoded using an identity CAS instruction preceding a true CAS instruction in the instruction sequence.

[0026] Whether a comparison operand is equal to a swap operand can be detected from the comparison of register specifiers (e.g., if the same register specifier is used to specify both the comparison operand and the swap operand, a hint can be considered present) – in this case, an "identity CAS instruction" would include an instruction that specifies the same register for both its comparison operand and swap operand register fields (instructions using different registers to indicate the comparison operand and swap operand may not be considered identity CAS instructions, even if the values ​​stored in those registers happen to be the same). Alternatively, the comparison between the comparison operand and the swap operand can be performed based on the actual values ​​stored in registers that reference these operands, in which case the CAS instruction can be considered an identity CAS instruction even if different registers are used for the comparison operand and the swap operand respectively. However, in practice, it may be more reliable for software to signal the presence of a hint by encoding the same register specifier for both the comparison operand and the swap operand, rather than relying on a specific value stored in a register (which may depend on an earlier instruction). Furthermore, comparing register specifiers may require comparing fewer bits compared to comparing values ​​stored in registers.

[0027] Regardless of how the processing circuitry determines whether the comparison operand is equal to the swap operand (based on register specifier comparison or on the operand value stored in a register), in normal use of the CAS instruction, the comparison operand and the swap operand are relatively unlikely to be equal to each other. This is because such instructions are typically used in scenarios where the value stored in memory needs to be modified from its current value depending on the memory location still holding that value. Therefore, the comparison operand expresses the expected current value, and the swap operand expresses the modified value to be written to memory if the comparison condition passes. Under normal use, the comparison operand and the swap operand will most likely be different. Therefore, the encoding of instructions where the comparison operand and the swap operand are the same may be redundant and can be reused to represent cache line retention hints.

[0028] Another advantage of using identity CAS instructions to encode hints is that, as is often the case, CAS instructions that require loading the value of a given cache line to compare with a comparison operand also have the side effect of keeping the given cache line in a uniquely consistent state in the local cache of the processing circuitry. Therefore, in addition to encoding hints that could be useful in preventing the abandonment of a uniquely consistent state for a period of time after a failed conditional write instruction, executing identity CAS instructions can increase the probability that a conditional write instruction will succeed on its first attempt, since the identity CAS instruction used as a hint has already brought the line into the local cache in a uniquely consistent state. In some cases, the identity CAS instruction itself can trigger a hold period during which the cache line specified by the identity CAS instruction is prevented from abandoning its uniquely consistent state in the local cache.

[0029] However, other encodings are also possible, and the identity CAS instruction is not the only option.

[0030] When a cache line hold hint is encoded in an instruction preceding a conditional write instruction, it may not be desirable for that hint to apply indefinitely to all subsequent instructions, as this could prevent other threads competing for the target cache line from making progress. Therefore, a cache line hold hint is considered applicable to a conditional write instruction when the earlier instruction specifies it and no hint cancellation event occurs between the earlier instruction and the conditional write instruction. If a hint cancellation event occurs between the earlier instruction and the conditional write instruction, the hint is no longer applicable to the conditional write instruction.

[0031] Depending on the microarchitectural design choices implemented in a given system, there can be a wide variety of events that can be considered as prompting cancellation events. For example, prompting cancellation events may include one of the following: • An exception is caught. If an exception is caught, the processing circuitry may be switching to another instruction set that is unrelated to the thread that includes the conditional write instruction. Therefore, there is no longer any benefit in maintaining the unique consistency of the target cache line, and overall system performance can be improved by re-enabling the option of the processing circuitry's local cache, thereby abandoning the unique consistency of the target cache line and allowing threads on other processors competing for that cache line to make some progress. • Determine if a predetermined conditional write instruction occurs between an earlier instruction and a conditional write instruction. Once the conditional write instruction succeeds after the prompt, the benefit of the prompt is considered no longer applicable, as the software has already made the necessary forward progress that the prompt was intended to expedite. • Another conditional write instruction is detected specifying the address of a cache line different from the target cache line. If a conditional write to a cache line different from the target cache line is detected, this again indicates that the program flow has left the loop attempting conditional writes to the target cache line. Therefore, it may be preferable to allow the unique consistency state of the target cache line to be abandoned, so that other threads can make progress when they need to write to that cache line. • Evict the target cache line from the local cache. In some cases, a target cache line may be selected to be evicted from the cache for cache capacity reasons, even before any conditional write instruction targeting that cache line has arrived (and regardless of any external contention with other processors for that cache line—eviction based on cache capacity may have already been triggered by a local access to another cache line issued by processing circuitry). If the target cache line is no longer held in the local cache, delaying the response to a snoop on the target cache line may no longer be beneficial, and therefore the hint can be considered no longer applicable to subsequent conditional write instructions. • Hardware counter timeout events. For example, a hardware counter timeout event may occur when a counter configured to count instances of a specific hardware event since a prompt has been detected reaches a specific threshold (e.g., zero or a specific non-zero threshold). Hardware events may include, for example, one or more processing loops since a previous hardware event, the execution of a predetermined number of commit commands since a previous hardware event, or the execution of a predetermined number of commit load / store commands since a previous hardware event. Typically, it may be useful to apply a specific maximum limit to the period during which a prompt remains applicable, as the longer the period between encountering a prompt and encountering a conditional write command, the lower the probability that the prompt remains relevant.

[0032] A given implementation may support any one or more of these types of hardware events.

[0033] In some examples, at least when a conditional write instruction includes a Compare-and-Swap (CAS) instruction whose compare operands differ from its swap operands, the processing circuitry can determine that cache line reservation hints apply to the conditional write instruction if a predetermined condition is not met, but determine that cache line reservation hints do not apply to the conditional write instruction if the predetermined condition is met. This recognizes that preventing the abandonment of a uniquely consistent state based on hints may be more useful after a failed "true" CAS instruction than after a successful true CAS instruction, since the true CAS instruction has been successfully managed to update memory, and therefore the instruction sequence is unlikely to request another write to that cache line soon. Therefore, for performance after a successful true CAS instruction, it may be better to allow the abandonment of the unique state of the target cache line if necessary based on access from other requesters. Thus, it may be preferable that hints are not considered applicable to subsequent successful CAS instructions. On the other hand, hints may be more beneficial for failed CAS instructions because there is a possibility that subsequent retries of failed CAS will benefit from hints if the failed CAS can be retried during the retention period during which the local cache has resisted attempts to abandon the uniquely consistent state of the target cache line.

[0034] On the other hand, in the specific implementation of using identity CAS as a prompting message, even when predetermined conditions are met, it may be beneficial to apply a retention period for a certain time after the identity CAS. Therefore, when a given CAS is an identity CAS, the applicability of the prompt to the given CAS may not depend on the success / failure of the predetermined conditions of the CAS.

[0035] In some examples, the cache line may or may not contain a hint message, but no further information about the hint may be specified.

[0036] However, in some examples, it may be useful that cache line reservation hints also specify additional information defining how to manage the retention period for a conditional write instruction or how to manage the application of hints. For example, processing circuitry may determine whether a cache line reservation hint is applicable to a conditional write instruction based on whether at least one applicability condition specified by the cache line reservation hint is met. This allows software developers or compilers to more precisely express the conditions under which subsequent conditional write instructions may benefit from or not benefit from hints. This can help improve system performance by enabling processing circuitry to make decisions about the retention of a target cache line that more carefully balance the needs of the thread that includes the hint with the needs of other threads that may be competing for access to the same cache line.

[0037] Applicability conditions can be specified in various ways by cache line retention hints.

[0038] In some examples, at least one applicability condition specifies a threshold number of intermediate instructions; and when the number of intermediate instructions between the earlier instruction specifying cache line retention of the hint and the conditional write instruction is greater than the threshold number, the processing circuitry determines that cache line retention of the hint is not applicable to the conditional write instruction. Again, this recognizes that the greater the distance between the hint and the conditional write instruction, the greater the potential performance penalty for other threads, exceeding the performance gain predicted for the thread involving the hint; therefore, it may be desirable to limit the maximum distance between instructions to which the hint remains applicable.

[0039] In some examples, at least one applicability condition specifies at least one branch result condition, and the processing circuitry can determine that the cache line-reserved hint is not applicable to the conditional write instruction when the pattern of the branch results of one or more branch instructions preceding the conditional write instruction fails to satisfy at least one branch result condition. In some examples, there may be multiple alternative routes through the code sequence, and therefore the branch result pattern (e.g., a sequence of unadopted / adopted results of a series of consecutive branches) can be used to determine whether the hint is still considered beneficial. For example, if the branch result pattern represents a pattern expected for a common case in which the read / modify / write sequence does not encounter any unusual error conditions, but the sequence may also include at least one error-checking branch conditionally branching off from the read / modify / write sequence midway through the sequence depending on whether an error condition is identified, and if such a branch is taken that could indicate that any subsequent conditional write instruction is no longer a conditional write instruction to which the hint is designed to be applied, then the hint may be considered beneficial. Therefore, considering branching patterns when determining the applicability of hints can reduce the likelihood that a target cache line remains in a uniquely consistent state in the local cache for too long when the thread associated with the local cache cannot benefit from that cache line, and other threads can make progress more quickly if the uniquely consistent state is abandoned more quickly.

[0040] In scenarios where the target cache line needs to be prevented from abandoning its unique consistent state during the retention period following a conditional write instruction, the processing circuitry can control the duration of the retention period in a variety of different ways.

[0041] For example, the processing circuitry may end the retention period in response to a hardware counter timeout event occurring after the processing of a conditional write instruction. For the hardware counter timeout event mentioned above used to determine the applicability of the prompt, the hardware counter timeout event may be based on whether the counter has reached a threshold, wherein the counter is advanced in response to the detection of an instance of a specific hardware event (e.g., after a predetermined number of processing loops, execution of a predetermined number of commit instructions, or processing of a predetermined number of load / store operations). To detect the end of the retention period, the counter may be initialized in response to a conditional write instruction rather than in response to the detection of a prompt.

[0042] There can be trade-offs when setting the duration of the retention period. A longer retention period can benefit threads associated with the local cache that are committed to a target cache line that is in a uniquely consistent state, but may impair the performance of other threads. On the other hand, a shorter retention period reduces the likelihood that threads associated with the local cache will make progress in the next iteration of a conditional write attempt, but reduces the impact on other threads.

[0043] In some examples, the retention period can have a specific fixed duration (which can be counted based on the number of processing loops that have elapsed, the number of instructions executed / committed, or the number of load / store operations performed, as mentioned above). Hardware microarchitecture designers can choose a specific maximum length of retention period to apply when the processing circuitry determines to retain the target cache line in a uniquely consistent state for a certain period of time after the processing of a conditional write instruction, based on the presence / absence of a hint.

[0044] However, other examples may support variable-duration retention periods. The processing circuitry can terminate a retention period after the variable-duration period, selected based on retention period duration information specified by cache line retention hints, has elapsed. For example, the retention period duration information can be selected among several pre-configured duration options (e.g., short / medium / long…), or a specific value can be specified to initialize on a counter tracking hardware counter timeout events, or a specific value can be specified for a threshold value that triggers a hardware counter timeout event when the counter is considered to have expired. By allowing software-specified information defining the retention period duration to influence the retention period duration, the software can indicate whether a longer or shorter retention period for the target cache line is predicted to be more beneficial to performance, and the hardware can use this hint to select the duration of the retention period to apply.

[0045] Furthermore, regardless of whether the cache line retention message specifies the retention period duration, the retention period can also be terminated by the processing circuitry if a specific retention period reset event occurs. A retention period reset event may include, for example, one of the following: • The anomaly was taken; • Determine if a predefined condition is satisfied by another condition write instruction that occurs after the condition write instruction; • Another conditional write instruction is detected as specifying the address of a cache line different from the target cache line; • Evict the target cache line from the local cache; or • Hardware counter timeout event.

[0046] For reasons similar to those given above for the corresponding types of prompt cancellation events, these types of retention period reset events can be used to terminate the retention period. A given implementation may support any one or more of these types of retention period reset events.

[0047] In some examples, during the retention period, other parts of the system may not be aware that the processing circuitry is resisting an attempt to abandon the unique consistent state of the target cache line, and may therefore continue to transmit snooping requests related to the target cache line.

[0048] However, in other examples, the processing circuitry may also provide hints to other parts of the processing system based on hints expressed by the software in the executing instruction sequence. For example, the processing circuitry may provide a hold hint signal to the consistency control circuitry responsible for managing the consistency between the local cache and other caches, indicating that the local cache will not relinquish its unique consistent state during the hold period. This allows other parts of the system (e.g., the consistency control circuitry itself or another processor associated with another cache) to modify their operation, for example, prioritizing requests involving cache lines other than the target cache line (if possible) during the period when the processing circuitry will prevent the local cache from relinquishing its unique consistent state. This allows threads at other processors to make better progress, for example, by prioritizing the use of requested bandwidth for requests to cache lines that are more likely to be available. Similarly, the processing circuitry may support a hold end hint signal, which communicates to the consistency control circuitry that the hold period has ended, and thus the local cache may again be able to relinquish the unique consistent state of the target cache line associated with a conditional write instruction.

[0049] Figure 1An example of a data processing system 2 (e.g., an integrated circuit or system-on-a-chip) is schematically illustrated, comprising multiple requesting devices 4, 6, 8 and an interconnect 10 for managing consistency between the requesting devices and other caches. In this example, the requesting devices include one or more central processing units (CPUs) 4 for performing general-purpose processing, a graphics processing unit (GPU) 6 for performing graphics processing, and a network interface controller (NIC) 8 for controlling the sending and receiving of data over a network. The CPU and GPU include caches 11, 12, 14, such as a L1 cache associated with a specific core 9 and a shared L2 cache 12 for the CPU or a shared cache 14 for the GPU (in practice, the GPU core 9 may also have a separate cache). The NIC 8 has processing circuitry 18 for controlling the sending and receiving of network packets, and a network interface 20 for sending packets to and receiving packets from the network. Each of the requesting devices 4, 6, 8 has a consistency interface 16, 22 for interacting with the consistency interconnect. For example, consistency interfaces 16 and 22 can be responsible for generating the necessary consistency protocol transactions in response to memory / cache accesses from relevant requesters, and for responding to sniffer requests from interconnect 10 with appropriate responses and consistency state changes. It should be understood that this is only one example of some requester devices, and other types of requesters may also be provided, such as a display controller for controlling the display of data on the screen, or a DMA (Direct Memory Access) controller for controlling data transfers, such as between memory and peripheral devices. Examples of usable consistency protocols are provided by ARM Cambridge, UK. ® AMBA provided by Limited Company ® 4. ACE and AMBA ® The 5 CHI conformance protocol is described herein, but it should be understood that the techniques described herein can also be applied to other conformance protocols.

[0050] A given core 9 within the CPU on the GPU may include instruction decoding circuitry 40 for decoding instructions into a sequence of instructions to be executed, processing circuitry 42 for performing processing operations in response to the decoded instructions, and register 44 for storing operands of the instructions and the results of the processing operations performed by the processing circuitry 42.

[0051] System cache 30 is coupled to consistency interconnect 10 but is not assigned to any specific requesting device. For example, system cache 30 may be provided to accelerate access to data by an uncached requesting device such as NIC 8, allowing for faster access than if all reads and writes from NIC 8 had to be serviced by main memory 33. System cache 30 has a consistency interface 31 for responding to snooping requests or line-filling from the consistency interconnect. This interconnect may also be coupled to other types of devices 34, such as cryptographic units for providing cryptographic support to operations performed on the requesting device.

[0052] like Figure 1 As shown, the consistency interconnect 10 may include a snoop filter 40 for tracking which data addresses are cached at certain requester devices 4, 6. The snoop filter 40 can be used to reduce snoop traffic by allowing the consistency interconnect 10 to determine when data is not cached at a particular requester. The snoop filter 40 is not required, and in some implementations, the interconnect 10 may be provided without attempting to track data cached at each requester. In this case, when a requester 4, 6, 8 publishes a read or write transaction for data that can be shared with other requesters, the consistency interconnect 10 may trigger snoop transactions to be published to each other requester that may have cached copies of data from the same address, and manage changes to the consistency state at those other requesters and / or, if necessary, responses to the requesting requester with an updated version of the data. However, if there are many requesters, this method of broadcasting snoops to all cache requesters can be complex and can result in a large amount of consistency traffic being exchanged within system 2.

[0053] By providing a snoop filter 40 that can at least partially track which addresses are cached at the respective requesters, this helps reduce the amount of snoop traffic. In some cases, the snoop filter 40 can precisely track the data stored in the cache of each requester, allowing the consistency interconnect 10 to accurately determine which data is cached where. Therefore, when a transaction for potentially shareable data is received from the initiating requester, the interconnect 10 can determine, based on the contents of the snoop filter 40, which other requesters are caching data from the same address, and forward the snoop transaction to those requesters indicated in the snoop filter, thus avoiding the need to forward snoops to other requesters that do not currently store data.

[0054] However, other snoop filters may not accurately track cached contents. For example, a filtering scheme could be used that ensures snoop filter 40 avoids false negatives, thus ensuring that any data present in caches 11, 12, and 14 is recorded as present in the snoop filter. However, it allows for some false positives, meaning that sometimes snoop filter 40 might indicate that data is cached in a given request, even when the requester has actually invalidated the data. This approach, allowing some inaccuracy, reduces the overhead of updating the snoop filter because it means that every invalidation in caches 11, 12, and 14 that does not originate from the requester must be reflected in the snoop filter.

[0055] In some examples, the system cache 30 and the snoop filter 40 can be combined, where a single structure is looked up based on an address to provide both cache data and snoop filter information associated with that address.

[0056] Figure 2 An example of a local cache 50 that can be associated with a processing circuit 42 in a given kernel 9 is shown (e.g., Figure 1 (Any of caches 11, 12, and 14 shown). The local cache is one of the caches for which the coherence interconnect 10 (an example of coherence control circuitry) manages coherence. Cache 50 includes multiple cache entries 52 for caching data retrieved from memory 33 (in this context, "data" can include any cached information, including not only functional data but also executable program instructions). Cache 50 may, for example, have a set-association structure comprising multiple sets 54 of entries, each set 54 including two or more entries 52, wherein data at a specific address is assigned to one of the entries 52 in the set 54 corresponding to that address. Figure 2A bidirectional set association structure is shown, but other examples may have different associations, or may be fully associated or directly mapped. Each entry 52 may specify, for example, a cache tag 60 derived from at least a portion of the address of the cached data (used to determine on a cache lookup whether the data in this entry 52 is associated with the address against which a lookup is performed), the cached data 62 itself, and a consistency state 64 associated with the cached data 62 (it should be understood that other information may also be stored in each entry 52). The consistency protocol implemented by the consistency interconnect 10 and the cache can define rules for how to handle various categories of access to the cache (e.g., various types of read, write, and snoop access) based on the current consistency state of the cached data. A request of a given type can trigger a transition of the consistency state 64 in the local caches 11, 12, and 14 based on the type of request being executed and the consistency state of the cache line targeted by the request in the various local caches 11, 12, and 14.

[0057] Therefore, each cache entry 52 can cache data 62 for a given cache line in the memory address space used to address memory 33. Here, the term "cache line" refers to a unit of address space of a specific size. The consistency protocol applied by the consistency interconnect tracks the consistency status at the granularity of cache lines.

[0058] One of the consistency states supported by a given cache line held in local cache 50 can be a “unique” consistency state. When a cache line is held in local cache 50 in a unique consistency state, it means that the processing circuitry 42 associated with that local cache 50 has exclusive permission to write to that cache line, and can do so without first checking with interconnect 10 or other requesters that may be holding the line. Before another requesting device can write to the cache line, it will issue a request to the consistency interconnect 10, which triggers a snooping request to the local cache 50 holding the cache line in a unique state, requesting that the local cache relinquish its unique consistency state.

[0059] In such Figure 1 In the system of the example device shown, the "compound operation single-word atom" is typically implemented in software using a sequence of instructions that includes loading a value, some comparisons and logical operations, and then writing the modified value back to the same address if and only if the value in memory for that address is still the same as the originally loaded value. This final test and commit is typically accomplished using conditional write instructions such as compare-and-swap (CAS) instructions.

[0060] When multiple processing elements (PE, for example, Figure 1When kernel 9 (as shown) attempts these operations, only one will succeed; the processing element that first submits the CAS (first stores the attribute), while the value in memory remains unchanged since the initial load.

[0061] As a simple example, imagine we want to perform the following operation atomically (decreasing the value at addrA if it is greater than 0), where multiple threads attempt to perform this operation on the same address simultaneously:

[0062]

[0063] This can be achieved using, for example, the following instruction sequence as an atomic read / modify / write sequence:

[0064]

[0065]

[0066] The challenge with these operations is that when multiple PEs compete concurrently for the same operation, only one will succeed, and the remaining competitors will spin through multiple retries. The observation here is that after a CAS failure, a PE will typically bring the line to a unique (U) consistent state in its local caches 11, 12, and 14; therefore, if a PE can spin back to the same CAS through retrying a cyclic spin without releasing the line from the uniquely consistent state, it may make progress under certain constraints and succeed in subsequent attempts.

[0067] Therefore, by providing hardware support to the processing circuitry 40 of PE 9 in response to software-provided prompts included in the sequence of instructions to be executed, instructing the CAS to be in one of these constrained retry loops, and if it fails, the target cache line (e.g., the line corresponding to address addrA in the example above) can be uniquely and consistently maintained in the local cache 50 for a period of time until the same CAS is retried, which allows the thread to make progress more efficiently when it puts the line in the U state.

[0068] There are many ways to achieve this. For example, the hint might want to simply annotate the chance, or it might want to specify certain constraints. For example, it could specify a limited number of instructions by which it must retry the failed CAS, or to a specific control flow path (the pattern of branch results) of that CAS, so that the hint is considered applicable.

[0069] For example, the above sequence can be extended to include a prompt by encoding the prompt using an earlier instruction preceding the CAS instruction:

[0070]

[0071]

[0072] This hint can be used for a wide range of "compound operation single-word atoms" and covers many idioms for near-atomic sequences. It should be noted that this is a hint and can be safely ignored by the hardware. The sequence it will cover is already functionally correct; this is merely a performance hint. Therefore, the hardware can apply other conditions that manage whether the hint is actually followed to prevent the U state of the target cache line addrA from being discarded during the retention period following a CAS instruction (conditional write instruction).

[0073] Furthermore, this hint can be provided using identity CAS without requiring specific hints (i.e., giving additional meaning to the schema definition of identity CAS). When race conditions are possible, the above code sequence can be written as follows:

[0074]

[0075] In the above sequence, the original `ldar` instruction is replaced by `cas`, where the comparison operand register and the swap operand register are the same register—we call this identity CAS. This is an unusual way of using CAS because we effectively make the comparison redundant—we only set the value in memory to the value in the register (i.e., set it to the same value) if the value in memory is the same as the value in the register; in almost every scenario, software developers would not use CAS like this. However, bringing the line into the cache with a uniquely consistent state is a useful technique; and if we can maintain that uniquely consistent state until subsequent CAS instructions, we should make progress.

[0076] Therefore, in some specific implementations, the identity CAS can be regarded as an instruction that expresses a cache line retention hint.

[0077] In other examples, cache line retention hints can be encoded using a dedicated hint instruction (which behaves as a schema NOP in addition to providing a hint) or the CAS instruction itself (e.g., by providing hint and non-hint variants of the CAS instruction that trigger the same functional CAS operation, but indicating the presence of a hint for its hint variant and not for its non-hint variant, or by encoding the hint in unused bits of a register used to encode the address operand to determine the destination address addrA).

[0078] Figure 3This is a flowchart illustrating the processing of a conditional write instruction (e.g., the CAS instruction mentioned above). In response to the instruction decoder 40 decoding the conditional write instruction at step 100, at step 102, the processing circuitry 42 determines whether a predetermined condition is met for the target cache line corresponding to the target address specified by the conditional write instruction. For example, in the case of a CAS instruction, the predetermined condition is considered met if the comparison between the comparison operand and the value loaded for the target cache line satisfies a specific comparison condition (e.g., the comparison condition could be requiring the comparison operand to be equal to the value loaded for the target cache line). If the predetermined condition is met, at step 104, a write request is issued to update the target cache line (e.g., for a CAS instruction, where the swap operand is written to the target cache line). In some examples, upon successful write, at step 104, the processing circuitry 42 may also return a success indication indicating whether the write was successful.

[0079] If it is determined that the predetermined conditions are not met, a failure indication is returned by the processing circuitry 42 at step 106. For example, the failure indication could be setting a general-purpose register to a specific value, or it could be setting a condition status code (which can be used to control the evaluation of conditions governing the execution of other conditional operations such as conditional comparison operations) to a specific condition status value. Furthermore, in the example shown in the sequence above, the failure indication could simply include a load value from the destination cache line itself. For example, in the example above, the load value is written to the destination register x1, so a subsequent comparison instruction can then compare that value with the expected value (x4 in the example above) to infer whether the conditional write was successful. Therefore, a failure indication can be represented in many different ways, but typically it is provided that allows subsequent instructions to evaluate whether the write was successful, such that if the write is unsuccessful, the conditional branch can loop back to retry the sequence.

[0080] At least if the predetermined conditions are not met at step 102 (and as shown by the dashed line, in some implementations, and if the predetermined conditions are met), then at step 108, the processing circuit 42 determines whether the instruction sequence including the conditional write instruction specifies cache line reservation hint information applicable to the conditional write instruction. This determination may be based on whether the conditional write instruction itself encodes cache line reservation hint information, or whether an earlier instruction preceding the conditional write instruction provides cache line reservation hint information if the hint still applies to the conditional write instruction.

[0081] If the instruction sequence is detected as a specified cache line retention hint, then at step 110, processing circuitry 42 prevents any unique consistency state of the target cache line from being abandoned by the local caches 11, 12, 14 associated with processing circuitry 42 during the retention period following the processing condition write instruction. The target cache line is prevented from abandoning its unique consistency state by not responding to snooping requests received from the consistency interconnect 10 during the retention period. At step 112, processing circuitry 42 determines whether the retention period has ended, and if not, continues to prevent the abandonment of the unique consistency state. The end of the retention period can occur when a hardware timeout event expires (which can be set to expire after a fixed or variable duration following a processing conditional write instruction), or when a retention period reset event occurs, such as when an exception is adopted, another conditional write instruction successfully completes its write, another conditional write instruction is encountered that uses a different cache line as the target cache line, or the target cache line is evicted from the cache for reasons other than receiving a snoop request from the coherence interconnect 10 (e.g., due to a cache capacity conflict, which means that the processing circuit 42 requires the cache entry 52 used for the target cache line to be reassigned to a different address).

[0082] Once it is determined at step 112 that the retention period has ended, at step 114, the processing circuit 42 may again allow the unique consistency state of the target cache line to be abandoned by its local caches 11, 12, 14 (although this does not necessarily mean that the unique consistency state will be abandoned immediately—the unique consistency state can persist beyond the end of the retention period if there is no snooping triggered by other requesters trying to access the same cache line, or if the target cache line does not need to be evicted from local caches 11, 12, 14 based on capacity).

[0083] On the other hand, if it is detected at step 108 that the instruction sequence does not specify any cache line retention hints, steps 110 and 112 are omitted, and the method proceeds to step 114 to allow local caches 11, 12, 14 to relinquish their unique consistency state (if required based on snooping from interconnect 10), even if the retention period has not yet expired.

[0084] Therefore, using this method, the software can provide a hint that suggests whether it might be beneficial to try to keep the thread in a uniquely consistent state for longer than the period of time that the conditional write instruction fails. This increases the likelihood that the thread that includes the failed conditional write instruction can make progress, thereby improving performance.

[0085] The dashed lines from steps 104 to 108 represent the following options: While the benefit of using hints (to trigger a forced hold of the uniquely consistent state during the hold period after a conditional write) can be greatest after a failed conditional write that fails its predetermined condition, in some scenarios, the hold can also be enforced after a successful conditional write. For example, in an implementation where the hint is encoded as an identity CAS, the identity CAS itself is detected as a conditional write instruction associated with a predetermined condition (e.g., whether the comparison operand is equal to the swap operand), and for the identity CAS, sometimes the predetermined condition (whether the value at the target address loaded from memory is equal to the comparison operand) can be satisfied. However, since the primary function of the identity CAS is to act as a hint and “prepare” the cache to load the target cache line before a later conditional write instruction (e.g., a “true” CAS with a comparison operand different from the swap operand), it may be advantageous that the identity CAS is treated as a conditional write instruction with applicable hint information even if the predetermined condition is satisfied for the identity CAS, and thus prevents the uniquely consistent state of the target cache line from being abandoned during the hold period after the identity CAS, as... Figure 3 Step 110 is shown.

[0086] Although Figure 3 The illustration shows a method in which the presence of a hint causes the processing circuit 42 to resist abandoning the unique consistent state of the target cache line during the retention period (and the absence of a hint means that there is no need to resist abandoning the unique consistent state). However, in other examples, the implementation may be the opposite, such that the default behavior (in the absence of a hint) is to perform steps 110, 112 to resist abandoning the unique consistent state of the target cache line during the retention period, while if the hint is provided by software, the processing circuit 42 does not resist the attempt to remove the unique consistent state of the target cache line from local caches 11, 12, 14 at step 114.

[0087] Figure 4 This is a flowchart illustrating in more detail how processing circuitry 42 determines whether a cache line retention hint specified by an instruction earlier than the condition write instruction is still applicable when a subsequent condition write instruction is encountered. At step 120, the instruction specifying the cache line retention hint is decoded by instruction decoding circuitry 40. Therefore, the period of applicability of the hint begins.

[0088] At step 122, processing circuitry 42 determines whether any cue cancellation event has occurred. For example, a cue cancellation event could be any of the following: an exception is taken; a predetermined condition is determined to be met for a subsequent conditional write instruction; a change is detected in a target cache line specified between one conditional write instruction and another; a target cache line is evicted from the local cache; or a hardware counter timeout event (e.g., a given number of processing loops, executed or committed instructions, or load / store operations have elapsed since the instruction specifying the cue was encountered). If a cue cancellation event occurs, at step 123, processing circuitry 42 determines that the cache line retention cue message is no longer applicable to subsequent conditional write instructions. Otherwise, the cue message may remain applicable.

[0089] If a prompt cancellation event has not yet occurred, and the condition write instruction has not yet been decoded (step 124), then the processing circuit 42 waits for the prompt cancellation event or the condition write instruction to be decoded.

[0090] When the conditional write instruction is decoded at step 124 (since no intermediate instance of a prompt cancellation event has occurred since the cache line hold prompt was detected at step 120), at step 126, the processing circuit 42 determines whether the cache line hold prompt specifies at least one applicability condition that governs whether the prompt applies to a particular instance of the conditional write instruction. If no specific applicability condition defined by the prompt does not exist, then at step 130, the processing circuit 42 determines that the cache line hold prompt applies to the conditional write instruction because no prompt cancellation event has occurred.

[0091] Alternatively, if the cache line reservation hint does specify at least one applicability condition, then at step 128, the processing circuit 42 determines whether the conditional write instruction satisfies each applicability condition specified by the cache line reservation hint. For example, the processing circuit 42 may determine whether the distance between the instruction specifying the hint and the conditional write instruction is no greater than a certain maximum number of instructions, or whether the pattern of branch results leading to one or more branches of the conditional write instruction satisfies some expected pattern of adopting / not adopting results. If the conditional write instruction satisfies each applicability condition, then again at step 130, the cache line reservation hint is considered applicable to the conditional write instruction. If none of the required applicability conditions are met, then at step 132, the processing circuit 42 determines that the cache line reservation hint is not applicable to that particular conditional write instruction (although this does not preclude the possibility that the hint may later apply to different instances of the conditional write instruction if a hint cancellation event has not yet occurred).

[0092] After step 130 or 132, the method returns to step 122 to await another instance of a prompt cancellation event or conditional write instruction. Once a prompt cancellation event has occurred, the prompt detected in step 120 is no longer applicable to subsequent conditional write instructions.

[0093] In some examples, additional applicability conditions may be applied to determine whether the hint applies to a conditional write instruction. This may include one or more applicability conditions not explicitly specified in the hint message. For example, in cases where the conditional write instruction is a true CAS (with a comparison operand that is different from the swap operand), the applicability condition could be that a predetermined condition is not met for a true CAS. This tends to improve performance by reducing the likelihood of unnecessarily preventing other requesters from making progress after a successful CAS has managed to execute its write operation, since the hint associated with the successful CAS is causing the local cache to prevent the release of the unique consistent state of the target cache line.

[0094] like Figure 5 As shown, in some examples, it may be useful for processing circuitry 42 to pass information outward to the system (e.g., to the consistency control circuitry at interconnect 10—which may also be referred to as the master node or "HN") based on cache line retention hints to indicate whether a particular local cache 11, 12, 14 might be resisting an attempt to make that local cache 11, 12, 14 relinquish its unique consistent state. For example, Figure 5 The illustration shows an example where two CPUs 2 (each associated with a corresponding local cache conforming to a coherence protocol) are attempting to access the same cache line X using the read / modify / write sequence shown above. When requester 1 enters a retention period in which it resists an attempt to relinquish the unique coherent state of its local cache line, processing circuitry 42 in requester 1 signals the coherence control circuitry 10 with a retention period start hint signal, thus indicating that the retention period has begun. Similarly, once the retention period ends, a retention period end signal can be conveyed by processing circuitry 42 in requester 1 to the coherence control circuitry 10. The response of the coherence control circuitry 10 to those hint signals can vary, but in cases such as... Figure 5In one example shown, the consistency control circuit 10 can signal to requester 2 that while requester 1 is in its reservation period, requester 2 can delay issuing a request to bring target cache line X into its local cache and prioritize using any memory request bandwidth for requests to other addresses. For example, in response to a reservation period start prompt, a "delay" prompt specifying the address of target cache line X can be sent by the consistency control circuit 10 to requester 2, and in response to receiving a reservation period end prompt from requester 1, a "resume" prompt specifying the address of target cache line X can be sent by the consistency control circuit 10 to requester 2. This helps improve performance because by allowing requester 2 to postpone issuing requests that cannot progress, such requesters for cache line X will not occupy buffer slots in the buffer structure at the consistency control circuit 10, making it less likely that other requests will be blocked because the consistency control circuit 10 exhausts its buffer capacity to buffer pending requests.

[0095] Alternative location, although Figure 5 Not shown, but another option is that requester 2 can issue a request to bring target cache line X into its local cache, but these requests can be buffered in the consistency control circuit 10 for a certain period of time and not passed to requester 1 when the consistency control circuit 10 knows that requester 1 is in the retention period of target cache line X. Again, this allows the consistency control circuit 10 to prioritize its own internal operations to benefit other operations related to other cache lines in the retention period when it knows that a probe request for target cache line X cannot make progress. Therefore, providing hints to system interconnect 10 during the retention period can enable more efficient system operations for other components of the system, such as master node 10 and requester 2.

[0096] The concepts described herein may be embodied in computer-readable code used to manufacture devices embodying the described concepts. For example, the computer-readable code may be used in one or more stages of the semiconductor design and manufacturing process, including the electronic design automation (EDA) stage, to manufacture integrated circuits including devices embodying these concepts. The aforementioned computer-readable code may additionally or alternatively enable the definition, modeling, simulation, verification, and / or testing of devices embodying the concepts described herein.

[0097] For example, computer-readable code for manufacturing a device embodying the concepts described herein may be embodied in code that defines the hardware description language (HDL) representation of these concepts. For instance, the code may define a register-transfer level (RTL) abstraction of one or more logic circuits for defining a device embodying these concepts. The code may define an HDL representation of one or more logic circuits embodying the device using Verilog, SystemVerilog, Chisel, or VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language) and intermediate representations such as FIRRTL. Computer-readable code may provide definitions of the concepts or other behavioral representations of the concepts embodying the concepts using system-level modeling languages ​​such as SystemC and SystemVerilog, which can be interpreted by a computer to enable simulation, functional and / or formal verification and testing of the concepts.

[0098] Additionally or alternatively, computer-readable code may define a low-level description of an integrated circuit component embodying the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. One or more netlists or other computer-readable representations of the integrated circuit component may be generated by applying one or more logic synthesis processes to the RTL representation to generate a definition for manufacturing a device embodying the invention. Alternatively or additionally, one or more logic synthesis processes may generate a bitstream from the computer-readable code to be loaded into a field-programmable gate array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for the purpose of verifying and testing the concepts prior to manufacturing integrated circuits, or the FPGA may be deployed directly in a product.

[0099] Computer-readable code may include a mixture of code representations for manufacturing apparatus, such as one or more of RTL representations, netlist representations, or other computer-readable definitions used in the semiconductor design and manufacturing process for manufacturing apparatus embodying the present invention. Alternatively or additionally, the concept may be defined in a combination of computer-readable definitions used in the semiconductor design and manufacturing process for manufacturing apparatus and computer-readable code defining instructions that will be executed by the defined apparatus once manufactured.

[0100] Such computer-readable code can be contained in any known transient computer-readable medium (such as wired or wireless transmission of code over a network) or non-transient computer-readable medium such as semiconductors, disks, or optical discs. Integrated circuits made using computer-readable code may include components such as one or more of the following: a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or other components that embody the concept independently or collectively.

[0101] In this application, the phrase "configured as..." is used to mean that the elements of the device have a configuration capable of performing the defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured as" does not mean that the elements of the device need to be changed in any way to provide the defined operation.

[0102] In this application, a list of features beginning with the phrase “at least one of” means that any one or more of those features can be provided independently or in combination. For example, “at least one of the following: A, B, and C” covers any of the following options: A only (without B or C), B only (without A or C), C only (without A or B), a combination of A and B (without C), a combination of A and C (without B), a combination of B and C (without A), or a combination of A, B, and C.

[0103] While exemplary embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments, and various changes and modifications can be made therein by those skilled in the art without departing from the scope of the invention as defined in the appended claims.

Claims

1. An apparatus, the apparatus comprising: An instruction decoding circuit is used to decode an instruction sequence; and Processing circuitry, the processing circuitry being configured to perform data processing in response to the decoding of the instruction sequence by the instruction decoding circuitry; wherein: In response to the instruction decoding circuit decoding the conditional write instruction, the processing circuit is configured to: Determine whether a predetermined condition is met for the target cache line corresponding to the target address specified by the condition write instruction; In response to determining that the predetermined conditions are met for the target cache line, a write request is issued to update the target cache line; and In response to determining that the predetermined condition is not met for the target cache line, a failure indication is returned; and Depending on whether the instruction sequence specifies cache line retention hints applicable to the conditional write instruction, it is selected whether to prevent the unique consistency state of the target cache line from being abandoned by the local cache associated with the processing circuit during a retention period after the processing of the conditional write instruction, the unique consistency state including a consistency state in which the processing circuit has exclusive rights to update the target cache line.

2. The apparatus according to claim 1, wherein the condition write instruction includes a comparison and swap instruction that specifies the target address, comparison operands, and swap operands; The processing circuit is configured to determine whether the predetermined condition is met based on a comparison of the comparison operand with a value loaded for the target cache line; and In response to determining that the predetermined condition is met, the processing circuitry is configured to issue the write request to write the swap operand to the target cache line.

3. The apparatus according to claim 2, wherein, At least when the conditional write instruction includes a compare and swap instruction for which the compare operand is different from the swap operand, the processing circuit is configured to determine that the cache line reservation prompt is applicable to the conditional write instruction when the predetermined condition is not met for the conditional write instruction, but to determine that the cache line reservation prompt is not applicable to the conditional write instruction when the predetermined condition is met for the conditional write instruction.

4. The apparatus according to any one of claims 1 to 3, wherein during the retention period, the processing circuitry is configured to prevent the unique consistency state of the target cache line from being abandoned by delaying the response to a snooping request associated with the target cache line until after the end of the retention period.

5. The apparatus according to any one of claims 1 to 4, wherein at least one of the instruction decoding circuit and the processing circuit is configured to detect whether the instruction sequence specifies the cache line retention information based on whether the conditional write instruction specifies the cache line retention information.

6. The apparatus according to any one of claims 1 to 4, wherein at least one of the instruction decoding circuit and the processing circuit is configured to detect whether the instruction sequence specifies the cache line hold information based on whether an instruction earlier than the conditional write instruction specifies the cache line hold information.

7. The apparatus according to claim 6, wherein: In response to decoding a compare and swap instruction specifying a given address, a compare operand, and a swap operand, the processing circuitry is configured to compare the compare operand with a value loaded for a given cache line corresponding to the given address, and in response to determining that a comparison condition is met, write the swap operand to the given cache line corresponding to the given address; and Earlier instructions included instances of the compare and swap instructions for which the compare operand was equal to the swap operand.

8. The apparatus of any one of claims 6 and 7, wherein the cache line retention prompt information applies to the conditional write instruction when the earlier instruction specifies the cache line retention prompt information and there is no instance of a prompt cancellation event occurring between the earlier instruction and the conditional write instruction.

9. The apparatus of claim 8, wherein the prompt cancellation event includes one of the following: The anomaly was taken; Determine that another conditional write instruction occurring between the earlier instruction and the conditional write instruction satisfies the predetermined condition; Another conditional write instruction is detected as specifying the address of a cache line different from the target cache line; Evict the target cache line from the local cache; or Hardware counter timeout event.

10. The apparatus of any one of claims 1 to 9, wherein the processing circuitry is configured to determine whether the cache line retention information is applicable to the conditional write instruction based on whether the conditional write instruction satisfies at least one applicability condition specified by the cache line retention information.

11. The apparatus of claim 10, wherein the at least one suitability condition specifies a threshold number of intermediate instructions; and The processing circuit is configured to determine that the cache line hold hint is not applicable to the conditional write instruction when the number of intermediate instructions between the earlier instruction specifying the cache line hold hint and the conditional write instruction is greater than the threshold number.

12. The apparatus according to any one of claims 10 and 11, wherein the at least one suitability condition specifies at least one branch result condition; and The processing circuit is configured to determine that the cache line retention hint is not applicable to the conditional write instruction when the pattern of the branch result of one or more branch instructions preceding the conditional write instruction fails to satisfy the at least one branch result condition.

13. The apparatus according to any one of claims 1 to 12, wherein the processing circuitry is configured to terminate the retention period in response to a hardware counter timeout event occurring after processing of the condition write instruction.

14. The apparatus according to any one of claims 1 to 13, wherein the processing circuitry is configured to end the retention period after a variable duration period selected based on retention period duration information specified by the cache line retention prompt information has elapsed.

15. The apparatus according to any one of claims 1 to 14, wherein the processing circuitry is configured to terminate the retention period in response to the occurrence of a retention period reset event.

16. The apparatus of claim 15, wherein the retention period reset event includes one of the following: The anomaly was taken; Determine that the predetermined condition is satisfied for another condition write instruction occurring after the condition write instruction. Another conditional write instruction is detected as specifying the address of a cache line different from the target cache line; Evict the target cache line from the local cache; or Hardware counter timeout event.

17. The apparatus of any one of claims 1 to 16, wherein the processing circuitry is configured to provide a retention cue signal to a consistency control circuitry responsible for managing consistency between the local cache and another cache, the retention cue signal indicating that the local cache will not relinquish the unique consistency state during the retention period.

18. A computer-readable code for manufacturing an apparatus, the apparatus comprising: An instruction decoding circuit is used to decode an instruction sequence; and Processing circuitry, the processing circuitry being configured to perform data processing in response to the decoding of the instruction sequence by the instruction decoding circuitry; wherein: In response to the instruction decoding circuit decoding the conditional write instruction, the processing circuit is configured to: Determine whether a predetermined condition is met for the target cache line corresponding to the target address specified by the condition write instruction; In response to determining that the predetermined conditions are met for the target cache line, a write request is issued to update the target cache line; and In response to determining that the predetermined condition is not met for the target cache line, a failure indication is returned; and Depending on whether the instruction sequence specifies cache line retention hints applicable to the conditional write instruction, it is selected whether to prevent the unique consistency state of the target cache line from being abandoned by the local cache associated with the processing circuit during a retention period after the processing of the conditional write instruction, the unique consistency state including a consistency state in which the processing circuit has exclusive rights to update the target cache line.

19. A storage medium storing computer-readable code according to claim 18.

20. A method, the method comprising: Decode the instruction sequence; as well as In response to the decoding of the instruction sequence, processing circuitry is used to perform data processing; wherein: In response to decoding a conditional write instruction, the data processing includes: Determine whether a predetermined condition is met for the target cache line corresponding to the target address specified by the condition write instruction; In response to determining that the predetermined conditions are met for the target cache line, a write request is issued to update the target cache line; and In response to determining that the predetermined condition is not met for the target cache line, a failure indication is returned; and Depending on whether the instruction sequence specifies cache line retention hints applicable to the conditional write instruction, it is selected whether to prevent the unique consistency state of the target cache line from being abandoned by the local cache associated with the processing circuit during a retention period after the processing of the conditional write instruction, the unique consistency state including a consistency state in which the processing circuit has exclusive rights to update the target cache line.

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