Dynamic grid-based geometry coding position adjustment method

Abstract

A method of decoding by a decoder is provided. The method can include decoding a first syntax element from a bitstream to determine a base grid. The method can include decoding a second syntax element from the bitstream to determine whether volumetric parallelogram prediction coding is allowed. The method can include, in response to the volumetric parallelogram prediction coding being allowed, decoding a third syntax element from the bitstream to determine whether volumetric parallelogram prediction coding is enabled for decoding the bitstream. The method can include, in response to the third syntax element indicating that the volumetric parallelogram prediction coding is enabled, decoding a fourth syntax element from the bitstream to determine a first position offset associated with the volumetric parallelogram prediction coding. The method can include decoding the bitstream based on the volumetric parallelogram prediction coding and the first position offset.

Description

[0001] Related cross-references This application claims priority to U.S. Provisional Application No. 63 / 613,602, filed December 21, 2023, entitled “Method for Adjusting Position of Dynamic Mesh Base Geometric Coding,” which is incorporated herein by reference in its entirety. Background Technology

[0002] Embodiments of this application relate to dynamic mesh coding.

[0003] A mesh consists of a set of vertices, edges, and faces that define the shape or topology of a polyhedral object. These faces are typically composed of triangles. Each vertex in three-dimensional (3D) space is associated with a geometric location, as well as connectivity and attributes (e.g., color, reflectivity, intensity, classification, etc.) or mapping and texture information. To effectively compress dynamic mesh data, the mesh's geometric information can be compressed first, and then the corresponding connectivity, attributes, and / or mappings can be compressed based on the geometric information using dynamic mesh coding techniques (e.g., such as versatile dynamic mesh coding (V-DMC)). Summary of the Invention

[0004] According to one aspect of this application, a method for decoding by a decoder is provided. The method may include: a processor decoding a first syntax element from a bitstream to determine an underlying grid. The method may include: a processor decoding a second syntax element from the bitstream to determine whether volumetric parallelogram predictive coding is allowed for the underlying grid. The method may include: in response to allowing volumetric parallelogram predictive coding for the underlying grid, a processor decoding a third syntax element from the bitstream to determine whether volumetric parallelogram predictive coding is enabled for decoding the bitstream. The method may include: in response to the third syntax element indicating that volumetric parallelogram predictive coding is enabled, a processor decoding a fourth syntax element from the bitstream to determine a first position offset associated with the volumetric parallelogram predictive coding. The method may include: in response to the third syntax element indicating that volumetric parallelogram predictive coding is enabled, a processor decoding the bitstream based on the volumetric parallelogram predictive coding and the first position offset.

[0005] According to another aspect of this application, an apparatus for decoding by a decoder is provided. The apparatus may include a processor and a memory storing instructions. The memory stores instructions that, when executed by the processor, cause the processor to decode a first syntax element from the bitstream to determine a base grid. The memory stores instructions that, when executed by the processor, cause the processor to decode a second syntax element from the bitstream to determine whether volumetric parallelogram predictive coding is allowed for the base grid. The memory stores instructions that, when executed by the processor, cause the processor to decode a third syntax element from the bitstream in response to allowing volumetric parallelogram predictive coding for the base grid, to determine whether volumetric parallelogram predictive coding is enabled for decoding the bitstream. The memory stores instructions that, when executed by the processor, cause the processor to decode a fourth syntax element from the bitstream in response to the third syntax element indicating that volumetric parallelogram predictive coding is enabled, to determine a first position offset associated with volumetric parallelogram predictive coding. The memory stores an instruction that, when executed by the processor, causes the processor to decode the bitstream in response to a third syntax element indicating that volumetric parallelogram predictive coding is enabled, based on the volumetric parallelogram predictive coding and a first position offset.

[0006] According to another aspect of this application, a non-transitory computer-readable storage medium is provided, the medium including instructions for a decoder. When executed by a processor of the decoder, the instructions cause the processor of the decoder to decode a first syntax element from the bitstream to determine a base grid. When executed by a processor of the decoder, the instructions cause the processor of the decoder to decode a second syntax element from the bitstream to determine whether volumetric parallelogram predictive coding is allowed for the base grid. When executed by a processor of the decoder, the instructions cause the processor of the decoder to decode a third syntax element from the bitstream in response to allowing volumetric parallelogram predictive coding for the base grid, to determine whether volumetric parallelogram predictive coding is enabled for decoding the bitstream. When executed by a processor of the decoder, the instructions cause the processor of the decoder to decode a fourth syntax element from the bitstream in response to the third syntax element indicating that volumetric parallelogram predictive coding is enabled, to determine a first position offset associated with volumetric parallelogram predictive coding. When executed by the decoder's processor, this instruction causes the decoder's processor to decode the bitstream based on the volume parallelogram predictive coding and the first position offset, in response to the third syntax element indicating that volume parallelogram predictive coding is enabled.

[0007] According to another aspect of this application, a method for encoding by an encoder is provided. The method may include: encoding a first syntax element into a bitstream by a processor to indicate a base grid. The method may include: encoding a second syntax element into the bitstream by a processor to indicate whether volumetric parallelogram predictive coding is allowed for the base grid. The method may include: in response to allowing volumetric parallelogram predictive coding for the base grid, encoding a third syntax element into the bitstream by a processor to indicate whether volumetric parallelogram predictive coding is enabled for the bitstream. The method may include: in response to the third syntax element indicating that volumetric parallelogram predictive coding is enabled, encoding a fourth syntax element into the bitstream by a processor to indicate a first position offset associated with the volumetric parallelogram predictive coding. The method may include: in response to the third syntax element indicating that volumetric parallelogram predictive coding is enabled, encoding the bitstream by a processor based on the volumetric parallelogram predictive coding and the first position offset.

[0008] According to another aspect of this application, an apparatus for encoding by an encoder is provided. The apparatus may include a processor and a memory storing instructions. The memory stores instructions that, when executed by the processor, cause the processor to encode a first syntax element into the bitstream to indicate a base grid. The memory stores instructions that, when executed by the processor, cause the processor to encode a second syntax element into the bitstream to indicate whether volumetric parallelogram predictive coding is allowed for the base grid. The memory stores instructions that, when executed by the processor, cause the processor to encode a third syntax element into the bitstream in response to allowing volumetric parallelogram predictive coding for the base grid to indicate whether volumetric parallelogram predictive coding is enabled for the bitstream. The memory stores instructions that, when executed by the processor, cause the processor to encode a fourth syntax element into the bitstream in response to the third syntax element indicating that volumetric parallelogram predictive coding is enabled to indicate a first position offset associated with volumetric parallelogram predictive coding. The memory stores an instruction that, when executed by the processor, causes the processor to enable volumetric parallelogram predictive coding in response to a third syntax element, and to encode the bitstream based on the volumetric parallelogram predictive coding and a first position offset.

[0009] According to another aspect of this application, a non-transitory computer-readable medium is provided that stores instructions for an encoder. When executed by a processor of the encoder, the instructions cause the processor to encode a first syntax element into the bitstream to indicate a base grid. When executed by the encoder's processor, the instructions cause the processor to encode a second syntax element into the bitstream to indicate whether volumetric parallelogram predictive coding is allowed for the base grid. When executed by the encoder's processor, the instructions cause the processor to encode a third syntax element into the bitstream in response to allowing volumetric parallelogram predictive coding for the base grid, to indicate whether volumetric parallelogram predictive coding is enabled for the bitstream. When executed by the encoder's processor, the instructions cause the processor to encode a fourth syntax element into the bitstream in response to the third syntax element indicating that volumetric parallelogram predictive coding is enabled, to indicate a first position offset associated with volumetric parallelogram predictive coding. When executed by the encoder's processor, this instruction causes the encoder's processor to respond to the third syntax element indicating that volumetric parallelogram predictive coding is enabled, and to encode the bitstream based on volumetric parallelogram predictive coding and a first position offset.

[0010] The illustrative embodiments mentioned are not intended to limit or restrict this application, but are provided as examples to aid in understanding this application. Further embodiments are described in the Detailed Description section and will be elaborated upon below. Attached Figure Description

[0011] The accompanying drawings are incorporated herein by reference and form part of the specification. The drawings illustrate embodiments of the present application and, in conjunction with the content of the specification, can further illustrate the principles of the present application and enable those skilled in the art to implement and use the present application.

[0012] Figure 1 A block diagram of an exemplary encoding system according to some embodiments of this application is shown; Figure 2 A block diagram of an exemplary decoding system according to some embodiments of this application is shown; Figure 3 Some embodiments according to this application are shown. Figure 1 A detailed block diagram of an exemplary encoder in an encoding system; Figure 4 Some embodiments according to this application are shown. Figure 2 A detailed block diagram of an exemplary decoder in a decoding system; Figure 5 A block diagram illustrating a geometry encoding process implemented by an encoder according to some embodiments of this application is shown; Figures 6A to 6CThis illustrates a mesh subdivision and mesh displacement approximation process implemented by an encoder according to some embodiments of this application; Figure 7 A diagram showing the decomposition of displacement components in a local coordinate system according to some embodiments of this application is illustrated; Figure 8 A diagram illustrating an example parallelogram predictive coding according to one aspect of this application is shown; Figure 9 A diagram illustrating a grid data structure according to some embodiments of this application is shown; Figure 10 A diagram of a mesh having four vertices and three triangular faces according to some embodiments of this application is shown; Figure 11 A connection diagram of a mesh having four vertices and three triangular faces according to some embodiments of this application is shown; Figure 12 A data structure diagram of a parameterized mesh according to some embodiments of this application is shown; Figure 13 A diagram of a mesh having four vertices, three triangular faces, and corresponding attribute mappings according to some embodiments of this application is shown; Figure 14 A diagram showing the mesh face orientation based on vertex index order according to some embodiments of this application is illustrated; Figure 15 A diagram illustrating exemplary parallelogram predictive coding techniques according to some embodiments of this application is shown; Figure 16 A flowchart illustrating an exemplary method of encoding by an encoder according to some embodiments of this application is shown; Figure 17 A flowchart illustrating an exemplary method of decoding by a decoder according to some embodiments of this application is shown.

[0013] The embodiments of this application will now be described with reference to the accompanying drawings. Detailed Implementation

[0014] The following section describes some configurations and architectures. It should be understood that the content is for illustrative purposes only. Those skilled in the art will recognize that other configurations and architectures can be used without departing from the spirit and scope of this application, and that this application can also be applied to various other application scenarios.

[0015] It should be noted that the terms "one embodiment," "embodiment," "exemplary embodiment," "some embodiments," and "certain embodiments" mentioned in this specification all indicate that the embodiment includes a specific feature, structure, or characteristic, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, the above statements do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in conjunction with an embodiment, whether or not it is explicitly stated, those skilled in the art can implement that feature, structure, or characteristic in conjunction with other embodiments.

[0016] In general, the meaning of relevant terms can be determined at least in conjunction with the context. For example, the term "one or more" as used in this application, depending on the context, describes a single feature, structure, or characteristic, but can also be configured to describe a combination of multiple features, structures, or characteristics. Similarly, the article "a" and the definite article "described" can be distinguished by their singular and plural meanings based on the context. Furthermore, the term "based on" is not limited to including only the listed factors; depending on the context, it can also cover other additional factors not explicitly stated.

[0017] The following sections describe various aspects of the dynamic mesh coding system in conjunction with different devices and methods. The specific embodiments described below will be illustrated using modules, components, circuits, steps, operations, processing flows, algorithms, etc. (collectively referred to as units). These units can be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether a unit is implemented in hardware, firmware, or software depends on the specific application scenario and the design constraints set for the overall system. The technical solutions described herein can be applied to various dynamic mesh coding scenarios, where dynamic mesh coding includes dynamic mesh coding and decoding processing.

[0018] V-DMC has been widely applied in entertainment and industrial fields such as virtual reality / augmented reality (VR / AR), communications, and autonomous driving, including applications such as game asset management, spatial media, architectural design modeling, and structural analysis. The Moving Picture Experts Group (MPEG) has released the first community draft of the V-DMC international standard, and the Alliance for Open Media (AOM) is also working on developing a grid coding standard.

[0019] However, the existing V-DMC standard struggles to adapt to diverse dynamic mesh input data across various application scenarios. For instance, besides hierarchical information (coefficients in some scenarios), other information used by V-DMC (such as parameters) can also be encoded into the bitstream as syntax elements. Since V-DMC divides data into different levels, dividing point sets into sequences, slices, and other data units, each corresponding to different attributes such as geometry and properties, the parameter set is also set at different levels, such as sequence-level, attribute-level, and slice-level, for example, within different header information. Furthermore, parsing some syntax elements in V-DMC may require multiple conditional checks, further increasing the complexity of organizing and parsing the representation of syntax elements.

[0020] To enhance the flexibility and versatility of dynamic trellis coding, this application proposes several novel syntax element representation and organization schemes that are compatible with any applicable V-DMC standard, including but not limited to the Alliance for Open Media (AOM) Volumetric Visual Media (VVM) standard and the MPEG V-DMC standard.

[0021] Figure 1 This is a block diagram of an exemplary encoding system 100 according to some embodiments of this application. Figure 2 This is a block diagram of an exemplary decoding system 200 according to some embodiments of this application. Both the encoding system 100 and the decoding system 200 can be applied to or integrated into various devices with data processing capabilities, such as computers and wireless communication devices. For example, the encoding system 100 or the decoding system 200 can be the whole or a component of a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality device, augmented reality device, or other electronic device with data processing capabilities. Figure 1 , Figure 2 As shown, both the encoding system 100 and the decoding system 200 include a processor 102, a memory 104, and an interface 106. The components are interconnected via a bus, but other connection methods can also be used. It should be understood that the encoding system 100 and the decoding system 200 can also be equipped with other adaptable components capable of implementing the functions described herein.

[0022] Processor 102 may be a microprocessor, such as a graphics processing unit (GPU), image signal processor (ISP), central processing unit (CPU), digital signal processor (DSP), tensor processing unit (TPU), vision processing unit (VPU), neural processing unit (NPU), synergistic processing unit (SPU), physics processing unit (PPU), microcontroller unit (MCU), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), programmable logic device (PLD), state machine, gated logic circuit, discrete hardware circuit, and other suitable hardware configured to perform the various functions described in this application. Figure 1 , Figure 2 Only one processor is shown, but multiple processors can actually be configured. Processor 102 is a hardware device with one or more processing cores, capable of running software programs. The term "software" here is used broadly to refer to instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, application programs, software application programs, software packages, program routines, subroutines, objects, executable programs, execution threads, processing flows, function calls, etc., regardless of whether they are software, firmware, middleware, microcode, hardware description languages, or other forms. Software can be written using interpreted languages, compiled languages, or machine languages; all instruction sets used to drive hardware operation fall under the category of software.

[0023] Memory 104 can broadly include memory (also known as main memory / system memory) and storage devices (also known as auxiliary memory). For example, memory 104 may include random-access memory (RAM), read-only memory (ROM), static random-access memory (SRAM), dynamic random-access memory (DRAM), ferro-electric random-access memory (FRAM), electrically erasable programmable read-only memory (EEPROM), compact disc ROM (CD-ROM) or other optical disc storage devices, hard disk drive (HDD) (e.g., disk storage or other magnetic storage devices), flash memory drive, solid-state drive (SSD), or any other medium that can be configured to carry or store required program code (in the form of instructions accessible and executable by processor 102). Broadly speaking, memory 104 can be embodied in any computer-readable medium (e.g., a non-transitory computer-readable medium). Although Figure 1 and Figure 2 Only one memory is shown, but it should be understood that multiple memories may also be included.

[0024] Interface 106 broadly includes both data and communication interfaces, used for transmitting and receiving signals during information exchange with external network elements. For example, interface 106 may include input / output (I / O) devices, wired or wireless transceivers. Although Figure 1 and Figure 2 Only one interface is shown, but it should be understood that multiple interfaces may be included.

[0025] Processor 102, memory 104, and interface 106 can be configured in various forms within encoding system 100 or decoding system 200 to implement dynamic trellis encoding functionality. In some embodiments, processor 102, memory 104, and interface 106 in encoding system 100 or decoding system 200 are integrated into one or more system-on-chips (SoCs). For example, processor 102, memory 104, and interface 106 may be integrated into an application processor SoC that performs application processing within an operating system environment, running dynamic trellis encoding / decoding applications. In another example, processor 102, memory 104, and interface 106 may also be integrated onto a dedicated dynamic trellis encoding processor chip, such as a GPU or ISP chip dedicated to graphics processing in a real-time operating system (RTOS).

[0026] like Figure 1 As shown, the processor 102 within the encoding system 100 may include one or more functional modules, such as the encoder 101. Although Figure 1 The encoder 101 is housed within a single processor 102. However, it should be understood that the encoder 101 may include one or more sub-modules, which may be implemented on different processors that are adjacent to or far from each other. The encoder 101 (and any corresponding sub-modules or sub-units) may be a hardware unit (e.g., an integrated circuit component) within the processor 102 adapted to work with other components, or a software unit implemented by the processor 102 by running at least a portion of a program (i.e., instructions). The program instructions may be stored in a computer-readable medium such as memory 104. When the processor 102 executes these instructions, it can perform one or more processing flows related to dynamic mesh coding, such as voxelization, transform processing, quantization, and arithmetic encoding, the specific flows of which are detailed below.

[0027] Similarly, such as Figure 2 As shown, the processor 102 within the decoding system 200 may include one or more functional modules, such as the decoder 201. Although Figure 2 The decoder 201 is located within a processor. It should be understood that the decoder 201 may include one or more sub-modules, which may be implemented on different processors that are adjacent to or far from each other. The decoder 201 (and any corresponding sub-modules or sub-units) may be a hardware unit (e.g., an integrated circuit component) in the processor 102 adapted to work with other components, or a software unit implemented by the processor 102 by running at least a portion of a program (i.e., instructions). The program instructions may be stored in a computer-readable medium such as memory 104. When the processor 102 executes the instructions, it is able to perform one or more processing flows related to dynamic mesh decoding, such as arithmetic decoding, inverse quantization, inverse transformation, reconstruction, and synthesis.

[0028] Figure 3 According to some embodiments of this application Figure 1 A detailed structural block diagram of an exemplary encoder 101 in the encoding system 100. (See attached diagram.) Figure 3 As shown, encoder 101 includes a coordinate transformation module 302, a voxelization module 304, a geometric analysis module 306, and an arithmetic coding module 308. These modules work together to encode the positional information associated with points in the dynamic mesh into a geometric code stream (i.e., geometric coding). Figure 3 As shown, encoder 101 also includes a color transformation module 310, an attribute transformation module 312, a quantization module 314, and an arithmetic encoding module 316. These modules work together to encode the attribute information associated with the vertices or faces of the dynamic mesh into an attribute code stream (i.e., attribute encoding). It should be noted that... Figure 3 The units in this paper are independently divided based on different functions within the dynamic mesh encoder, and do not represent independent hardware structures or independent software units. In other words, the division of units is for illustrative purposes only; in practical applications, at least two units can be combined into one functional unit, or a single unit can be divided into multiple functional units to achieve corresponding functions. Furthermore, some units are not essential for implementing the technical solution of this application, but are optional units for optimizing operational performance. All of the above units can be implemented through electronic hardware, firmware, computer software, or any combination thereof, and the specific implementation can be determined based on the actual application scenario and the design constraints of the encoder 101. In addition, Figure 3 The modules shown are merely exemplary configurations; in some examples, encoder 101 may be configured with other different modules to implement dynamic mesh coding.

[0029] like Figure 3 As shown, the geometric position and attribute information associated with the vertices and faces of a mesh can be encoded separately. The geometric information of the mesh consists of multiple vertices with position coordinates, denoted as: , Where K is the number of vertices in the mesh; attribute information is denoted as , Where D is the number of attributes corresponding to a single vertex. In some embodiments, attribute encoding depends on the decoded geometric information; therefore, the vertex positions of the mesh are encoded first. Since the geometric positions in the original coordinate system can be represented using floating-point numbers, the coordinate transformation module 302 and the voxelization module 304 can be configured to perform coordinate transformation first, followed by voxelization, which quantizes the positions and removes duplicate vertices. The process of position quantization, duplicate vertex removal, and attribute assignment to the remaining vertices is called voxelization. The voxelized mesh can be represented, for example, using a list structure in a lossless manner. The geometry analysis module 306 can be configured to perform geometry analysis, for example, using a predicted vertex position code scheme. The arithmetic encoding module 308 can be configured to perform arithmetic encoding on the output of the geometry analysis module 306 to obtain a geometry bitstream.

[0030] In some embodiments, the geometry analysis module 306 is configured to perform geometry analysis using a predicted vertex position code scheme. Under this scheme, the geometric information (x, y, z) at a given location can be represented by the defined predicted vertex position code structure. Since mesh vertices may be repeated, multiple mesh vertices may be mapped to the same sub-cube (i.e., the same voxel) of size 1. To address this, for each sub-cube of size 1, the attributes corresponding to the vertices mapped to that sub-cube are averaged.

[0031] Continue to refer to Figure 3 Regarding attribute encoding, optionally, if the attribute includes color, the color transformation module 310 can be configured to convert the red / green / blue (RGB) color attribute of each point to a lightness / chromaticity (YCbCr) color attribute. The attribute transformation module 312 can be configured to perform attribute transformation based on the results of the geometry analysis module 306 (e.g., using a predicted vertex position scheme), including but not limited to hybrid video coding. Optionally, the quantization module 314 can be configured to quantize the attribute transformation coefficients output by the attribute transformation module 312 to generate an attribute quantization level associated with each point, thereby reducing the dynamic range. The arithmetic coding module 316 can be configured to arithmetically encode the resulting attribute transformation coefficients or their quantization levels associated with each grid vertex to encode them into the attribute bitstream.

[0032] Figure 4 The present application illustrates some embodiments of the present application. Figure 2 A detailed structural block diagram of an exemplary decoder 201 in the decoding system 200 shown. Figure 4 As shown, the decoder 201 may include an arithmetic decoding module 402, a geometric synthesis module 404, a reconstruction module 406, and a coordinate inverse transformation module 408. These modules work together to decode the position information associated with the vertices of the dynamic mesh from the geometric bitstream (i.e., perform geometric decoding). Figure 4As shown, the decoder 201 may further include an arithmetic decoding module 410, an inverse quantization module 412, an inverse attribute transformation module 414, and an inverse color transformation module 416. These modules work together to decode the attribute information associated with the vertices or faces of the dynamic mesh from the attribute bitstream (i.e., perform attribute decoding). It should be understood that... Figure 4 The units shown are presented independently to characterize the different functional characteristics within the dynamic mesh decoder, and do not represent that each component consists of independent hardware configuration units or single software. That is, the units are listed for illustrative purposes only; at least two units may be combined into one unit, or one unit may be divided into multiple units to achieve the corresponding function. It should also be understood that some units are not essential for implementing the functions described in this application, but are optional units used to improve performance. Furthermore, these units can be implemented through electronic hardware, firmware, computer software, or any combination thereof. Whether these units are implemented in hardware, firmware, or software depends on the specific application scenario and design constraints faced by the decoder 201. It should also be further understood that... Figure 4 The modules shown are merely illustrative; in some examples, other different modules may be configured within the decoder 201 to implement dynamic grid decoding functionality.

[0033] When the encoded dynamic mesh bitstream (e.g., a geometric bitstream or an attribute bitstream) is input from the dynamic mesh encoder (e.g., encoder 101) to the decoder 201, the decoder 201 can decode the input bitstream according to the reverse process of the dynamic mesh encoder encoding process. Therefore, for ease of description, the decoding details related to the encoding mentioned above will not be repeated here. The arithmetic decoding module 402 and the arithmetic decoding module 410 can be configured to decode the geometric bitstream and the attribute bitstream, respectively, to obtain the information encoded into the bitstream. For example, the arithmetic decoding module 410 can decode the attribute bitstream to obtain the attribute information associated with each vertex or face, such as the attribute quantization level or attribute coefficient associated with each vertex or face. Optionally, the dequantization module 412 can be configured to perform dequantization processing on the attribute quantization level associated with each vertex or face to obtain the attribute coefficient associated with each vertex or face. In addition to attribute information, the arithmetic decoding module 410 can also parse the bitstream to obtain various other information (e.g., presented in the form of syntax elements), such as the attribute encoding order followed by the vertex list, connection information, mapping information, and syntax elements for dynamic mesh encoding.

[0034] The attribute inverse transformation module 414 can be configured to perform attribute inverse transformation operations, such as implementing the inverse mapping from a two-dimensional texture image to a three-dimensional mesh model, converting data from the projection domain (e.g., the texture image) back to the attribute domain (e.g., brightness information and / or chromaticity information corresponding to color attributes). Optionally, the color inverse transformation module 416 can be configured to convert YCbCr color attributes to RGB color attributes.

[0035] For geometric decoding, the geometric synthesis module 404, reconstruction module 406 and coordinate inverse transformation module 408 in decoder 201 can be configured to perform inverse processing operations corresponding to the geometric analysis module 306, voxelization module 304 and coordinate transformation module 302 in encoder 101, respectively.

[0036] Where it falls within the scope of protection of this application, both encoder 101 and decoder 201 can be configured to use the new syntax element representation and organization schemes proposed in this application, thereby improving the flexibility and versatility of dynamic trellis coding.

[0037] Some existing technologies use a two-level coding process for geometric information encoding. First, the geometric information is decimated to create a basic mesh, which is then encoded using a general geometric coding method (e.g., edgebreaker). Next, the basic mesh is subdivided hierarchically, and the difference between the subdivided points and the approximate points of the original mesh is stored as a geometric displacement component. This displacement component is then packaged into a two-dimensional image and encoded using a lossless video coding method. The following section combines... Figure 5 The overall architecture of the two-level geometric coding process 500 is explained.

[0038] Reference Figure 5 The encoder can receive static or dynamic meshes corresponding to videos, images, image frames, scenes, etc. In step 502, the encoder can perform preprocessing operations to generate basic mesh geometry and mesh displacement. This basic mesh geometry may include an extracted basic mesh, which has fewer points than the initially received static or dynamic mesh. This extracted basic mesh can be input into the mesh encoder 504, where it performs, for example, an edgebreaker encoding process. The mesh encoder can perform geometric encoding of the extracted basic mesh. On the other hand, the mesh displacement can be input into the displacement packing component 506. The displacement packing component 506 can pack the displacement into a two-dimensional image; the specific implementation is described below. Figures 6A to 6CThe displacement packing information can be input to the video encoder 508 used for displacement, such as a High Efficiency Video Coding (HEVC) component. The mesh encoder 504 and the video encoder 508 can each input their information to a multiplexer (MUX) 510, which encodes the information into the bitstream.

[0039] Figures 6A to 6C The following diagram illustrates mesh subdivision and mesh displacement approximation processing flow 600, 625, 650 performed by the displacement packing component of an encoder according to some embodiments of this application. Figure 7 A schematic diagram 700 showing the decomposition of displacement components in a local coordinate system according to some embodiments of this application is illustrated. Figures 6A to 6C The processing flow is illustrated using a single face in the base mesh as an example.

[0040] Reference Figure 6A PB1, PB2, and PB3 are the basic grid points; Figure 6B PS1, PS2, and PS3 are subdivided points; Figure 6C PSD1, PSD2, and PSD3 in the diagram represent subdivision offset points. Subdivision point PS1 can be obtained by finding the midpoint between points PB1 and PB2; this process can be recursively repeated. Combined with... Figure 6C and Figure 7 It can be seen that each vector of point PS1 and point PSD1 can be decomposed into three components: normal, tangent, and double tangent directions. These components can also be mapped to color planes (e.g., the Y, U, and V components in the YUV 444 color space). Other color subsampling methods can be used to map the normal, tangent, and double tangent direction components of the displacement to a single Y plane in the YUV 420 color space, while setting the U and V components to default values.

[0041] Figure 8 This is a schematic diagram illustrating a parallelogram prediction coding example according to one aspect of this application.

[0042] The base grid frame can be quantized and encoded using a static grid encoder. This process is independent of which grid encoding scheme is used to compress the base grid.

[0043] like Figure 8 As shown, a parallelogram prediction model can be used, combined with the difference encoding method between the actual vertex position and the predicted vertex position, to encode the vertex position of the basic grid.

[0044] exist Figure 8In the encoding method shown, given surfaces ABC and BCD, to predict the position of point D, the prediction vector AD_pred can be determined using the diagonal of the parallelogram formed by adding the vectors of sides AC and AB. Here, D_pred is the predicted position of point D. Then, the difference between point D and the predicted position D_pred is encoded.

[0045] The displacement is processed using a hierarchical wavelet transform (or other transform method), which recursively applies a thinning layer to the reconstructed base mesh. The wavelet coefficients are then quantized (e.g., via quantization module 314), packaged into a two-dimensional image / video, and compressed by encoder 101. After generating the reconstructed wavelet coefficient image / video during image / video decoding, it is unpacked and inverse quantized (e.g., via inverse quantization module 412) to obtain the reconstructed wavelet coefficients. Then, an inverse wavelet transform is performed on the reconstructed wavelet (e.g., via attribute inverse transform module 414) to calculate the reconstructed displacement.

[0046] Wavelet transform coefficients are calculated using floating-point format and can take positive or negative values. In existing technologies, these coefficients are typically first converted to positive values ​​and then mapped to a specified bit depth to generate a two-dimensional image. The specific conversion method is shown in formula (1): c'(i) = 2^[bit_depth - 1] + [c(i)] 2^bit_depth] / [c_max-c_min] (1), Where c'(i) is the rounded displacement coefficient value, c(i) is the current displacement coefficient, c_max is the maximum displacement coefficient value, c_min is the minimum displacement coefficient value, and bit_depth is a value that limits the number of fixed layers used for image encoding.

[0047] An example of the geometric information corresponding to a single frame mesh can be found through... Figure 9 The grid data structure shown is presented as 900. Figure 10 A schematic diagram 1000 of a mesh having four vertices and three triangular faces according to some embodiments of this application is shown. Figure 11 A schematic diagram 1100 illustrates the connection relationship of a mesh having four vertices and three triangular faces according to some embodiments of this application.

[0048] Reference Figure 10 This example illustrates a surface represented by a mesh with per-vertex color characteristics, having four vertices and three faces. The spatial position of each vertex is described by coordinates X, Y, Z and color attributes red (R), green (G), and blue (B). Figure 10 As shown, each face is defined by the indices of the three vertices that form a triangle, and the connection relationships of these features are as follows: Figure 11 As shown.

[0049] Figure 12 A schematic diagram 1200 of the data structure of a parameterized mesh according to some embodiments of this application is shown. Figure 13 A schematic diagram 1300 of a mesh having four vertices, three triangular faces and corresponding attribute mappings according to some embodiments of this application is shown.

[0050] Figure 13 It shows features with attribute mapping characteristics (such as...) Figure 12 The example shown is a mesh representing a face, including four vertices and three faces. Each vertex is located in space by coordinates X, Y, and Z, while U and V represent attribute coordinates within a 2D texture vertex map. Each face is defined by three sets of vertex indices and texture vertex coordinates, and can form triangles in 3D space as well as within a 2D texture map.

[0051] Figure 14 A schematic diagram 1400 illustrates how, in some embodiments of this application, the mesh face orientation is determined based on vertex index order. (Refer to...) Figure 14 The orientation of a face can be determined using the coordinate system on the right. A face comprises three vertices belonging to three edges, and each face is defined by three sets of vertex indices. For example... Figure 14 As shown on the left, a manifold mesh is a mesh in which a single edge belongs to at most two different faces; in contrast, a non-manifold mesh is a mesh in which a single edge belongs to more than two faces, as shown in the diagram below. Figure 14 As shown on the right.

[0052] Due to the aforementioned diagonal parallelogram prediction rules (i.e., the vector superposition operation described above), the conventional parallelogram prediction coding method described above can only predict point D with high accuracy when the areas of triangle ABC and triangle BCD are approximately equal. However, due to the characteristics of grid parametric design, the areas of each triangle within the grid usually differ. The lower the prediction accuracy, the more coding bits are used to indicate the position prediction residual.

[0053] To address the aforementioned existing problems, this application proposes an exemplary parallelogram predictive coding technique using multiple different prediction modes. Once the parallelogram predictive coding modes are applied to the triangular structure of the base grid to predict multiple candidate positions of the vertices, the encoder can select the position closest to the actual position of the vertex and encode only the offset of the closest predicted position and the associated parallelogram predictive coding mode, thereby reducing the bitstream overhead.

[0054] The following text combines Figures 15 to 17 The exemplary parallelogram predictive coding technique will be described in further detail.

[0055] Figure 15 A diagram is shown of an exemplary parallelogram predictive coding technique 1500 according to some embodiments of this application.

[0056] Reference Figure 15 To more accurately predict the point location D_pred, a correction estimate can be performed on the plane defined by triangle ABC. To achieve efficient encoding of the vertex positions of the base mesh, previously encoded positions that share a common edge with the faces of the encoded mesh can be selected, for example, using... Figure 15 The two adjacent triangles shown are triangle ACK and triangle ABL. Figure 4 As described in the paper, by applying the same method to triangles ACK and ABL, we can obtain the corrected predicted vertices B' and C'.

[0057] Furthermore, point D_pred can be predicted using triangle AB'C', and the difference delta(D-D_pred) can be stored to encode the positional residual.

[0058] After incorporating points K and L into the position estimation process of point D_pred, the prediction process is carried out in three-dimensional space, which is different from the plane in which triangle ABC is located.

[0059] Figure 15 The exemplary parallelogram predictive coding technique shown can replace Figure 8 The existing parallelogram prediction technique shown can be supplemented as an additional prediction mode by setting corresponding values ​​in the bitstream to indicate the selected coding method at the sequence parameter set, image parameter set, tile parameter set, block coding mode, or face coding mode level. Each new candidate constitutes a different coding mode, and fixed-length or variable-length coding is used to indicate the corresponding coding mode.

[0060] Continue to refer to Figure 15The encoder 101 can determine the volume prediction position of point D (e.g., D_pred_vl) using an exemplary volume parallelogram predictive coding method, or determine the planar prediction position of point D (e.g., D_pred_pl) using a conventional planar parallelogram predictive coding method. Subsequently, the encoder 101 can determine the prediction position D_pred (D_pred_vl or D_pred_pl) that represents the distance between point D and point D_pred using the fewest number of coding bits, and select the corresponding parallelogram predictive coding mode for bitstream coding. For example, when performing volume parallelogram predictive coding on point D, the encoder 101 can determine adjacent grid faces (e.g., triangles) ACK and ABL. Vector AC' can be determined by adding vector LA and vector LB (e.g., AC' = LA + LB), and vector AB' can be determined by adding vector KA and vector KC (e.g., AB' = KA + KC). By adding vectors AC' and AB', the vector pointing from point A to point D_pred_vl can be determined (e.g., AD_pred_vl = AC' + AB'). Neither point D nor point D_pred_vl lies in the same plane as the grid surface ABC. Encoder 101 can use the above combination... Figure 8 The technique described performs planar parallelogram predictive coding to determine the vector (e.g., AD_pred_pl) pointing from point A to D_pred_pl. Figure 15 The midpoint D_pred_pl lies within the plane containing the mesh surface ABC. Figure 15 In the non-limiting example shown, the volumetric parallelogram prediction coding pattern for point D_pred_vl provides the predicted grid vertex closest to grid vertex D. Therefore, encoder 101 can select this volumetric parallelogram prediction coding pattern, encoding syntax elements indicating the parallelogram prediction coding pattern corresponding to D_pred_vl, and encoding other syntax elements indicating the associated positional offset, as described below.

[0061] Table 1 below shows exemplary syntax elements that can be encoded into the bitstream, indicating the selected parallelogram predictive coding mode and the corresponding position offset. For example, encoder 101 can encode a first syntax element (such as sismu_intra_unit_default) to indicate the vertex position information of the base mesh. If the number of vertices of the base mesh is greater than 0, encoder 101 can encode a second syntax element (such as sismu_derived_pos_present_flag) into the bitstream to indicate whether volumetric parallelogram predictive coding is allowed. If volumetric parallelogram predictive coding is allowed, encoder 101 can encode a third syntax element (such as sismu_pos_mode) to indicate whether volumetric parallelogram predictive coding is enabled for decoding the bitstream. As described above, when the number of bits required to encode the difference corresponding to volumetric parallelogram predictive coding is less than the difference of planar parallelogram predictive coding, the volumetric predictive coding mode can be selected, and the specific determination rules are shown in Table 2; otherwise, the planar parallelogram predictive coding mode is selected, and is indicated by the third syntax element, as shown in Table 2. Encoder 101 may encode a fourth syntax element (e.g., sismu_pos_signalled_diff) to indicate the positional offset between D_pred of the volumetric parallelogram predictive coding (e.g., D_pred_vl) or the planar parallelogram predictive coding (e.g., D_pred_pl) and the actual position of the mesh vertex D.

[0062]

[0063] Table 1: Exemplary Syntax Elements

[0064] Table 2: Third Syntax Element Figure 16 A flowchart illustrating an exemplary method 1600 of encoding by an encoder according to some embodiments of this application is shown. Method 1600 can be performed by an encoder 101 of encoding system 100 or any other suitable dynamic mesh encoding system. Method 1600 may include operations 1602-1616 as described below. It should be understood that some operations may be optional, and some operations may be performed simultaneously or in different ways. Figure 16 The sequence shown is executed sequentially.

[0065] refer to Figure 16 At position 1602, the encoder can select either volumetric parallelogram predictive coding or planar parallelogram predictive coding. For example, refer to... Figure 1 and Figure 15The encoder 101 can determine D_pred_vl and D_pre_pl and their corresponding differences (delta). When it is possible to encode the corresponding difference of the volumetric parallelogram predictive coding using fewer bits than the difference associated with the planar parallelogram predictive coding, the encoder 101 may choose the volumetric parallelogram predictive coding; otherwise, it may choose the planar parallelogram predictive coding.

[0066] At 1604, the encoder can encode the first syntax element into the bitstream to indicate the underlying grid. For example, refer to... Figure 1 According to Table 1, encoder 101 can encode a first syntax element (e.g., sismu_intra_unit_default) to indicate the vertex positions of the underlying mesh.

[0067] At 1606, the encoder can encode the second syntax element into the bitstream to indicate whether volumetric parallelogram predictive coding is allowed. For example, refer to... Figure 1 According to Table 1, if the number of vertices in the base grid is greater than 0, the encoder 101 may encode a second syntax element (e.g., sismu_derived_pos_present_flag) into the bitstream to indicate whether volumetric parallelogram predictive coding is allowed.

[0068] At 1608, in response to allowing volumetric parallelogram predictive coding for the underlying grid, the encoder may encode a third syntax element into the bitstream to indicate whether volumetric parallelogram predictive coding is enabled for the bitstream. For example, refer to... Figure 1 As shown in Table 1, when volumetric parallelogram predictive coding is enabled, encoder 101 may encode a third syntax element (e.g., sismu_pos_mode) to indicate whether volumetric parallelogram predictive coding is enabled for encoding the bitstream. As described above, volumetric parallelogram predictive coding can be selected when fewer bits than the difference associated with planar parallelogram predictive coding can be used to encode the corresponding difference, as shown in Table 2 below; otherwise, planar parallelogram predictive coding can be selected and indicated using a third syntax element, as shown in Table 2 below.

[0069] At 1610, in response to the third syntax element indicating that volumetric parallelogram predictive coding is enabled, the encoder can encode a fourth syntax element into the bitstream to indicate the first positional offset associated with the volumetric parallelogram predictive coding. For example, refer to Figure 1 and Figure 15 And according to Table 1, encoder 101 can encode a fourth syntax element (e.g., sismu_pos_signalled_diff) to indicate the positional offset between D_pred of the volume parallelogram predictive code (e.g., D_pred_vl).

[0070] At 1612, in response to the third syntax element indicating that volumetric parallelogram predictive coding is enabled, the encoder can encode the bitstream based on the volumetric parallelogram predictive coding and the first position offset. For example, refer to Figure 1 and Figure 15 According to Table 1, encoder 101 can encode the bitstream based on volume parallelogram predictive coding (e.g., D_pred_vl) and its difference (e.g., D-D_pred_vl).

[0071] At 1614, in response to the third syntax element indicating that volumetric parallelogram predictive coding is not enabled, the encoder may encode a fourth syntax element into the bitstream to indicate a second positional offset associated with planar parallelogram predictive coding. For example, refer to Figure 1 and Figure 15 And according to Table 1, encoder 101 can encode a fourth syntax element (e.g., sismu_pos_signalled_diff) to indicate the positional offset between D_pred of the planar parallelogram predictive encoding (e.g., D_pred_pl) and the actual position of the grid vertex D.

[0072] At 1616, in response to the third syntax element indicating that volumetric parallelogram predictive coding is not enabled, the encoder can encode the bitstream based on planar parallelogram predictive coding and a second positional offset. For example, refer to Figure 1 and Figure 15 According to Table 1, encoder 101 can encode the bitstream based on planar parallelogram predictive coding (e.g., D_pred_pl) and its difference (e.g., D-D_pred_pl).

[0073] Figure 17 A flowchart illustrating an exemplary method 1700 for decoding by a decoder according to some embodiments of this application is shown. Method 1700 can be performed by decoder 201 of decoding system 200 or any other suitable decoding system. Method 1700 may include operations 1702-1714 as described below. It should be understood that some operations may be optional, and some operations may be performed simultaneously or in different ways. Figure 17 The sequence shown is executed sequentially.

[0074] refer to Figure 17 At 1702, the decoder can decode the first syntax element from the bitstream to determine the underlying grid. For example, refer to... Figure 2 According to Table 1, decoder 201 can decode the first syntax element (e.g., sismu_intra_unit_default) to determine the vertex positions of the underlying mesh.

[0075] At 1704, the decoder can decode the second syntax element from the bitstream to determine whether volumetric parallelogram predictive coding is allowed for the underlying grid. For example, refer to Figure 2 According to Table 1, if the number of vertices in the base grid is greater than 0, encoder 101 can decode the second syntax element (e.g., sismu_derived_pos_present_flag) from the bitstream to determine whether volumetric parallelogram predictive coding is allowed.

[0076] At 1706, in response to allowing volumetric parallelogram predictive coding for the underlying grid, the decoder can decode a third syntax element from the bitstream to determine whether volumetric parallelogram predictive coding is enabled for decoding the bitstream. For example, refer to... Figure 2 Referring to Tables 1 and 2, when volumetric parallelogram predictive coding is enabled, decoder 201 can decode a third syntax element (e.g., sismu_pos_mode) to determine whether volumetric parallelogram predictive coding is enabled. As described above, when it is possible to encode the corresponding difference of volumetric parallelogram predictive coding using fewer bits than the difference associated with planar parallelogram predictive coding, volumetric parallelogram predictive coding can be selected for encoding, as shown in Table 2 above; otherwise, a third syntax element can be used to select and indicate planar parallelogram predictive coding, as shown in Table 2 above.

[0077] At 1708, in response to the third syntax element indicating that volumetric parallelogram predictive coding is enabled, the decoder can decode the fourth syntax element from the bitstream to determine the first positional offset associated with the volumetric parallelogram predictive coding. For example, refer to... Figure 2 and Figure 15 According to Table 1, decoder 201 can decode the fourth syntax element (e.g., sismu_pos_signalled_diff) to determine the positional offset between D_pred in the volume parallelogram predictive code (e.g., D_pred_vl).

[0078] At 1710, in response to the third syntax element indicating that volumetric parallelogram predictive coding is enabled, the decoder can decode the bitstream based on the volumetric parallelogram predictive coding and the first position offset. For example, refer to Figure 2 and Figure 15 According to Table 1, decoder 201 can decode the bitstream based on volume parallelogram predictive coding (e.g., D_pred_vl) and its difference (e.g., D-D_pred_vl).

[0079] At 1712, in response to the third syntax element indicating that volumetric parallelogram predictive coding is not enabled, the decoder can decode the fourth syntax element from the bitstream to determine the second positional offset associated with planar parallelogram predictive coding. For example, refer to Figure 2 and Figure 15 According to Table 1, decoder 201 can decode the fourth syntax element (e.g., sismu_pos_signalled_diff) to determine the positional offset between D_pred of the planar parallelogram predictive code (e.g., D_pred_pl) and the actual position of the grid vertex D.

[0080] At 1714, in response to the third syntax element indicating that volumetric parallelogram predictive coding is not enabled, the decoder can decode the bitstream based on planar parallelogram predictive coding and a second positional offset. For example, refer to Figure 2 and Figure 15 According to Table 1, decoder 201 can decode the bitstream based on planar parallelogram predictive coding (e.g., D_pred_pl) and its difference (e.g., D-D_pred_pl).

[0081] In all aspects of this application, the functions described herein can be implemented by hardware, software, firmware, or any combination thereof. If implemented by software, the relevant functions can be stored as instructions in a non-transitory computer-readable storage medium. Computer-readable media include computer storage media, which may be a processor (e.g., Figure 1 , Figure 2 The processor 102 in the document can read any medium. Exemplarily, and not limitingly, this computer-readable medium may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), optical disc read-only memory (CD-ROM) and other optical disc storage devices, hard disk drive (HDD) (e.g., disk storage or other magnetic storage devices), flash drive, solid-state drive (SSD), or other media capable of carrying and storing program code in the form of instructions or data structures, readable by processing devices such as mobile devices and computers. The disks and optical discs described herein include compact optical discs (CDs), laser optical discs, optical discs, digital video optical discs (DVDs), and floppy disks, wherein disks store data magnetically and optical discs store data optically using lasers; combinations of these media also fall within the scope of computer-readable media.

[0082] According to one aspect of this application, a method for decoding by a decoder is provided. The method may include: a processor decoding a first syntax element from a bitstream to determine a base grid. The method may include: a processor decoding a second syntax element from the bitstream to determine whether volumetric parallelogram predictive coding is allowed for the base grid. The method may include: in response to allowing volumetric parallelogram predictive coding for the base grid, a processor decoding a third syntax element from the bitstream to determine whether volumetric parallelogram predictive coding is enabled for decoding the bitstream. The method may include: in response to the third syntax element indicating that volumetric parallelogram predictive coding is enabled, a processor decoding a fourth syntax element from the bitstream to determine a first position offset associated with the volumetric parallelogram predictive coding. The method may include: in response to the third syntax element indicating that volumetric parallelogram predictive coding is enabled, a processor decoding the bitstream based on the volumetric parallelogram predictive coding and the first position offset.

[0083] In some implementations, the base mesh may include multiple vertices forming multiple mesh faces. In some implementations, decoding the bitstream by the processor based on volumetric parallelogram predictive coding and a first position offset may include: identifying second and third mesh faces, wherein the second mesh face shares the edge of the first mesh face with the first mesh face, and the third mesh face shares the edge of the second mesh face with the first mesh face. In some implementations, decoding the bitstream by the processor based on volumetric parallelogram predictive coding and a first position offset may include: calculating intermediate mesh faces based on the second and third mesh faces. In some implementations, decoding the bitstream by the processor based on volumetric parallelogram predictive coding and a first position offset may include: calculating the initial positions of the mesh vertices based on the intermediate mesh faces and volumetric parallelogram predictive coding. In some implementations, decoding the bitstream by the processor based on volumetric parallelogram predictive coding and a first position offset may include: calculating the final positions of the mesh vertices based on the initial positions and the first position offset.

[0084] In some implementations, calculating intermediate grid faces based on second and third grid faces may include: calculating a first position of a vertex of a first intermediate grid face based on a first vector addition associated with the second grid face, and calculating a second position of a vertex of a second intermediate grid face based on a second vector addition associated with the third grid face, wherein the vertices of the third intermediate grid face correspond to vertices of the first grid face.

[0085] In some implementations, the first value of the third syntax element may indicate that volumetric parallelogram coding is enabled. In some implementations, the second value of the third syntax element may indicate that planar parallelogram predictive coding is enabled.

[0086] In some implementations, the third syntax element may include a single bit.

[0087] In some implementations, the method may include: in response to a third syntax element indicating that volumetric parallelogram predictive coding is not enabled, a processor decodes a fourth syntax element from the bitstream to determine a second positional offset associated with planar parallelogram predictive coding. In some implementations, the method may include: in response to a third syntax element indicating that volumetric parallelogram predictive coding is not enabled, a processor decodes the bitstream based on planar parallelogram predictive coding and the second positional offset.

[0088] In some implementations, volumetric parallelogram predictive coding is enabled when the number of bits associated with the first position offset is less than the number of bits associated with the second position offset of the planar parallelogram predictive coding. In some implementations, planar parallelogram predictive coding is enabled when the number of bits associated with the second position offset is less than the number of bits associated with the first position offset of the volumetric parallelogram predictive coding.

[0089] According to another aspect of this application, an apparatus for decoding by a decoder is provided. The apparatus may include a processor and a memory storing instructions. The memory stores instructions that, when executed by the processor, cause the processor to decode a first syntax element from the bitstream to determine a base grid. The memory stores instructions that, when executed by the processor, cause the processor to decode a second syntax element from the bitstream to determine whether volumetric parallelogram predictive coding is allowed for the base grid. The memory stores instructions that, when executed by the processor, cause the processor to decode a third syntax element from the bitstream in response to allowing volumetric parallelogram predictive coding for the base grid, to determine whether volumetric parallelogram predictive coding is enabled for decoding the bitstream. The memory stores instructions that, when executed by the processor, cause the processor to decode a fourth syntax element from the bitstream in response to the third syntax element indicating that volumetric parallelogram predictive coding is enabled, to determine a first position offset associated with volumetric parallelogram predictive coding. The memory stores an instruction that, when executed by the processor, causes the processor to decode the bitstream in response to a third syntax element indicating that volumetric parallelogram predictive coding is enabled, based on the volumetric parallelogram predictive coding and a first position offset.

[0090] In some implementations, the base mesh may include multiple vertices forming multiple mesh faces. In some implementations, to decode the bitstream based on volume parallelogram predictive coding and a first position offset, memory stores instructions that, when executed by a processor, cause the processor to: identify a second mesh face and a third mesh face, wherein the second mesh face shares the edge of the first mesh face with the first mesh face, and the third mesh face shares the edge of the second mesh face with the first mesh face. In some implementations, to decode the bitstream based on volume parallelogram predictive coding and a first position offset, memory stores instructions that, when executed by a processor, cause the processor to: calculate an intermediate mesh face based on the second and third mesh faces. In some implementations, to decode the bitstream based on volume parallelogram predictive coding and a first position offset, memory stores instructions that, when executed by a processor, cause the processor to: calculate the initial positions of the mesh vertices based on the intermediate mesh face and the volume parallelogram predictive coding. In some implementations, in order to decode the bitstream based on volume parallelogram predictive coding and a first position offset, the memory stores instructions that, when executed by the processor, cause the processor to: calculate the final position of the mesh vertices based on the initial position and the first position offset.

[0091] In some implementations, in order to calculate intermediate mesh faces based on second and third mesh faces, memory stores instructions that, when executed by a processor, cause the processor to: calculate a first position of a vertex of a first intermediate mesh face based on a first vector addition associated with the second mesh face, and calculate a second position of a vertex of a second intermediate mesh face based on a second vector addition associated with the third mesh face, wherein the vertices of the third intermediate mesh face correspond to vertices of the first mesh face.

[0092] In some implementations, the first value of the third syntax element may indicate that volumetric parallelogram coding is enabled. In some implementations, the second value of the third syntax element may indicate that planar parallelogram predictive coding is enabled.

[0093] In some implementations, the third syntax element may include a single bit.

[0094] In some implementations, the memory stores instructions that, when executed by the processor, also cause the processor to: decode a fourth syntax element from the bitstream to determine a second position offset associated with planar parallelogram predictive coding, in response to a third syntax element indicating that volumetric parallelogram predictive coding is not enabled. In some implementations, the memory stores instructions that, when executed by the processor, also cause the processor to: decode the bitstream based on planar parallelogram predictive coding and the second position offset, in response to a third syntax element indicating that volumetric parallelogram predictive coding is not enabled.

[0095] In some implementations, volumetric parallelogram predictive coding is enabled when the number of bits associated with the first position offset is less than the number of bits associated with the second position offset of the planar parallelogram predictive coding. In some implementations, planar parallelogram predictive coding is enabled when the number of bits associated with the second position offset is less than the number of bits associated with the first position offset of the volumetric parallelogram predictive coding.

[0096] According to another aspect of this application, a non-transitory computer-readable storage medium is provided, the medium including instructions for a decoder. When executed by a processor of the decoder, the instructions cause the processor of the decoder to decode a first syntax element from the bitstream to determine a base grid. When executed by a processor of the decoder, the instructions cause the processor of the decoder to decode a second syntax element from the bitstream to determine whether volumetric parallelogram predictive coding is allowed for the base grid. When executed by a processor of the decoder, the instructions cause the processor of the decoder to decode a third syntax element from the bitstream in response to allowing volumetric parallelogram predictive coding for the base grid, to determine whether volumetric parallelogram predictive coding is enabled for decoding the bitstream. When executed by a processor of the decoder, the instructions cause the processor of the decoder to decode a fourth syntax element from the bitstream in response to the third syntax element indicating that volumetric parallelogram predictive coding is enabled, to determine a first position offset associated with volumetric parallelogram predictive coding. When executed by the decoder's processor, this instruction causes the decoder's processor to decode the bitstream based on the volume parallelogram predictive coding and the first position offset, in response to the third syntax element indicating that volume parallelogram predictive coding is enabled.

[0097] In some implementations, the base mesh may include multiple vertices forming multiple mesh faces. In some implementations, to decode the bitstream based on volume parallelogram predictive coding and a first position offset, the instruction, when executed by the decoder's processor, causes the processor to: identify a second mesh face and a third mesh face, wherein the second mesh face shares the edge of the first mesh face with the first mesh face, and the third mesh face shares the edge of the second mesh face with the first mesh face. In some implementations, to decode the bitstream based on volume parallelogram predictive coding and a first position offset, the instruction, when executed by the decoder's processor, causes the processor to: compute an intermediate mesh face based on the second and third mesh faces. In some implementations, to decode the bitstream based on volume parallelogram predictive coding and a first position offset, the instruction, when executed by the decoder's processor, causes the processor to: compute the initial positions of the mesh vertices based on the intermediate mesh face and the volume parallelogram predictive coding. In some implementations, in order to decode the bitstream based on volume parallelogram predictive coding and a first position offset, the instruction, when executed by the decoder's processor, causes the processor to: calculate the final position of the mesh vertices based on the initial position and the first position offset.

[0098] In some implementations, in order to calculate an intermediate mesh face based on a second mesh face and a third mesh face, the instruction, when executed by the decoder's processor, causes the processor to: calculate a first position of a vertex of a first intermediate mesh face based on a first vector addition associated with the second mesh face, and calculate a second position of a vertex of a second intermediate mesh face based on a second vector addition associated with the third mesh face, wherein the vertices of the third intermediate mesh face correspond to vertices of the first mesh face.

[0099] In some implementations, the first value of the third syntax element may indicate that volumetric parallelogram coding is enabled. In some implementations, the second value of the third syntax element may indicate that planar parallelogram predictive coding is enabled.

[0100] In some implementations, the third syntax element may include a single bit.

[0101] In some implementations, the memory stores instructions that, when executed by the processor, also cause the processor to: decode a fourth syntax element from the bitstream to determine a second position offset associated with planar parallelogram predictive coding, in response to a third syntax element indicating that volumetric parallelogram predictive coding is not enabled. In some implementations, the memory stores instructions that, when executed by the processor, also cause the processor to: decode the bitstream based on planar parallelogram predictive coding and the second position offset, in response to a third syntax element indicating that volumetric parallelogram predictive coding is not enabled.

[0102] In some implementations, volumetric parallelogram predictive coding is enabled when the number of bits associated with the first position offset is less than the number of bits associated with the second position offset of the planar parallelogram predictive coding. In some implementations, planar parallelogram predictive coding is enabled when the number of bits associated with the second position offset is less than the number of bits associated with the first position offset of the volumetric parallelogram predictive coding.

[0103] According to another aspect of this application, a method for encoding by an encoder is provided. The method may include: encoding a first syntax element into a bitstream by a processor to indicate a base grid. The method may include: encoding a second syntax element into the bitstream by a processor to indicate whether volumetric parallelogram predictive coding is allowed for the base grid. The method may include: in response to allowing volumetric parallelogram predictive coding for the base grid, encoding a third syntax element into the bitstream by a processor to indicate whether volumetric parallelogram predictive coding is enabled for the bitstream. The method may include: in response to the third syntax element indicating that volumetric parallelogram predictive coding is enabled, encoding a fourth syntax element into the bitstream by a processor to indicate a first position offset associated with the volumetric parallelogram predictive coding. The method may include: in response to the third syntax element indicating that volumetric parallelogram predictive coding is enabled, encoding the bitstream by a processor based on the volumetric parallelogram predictive coding and the first position offset.

[0104] In some implementations, the base mesh may include multiple vertices forming multiple mesh faces. In some implementations, encoding the bitstream by the processor based on volumetric parallelogram predictive coding and a first position offset may include: identifying a second mesh face and a third mesh face, wherein the second mesh face shares the edge of the first mesh face with the first mesh face, and the third mesh face shares the edge of the second mesh face with the first mesh face. In some implementations, encoding the bitstream by the processor based on volumetric parallelogram predictive coding and a first position offset may include: calculating an intermediate mesh face based on the second and third mesh faces. In some implementations, encoding the bitstream by the processor based on volumetric parallelogram predictive coding and a first position offset may include: calculating the initial positions of the mesh vertices based on the intermediate mesh faces and volumetric parallelogram predictive coding. In some implementations, encoding the bitstream by the processor based on volumetric parallelogram predictive coding and a first position offset may include: calculating the final positions of the mesh vertices based on the initial positions and the first position offset.

[0105] In some implementations, calculating intermediate grid faces based on second and third grid faces may include: calculating a first position of a vertex of a first intermediate grid face based on a first vector addition associated with the second grid face, and calculating a second position of a vertex of a second intermediate grid face based on a second vector addition associated with the third grid face, wherein the vertices of the third intermediate grid face correspond to vertices of the first grid face.

[0106] In some implementations, the first value of the third syntax element may indicate that volumetric parallelogram coding is enabled. In some implementations, the second value of the third syntax element may indicate that planar parallelogram predictive coding is enabled.

[0107] In some implementations, the third syntax element may include a single bit.

[0108] In some implementations, the method may include: in response to a third syntax element indicating that volumetric parallelogram predictive coding is not enabled, the processor encodes a fourth syntax element into the bitstream to indicate a second positional offset associated with planar parallelogram predictive coding. In some implementations, the method may include: in response to a third syntax element indicating that volumetric parallelogram predictive coding is not enabled, the processor encodes the bitstream based on planar parallelogram predictive coding and the second positional offset.

[0109] In some implementations, volumetric parallelogram predictive coding is enabled when the number of bits associated with the first position offset is less than the number of bits associated with the second position offset of the planar parallelogram predictive coding. In some implementations, planar parallelogram predictive coding is enabled when the number of bits associated with the second position offset is less than the number of bits associated with the first position offset of the volumetric parallelogram predictive coding.

[0110] According to another aspect of this application, an apparatus for encoding by an encoder is provided. The apparatus may include a processor and a memory storing instructions. The memory stores instructions that, when executed by the processor, cause the processor to encode a first syntax element into the bitstream to indicate a base grid. The memory stores instructions that, when executed by the processor, cause the processor to encode a second syntax element into the bitstream to indicate whether volumetric parallelogram predictive coding is allowed for the base grid. The memory stores instructions that, when executed by the processor, cause the processor to encode a third syntax element into the bitstream in response to allowing volumetric parallelogram predictive coding for the base grid to indicate whether volumetric parallelogram predictive coding is enabled for the bitstream. The memory stores instructions that, when executed by the processor, cause the processor to encode a fourth syntax element into the bitstream in response to the third syntax element indicating that volumetric parallelogram predictive coding is enabled to indicate a first position offset associated with volumetric parallelogram predictive coding. The memory stores an instruction that, when executed by the processor, causes the processor to enable volumetric parallelogram predictive coding in response to a third syntax element, and to encode the bitstream based on the volumetric parallelogram predictive coding and a first position offset.

[0111] In some implementations, the base mesh may include multiple vertices forming multiple mesh faces. In some implementations, to encode the bitstream based on volume parallelogram predictive coding and a first position offset, memory stores instructions that, when executed by a processor, cause the processor to: identify a second mesh face and a third mesh face, wherein the second mesh face shares the edge of the first mesh face with the first mesh face, and the third mesh face shares the edge of the second mesh face with the first mesh face. In some implementations, to encode the bitstream based on volume parallelogram predictive coding and a first position offset, memory stores instructions that, when executed by a processor, cause the processor to: compute an intermediate mesh face based on the second and third mesh faces. In some implementations, to encode the bitstream based on volume parallelogram predictive coding and a first position offset, memory stores instructions that, when executed by a processor, cause the processor to: compute the initial positions of the mesh vertices based on the intermediate mesh face and the volume parallelogram predictive coding. In some implementations, in order to encode the bitstream based on volume parallelogram predictive coding and a first position offset, the memory stores instructions that, when executed by the processor, cause the processor to: calculate the final position of the mesh vertices based on the initial position and the first position offset.

[0112] In some implementations, in order to calculate intermediate mesh faces based on second and third mesh faces, memory stores instructions that, when executed by a processor, cause the processor to: calculate a first position of a vertex of a first intermediate mesh face based on a first vector addition associated with the second mesh face, and calculate a second position of a vertex of a second intermediate mesh face based on a second vector addition associated with the third mesh face, wherein the vertices of the third intermediate mesh face correspond to vertices of the first mesh face.

[0113] In some implementations, the first value of the third syntax element may indicate that volumetric parallelogram coding is enabled. In some implementations, the second value of the third syntax element may indicate that planar parallelogram predictive coding is enabled.

[0114] In some implementations, the third syntax element may include a single bit.

[0115] In some implementations, the memory stores instructions that, when executed by the processor, also cause the processor to: encode a fourth syntax element into the bitstream in response to a third syntax element indicating that volumetric parallelogram predictive coding is not enabled, to indicate a second positional offset associated with planar parallelogram predictive coding. In some implementations, the memory stores instructions that, when executed by the processor, also cause the processor to: encode the bitstream based on planar parallelogram predictive coding and the second positional offset in response to a third syntax element indicating that volumetric parallelogram predictive coding is not enabled.

[0116] In some implementations, volumetric parallelogram predictive coding is enabled when the number of bits associated with the first position offset is less than the number of bits associated with the second position offset of the planar parallelogram predictive coding. In some implementations, planar parallelogram predictive coding is enabled when the number of bits associated with the second position offset is less than the number of bits associated with the first position offset of the volumetric parallelogram predictive coding.

[0117] According to another aspect of this application, a non-transitory computer-readable medium is provided that stores instructions for an encoder. When executed by a processor of the encoder, the instructions cause the processor to encode a first syntax element into the bitstream to indicate a base grid. When executed by the encoder's processor, the instructions cause the processor to encode a second syntax element into the bitstream to indicate whether volumetric parallelogram predictive coding is allowed for the base grid. When executed by the encoder's processor, the instructions cause the processor to encode a third syntax element into the bitstream in response to allowing volumetric parallelogram predictive coding for the base grid, to indicate whether volumetric parallelogram predictive coding is enabled for the bitstream. When executed by the encoder's processor, the instructions cause the processor to encode a fourth syntax element into the bitstream in response to the third syntax element indicating that volumetric parallelogram predictive coding is enabled, to indicate a first position offset associated with volumetric parallelogram predictive coding. When executed by the encoder's processor, this instruction causes the encoder's processor to respond to the third syntax element indicating that volumetric parallelogram predictive coding is enabled, and to encode the bitstream based on volumetric parallelogram predictive coding and a first position offset.

[0118] In some implementations, the base mesh may include multiple vertices forming multiple mesh faces. In some implementations, to encode the bitstream based on volume parallelogram predictive coding and a first position offset, the instruction, when executed by the encoder's processor, causes the processor to: identify a second mesh face and a third mesh face, wherein the second mesh face shares the edge of the first mesh face with the first mesh face, and the third mesh face shares the edge of the second mesh face with the first mesh face. In some implementations, to encode the bitstream based on volume parallelogram predictive coding and a first position offset, the instruction, when executed by the encoder's processor, causes the processor to: calculate an intermediate mesh face based on the second and third mesh faces. In some implementations, to encode the bitstream based on volume parallelogram predictive coding and a first position offset, the instruction, when executed by the encoder's processor, causes the processor to: calculate the initial positions of the mesh vertices based on the intermediate mesh face and the volume parallelogram predictive coding. In some implementations, in order to encode the bitstream based on volume parallelogram predictive coding and a first position offset, the instruction, when executed by the encoder's processor, causes the processor to: calculate the final position of the mesh vertices based on the initial position and the first position offset.

[0119] In some implementations, in order to calculate an intermediate mesh face based on a second mesh face and a third mesh face, the instruction, when executed by the encoder's processor, causes the processor to: calculate a first position of a vertex of a first intermediate mesh face based on a first vector addition associated with the second mesh face, and calculate a second position of a vertex of a second intermediate mesh face based on a second vector addition associated with the third mesh face, wherein the vertices of the third intermediate mesh face correspond to vertices of the first mesh face.

[0120] In some implementations, the first value of the third syntax element may indicate that volumetric parallelogram coding is enabled. In some implementations, the second value of the third syntax element may indicate that planar parallelogram predictive coding is enabled.

[0121] In some implementations, the third syntax element may include a single bit.

[0122] In some implementations, the memory stores instructions that, when executed by the processor, also cause the processor to: encode a fourth syntax element into the bitstream in response to a third syntax element indicating that volumetric parallelogram predictive coding is not enabled, to indicate a second positional offset associated with planar parallelogram predictive coding. In some implementations, the memory stores instructions that, when executed by the processor, also cause the processor to: encode the bitstream based on planar parallelogram predictive coding and the second positional offset in response to a third syntax element indicating that volumetric parallelogram predictive coding is not enabled.

[0123] In some implementations, volumetric parallelogram predictive coding is enabled when the number of bits associated with the first position offset is less than the number of bits associated with the second position offset of the planar parallelogram predictive coding. In some implementations, planar parallelogram predictive coding is enabled when the number of bits associated with the second position offset is less than the number of bits associated with the first position offset of the volumetric parallelogram predictive coding.

[0124] The foregoing description of the embodiments will fully reveal the general characteristics of this application, enabling those skilled in the art to easily modify and / or adapt the above embodiments to various applications using their knowledge in the art, without excessive experimentation and without departing from the general concept of this application. Therefore, based on the teachings and guidance herein, such adaptations and modifications are intended to fall within the equivalent meaning and scope of the disclosed embodiments. It should be understood that the wording or terminology used herein is for descriptive purposes and not for limiting purposes; therefore, the terminology or terminology in this specification should be interpreted by those skilled in the art based on the teachings and guidance herein.

[0125] The embodiments of this application have been described above using functional building blocks, which illustrate specific functions and their implementation relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Boundaries may be defined elsewhere as long as the specific functions and their relationships can be properly executed.

[0126] The summary and abstract section may list one or more, but not all, exemplary embodiments of this application, which were conceived by the inventors and are therefore not intended to limit this application and the appended claims in any way.

[0127] Various functional blocks, modules, and steps have been disclosed above. The provided arrangement is exemplary and not limiting. Therefore, the functional blocks, modules, and steps described above can be rearranged or combined in ways different from the examples above. Similarly, some embodiments may include only a subset of the functional blocks, modules, and steps described above, and any such subset is permitted.

[0128] The scope of protection of this application should not be limited to any of the exemplary embodiments described above, but should be defined only by the claims and their equivalents.

Claims

1. A method for decoding by a decoder, comprising: The processor decodes the first syntax element from the bitstream to determine the underlying grid. The processor decodes a second syntax element from the bitstream to determine whether volumetric parallelogram predictive coding is allowed for the underlying grid. In response to allowing volume parallelogram predictive coding for the underlying grid, the processor decodes a third syntax element from the bitstream to determine whether volume parallelogram predictive coding is enabled for decoding the bitstream; In response to the third syntax element indicating that the volume parallelogram predictive coding is enabled, the processor decodes the fourth syntax element from the bitstream to determine the first position offset associated with the volume parallelogram predictive coding; as well as In response to the third syntax element indicating that the volume parallelogram predictive coding is enabled, the processor decodes the bitstream based on the volume parallelogram predictive coding and the first position offset.

2. The method according to claim 1, wherein, The basic mesh includes multiple vertices forming multiple mesh faces, and Decoding the bitstream by the processor based on the volume parallelogram predictive encoding and the first position offset includes: Identify a second grid surface and a third grid surface, wherein the second grid surface shares the edge of the first grid surface with the first grid surface, and the third grid surface shares the edge of the second grid surface with the first grid surface; The intermediate grid surface is calculated based on the second grid surface and the third grid surface; The initial positions of the mesh vertices are calculated based on the intermediate mesh face and the volume parallelogram predictive encoding; and The final position of the mesh vertex is calculated based on the initial position and the first position offset.

3. The method according to claim 2, wherein, Calculating the intermediate grid surface based on the second grid surface and the third grid surface includes: The first position of the vertex of the first intermediate grid face is calculated based on the first vector addition associated with the second grid face, and the second position of the vertex of the second intermediate grid face is calculated based on the second vector addition associated with the third grid face, wherein the vertex of the third intermediate grid face corresponds to the vertex of the first grid face.

4. The method according to claim 1, wherein, The first value of the third syntax element indicates that the volume parallelogram encoding is enabled, and The second value of the third syntax element indicates that planar parallelogram predictive coding is enabled.

5. The method according to claim 1, wherein, The third syntax element consists of a single bit.

6. The method according to claim 1, further comprising: In response to the third syntax element indicating that the volumetric parallelogram predictive coding is not enabled, the processor decodes the fourth syntax element from the bitstream to determine a second position offset associated with the planar parallelogram predictive coding; as well as In response to the third syntax element indicating that the volume parallelogram predictive coding is not enabled, the processor decodes the bitstream based on the planar parallelogram predictive coding and the second position offset.

7. The method according to claim 6, wherein, When the number of bits associated with the first position offset is less than the number of bits associated with the second position offset of the planar parallelogram predictive coding, the volumetric parallelogram predictive coding is enabled, and The planar parallelogram predictive coding is enabled when the number of bits associated with the second position offset is less than the number of bits associated with the first position offset of the volume parallelogram predictive coding.

8. An apparatus for decoding by a decoder, comprising: processor; as well as The memory stores instructions that, when executed by the processor, cause the processor to: Decode the first syntax element from the bitstream to determine the underlying grid; Decode the second syntax element from the bitstream to determine whether volume parallelogram predictive coding is allowed for the underlying grid; In response to allowing volume parallelogram predictive coding for the underlying grid, a third syntax element is decoded from the bitstream to determine whether volume parallelogram predictive coding is enabled for decoding the bitstream; In response to the third syntax element indicating that the volume parallelogram predictive coding is enabled, a fourth syntax element is decoded from the bitstream to determine a first position offset associated with the volume parallelogram predictive coding; as well as In response to the third syntax element indicating that the volume parallelogram predictive coding is enabled, the bitstream is decoded based on the volume parallelogram predictive coding and the first position offset.

9. The apparatus according to claim 8, wherein, The basic mesh includes multiple vertices forming multiple mesh faces, and In order to decode the bitstream based on the volume parallelogram predictive coding and the first position offset, the memory stores instructions that, when executed by the processor, cause the processor to: Identify a second grid surface and a third grid surface, wherein the second grid surface shares the edge of the first grid surface with the first grid surface, and the third grid surface shares the edge of the second grid surface with the first grid surface; The intermediate grid surface is calculated based on the second grid surface and the third grid surface; The initial positions of the mesh vertices are calculated based on the intermediate mesh face and the volume parallelogram predictive encoding; and The final position of the mesh vertex is calculated based on the initial position and the first position offset.

10. The apparatus according to claim 9, wherein, In order to calculate the intermediate mesh face based on the second mesh face and the third mesh face, the memory stores instructions that, when executed by the processor, cause the processor to: The first position of the vertex of the first intermediate grid face is calculated based on the first vector addition associated with the second grid face, and the second position of the vertex of the second intermediate grid face is calculated based on the second vector addition associated with the third grid face, wherein the vertex of the third intermediate grid face corresponds to the vertex of the first grid face.

11. The apparatus according to claim 8, wherein, The first value of the third syntax element indicates that the volume parallelogram encoding is enabled, and The second value of the third syntax element indicates that planar parallelogram predictive coding is enabled.

12. The apparatus according to claim 8, wherein, The third syntax element consists of a single bit.

13. The apparatus according to claim 8, wherein, The memory stores instructions, which, when executed by the processor, also cause the processor to: In response to the third syntax element indicating that the volumetric parallelogram predictive coding is not enabled, the processor decodes the fourth syntax element from the bitstream to determine a second position offset associated with the planar parallelogram predictive coding; as well as In response to the third syntax element indicating that the volume parallelogram predictive coding is not enabled, the processor decodes the bitstream based on the planar parallelogram predictive coding and the second position offset.

14. The apparatus according to claim 13, wherein, When the number of bits associated with the first position offset is less than the number of bits associated with the second position offset of the planar parallelogram predictive coding, the volumetric parallelogram predictive coding is enabled, and The planar parallelogram predictive coding is enabled when the number of bits associated with the second position offset is less than the number of bits associated with the first position offset of the volume parallelogram predictive coding.

15. A non-transitory computer-readable medium storing instructions that, when executed by a processor of a decoder, cause the processor of the decoder to: Decode the first syntax element from the bitstream to determine the underlying grid; Decode the second syntax element from the bitstream to determine whether volume parallelogram predictive coding is allowed for the underlying grid; In response to allowing volume parallelogram predictive coding for the underlying grid, a third syntax element is decoded from the bitstream to determine whether volume parallelogram predictive coding is enabled for decoding the bitstream; In response to the third syntax element indicating that the volume parallelogram predictive coding is enabled, a fourth syntax element is decoded from the bitstream to determine a first position offset associated with the volume parallelogram predictive coding; as well as In response to the third syntax element indicating that the volume parallelogram predictive coding is enabled, the bitstream is decoded based on the volume parallelogram predictive coding and the first position offset.

16. The non-transitory computer-readable medium according to claim 15, wherein, The basic mesh includes multiple vertices forming multiple mesh faces, and In order to decode the bitstream based on the volume parallelogram predictive coding and the first position offset, the instruction, when executed by the processor of the decoder, causes the processor to: Identify a second grid surface and a third grid surface, wherein the second grid surface shares the edge of the first grid surface with the first grid surface, and the third grid surface shares the edge of the second grid surface with the first grid surface; The intermediate grid surface is calculated based on the second grid surface and the third grid surface; The initial positions of the mesh vertices are calculated based on the intermediate mesh face and the volume parallelogram predictive encoding; and The final position of the mesh vertex is calculated based on the initial position and the first position offset.

17. The non-transitory computer-readable medium according to claim 16, wherein, In order to calculate the intermediate mesh face based on the second mesh face and the third mesh face, the instruction, when executed by the processor of the decoder, causes the processor to: The first position of the vertex of the first intermediate grid face is calculated based on the first vector addition associated with the second grid face, and the second position of the vertex of the second intermediate grid face is calculated based on the second vector addition associated with the third grid face, wherein the vertex of the third intermediate grid face corresponds to the vertex of the first grid face.

18. The non-transitory computer-readable medium according to claim 15, wherein, The first value of the third syntax element indicates that the volume parallelogram encoding is enabled, and The second value of the third syntax element indicates that planar parallelogram predictive coding is enabled.

19. The non-transitory computer-readable medium according to claim 15, wherein, The third syntax element consists of a single bit.

20. The non-transitory computer-readable medium according to claim 15, wherein, When the instruction is executed by the processor of the decoder, the processor also causes the processor to: In response to the third syntax element indicating that the volumetric parallelogram predictive coding is not enabled, the processor decodes the fourth syntax element from the bitstream to determine a second position offset associated with the planar parallelogram predictive coding; as well as In response to the third syntax element indicating that the volume parallelogram predictive coding is not enabled, the processor decodes the bitstream based on the planar parallelogram predictive coding and the second position offset.

21. The non-transitory computer-readable medium according to claim 20, wherein, When the number of bits associated with the first position offset is less than the number of bits associated with the second position offset of the planar parallelogram predictive coding, the volumetric parallelogram predictive coding is enabled, and The planar parallelogram predictive coding is enabled when the number of bits associated with the second position offset is less than the number of bits associated with the first position offset of the volume parallelogram predictive coding.

22. A method for encoding by an encoder, comprising: The processor encodes the first syntax element into the bitstream to indicate the underlying grid; The processor encodes a second syntax element into the bitstream to indicate whether volume parallelogram prediction coding is allowed for the underlying grid. In response to allowing volume parallelogram predictive coding for the underlying grid, the processor encodes a third syntax element into the bitstream to indicate whether volume parallelogram predictive coding is enabled for the bitstream. In response to the third syntax element indicating that the volume parallelogram predictive coding is enabled, the processor encodes a fourth syntax element into the bitstream to indicate a first position offset associated with the volume parallelogram predictive coding. as well as In response to the third syntax element indicating that the volume parallelogram predictive coding is enabled, the processor encodes the bitstream based on the volume parallelogram predictive coding and the first position offset.

23. The method according to claim 22, wherein, The basic mesh includes multiple vertices forming multiple mesh faces, and The processor encodes the bitstream based on the volume parallelogram predictive coding and the first position offset, including: Identify a second grid surface and a third grid surface, wherein the second grid surface shares the edge of the first grid surface with the first grid surface, and the third grid surface shares the edge of the second grid surface with the first grid surface; The intermediate grid surface is calculated based on the second grid surface and the third grid surface; The initial positions of the mesh vertices are calculated based on the intermediate mesh face and the volume parallelogram predictive encoding; and The final position of the mesh vertex is calculated based on the initial position and the first position offset.

24. The method according to claim 23, wherein, Calculating the intermediate grid surface based on the second grid surface and the third grid surface includes: The first position of the vertex of the first intermediate grid face is calculated based on the first vector addition associated with the second grid face, and the second position of the vertex of the second intermediate grid face is calculated based on the second vector addition associated with the third grid face, wherein the vertex of the third intermediate grid face corresponds to the vertex of the first grid face.

25. The method according to claim 22, wherein, The first value of the third syntax element indicates that the volume parallelogram encoding is enabled, and The second value of the third syntax element indicates that planar parallelogram predictive coding is enabled.

26. The method according to claim 22, wherein, The third syntax element consists of a single bit.

27. The method of claim 22, further comprising: In response to the third syntax element indicating that the volumetric parallelogram predictive coding is not enabled, the processor encodes a fourth syntax element into the bitstream to indicate a second position offset associated with the planar parallelogram predictive coding. as well as In response to the third syntax element indicating that the volumetric parallelogram predictive coding is not enabled, the processor encodes the bitstream based on the planar parallelogram predictive coding and the second position offset.

28. The method according to claim 27, wherein, When the number of bits associated with the first position offset is less than the number of bits associated with the second position offset of the planar parallelogram predictive coding, the volumetric parallelogram predictive coding is enabled, and The planar parallelogram predictive coding is enabled when the number of bits associated with the second position offset is less than the number of bits associated with the first position offset of the volume parallelogram predictive coding.

29. An apparatus for encoding by an encoder, comprising: processor; as well as The memory stores instructions that, when executed by the processor, cause the processor to: The first syntax element is encoded into the bitstream to indicate the underlying grid; The second syntax element is encoded into the bitstream to indicate whether volumetric parallelogram prediction coding is allowed for the underlying grid. In response to allowing volume parallelogram predictive coding for the underlying grid, a third syntax element is encoded into the bitstream to indicate whether volume parallelogram predictive coding is enabled for the bitstream. In response to the third syntax element indicating that the volume parallelogram predictive coding is enabled, a fourth syntax element is encoded into the bitstream to indicate a first position offset associated with the volume parallelogram predictive coding. as well as In response to the third syntax element indicating that the volume parallelogram predictive coding is enabled, the bitstream is encoded based on the volume parallelogram predictive coding and the first position offset.

30. The apparatus according to claim 29, wherein, The basic mesh includes multiple vertices forming multiple mesh faces, and In order to encode the bitstream based on the volume parallelogram predictive coding and the first position offset, the memory stores instructions that, when executed by the processor, cause the processor to: Identify a second grid surface and a third grid surface, wherein the second grid surface shares the edge of the first grid surface with the first grid surface, and the third grid surface shares the edge of the second grid surface with the first grid surface; The intermediate grid surface is calculated based on the second grid surface and the third grid surface; The initial positions of the mesh vertices are calculated based on the intermediate mesh face and the volume parallelogram predictive encoding; and The final position of the mesh vertex is calculated based on the initial position and the first position offset.

31. The apparatus according to claim 30, wherein, In order to calculate the intermediate mesh face based on the second mesh face and the third mesh face, the memory stores instructions that, when executed by the processor, cause the processor to: The first position of the vertex of the first intermediate grid face is calculated based on the first vector addition associated with the second grid face, and the second position of the vertex of the second intermediate grid face is calculated based on the second vector addition associated with the third grid face, wherein the vertex of the third intermediate grid face corresponds to the vertex of the first grid face.

32. The apparatus according to claim 29, wherein, The first value of the third syntax element indicates that the volume parallelogram encoding is enabled, and The second value of the third syntax element indicates that planar parallelogram predictive coding is enabled.

33. The apparatus according to claim 29, wherein, The third syntax element consists of a single bit.

34. The apparatus according to claim 29, wherein, The memory stores instructions, which, when executed by the processor, also cause the processor to: In response to the third syntax element indicating that the volumetric parallelogram predictive coding is not enabled, a fourth syntax element is encoded into the bitstream to indicate a second position offset associated with the planar parallelogram predictive coding. as well as In response to the third syntax element indicating that the volumetric parallelogram predictive coding is not enabled, the processor encodes the bitstream based on the planar parallelogram predictive coding and the second position offset.

35. The apparatus according to claim 34, wherein, When the number of bits associated with the first position offset is less than the number of bits associated with the second position offset of the planar parallelogram predictive coding, the volumetric parallelogram predictive coding is enabled, and The planar parallelogram predictive coding is enabled when the number of bits associated with the second position offset is less than the number of bits associated with the first position offset of the volume parallelogram predictive coding.

36. A non-transitory computer-readable medium storing instructions that, when executed by a processor of an encoder, cause the processor of the encoder to: The first syntax element is encoded into the bitstream to indicate the underlying grid; The second syntax element is encoded into the bitstream to indicate whether volumetric parallelogram prediction coding is allowed for the underlying grid. In response to allowing volume parallelogram predictive coding for the underlying grid, a third syntax element is encoded into the bitstream to indicate whether volume parallelogram predictive coding is enabled for the bitstream. In response to the third syntax element indicating that the volume parallelogram predictive coding is enabled, a fourth syntax element is encoded into the bitstream to indicate a first position offset associated with the volume parallelogram predictive coding. as well as In response to the third syntax element indicating that the volume parallelogram predictive coding is enabled, the bitstream is encoded based on the volume parallelogram predictive coding and the first position offset.

37. The non-transitory computer-readable medium according to claim 36, wherein, The basic mesh includes multiple vertices forming multiple mesh faces, and In order to encode the bitstream based on the volume parallelogram predictive coding and the first position offset, the instructions, when executed by the processor of the encoder, cause the processor to: Identify a second grid surface and a third grid surface, wherein the second grid surface shares the edge of the first grid surface with the first grid surface, and the third grid surface shares the edge of the second grid surface with the first grid surface; The intermediate grid surface is calculated based on the second grid surface and the third grid surface; The initial positions of the mesh vertices are calculated based on the intermediate mesh face and the volume parallelogram predictive encoding; and The final position of the mesh vertex is calculated based on the initial position and the first position offset.

38. The non-transitory computer-readable medium according to claim 37, wherein, In order to calculate the intermediate mesh surface based on the second mesh surface and the third mesh surface, the instruction, when executed by the processor of the encoder, causes the processor to: The first position of the vertex of the first intermediate grid face is calculated based on the first vector addition associated with the second grid face, and the second position of the vertex of the second intermediate grid face is calculated based on the second vector addition associated with the third grid face, wherein the vertex of the third intermediate grid face corresponds to the vertex of the first grid face.

39. The non-transitory computer-readable medium according to claim 36, wherein, The first value of the third syntax element indicates that the volume parallelogram encoding is enabled, and The second value of the third syntax element indicates that planar parallelogram predictive coding is enabled.

40. The non-transitory computer-readable medium according to claim 36, wherein, The third syntax element consists of a single bit.

41. The non-transitory computer-readable medium according to claim 36, wherein, When the instruction is executed by the processor of the encoder, the processor also causes the processor to: In response to the third syntax element indicating that the volumetric parallelogram predictive coding is not enabled, a fourth syntax element is encoded into the bitstream to indicate a second position offset associated with the planar parallelogram predictive coding. as well as In response to the third syntax element indicating that the volumetric parallelogram predictive coding is not enabled, the processor encodes the bitstream based on the planar parallelogram predictive coding and the second position offset.

42. The non-transitory computer-readable medium according to claim 41, wherein, When the number of bits associated with the first position offset is less than the number of bits associated with the second position offset of the planar parallelogram predictive coding, the volumetric parallelogram predictive coding is enabled, and The planar parallelogram predictive coding is enabled when the number of bits associated with the second position offset is less than the number of bits associated with the first position offset of the volume parallelogram predictive coding.

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