Shift register unit, control method thereof, and gate driving circuit

Abstract

The present disclosure provides a shift register unit, a control method thereof, and a gate driving circuit. The shift register unit comprises: an input circuit connected to an input signal terminal, a first clock signal terminal and a pull-up node, configured to provide a signal of the input signal terminal to the pull-up node under control of the first clock signal terminal; an output circuit configured to provide a signal of a second clock signal terminal to an output signal terminal under control of the pull-up node; a control circuit connected to a control voltage terminal, the first clock signal terminal, the pull-up node and a pull-down node, configured to provide a signal of the control voltage terminal to the pull-down node under control of the first clock signal terminal, and provide a signal of the first clock signal terminal to the pull-down node under control of the pull-up node; and a first pull-down circuit connected to the pull-up node, the pull-down node, the second clock signal terminal and a reference signal terminal, configured to provide a signal of the reference signal terminal to the pull-up node under control of the pull-down node and the second clock signal terminal.

Description

Shift register unit and its control method and gate drive circuit Technical Field

[0001] This disclosure relates to the field of display technology, specifically to a shift register unit, a gate driving circuit, and a control method for the shift register unit. Background Technology

[0002] In display technology, driving circuits are used to generate driving signals to drive pixels for display. These driving circuits can be implemented using GOA (Gate on Array) technology, which cascades multiple shift registers to generate multi-stage driving signals. These signals are then provided to the pixel array to drive it for display. For display devices such as electronic paper displays (EPDs), the driving circuits require high driving voltages to power the pixels, which can easily burn out components within the circuit, thus affecting the display.

[0003] Summary of the Invention

[0004] Embodiments of this disclosure provide a shift register unit, a gate drive circuit, and a control method for the shift register unit.

[0005] According to one aspect of this disclosure, a shift register unit is provided, comprising: an input circuit connected to an input signal terminal, a first clock signal terminal, and a pull-up node of the shift register unit, for providing a signal from the input signal terminal to the pull-up node under the control of the first clock signal terminal; an output circuit connected to an output signal terminal, a second clock signal terminal, and a pull-up node of the shift register unit, for providing a signal from the second clock signal terminal to the output signal terminal under the control of the pull-up node; a control circuit connected to a control voltage terminal, the first clock signal terminal, the pull-up node, and a pull-down node of the shift register unit, for providing a signal from the control voltage terminal to the pull-down node under the control of the first clock signal terminal, and providing a signal from the first clock signal terminal to the pull-down node under the control of the pull-up node; and a first pull-down circuit connected to the pull-up node, the pull-down node, the second clock signal terminal, and a reference signal terminal of the shift register unit, for providing a signal from the reference signal terminal to the pull-up node under the control of the pull-down node and the second clock signal terminal.

[0006] For example, the shift register unit further includes: a first voltage regulator circuit, which is connected between the pull-up node and the power supply signal terminal or the reference signal terminal, and is used to stabilize the potential of the pull-up node.

[0007] For example, the first voltage regulator circuit includes a first capacitor, the first terminal of which is connected to the power supply signal terminal or reference signal terminal of the shift register unit, and the second terminal of which is connected to the pull-up node.

[0008] For example, the input circuit includes a first transistor, the gate of the first transistor is connected to a first clock signal terminal, the first terminal of the first transistor is connected to an input signal terminal, and the second terminal of the first transistor is connected to a pull-up node.

[0009] For example, the input circuit includes a first transistor and a second transistor. The gates of the first transistor and the second transistor are connected to a first clock signal terminal. The first terminal of the first transistor is connected to the input signal terminal. The second terminal of the first transistor is connected to the first terminal of the second transistor. The second terminal of the second transistor is connected to a pull-up node.

[0010] For example, the control circuit includes a third transistor and a fourth transistor. The gate of the third transistor is connected to the first clock signal terminal, the first terminal of the third transistor is connected to the control voltage terminal, and the second terminal of the third transistor is connected to the pull-down node. The gate of the fourth transistor is connected to the pull-up node, the first terminal of the fourth transistor is connected to the first clock signal terminal, and the second terminal of the fourth transistor is connected to the pull-down node.

[0011] For example, the control circuit also includes a fifth transistor, the second terminal of the fourth transistor is connected to a pull-down node via the fifth transistor, the gate of the fifth transistor is connected to the control voltage terminal, the first terminal of the fifth transistor is connected to the second terminal of the fourth transistor, and the second terminal of the fifth transistor is connected to the pull-down node.

[0012] For example, the control circuit includes a first control circuit and a second control circuit, the pull-down node includes a first pull-down node and a second pull-down node, the control voltage terminal includes a first control voltage terminal and a second control voltage terminal, the first control circuit is connected to the first control voltage terminal, the first pull-down node, the pull-up node and the first clock signal terminal, and is used to provide the signal of the first control voltage terminal to the first pull-down node under the control of the first clock signal terminal, and to provide the signal of the first clock signal terminal to the first pull-down node under the control of the pull-up node; the second control circuit is connected to the second control voltage terminal, the second pull-down node, the pull-up node and the first clock signal terminal, and is used to provide the signal of the second control voltage terminal to the first pull-down node under the control of the first clock signal terminal, and to provide the signal of the first clock signal terminal to the second pull-down node under the control of the pull-up node.

[0013] For example, the first control circuit includes a third transistor, a fourth transistor, and a fifth transistor. The gate of the third transistor is connected to a first clock signal terminal, the first terminal of the third transistor is connected to a first control voltage terminal, and the second terminal of the third transistor is connected to a first pull-down node. The gate of the fourth transistor is connected to a pull-up node, the first terminal of the fourth transistor is connected to the first clock signal terminal, and the second terminal of the fourth transistor is connected to the first pull-down node via the fifth transistor. The gate of the fifth transistor is connected to the first control voltage terminal, the first terminal of the fifth transistor is connected to the second terminal of the fourth transistor, and the second terminal of the fifth transistor is connected to the first pull-down node. The second control circuit includes a sixth transistor, a seventh transistor, and an eighth transistor. The gate of the sixth transistor is connected to the first clock signal terminal, the first terminal of the sixth transistor is connected to a second control voltage terminal, and the second terminal of the sixth transistor is connected to a second pull-down node. The gate of the seventh transistor is connected to a pull-up node, the first terminal of the seventh transistor is connected to the first clock signal terminal, and the second terminal of the seventh transistor is connected to the second pull-down node via the fifth transistor. The gate of the eighth transistor is connected to the second control voltage terminal, the first terminal of the eighth transistor is connected to the second terminal of the seventh transistor, and the second terminal of the eighth transistor is connected to the second pull-down node.

[0014] For example, the first pull-down circuit includes an isolation sub-circuit and a pull-down sub-circuit, wherein the isolation sub-circuit is connected between the pull-down sub-circuit and the pull-up node, and is used to turn on or off under the control of the second clock signal terminal; the pull-down sub-circuit is connected between the isolation sub-circuit and the reference signal terminal, and is used to provide the signal from the reference signal terminal to the isolation sub-circuit under the control of the pull-down node.

[0015] For example, the isolation sub-circuit includes a ninth transistor, the gate of which is connected to a second clock signal terminal, the first terminal of which is connected to a pull-down sub-circuit, and the second terminal of which is connected to a pull-up node.

[0016] For example, a pull-down sub-circuit includes a tenth transistor, the gate of which is connected to the pull-down node, the first terminal of which is connected to the reference signal terminal, and the second terminal of which is connected to the first terminal of the ninth transistor.

[0017] For example, the pull-down node includes a first pull-down node and a second pull-down node, and the pull-down sub-circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor. The gates of the tenth transistor and the eleventh transistor are connected to the first pull-down node. The first terminal of the eleventh transistor is connected to the reference signal terminal, and the second terminal of the eleventh transistor is connected to the first terminal of the tenth transistor. The second terminal of the tenth transistor is connected to the first terminal of the ninth transistor. The gates of the twelfth transistor and the thirteenth transistor are connected to the second pull-down node. The first terminal of the thirteenth transistor is connected to the reference signal terminal, and the second terminal of the thirteenth transistor is connected to the first terminal of the twelfth transistor. The second terminal of the twelfth transistor is connected to the first terminal of the ninth transistor.

[0018] For example, the shift register unit also includes a second voltage regulator circuit connected between the pull-down node and the reference signal terminal to stabilize the potential of the pull-down node.

[0019] For example, the pull-down node includes a first pull-down node and a second pull-down node, and the second voltage regulator circuit includes a second capacitor and a third capacitor, wherein the first terminal of the second capacitor is connected to the reference signal terminal, the second terminal of the second capacitor is connected to the first pull-down node, the first terminal of the third capacitor is connected to the reference signal terminal, and the second terminal of the third capacitor is connected to the second pull-down node.

[0020] For example, the output circuit includes a fourteenth transistor and a fourth capacitor. The gate of the fourteenth transistor is connected to a pull-up node, the first terminal of the fourteenth transistor is connected to a second clock signal terminal, and the second terminal of the fourteenth transistor is connected to an output signal terminal. The first terminal of the fourth capacitor is connected to the second terminal of the fourteenth transistor, and the second terminal of the fourth capacitor is connected to the gate of the fourteenth transistor.

[0021] For example, the output signal terminal includes a first output signal terminal and a second output signal terminal, wherein the second terminal of the fourteenth transistor is connected to the first output signal terminal; the output circuit also includes a fifteenth transistor and a fifth capacitor, the gate of the fifteenth transistor is connected to a pull-up node, the first terminal of the fifteenth transistor is connected to a second clock signal terminal, and the second terminal of the fifteenth transistor is connected to a second output signal terminal; the first terminal of the fifth capacitor is connected to the second terminal of the fifteenth transistor, and the second terminal of the fifth capacitor is connected to the gate of the fifteenth transistor.

[0022] For example, the shift register unit also includes a reset circuit, which is connected to the reset signal terminal, pull-up node and reference signal terminal of the shift register unit, and is used to provide the signal from the reference signal terminal to the pull-up node under the control of the reset signal terminal.

[0023] For example, the reset circuit includes a sixteenth transistor, the gate of which is connected to the reset signal terminal, the first terminal of which is connected to the reference signal terminal, and the second terminal of which is connected to the pull-up node.

[0024] For example, the reset circuit includes a sixteenth transistor and a seventeenth transistor. The gate of the sixteenth transistor is connected to the reset signal terminal, the first terminal of the sixteenth transistor is connected to the reference signal terminal via the seventeenth transistor, the second terminal of the sixteenth transistor is connected to the pull-up node, the gate of the seventeenth transistor is connected to the reset signal terminal, the first terminal of the seventeenth transistor is connected to the reference signal terminal, and the second terminal of the seventeenth transistor is connected to the first terminal of the sixteenth transistor.

[0025] For example, the reset circuit also includes an eighteenth transistor and a nineteenth transistor; the gate of the eighteenth transistor is connected to the total reset signal terminal of the shift register unit, the first terminal of the eighteenth transistor is connected to the reference signal terminal via the nineteenth transistor, the second terminal of the eighteenth transistor is connected to the pull-up node, the gate of the nineteenth transistor is connected to the total reset signal terminal, the first terminal of the nineteenth transistor is connected to the reference signal terminal, and the second terminal of the nineteenth transistor is connected to the first terminal of the eighteenth transistor.

[0026] For example, the shift register unit further includes: a first leakage protection circuit, which is connected to the first leakage protection node, the power signal terminal, and the output signal terminal of the shift register unit, and is used to provide the signal from the power signal terminal to the first leakage protection node under the control of the signal from the output signal terminal; wherein at least one of the input circuit, the first pull-down circuit, and the reset circuit is connected to the first leakage protection node.

[0027] For example, the first leakage protection circuit includes a twentieth transistor, the gate of which is connected to the output signal terminal, the first terminal of which is connected to the power signal terminal, and the second terminal of which is connected to the first leakage protection node.

[0028] For example, in the input circuit, the second terminal of the first transistor and the first terminal of the second transistor are connected to the first leakage protection node; in the reset circuit, the first terminal of the sixteenth transistor and the second terminal of the seventeenth transistor are connected to the first leakage protection node; in the first pull-down circuit, the second terminal of the tenth transistor and the first terminal of the eleventh transistor are connected to the first leakage protection node, and the second terminal of the twelfth transistor and the first terminal of the thirteenth transistor are connected to the first leakage protection node.

[0029] For example, the shift register unit further includes a second leakage protection circuit, which is connected to the second leakage protection node, the power signal terminal, and the output signal terminal of the shift register unit. It is used to provide the signal from the power signal terminal to the second leakage protection node under the control of the signal from the output signal terminal. The input circuit is connected to the first leakage protection node, and at least one of the first pull-down circuit and the reset circuit is connected to the second leakage protection node.

[0030] For example, the second leakage protection circuit includes a twenty-first transistor, the gate of which is connected to the output signal terminal, the first terminal of which is connected to the power signal terminal, and the second terminal of which is connected to the second leakage protection node.

[0031] For example, in the input circuit, the second terminal of the first transistor and the first terminal of the second transistor are connected to the first leakage protection node; in the reset circuit, the second terminal of the sixteenth transistor and the first terminal of the seventeenth transistor are connected to the second leakage protection node, and the first terminal of the eighteenth transistor and the second terminal of the nineteenth transistor are connected to the second leakage protection node; in the first pull-down circuit, the second terminal of the tenth transistor and the first terminal of the eleventh transistor are connected to the second leakage protection node, and the second terminal of the twelfth transistor and the first terminal of the thirteenth transistor are connected to the second leakage protection node.

[0032] For example, the shift register unit also includes a second pull-down circuit, which connects the pull-down node, the output signal terminal, and the reference signal terminal of the shift register unit, and is used to provide the signal from the reference signal terminal to the output signal terminal under the control of the pull-down node.

[0033] For example, the second pull-down circuit includes a 22nd transistor, the gate of which is connected to the pull-down node, the first terminal of which is connected to the reference signal terminal, and the second terminal of which is connected to the output signal terminal.

[0034] For example, the pull-down node includes a first pull-down node and a second pull-down node, and the output signal terminal includes a first output signal terminal and a second output signal terminal; the second pull-down circuit includes a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, and a twenty-fifth transistor. The gate of the twenty-second transistor is connected to the first pull-down node, the first terminal of the twenty-second transistor is connected to the reference signal terminal, and the second terminal of the twenty-second transistor is connected to the first output signal terminal; the gate of the twenty-third transistor is connected to the second pull-down node, the first terminal of the twenty-third transistor is connected to the reference signal terminal, and the second terminal of the twenty-third transistor is connected to the first output signal terminal; the gate of the twenty-fourth transistor is connected to the first pull-down node, the first terminal of the twenty-fourth transistor is connected to the reference signal terminal, and the second terminal of the twenty-fourth transistor is connected to the second output signal terminal; the gate of the twenty-fifth transistor is connected to the second pull-down node, the first terminal of the twenty-fifth transistor is connected to the reference signal terminal, and the second terminal of the twenty-fifth transistor is connected to the second output signal terminal.

[0035] For example, the control circuit, the input circuit, and the first pull-down circuit are arranged along a first direction. The shift register unit also includes a first clock signal connection line having a first branch and a second branch. The first clock signal terminal is electrically connected to the input circuit through the first branch and electrically connected to the control circuit through the second branch. The first branch extends at least partially along the first direction, and the second branch extends at least partially along a second direction perpendicular to the first direction.

[0036] For example, the shift register unit also includes a second clock signal connection line, the second clock signal terminal being connected to the output circuit via the second clock signal connection line, wherein the second clock signal connection line extends at least partially along a first direction, and a first branch of the first clock signal line is located between the second clock signal connection line and the control circuit.

[0037] For example, the shift register unit also includes a first voltage regulator circuit and a second pull-down circuit. The second pull-down circuit is located along a second direction on the side of the first pull-down circuit away from the second clock signal connection line. At least a portion of the first voltage regulator circuit is located between the second pull-down circuit and the second clock signal connection line.

[0038] For example, the first voltage regulator circuit includes a first capacitor, which includes a first portion and a second portion. The first portion is located between a first pull-down circuit and a second pull-down circuit and extends along a first direction. The second portion is located between the first portion and the output circuit and extends along a second direction.

[0039] For example, the shift register unit also includes a second capacitor and a third capacitor, wherein the third capacitor, the second capacitor and the first capacitor are arranged along a first direction, and the first part of the first capacitor, the second capacitor and the third capacitor are substantially the same in size in a second direction.

[0040] According to another aspect of this disclosure, a gate drive circuit is provided, including N shift register units as described above, wherein the N shift register units are cascaded, wherein the input signal terminal of the nth stage shift register unit is connected to the output signal terminal of the (n-1)th stage shift register unit, and the reset signal terminal of the nth stage shift register unit is connected to the output signal terminal of the (n+1)th stage shift register unit, wherein N is an integer greater than 1, and 1 < n < N.

[0041] For example, the gate drive circuit further includes a first clock signal line and a second clock signal line, wherein the first clock signal line is configured to receive a first clock signal and the second clock signal line is configured to receive a second clock signal; wherein, in two adjacent shift register units, the first clock signal terminal of one shift register unit is connected to the first clock signal line and the second clock signal terminal is connected to the second clock signal line; the first clock signal terminal of the other shift register unit is connected to the second clock signal line and the second clock signal terminal is connected to the first clock signal line.

[0042] For example, during the period when the first clock signal is high, the second clock signal is low; during the period when the second clock signal is high, the first clock signal is low.

[0043] According to another aspect of this disclosure, a control method for the above-described shift register unit is provided, comprising: during an input period, an input circuit provides a signal from an input signal terminal to a pull-up node under the control of a first clock signal terminal; a control circuit provides a signal from a control voltage terminal to a pull-down node under the control of the first clock signal terminal, and provides a signal from the first clock signal terminal to the pull-down node under the control of the pull-up node; during an output period, an output circuit provides a signal from a second clock signal terminal to an output signal terminal under the control of the pull-up node, a control circuit provides a signal from the first clock signal terminal to the pull-down node under the control of the pull-up node, and disconnects the control voltage terminal from the pull-down node under the control of the first clock signal terminal; during a reset period, a reset circuit provides a signal from a reference signal terminal to a pull-up node under the control of a reset signal terminal, a control circuit disconnects the first clock signal terminal from the pull-down node under the control of the pull-up node, and provides a signal from the control voltage terminal to the pull-down node under the control of the first clock signal terminal; and during a hold period, a first pull-down circuit provides a signal from a reference signal terminal to a pull-up node under the control of the pull-down node and the second clock signal terminal. Attached Figure Description

[0044] Figure 1 shows a schematic block diagram of a shift register unit according to an embodiment of the present disclosure.

[0045] Figure 2 shows a circuit diagram of a shift register unit according to an embodiment of the present disclosure.

[0046] Figure 3 shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure.

[0047] Figure 4 shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure.

[0048] Figure 5 shows a signal timing diagram of a shift register unit according to an embodiment of the present disclosure.

[0049] Figure 6A shows a schematic diagram of the working principle of the control circuit of a shift register unit.

[0050] Figure 6B shows a signal simulation diagram of the pull-up node, pull-down node, and output signal terminal of a shift register unit.

[0051] Figure 6C shows a simulation diagram of the voltage and current of the pull-up node of a shift register unit.

[0052] Figure 7A shows a schematic diagram of the working principle of the control circuit of a shift register unit.

[0053] Figure 7B shows a signal simulation diagram of the pull-up node, pull-down node, and output signal terminal of the shift register unit according to an embodiment of the present disclosure.

[0054] Figure 7C shows a simulation diagram of the voltage and current of the pull-up node of the shift register unit according to an embodiment of the present disclosure.

[0055] Figure 8 shows a signal simulation diagram of a shift register unit according to an embodiment of the present disclosure.

[0056] Figure 9 shows a schematic block diagram of a gate drive circuit according to an embodiment of the present disclosure.

[0057] Figures 10A to 10C show plan layout diagrams of shift register units according to embodiments of the present disclosure. Detailed Implementation

[0058] While this disclosure will be fully described with reference to the accompanying drawings containing preferred embodiments, it should be understood before this description that those skilled in the art can modify the disclosure described herein to obtain the technical effects of this disclosure. Therefore, it should be understood that the above description is a broad disclosure to those skilled in the art and is not intended to limit the exemplary embodiments described herein.

[0059] Furthermore, in the following detailed description, numerous specific details are set forth for ease of explanation to provide a thorough understanding of the embodiments disclosed herein. However, it will be apparent that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and apparatuses are illustrated to simplify the figures.

[0060] Figure 1 shows a schematic block diagram of a shift register unit according to an embodiment of the present disclosure.

[0061] As shown in Figure 1, the shift register unit includes an input circuit 110, an output circuit 120, a control circuit 130, and a first pull-down circuit 140.

[0062] The input circuit 110 connects the input signal terminal In, the first clock signal terminal CLKB, and the pull-up node PU of the shift register unit, and is used to provide the signal of the input signal terminal In to the pull-up node PU under the control of the first clock signal terminal CLKB.

[0063] The output circuit 120 connects the output signal terminal Out, the second clock signal terminal CLK, and the pull-up node PU of the shift register unit, and is used to provide the signal of the second clock signal terminal CLK to the output signal terminal Out under the control of the pull-up node PU.

[0064] The control circuit 130 is connected to the control voltage terminal VDD, the first clock signal terminal CLKB, the pull-up node PU, and the pull-down node PD of the shift register unit. It is used to provide the signal of the control voltage terminal VDD to the pull-down node PD under the control of the first clock signal terminal CLKB, and to provide the signal of the first clock signal terminal CLKB to the pull-down node PD under the control of the pull-up node PU.

[0065] The first pull-down circuit 140 connects the pull-up node PU, the pull-down node PD, the second clock signal terminal CLK, and the reference signal terminal VGL of the shift register unit, and is used to provide the signal of the reference signal terminal VGL to the pull-up node PU under the control of the pull-down node PD and the second clock signal terminal CLK.

[0066] In the embodiments of this disclosure, the input circuit can provide the signal of the input signal terminal In to the pull-up node PU under the control of the first clock signal terminal CLKB. The control circuit can provide the signal of the control voltage terminal VDD to the pull-down node PD under the control of the first clock signal terminal CLKB, and provide the signal of the first clock signal terminal CLKB to the pull-down node PD under the control of the pull-up node PU. Thus, during the period when the pull-up node PU is at an active level, the control circuit can discharge the pull-down node PD using the signal of the first clock signal terminal CLKB, and simultaneously disconnect the control voltage terminal VDD from the pull-down node PD using the signal of the first clock signal terminal CLKB. This effectively eliminates the quiescent current flowing through the control circuit, thereby reducing the risk of damage to the devices in the control circuit due to excessive quiescent current. Furthermore, since the first pull-down circuit is controlled not only by the pull-down node PD but also by the second clock signal terminal CLK, during the period when both the pull-up node PU and the pull-down node PD are at active levels, the first pull-down circuit can use the signal of the second clock signal terminal CLK to block the influence of the pull-down node PD on the pull-up node PU, thereby preventing leakage current in the pull-up node PU.

[0067] Figure 2 shows a circuit diagram of a shift register unit according to an embodiment of the present disclosure. As shown in Figure 2, the shift register unit includes an input circuit 210, an output circuit 220, a control circuit 230, and a first pull-down circuit 240. The description of the input circuit, output circuit, control circuit, first pull-down circuit, and reset circuit 260 with reference to Figure 1 also applies to this embodiment.

[0068] As shown in Figure 2, the input circuit 210 includes transistor M1 (first transistor). The gate of transistor M1 is connected to the first clock signal terminal CLKB, the first terminal of transistor M1 is connected to the input signal terminal In, and the second terminal of transistor M1 is connected to the pull-up node PU.

[0069] The output circuit 220 includes transistor M3 (the fourteenth transistor) and capacitor C1 (the fourth capacitor). The gate of transistor M3 is connected to the pull-up node PU, the first terminal of transistor M3 is connected to the second clock signal terminal CLK, and the second terminal of transistor M3 is connected to the output signal terminal Out. The first terminal of capacitor C1 is connected to the second terminal of transistor M3, and the second terminal of capacitor C1 is connected to the gate of transistor M3.

[0070] The control circuit 230 includes transistors M5 (third transistor) and M6 (fourth transistor). The gate of transistor M5 is connected to the first clock signal terminal CLKB, the first terminal of transistor M5 is connected to the control voltage terminal VDD, and the second terminal of transistor M5 is connected to the pull-down node PD. The gate of transistor M6 is connected to the pull-up node PU, the first terminal of transistor M6 is connected to the first clock signal terminal CLKB, and the second terminal of transistor M6 is connected to the pull-down node PD. In some embodiments, the control circuit 230 may further include transistor M9 (fifth transistor), the second terminal of transistor M6 may be connected to the pull-down node PD via transistor M9, wherein the gate of transistor M9 is connected to the control voltage terminal VDD, the first terminal of transistor M9 is connected to the second terminal of transistor M6, and the second terminal of transistor M9 is connected to the pull-down node PD.

[0071] The first pull-down circuit 240 includes an isolation sub-circuit 2401 and a pull-down sub-circuit 2402. The isolation sub-circuit 2401 is connected between the pull-down sub-circuit 2402 and the pull-up node PU, and is used to turn on or off under the control of the second clock signal terminal CLK. The pull-down sub-circuit 2402 is connected between the isolation sub-circuit 2401 and the reference signal terminal VGL, and is used to provide the signal from the reference signal terminal VGL to the isolation sub-circuit 2401 under the control of the pull-down node PD. For example, as shown in FIG2, the isolation sub-circuit 2401 may include a transistor M7 (ninth transistor), the gate of which is connected to the second clock signal terminal CLK, the first terminal of which is connected to the pull-down sub-circuit, and the second terminal of which is connected to the pull-up node PU. The pull-down circuit 2402 may include a transistor M8 (tenth transistor), the gate of which is connected to the pull-down node PD, the first terminal of which is connected to the reference signal terminal VGL, and the second terminal of which is connected to the first terminal of which is connected to the transistor M7.

[0072] In some embodiments, as shown in FIG2, the shift register unit may further include a reset circuit 260. The reset circuit 260 is connected to the reset signal terminal Rst, the pull-up node PU, and the reference signal terminal VGL of the shift register unit, and is used to provide the signal of the reference signal terminal VGL to the pull-up node PU under the control of the reset signal terminal Rst. For example, the reset circuit 260 may include transistor M2 (the sixteenth transistor M2), the gate of transistor M2 is connected to the reset signal terminal Rst, the first terminal of transistor M2 is connected to the reference signal terminal VGL, and the second terminal of transistor M2 is connected to the pull-up node PU.

[0073] In some embodiments, as shown in FIG2, the shift register unit may further include a second pull-down circuit 270. The second pull-down circuit 270 is connected to the pull-down node PD, the output signal terminal Out, and the reference signal terminal VGL of the shift register unit, and is used to provide the signal of the reference signal terminal VGL to the output signal terminal Out under the control of the pull-down node PD. For example, the second pull-down circuit 270 may include a transistor M10 (the twenty-second transistor), the gate of the transistor M10 is connected to the pull-down node PD, the first terminal of the transistor M10 is connected to the reference signal terminal VGL, and the second terminal of the transistor M10 is connected to the output signal terminal Out.

[0074] In some embodiments, as shown in FIG2, the shift register unit may further include a first voltage regulator circuit 250. The first voltage regulator circuit 250 is connected between pull-up nodes PU and is used to stabilize the potential of the pull-up nodes PU. For example, the first voltage regulator circuit 250 may include a capacitor Cpu (first capacitor), the first terminal of which is connected to the power supply signal terminal VGH or the reference signal terminal VGL of the shift register unit, and the second terminal of which is connected to the pull-up node PU.

[0075] Figure 3 shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure.

[0076] As shown in Figure 3, the shift register unit also includes an input circuit 310, an output circuit 320, a control circuit, a first pull-down circuit 340, a second pull-down circuit 370, and a reset circuit 360. In the example of Figure 3, unlike Figure 2, the pull-down nodes include a first pull-down node PD1 and a second pull-down node PD2; the control voltage terminals include a first control voltage terminal VDD1 and a second control voltage terminal VDD2; and the output signal terminals include a first output signal terminal Gout and a second output signal terminal Out_C. Correspondingly, the structures of each circuit are also different. A detailed description will follow with reference to Figure 3.

[0077] The input circuit 310 includes transistors M1a (first transistor) and M1b (second transistor). The gates of transistors M1a and M1b are connected to the first clock signal terminal CLKB, the first terminal of transistor M1a is connected to the input signal terminal In, the second terminal of transistor M1a is connected to the first terminal of transistor M1b, and the second terminal of transistor M1b is connected to the pull-up node PU.

[0078] The control circuit includes a first control circuit 3301 and a second control circuit 3302.

[0079] The first control circuit 3301 is connected to the first control voltage terminal VDD1, the first pull-down node PD1, the pull-up node PU, and the first clock signal terminal CLKB. It is used to provide the signal of the first control voltage terminal VDD1 to the first pull-down node PD1 under the control of the first clock signal terminal CLKB, and to provide the signal of the first clock signal terminal CLKB to the first pull-down node PD1 under the control of the pull-up node PU. For example, the first control circuit 3301 may include transistors M5a (third transistor), M6a (fourth transistor), and M9a (fifth transistor). The gate of transistor M5a is connected to the first clock signal terminal CLKB, the first terminal of transistor M5a is connected to the first control voltage terminal VDD1, and the second terminal of transistor M5a is connected to the first pull-down node PD1. The gate of transistor M6a is connected to the pull-up node PU, the first terminal of transistor M6a is connected to the first clock signal terminal CLKB, the second terminal of transistor M6a is connected to the first pull-down node PD1 via transistor M9a, the gate of transistor M9a is connected to the first control voltage terminal VDD1, the first terminal of transistor M9a is connected to the second terminal of transistor M6a, and the second terminal of transistor M9a is connected to the first pull-down node PD1.

[0080] The second control circuit 3302 is connected to the second control voltage terminal VDD2, the second pull-down node PD2, the pull-up node PU, and the first clock signal terminal CLKB. It is used to provide the signal of the second control voltage terminal VDD2 to the first pull-down node PD1 under the control of the first clock signal terminal CLKB, and to provide the signal of the first clock signal terminal CLKB to the second pull-down node PD2 under the control of the pull-up node PU. For example, the second control circuit 3302 may include transistors M5b (sixth transistor), M6b (seventh transistor), and M9b (eighth transistor). The gate of transistor M5b is connected to the first clock signal terminal CLKB, the first terminal of transistor M5b is connected to the second control voltage terminal VDD2, and the second terminal of transistor M5b is connected to the second pull-down node PD2. The gate of transistor M6b is connected to the pull-up node PU, the first terminal of transistor M6b is connected to the first clock signal terminal CLKB, and the second terminal of transistor M6b is connected to the second pull-down node PD2 via transistor M9b. The gate of transistor M9b is connected to the second control voltage terminal VDD2, the first terminal of transistor M9b is connected to the second terminal of transistor M6b, and the second terminal of transistor M9b is connected to the second pull-down node PD2.

[0081] The output circuit 320 may include a first output circuit 3201 and a second output circuit 3202. The first output circuit 3201 is connected to the first output signal terminal Gout, and the second output circuit 3202 is connected to the second output signal terminal Out_C. The output signal generated by the first output circuit 3201 at the first output signal terminal Gout can be provided to other shift registers to realize the cascading of shift registers, and the output signal generated by the second output circuit 3202 at the second output signal terminal Out_C can be provided to each sub-pixel to realize display driving.

[0082] As shown in Figure 3, the first output circuit 3201 may include transistor M3 (the fourteenth transistor) and capacitor C1 (the fourth capacitor), and the second output circuit 3202 may include transistor M13 (the fifteenth transistor) and capacitor C2 (the fifth capacitor). The gate of transistor M3 is connected to the pull-up node PU, the first terminal of transistor M3 is connected to the second clock signal terminal CLK, and the second terminal of transistor M3 is connected to the first output signal terminal Gout. The first terminal of capacitor C1 is connected to the second terminal of transistor M3, and the second terminal of capacitor C1 is connected to the gate of transistor M3. The gate of transistor M13 is connected to the pull-up node PU, the first terminal of transistor M13 is connected to the second clock signal terminal CLK, and the second terminal of transistor M13 is connected to the second output signal terminal Out_C. The first terminal of capacitor C2 is connected to the second terminal of transistor M13, and the second terminal of capacitor C2 is connected to the gate of transistor M13. Transistor M13 can be the same as transistor M3, for example, having the same threshold voltage, and capacitor C2 can be the same as capacitor C1, for example, having the same capacitance value, to ensure that the output signals generated by the first output circuit 3201 and the second output circuit 3202 are substantially consistent.

[0083] The reset circuit 360 includes transistors M2a (the sixteenth transistor) and M2b (the seventeenth transistor). The gate of transistor M2a is connected to the reset signal terminal Rst, the first terminal of transistor M2a is connected to the reference signal terminal LVGL via the seventeenth transistor, and the second terminal of transistor M2a is connected to the pull-up node PU. The gate of transistor M2a is connected to the reset signal terminal Rst, the first terminal of transistor M2b is connected to the reference signal terminal LVGL, and the second terminal of transistor M2b is connected to the first terminal of transistor M2a.

[0084] The first pull-down circuit 340 includes an isolation sub-circuit and a pull-down sub-circuit. The isolation sub-circuit may include transistor M7 (ninth transistor), whose gate is connected to the second clock signal terminal CLK, whose first terminal is connected to the pull-down sub-circuit, and whose second terminal is connected to the pull-up node PU. The pull-down sub-circuit may include transistors M8Aa (tenth transistor), M8Ab (eleventh transistor), M8Ba (twelfth transistor), and M8Bb (thirteenth transistor). The gates of transistors M8Aa and M8Ab are connected to the first pull-down node PD1, the first terminal of transistor M8Ab is connected to the reference signal terminal LVGL, the second terminal of transistor M8Ab is connected to the first terminal of M8Aa, and the second terminal of transistor M8Aa is connected to the first terminal of transistor M7. The gates of transistors M8Ba and M8Bb are connected to the second pull-down node PD2, the first terminal of transistor M8Bb is connected to the reference signal terminal LVGL, the second terminal of transistor M8Bb is connected to the first terminal of transistor M8Ba, and the second terminal of transistor M8Ba is connected to the first terminal of transistor M7.

[0085] The second pull-down circuit 370 includes transistors M11a (the twenty-second transistor), M11b (the twenty-third transistor), M10a (the twenty-fourth transistor), and M10b (the twenty-fifth transistor). The gate of transistor M11a is connected to the first pull-down node PD1, its first terminal is connected to the reference signal terminal VGL, and its second terminal is connected to the first output signal terminal Gout. The gate of transistor M11b is connected to the second pull-down node PD2, its first terminal is connected to the reference signal terminal VGL, and its second terminal is connected to the first output signal terminal Gout. The gate of transistor M10a is connected to the first pull-down node PD1, its first terminal is connected to the reference signal terminal LVGL, and its second terminal is connected to the second output signal terminal Out_C. The gate of transistor M10b is connected to the second pull-down node PD2, its first terminal is connected to the reference signal terminal LVGL, and its second terminal is connected to the second output signal terminal Out_C.

[0086] In some embodiments, the shift register unit may further include a first leakage protection circuit 380. The first leakage protection circuit 380 is connected to the first leakage protection node CBD, the power signal terminal VGH, and the output signal terminal (e.g., the second output signal terminal Out_C) of the shift register unit, and is used to provide the signal from the power signal terminal VGH to the first leakage protection node CBD under the control of the signal from the output signal terminal. For example, the first leakage protection circuit 380 includes a transistor M1c (the twentieth transistor), the gate of which is connected to the output signal terminal Out_C, the first terminal of which is connected to the power signal terminal VGH, and the second terminal of which is connected to the first leakage protection node CBD. At least one of the input circuit 310, the reset circuit 360, and the first pull-down circuit 340 may be connected to the first leakage protection node CBD. For example, in Figure 3, the second terminal of transistor M1a and the first terminal of transistor M1b are connected to the first leakage protection node CBD, the first terminal of transistor M2a and the second terminal of transistor M2b are connected to the first leakage protection node CBD, the second terminal of transistor M8Aa and the first terminal of transistor M8Ab are connected to the first leakage protection node, and the second terminal of transistor M8Ba and the first terminal of transistor M8Bb are connected to the first leakage protection node. The first leakage protection circuit 380 can provide a stable high level at the first leakage protection node CBD, thereby causing leakage in the circuit connected to the leakage protection node. For example, when the output signal terminal Out_C outputs a high-level output signal, the first clock signal terminal CLKB is low, the pull-up node PU is high, and the input signal terminal In is low. The low level of the first clock signal terminal CLKB disconnects transistors M1a and M1b. At this time, since the pull-up node PU is high and In is low, there is a large voltage difference between In and PU, which causes leakage in transistors M1a and M1b. By configuring transistor M1c, a high level of VGH can be provided to node CBD between transistors M1a and M1b during the generation of the output signal, thereby reducing the voltage difference across transistors M1a or M1b and preventing leakage current. Based on the same principle, the connection between CBD and the first pull-down circuit 340 and / or the reset circuit 360 can also provide corresponding leakage current prevention, which will not be elaborated here.

[0087] In the above embodiments, the voltages of the first control voltage terminal VDD1 and the second control voltage terminal VDD2 are alternately set. For example, for a period of time, the first control voltage terminal VDD1 is at a constant high level, and the second control voltage terminal VDD2 is at a constant low level; for another period of time, the first control voltage terminal VDD1 is at a constant low level, and the second control voltage terminal VDD2 is at a constant high level. This setting allows the first control circuit 3301 and the second control circuit 3302 to operate alternately, thereby preventing the transistors in the control circuit from having their lifespan reduced due to prolonged operation. In some embodiments, the alternation period of the first control voltage terminal VDD1 and the second control voltage terminal VDD2 can be one frame or multiple frames.

[0088] In the above embodiments, two reference signal terminals LVGL and VGL are provided. Both LVGL and VGL are used to receive a reference voltage, which can be a constant low level. In some embodiments, the voltage of the reference signal terminal LVGL can be lower than the voltage of the reference signal terminal VGL. The second pull-down circuit 370 may include a first sub-circuit and a second sub-circuit. The first sub-circuit includes transistors M11a and M11b for pulling down the first output signal terminal Out_C; the second sub-circuit includes transistors M10a and M10b for pulling down the second output signal terminal Gout. In some embodiments, the first sub-circuit of the second pull-down circuit 370 can be connected to the reference signal terminal VGL, and the second sub-circuit can be connected to the reference signal terminal VGL. By connecting the first and second sub-circuits of the second pull-down circuit 370 to different reference signal terminals, mutual interference between them can be reduced. In some embodiments, as shown in FIG4, the first sub-circuit of the second pull-down circuit 370 can be connected to the reference signal terminal LVGL, while other circuits (such as the second sub-circuit of the second pull-down circuit 370, the first pull-down circuit 340, the control circuits 3301, 3302, and the reset circuit 360) are connected to the reference signal terminal LVGL. In this way, the influence of other circuits in the shift register unit on the output of the first output signal terminal can be avoided. Since the output signal of the first output signal terminal is used to drive the sub-pixels for display, this connection method further improves the stability of the output signal generated by the first output circuit.

[0089] Figure 4 shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure. As shown in Figure 4, similar to Figure 3, the shift register unit also includes an input circuit 310, an output circuit 320, a control circuit, a first pull-down circuit 340, and a second pull-down circuit 370. The description of the input circuit, output circuit, control circuit, first pull-down circuit, and second pull-down circuit with reference to Figure 3 above also applies to this embodiment. For ease of explanation, the differences will be described in detail below.

[0090] As shown in Figure 4, unlike Figure 3, the shift register unit also includes a first voltage regulator circuit 350. The first voltage regulator circuit 350 is connected between the pull-up node and the power supply signal terminal or the reference signal terminal to stabilize the potential of the pull-up node PU. For example, the first voltage regulator circuit 350 includes a capacitor Cpu (first capacitor). The first terminal of the capacitor Cpu is connected to the power supply signal terminal VGH or the reference signal terminal LVGL of the shift register unit (connected to the power supply signal terminal VGH in Figure 4), and the second terminal of the capacitor Cpu is connected to the pull-up node PU.

[0091] In some embodiments, as shown in FIG4, the shift register unit may include a second voltage regulator circuit 390 in addition to the first voltage regulator circuit 350. The second voltage regulator circuit 390 is connected between the pull-down nodes PD1 and PD2 and the reference signal terminal LVGL, and is used to stabilize the potential of the pull-down nodes PD1 and PD2. For example, the second voltage regulator circuit 390 may include capacitors Cpd1 (second capacitor) and Cpd2 (third capacitor), wherein the first terminal of capacitor Cpd1 is connected to the reference signal terminal LVGL, the second terminal of capacitor Cpd1 is connected to the first pull-down node PD1, the first terminal of capacitor Cpd2 is connected to the reference signal terminal LVGL, and the second terminal of capacitor Cpd2 is connected to the second pull-down node PD2. However, the above is merely an example, and the embodiments of this disclosure are not limited thereto. For example, the second voltage regulator circuit 390 may include one of capacitors Cpd1 and Cpd2. As another example, when the shift register unit includes a single pull-down node, such as for the shift register unit shown in FIG2, the second voltage regulator circuit 390 may include a capacitor connected to the single pull-down node PD.

[0092] In some embodiments, as shown in FIG4, the shift register unit may further include a reset circuit 360'. Unlike the reset circuit 360 in FIG3, the reset circuit 360' may include a first reset circuit and a second reset circuit. The first reset circuit includes transistors M2a (the sixteenth transistor) and M2b (the seventeenth transistor), and the second reset circuit includes transistors M14a (the eighteenth transistor) and M14b (the nineteenth transistor). The connection method of transistors M2a and M2b is the same as in FIG3, and will not be repeated here. The gate of transistor M14a is connected to the total reset signal terminal T_Rst of the shift register unit. The first terminal of transistor M14a is connected to the reference signal terminal via transistor M14b, and the second terminal of transistor M14a is connected to the pull-up node PU. The gate of transistor M14b is connected to the total reset signal terminal T_Rst. The first terminal of transistor M14b is connected to the reference signal terminal LVGL, and the second terminal of transistor M14b is connected to the first terminal of transistor M14a. The first reset circuit is used for cascading connection, and the second reset circuit is used for overall reset. For example, the reset signal terminal Rst connected to the first reset circuit of one shift register unit can be connected to the output signal terminal of another shift register unit, allowing the shift register unit to be reset under the control of the output signal of the other shift register unit, thereby realizing the cascading connection between shift register units. The common reset signal terminal T_Rst connected to the second reset circuits of each shift register unit can receive a common reset signal, also referred to here as the total reset signal. Thus, when the total reset signal arrives, each shift register unit is reset.

[0093] In some embodiments, as shown in FIG4, the shift register unit may include a second leakage protection circuit 391 in addition to the first leakage protection circuit 380 described above. The second leakage protection circuit 391 is connected to the second leakage protection node CBC, the power supply signal terminal VGH, and the output signal terminal Out_C of the shift register unit, and is used to provide the signal from the power supply signal terminal VGH to the second leakage protection node CBC under the control of the signal from the output signal terminal Out_C. For example, the second leakage protection circuit may include a transistor M0 (the twenty-first transistor), the gate of which is connected to the output signal terminal Out_C, the first terminal of which is connected to the power supply signal terminal VGH, and the second terminal of which is connected to the second leakage protection node CBC. The input circuit 310 may be connected to the first leakage protection node, and at least one of the reset circuit 360' and the first pull-down circuit 340 may be connected to the second leakage protection node CBC. For example, in Figure 4, the second terminal of transistor M1a and the first terminal of transistor M1b are connected to the first leakage protection node; the second terminal of transistor M2a and the first terminal of transistor M2b are connected to the second leakage protection node CBC; the second terminal of transistor M14a and the first terminal of transistor M14b are connected to the second leakage protection node CBC; the second terminal of transistor M8Aa and the first terminal of transistor M8Ab are connected to the second leakage protection node CBC; and the second terminal of transistor M8Ba and the first terminal of transistor M8Bb are connected to the second leakage protection node CBC. The working principle of the second leakage protection circuit 391 is similar to that of the first leakage protection circuit 380, and will not be described again here. By providing the first leakage protection circuit 380 and the second leakage protection circuit 391, the leakage protection node of the input circuit 310 is made independent of the leakage protection nodes of other circuits (the first pull-down circuit 340 and / or the reset circuit 360'), thereby enhancing the leakage protection effect of each circuit.

[0094] This disclosure also provides a control method for a shift register unit, applicable to the shift register units of any of the above embodiments. During the input phase, the input circuit, under the control of the first clock signal terminal, provides the signal from the input signal terminal to the pull-up node; the control circuit, under the control of the first clock signal terminal, provides the signal from the control voltage terminal to the pull-down node, and under the control of the pull-up node, provides the signal from the first clock signal terminal to the pull-down node. During the output phase, the output circuit, under the control of the pull-up node, provides the signal from the second clock signal terminal to the output signal terminal; the control circuit, under the control of the pull-up node, provides the signal from the first clock signal terminal to the pull-down node, and under the control of the first clock signal terminal, disconnects the control voltage terminal from the pull-down node. During the reset phase, the reset circuit, under the control of the reset signal terminal, provides the signal from the reference signal terminal to the pull-up node; the control circuit, under the control of the pull-up node, disconnects the first clock signal terminal from the pull-down node, and under the control of the first clock signal terminal, provides the signal from the control voltage terminal to the pull-down node. During the hold phase, the first pull-down circuit, under the control of the pull-down node and the second clock signal terminal, provides the signal from the reference signal terminal to the pull-up node. The control method of the shift register unit of this disclosure embodiment will now be described with reference to FIG5.

[0095] Figure 5 shows a signal timing diagram of a shift register unit according to an embodiment of the present disclosure. This timing diagram is applicable to the shift register unit of any of the above embodiments, and the shift register unit of Figure 3 will be used as an example for description below.

[0096] During time period P1, the input signal terminal In is at a high level, the first clock signal terminal CLKB is at a high level, the second clock signal terminal CLK is at a low level, the first control voltage terminal VDD1 is at a high level, the second control voltage terminal VDD2 is at a low level, and the reset signal terminal Rst is at a low level.

[0097] Pull-up node PU: The high level of the first clock signal terminal CLKB and the input signal terminal In turns on the transistor M1, which charges the pull-up node PU, thus making the pull-up node PU high.

[0098] First pull-down node PD1: The high level of the first clock signal terminal CLKB turns on transistor M5a, and the high level of the pull-up node PU turns on transistor M6a. Since the first control voltage terminal VDD1 is at a high level, the first pull-down node PD1 is charged through transistors M5a and M6a, thus making the first pull-down node PD1 high.

[0099] Second pull-down node PD2: The high level of the first clock signal terminal CLKB turns on transistor M5b, the high level of the pull-up node PU turns on transistor M6a, and since the second control voltage terminal VDD2 is low, transistor M9b is turned off, and the second pull-down node PD2 remains low.

[0100] The second output signal terminal Out_C: The high level of the pull-up node PU turns on transistor M13, and the high level of the first pull-down node PD1 turns on transistor M10a. Since the second clock signal terminal CLK is low and the reference signal terminal LVGL is low, the second output signal terminal Out_C is discharged through transistors M13 and M10A, and thus the second output signal terminal Out_C is low.

[0101] First output signal terminal Gout: The high level of the pull-up node PU turns on transistor M3, and the high level of the first pull-down node PD1 turns on transistor M11a. Since the second clock signal terminal CLK is low and VGL is low, the first output signal terminal Gout is discharged through transistors M3 and M11a, and the first output signal terminal Gout is low.

[0102] During this period P1, the input signal is provided to the pull-up node PU. Therefore, period P1 is also called the input period. During this input period, the first pull-down node PD1 and the second pull-down node PD2 remain at a high level, and transistor M8 is in the on state. To maintain the pull-up node PU at a high level, as shown in Figure 3, transistor M7 is provided, and the second clock signal terminal CLK is connected to the gate of transistor M7. When the input signal at the input signal terminal In is at a high level, the second clock signal terminal CLK is at a low level, transistor M7 is turned off, thereby disconnecting the pull-up node PU from transistors M8Aa, M8Ab, M8Ba, and M8Bb. In this way, even if the high level of the first pull-down node PD1 and the second pull-down node PD2 turns on transistors M8Aa, M8Ab, M8Ba, and M8Bb, it will not pull down the potential of the pull-up node PU. This prevents the high level of the pull-down node from causing leakage in the pull-up node.

[0103] During time period P2, the input signal terminal In is at a low level, the first clock signal terminal CLKB is at a low level, the second clock signal terminal CLK is at a high level, the first control voltage terminal VDD1 is at a high level, the second control voltage terminal VDD2 is at a low level, and the reset signal terminal Rst is at a low level.

[0104] Pull-up node PU: The low level of the first clock signal terminal CLKB turns off transistor M1, and the pull-up node PU remains at a high level.

[0105] First pull-down node PD1: The low level of the first clock signal terminal CLKB turns off transistor M5a, the high level of the pull-up node PU turns on transistor M6a, and the high level of the first control voltage terminal VDD1 turns on transistor M9a. The first pull-down node PD1 is discharged through transistors M6a and M9a, and the first pull-down node PD1 is at a low level.

[0106] Second pull-down node PD2: The low level of the first clock signal terminal CLKB turns off transistor M5b, the high level of the pull-up node PU turns on transistor M6a, the low level of the second control voltage terminal VDD2 turns off transistor M9b, and the second pull-down node PD2 remains at a low level.

[0107] The second output signal terminal Out_C: The high level of the pull-up node PU turns on the transistor M13, and the low level of the first pull-down node PD1 turns off the transistor M10a. Since the second clock signal terminal CLK is at a high level, the second output signal terminal Out_C is charged through the transistor M13, thus making the second output signal terminal Out_C high.

[0108] The first output signal terminal Gout: the high level of the pull-up node PU turns on the transistor M3, and the low level of the first pull-down node PD1 turns off the transistor M11a. Since the second clock signal terminal CLK is at a high level, the first output signal terminal Gout is charged through the transistor M3, thus making the first output signal terminal Gout high.

[0109] During time period P2, as the first output signal terminal Gout changes from low to high, the voltage of the pull-up node PU is pulled to a higher level due to the bootstrap effect of C1. As shown in Figure 5, the bootstrap effect of C1 causes the voltage of the pull-up node PU in time period P2 to rise relative to time period P1. C2 exhibits the same bootstrap effect, which will not be elaborated here.

[0110] The output signal is generated during period P2, hence this period is also called the output period. During this output period, transistor M5a is turned off, while transistors M6a and M9a are turned on. The first pull-down node PD1 is discharged through transistors M6a and M9a, which almost completely eliminates the quiescent current of transistor M5a.

[0111] During time period P3, the input signal terminal In is low, the first clock signal terminal CLKB is high, the second clock signal terminal CLK is low, the first control voltage terminal VDD1 is high, the second control voltage terminal VDD2 is low, and the reset signal terminal Rst is high.

[0112] Pull-up node PU: The first clock signal terminal CLKB and the reset signal terminal Rst are both high, and the input signal terminal In is low. Therefore, transistors M1a, M1b, M2a and M2b are turned on, and the pull-up node PU is discharged through transistors M1a, M1b, M2a and M2b, thus pulling up node PU to a low level.

[0113] First pull-down node PD1: The high level of the first clock signal terminal CLKB turns on the transistor M5a, and the low level of the pull-up node PU turns off the transistor M6a. Since the first control voltage terminal VDD1 is at a high level, the first pull-down node PD1 is charged through the transistor M5a, making the first pull-down node PD1 at a high level.

[0114] Second pull-down node PD2: The high level of the first clock signal terminal CLKB turns on transistor M5b, and the high level of the pull-up node PU turns on transistor M6a. Since the second control voltage terminal VDD2 is low, transistor M9b is turned off, and the second pull-down node PD2 remains low.

[0115] The second output signal terminal Out_C: The low level of the pull-up node PU turns off the transistor M13, and the high level of the first pull-down node PD1 turns on the transistor M10a. Since the reference signal terminal LVGL is low, the second output signal terminal Out_C is discharged through the transistor M10A, and the second output signal terminal Out_C is low.

[0116] First output signal terminal Gout: The low level of the pull-up node PU turns off transistor M3, and the high level of the first pull-down node PD1 turns on transistor M11a. Since VGL is low, the first output signal terminal Gout is discharged through transistor M11a, and the first output signal terminal Gout is low.

[0117] The pull-up node PU was reset during time period P3, so this time period is also called the reset time period.

[0118] During time period P4, the input signal terminal In is at a low level, the first clock signal terminal CLKB is at a low level, the second clock signal terminal CLK is at a high level, the first control voltage terminal VDD1 is at a high level, the second control voltage terminal VDD2 is at a low level, and the reset signal terminal Rst is at a low level.

[0119] Pull-up node PU: Both the first clock signal terminal CLKB and the reset signal terminal Rst are at low level, so transistors M1a, M1b, M2a and M2b are turned off. Since the second clock signal terminal CLK is at high level and the first pull-down node PD1 is at high level, the pull-up node PU is discharged through transistors M7, M8Aa, M8Ab, M8Ba and M8Bb, so that the pull-up node PU is kept at low level.

[0120] First pull-down node PD1: The low level of the first clock signal terminal CLKB turns off transistor M5a, the low level of the pull-up node PU turns off transistor M6a, and the first pull-down node PD1 remains at a high level.

[0121] Second pull-down node PD2: The low level of the first clock signal terminal CLKB turns on transistor M5b, the low level of the pull-up node PU turns off transistor M6a, and the low level of the second control voltage terminal VDD2 turns off transistor M9b. The second pull-down node PD2 remains at a low level.

[0122] The second output signal terminal Out_C: The low level of the pull-up node PU turns off the transistor M13, and the high level of the first pull-down node PD1 turns on the transistor M10a. The second output signal terminal Out_C is discharged through the transistor M10A, and the second output signal terminal Out_C remains at a low level.

[0123] The first output signal terminal Gout: the low level of the pull-up node PU turns off the transistor M3, and the high level of the first pull-down node PD1 turns on the transistor M11a. The first output signal terminal Gout is discharged through the transistor M11a, and the first output signal terminal Gout remains at a low level.

[0124] Signals at each node are maintained during time period P4, hence this time period is also called the hold period.

[0125] During time period P5, the input signal terminal In is low, the first clock signal terminal CLKB is high, the second clock signal terminal CLK is low, the first control voltage terminal VDD1 is high, the second control voltage terminal VDD2 is low, and the reset signal terminal Rst is low.

[0126] Pull-up node PU: The first clock signal terminal CLKB is high and the input signal terminal In is low, so transistors M1a and M1b are turned on, and the pull-up node PU is discharged through transistor M1, so the pull-up node PU continues to remain at a low level.

[0127] First pull-down node PD1: A high level at the first clock signal terminal CLKB turns on the flat transistor M5a, and a low level at the pull-up node PU turns off the transistor M6a. The first pull-down node PD1 is charged through the transistor M5a, and the first pull-down node PD1 continues to maintain a high level.

[0128] Second pull-down node PD2: The high level of the first clock signal terminal CLKB turns on transistor M5b, the low level of the pull-up node PU turns off transistor M6a, and the low level of the second control voltage terminal VDD2 turns off transistor M9b. The second pull-down node PD2 is discharged through transistor M5b, and the second pull-down node PD2 continues to remain at a low level.

[0129] The second output signal terminal Out_C: The low level of the pull-up node PU turns off the transistor M13, and the high level of the first pull-down node PD1 turns on the transistor M10a. The second output signal terminal Out_C is discharged through the transistor M10A, and the second output signal terminal Out_C continues to remain at a low level.

[0130] The first output signal terminal Gout: the low level of the pull-up node PU turns off the transistor M3, and the high level of the first pull-down node PD1 turns on the transistor M11a. The first output signal terminal Gout is discharged through the transistor M11a, and the first output signal terminal Gout continues to remain at a low level.

[0131] The signals at each node remain in place during period P5, hence this period is also called the hold period.

[0132] At this point, the shift register unit has completed its signal output.

[0133] In a traditional shift register unit, the control circuit operates as shown in Figure 6A. The pull-up node PU, pull-down node PD, and first output signal terminal Gout of the shift register unit have the signal waveforms shown in Figure 6B. As shown in Figures 6A and 6B, the gate and first electrode of transistor M5 in the control circuit are both connected to the power supply signal terminal VGH, and the first electrode of transistor M6 is connected to the reference signal terminal VGL. Since VGH is high, transistor M5 is always in the on state. When the pull-up node PU changes from low to high, transistor M6 turns on. For electronic devices such as electronic paper EPDs, a high driving voltage is required. For example, the voltage difference between the power supply signal terminal VGH and the reference signal terminal VGL of the shift register unit is approximately 70V or higher. Thus, when the pull-up node PU is high, both transistors M5 and M6 are in the on state, generating a high quiescent current between the power supply signal terminal VGH and the reference signal terminal VGL. As shown in Figure 6C, during the period when the pull-up node PU is high, the quiescent current through the pull-up node PU reaches approximately 91μA. The increase in quiescent current makes transistor M5 more susceptible to burnout, thus affecting the display.

[0134] In contrast, the shift register unit of this disclosure, by setting a first clock signal terminal, a second clock signal terminal, an input circuit, a control circuit, and a first pull-down circuit, can substantially eliminate the quiescent current flowing through the control circuit during the voltage bootstrap of the pull-up node PU, thereby reducing the risk of damage to the control circuit due to excessive quiescent current. The following description uses the shift register unit of FIG2 as an example, referring to FIGS. 7A to 7C. As shown in FIG. 7A, in the shift register unit of this disclosure embodiment, the gate of transistor M5 and the first terminal of transistor M6 in the control circuit are both connected to the first clock signal terminal CLKB. As shown in FIG. 7B, during time period P2, the pull-up node PU is at a high level and the first clock signal terminal CLKB is at a low level. Transistor M5 is turned off and transistor M6 is turned on. This allows the pull-down node PD to discharge through the turned-on transistor M6 throughout time period P2, that is, during the voltage bootstrap of the pull-up node PU, thus substantially eliminating the quiescent current. As shown in Figure 7C, the quiescent current flowing through transistor M5 can reach several nA, for example, approximately 2 nA (2.65 nA in the example of Figure 7C), and the transient current is approximately 208 μA. Comparing Figures 6C and 7C, it can be seen that the quiescent current flowing through transistor M5 in a conventional shift register unit is 0.9 mA, while the shift register unit of this disclosure embodiment can reduce this quiescent current to approximately 0.1 nA, greatly reducing the risk of device burnout. Although the shift register unit of Figure 2 has been described above as an example, the content described with reference to Figures 7A to 7C is applicable to the shift register units of any of the above embodiments, and will not be repeated here.

[0135] The signal timing shown in Figure 5 can also be applied to the shift register unit shown in Figure 4. In this case, the operation of the shift register unit in Figure 4 during periods P1 to P5 is the same as described above, and it can also reduce the quiescent current, thereby reducing the risk of circuit damage, which will not be elaborated here. In addition, the shift register unit shown in Figure 4, due to the inclusion of a capacitor Cpu, can also reduce the bootstrap voltage of the pull-up node PU, thereby improving the reliability of the shift register unit. A detailed explanation will follow with reference to Figures 4, 5, and 8.

[0136] Referring to Figures 4 and 5, capacitor C1 is connected between the pull-up node PU and the first output signal terminal Gout, and capacitor Cpu is connected between the pull-up node PU and the power signal terminal VGH. Therefore, the voltage V at the pull-up node PU is... PU The following equations must be satisfied:

[0137] V PU =VGH-Vth_M1+ΔV PU

[0138] ΔV PU=C1 / (C1+C PU )*ΔGout (1)

[0139] ΔGout=ΔV CLK

[0140] Where Vth_M1 represents the threshold voltage of transistor M1 (a combination of M1a and M1b in the example of Figure 4), C1 represents the capacitance value of capacitor C1, and C PU This represents the capacitance value of the CPU, ΔV. CLK This represents the voltage amplitude of the second clock signal at the second clock signal terminal CLK. In some embodiments, ΔV CLK =VGH-VGL, where VGH represents the power supply voltage at the power supply signal terminal and VGL represents the reference voltage at the reference signal terminal VGL.

[0141] As mentioned above, in some display devices such as electronic paper, the voltage difference between VGH and VGL is very large, for example, it can reach over 70V. This causes the pull-up node PU to be pulled up to an excessively high voltage due to the bootstrap effect when the shift register unit generates an output signal. Embodiments of this disclosure enable the adjustment of the bootstrap voltage of the pull-up node PU in time period P2 by setting the capacitance value of capacitor Cpu. Figure 8 shows the voltages of the pull-up node PU and the first output signal terminal Gout when the capacitance values ​​of capacitor Cpu are 0pF, 1pF, 2pF, and 5pF. As shown in Figure 8, in time period P2, when the capacitance value of capacitor Cpu is 0pF, the voltage V of the pull-up node PU is... PU It is approximately 107V; with the capacitance of the CPU being 1pF, the voltage V at the pull-up node PU is... PU It is approximately 91V; with the capacitance of the CPU being 2pF, the voltage V at the pull-up node PU is... PU It is approximately 81V; with the capacitance of the CPU being 5pF, the voltage V at the pull-up node PU is... PU It is approximately 64V. Therefore, during period P2, that is, during the voltage bootstrap phase of the pull-up node PU, the larger the capacitance value of capacitor Cpu, the higher the voltage V of the pull-up node PU. PU The smaller. Thus, by setting C... PU The capacitance value can be adjusted to lower the bootstrap voltage of the pull-up node PU during time period P2, thereby improving the reliability of the shift register unit. Meanwhile, as shown in Figure 8, when the capacitance Cpu is 0pF, 1pF, 2pF, and 5pF, the first output signal terminal Gout remains relatively stable at approximately 37V, indicating that changes in the capacitance value of Cpu have virtually no impact on the voltage of the first output signal terminal Gout.

[0142] Figure 9 shows a schematic block diagram of a gate drive circuit according to an embodiment of the present disclosure.

[0143] As shown in Figure 9, the gate drive circuit includes N shift register units GOA(1), GOA(2), ..., GOA(N), which can be implemented as any of the shift register units described in the above embodiments. The N shift register units are cascaded together. The input signal terminal of the nth-stage shift register unit is connected to the output signal terminal of the (n-1)th-stage shift register unit, and the reset signal terminal of the nth-stage shift register unit is connected to the output signal terminal of the (n+1)th-stage shift register unit, where N is an integer greater than 1, and 1 < n < N. In Figure 9, each shift register unit has a first output signal terminal Gout and a second output signal terminal Out_C. The first output signal terminal Gout can be connected to each sub-pixel to provide a driving signal to the sub-pixel, and the second output signal terminal Out_C is connected to other shift register units to achieve cascading connection of the shift register units. For example, the input signal terminal In of shift register unit GOA(1) can receive a start signal G_STV to start the first-stage output. The Out_C of shift register unit GOA(1) is connected to the In of shift register unit GOA(2), the Out_C of shift register unit GOA(2) is connected to the In of shift register unit GOA(3), the Out_C of shift register unit GOA(3) is connected to the In of shift register unit GOA(4), and so on. The Out_C of shift register unit GOA(2) is connected to the Rst of shift register unit GOA(1), the Out_C of shift register unit GOA(3) is connected to the Rst of shift register unit GOA(2), the Out_C of shift register unit GOA(4) is connected to the Rst of shift register unit GOA(3), and so on. In this way, each shift register unit can generate an output under the control of the output signal of the previous shift register unit and be reset under the control of the output signal of the next shift register unit, so that each shift register unit generates output signals Gout(1), Gout(2), ..., Gout(N) step by step.

[0144] In some embodiments, the gate drive circuit further includes a first clock signal line CLK1 and a second clock signal line CLK2. The first clock signal line CLK1 is configured to receive a first clock signal, and the second clock signal line CLK2 is configured to receive a second clock signal. In adjacent shift register units, the first clock signal terminal CLKB of one shift register unit is connected to the first clock signal line CLK1, and the second clock signal terminal CLK is connected to the second clock signal line CLK2. The first clock signal terminal CLKB of another shift register unit is connected to the second clock signal line CLK2, and the second clock signal terminal CLK is connected to the first clock signal line CLK1. In some embodiments, the second clock signal is low during the period when the first clock signal is high, and the first clock signal is low during the period when the second clock signal is high. This ensures that the high-level pulses of the first clock signal terminal CLKB and the second clock signal terminal CLK do not overlap. For example, in the example shown in Figure 5, the clock signal waveforms of the first clock signal terminal CLKB and the second clock signal terminal CLK are the same but have a phase difference, preventing them from being at a high level simultaneously. In some embodiments, the first clock signal and the second clock signal can be inversely related.

[0145] Figures 10A to 10C show plan layout diagrams of shift register units according to embodiments of the present disclosure. For example, these plan layout diagrams can be applied to shift register units of any of the above embodiments, and the shift register unit of Figure 4 will be used as an example for the following description.

[0146] Figures 10A to 10C illustrate the various parts of the shift register unit along a first direction. As shown in Figures 10A to 10C, the input circuit includes transistors M1a and M1b, the control circuit includes transistors M5a, M5b, M6a, M6b, M9a, and M9b, the output circuit includes transistor M3, capacitor C1, transistor M13, and capacitor C2, and the first pull-down circuit includes transistor M7 and transistors M8Aa, M8Ab, M8Ba, and M8Bb. The control circuit, input circuit, and first pull-down circuit are arranged sequentially along the first direction (horizontal direction in the figures, from left to right).

[0147] As shown in Figures 10A to 10C, multiple signal lines are arranged on one side of the shift register unit, including but not limited to start signal lines STV1, STV3, clock signal lines CLK1, CLK3, CLK5 and CLK7, power signal line VGH, total reset signal line T_Rst, first control voltage line VDD1, second control voltage line VDD2, reference signal line LVGL, etc. The first clock signal terminal CLKB of the shift register unit is connected to clock signal line CLK1 to receive the first clock signal, and the second clock signal terminal CLK is connected to clock signal line CLK3 to receive the second clock signal. The power signal terminal VGH of the shift register unit is connected to power signal line VGH to receive the power supply voltage. The shift register unit also includes a first clock signal connection line with a first branch CLKB_L1 and a second branch CLKB_L2. The first clock signal terminal is electrically connected to the input circuit through the first branch CLKB_L1 and electrically connected to the control circuit through the second branch CLKB_L2. The first branch CLKB_L1 extends at least partially along a first direction, and the second branch CLKB_L2 extends at least partially along a second direction. The first direction is different from the second direction, for example, it may be perpendicular to the second direction. In some embodiments, when transistors M1c and M10 are provided, the first branch CLKB_L1 may extend partly along the first direction and partly along the second direction to achieve a bent pattern, thereby bypassing transistors M1c and M10 to connect to the input circuit.

[0148] In the layout diagrams of Figures 10C to 10C, unlike Figure 4, the capacitor Cpu is connected to the reference signal terminal LVGL instead of the power signal terminal VGH. Connecting the capacitor Cpu to the reference signal terminal LVGL can also achieve the adjustment of the PU bootstrap voltage, so that the voltage of the pull-up node PU also satisfies the above equation (1), which will not be repeated here.

[0149] In some embodiments, the shift register unit may further include a second clock signal connection line CLK_L, the second clock signal terminal CLK being connected to the output circuit (e.g., transistors M3 and M13 in the output circuit) via the second clock signal connection line CLK_L, wherein the second clock signal connection line CLK_L extends at least partially along a first direction, and the first branch CLKB_L1 of the first clock signal line is located between the second clock signal connection line CLK_L and the control circuit (the control circuit includes transistors M5a, M5b, M6a, and M6b).

[0150] In some embodiments, the shift register unit may further include a first voltage regulator circuit and a second pull-down circuit. For example, the first voltage regulator circuit may include a capacitor Cpu, and the second pull-down circuit may include transistors M10a, M10b, M11a, and M11b. The second pull-down circuit is located along a second direction on the side of the first pull-down circuit away from the second clock signal connection line CLK_L, and at least a portion of the first voltage regulator circuit is located between the second pull-down circuit and the second clock signal connection line CLK_L. For example, the capacitor Cpu includes a first portion Cpu_1 and a second portion Cpu_2. The first portion Cpu_1 is located between the first pull-down circuit (e.g., a combination of M8Aa and M8Ab in the first pull-down circuit) and the second pull-down circuit (e.g., M11a in the second pull-down circuit), and may extend along a first direction. The second portion Cpu_2 is located between the first portion Cpu_1 and the output circuit (e.g., C1 in the output circuit), and may extend along a second direction.

[0151] In some embodiments, the shift register unit further includes capacitors Cpd1 and Cpd2. Capacitors Cpd2, Cpd1, and Cpu are arranged along a first direction; for example, Cpd1 may be located between Cpd2 and Cpu in the first direction. The dimensions of Cpd1, Cpd2, and the first portion of Cpu in a second direction may be substantially the same. In some embodiments, the dimension of the first portion of Cpu, Cpu_1, in the second direction may be substantially the same as the dimension of the second portion, Cpu_2, in the first direction.

[0152] According to embodiments of this disclosure, the transistors in the shift register unit may be oxide transistors, and in some embodiments may be top-gate or bottom-gate transistors. The active layer of the oxide transistor may include metal oxide materials and / or metal oxide nitride materials. In some embodiments, the metal oxide materials include, but are not limited to, one or more of the following: indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxide (In-free OS), rare earth doped oxide (Ln-OS), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O. In some embodiments, the metal oxide nitride material includes, but is not limited to, zinc nitride, indium nitride, gallium nitride, tin nitride, cadmium nitride, aluminum nitride, germanium nitride, titanium nitride, silicon nitride, or combinations thereof. The active layer material can be amorphous, partially crystalline, single-crystal, or polycrystalline, and can also be a single-layer or multi-layer structure. In some cases, when the threshold voltage of the oxide transistor is below 0V, negative bias occurs, which may lead to leakage. The embodiments of this disclosure effectively alleviate this problem by providing a leakage protection circuit. Taking the shift register unit of Figures 3 and 4 as an example, assuming that transistors M1a and M1b are both oxide transistors, when the shift register unit generates an output, for example, during time period P2 in Figure 5, transistors M1a and M1b are in the off state, the pull-up node PU is at a high level, and the input signal terminal In is at a low level. At this time, a high voltage difference appears between the first terminal of transistor M1a and the second terminal of M1b, causing transistors M1a and M1b to be negatively biased, and leakage occurs at the pull-up node PU. By configuring transistor M1c, the power supply voltage at the power signal terminal VGH is supplied to the first leakage protection node CBD. This reduces the voltage difference across transistor M1b, effectively preventing leakage at the pull-up node PU. The leakage protection principle of transistor M0 is similar to that of M1c, and will not be elaborated here.

[0153] The shift register unit, gate drive circuit, and control method of the shift register unit provided in this disclosure are applicable to various display devices. For display devices that require high voltage drive signals, such as electronic paper devices (EPDs), the stability of the drive signal and the reliability of the drive circuit can be improved.

[0154] Those skilled in the art will understand that the embodiments described above are exemplary and can be improved upon. The structures described in the various embodiments can be freely combined without causing any conflict in structure or principle.

[0155] After a detailed description of the preferred embodiments of this disclosure, those skilled in the art will clearly understand that various changes and modifications can be made without departing from the scope and spirit of the appended claims, and that this disclosure is not limited to the implementation of the exemplary embodiments described in the specification.

Claims

1. A shift register unit, comprising: The input circuit connects the input signal terminal, the first clock signal terminal, and the pull-up node of the shift register unit, and is used to provide the signal from the input signal terminal to the pull-up node under the control of the first clock signal terminal. The output circuit connects the output signal terminal, the second clock signal terminal, and the pull-up node of the shift register unit, and is used to provide the signal of the second clock signal terminal to the output signal terminal under the control of the pull-up node. A control circuit is connected to the control voltage terminal, the first clock signal terminal, the pull-up node, and the pull-down node of the shift register unit. It is used to provide the signal of the control voltage terminal to the pull-down node under the control of the first clock signal terminal, and to provide the signal of the first clock signal terminal to the pull-down node under the control of the pull-up node. The first pull-down circuit connects the pull-up node, pull-down node, second clock signal terminal, and reference signal terminal of the shift register unit, and is used to provide the signal of the reference signal terminal to the pull-up node under the control of the pull-down node and the second clock signal terminal.

2. The shift register unit according to claim 1, further comprising: A first voltage regulator circuit is connected between the pull-up node and the power signal terminal or the reference signal terminal to stabilize the potential of the pull-up node.

3. The shift register unit according to claim 2, wherein, The first voltage regulator circuit includes a first capacitor, the first terminal of which is connected to the power supply signal terminal or the reference signal terminal of the shift register unit, and the second terminal of which is connected to the pull-up node.

4. The shift register unit according to any one of claims 1 to 3, wherein, The input circuit includes a first transistor, the gate of which is connected to the first clock signal terminal, the first terminal of which is connected to the input signal terminal, and the second terminal of which is connected to the pull-up node.

5. The shift register unit according to any one of claims 1 to 3, wherein, The input circuit includes a first transistor and a second transistor. The gates of the first transistor and the second transistor are connected to the first clock signal terminal. The first terminal of the first transistor is connected to the input signal terminal. The second terminal of the first transistor is connected to the first terminal of the second transistor. The second terminal of the second transistor is connected to the pull-up node.

6. The shift register unit according to any one of claims 1 to 5, wherein, The control circuit includes a third transistor and a fourth transistor. The gate of the third transistor is connected to the first clock signal terminal, the first terminal of the third transistor is connected to the control voltage terminal, and the second terminal of the third transistor is connected to the pull-down node; The gate of the fourth transistor is connected to the pull-up node, the first terminal of the fourth transistor is connected to the first clock signal terminal, and the second terminal of the fourth transistor is connected to the pull-down node.

7. The shift register unit according to claim 6, wherein, The control circuit further includes a fifth transistor, the second terminal of the fourth transistor is connected to the pull-down node via the fifth transistor, wherein the gate of the fifth transistor is connected to the control voltage terminal, the first terminal of the fifth transistor is connected to the second terminal of the fourth transistor, and the second terminal of the fifth transistor is connected to the pull-down node.

8. The shift register unit according to any one of claims 1 to 5, wherein, The control circuit includes a first control circuit and a second control circuit; the pull-down node includes a first pull-down node and a second pull-down node; and the control voltage terminal includes a first control voltage terminal and a second control voltage terminal. The first control circuit is connected to the first control voltage terminal, the first pull-down node, the pull-up node and the first clock signal terminal, and is used to provide the signal of the first control voltage terminal to the first pull-down node under the control of the first clock signal terminal, and to provide the signal of the first clock signal terminal to the first pull-down node under the control of the pull-up node; The second control circuit is connected to the second control voltage terminal, the second pull-down node, the pull-up node and the first clock signal terminal, and is used to provide the signal of the second control voltage terminal to the first pull-down node under the control of the first clock signal terminal, and to provide the signal of the first clock signal terminal to the second pull-down node under the control of the pull-up node.

9. The shift register unit according to claim 8, wherein, The first control circuit includes a third transistor, a fourth transistor, and a fifth transistor. The gate of the third transistor is connected to the first clock signal terminal, the first terminal of the third transistor is connected to the first control voltage terminal, and the second terminal of the third transistor is connected to the first pull-down node. The gate of the fourth transistor is connected to the pull-up node, the first terminal of the fourth transistor is connected to the first clock signal terminal, the second terminal of the fourth transistor is connected to the first pull-down node via the fifth transistor, the gate of the fifth transistor is connected to the first control voltage terminal, the first terminal of the fifth transistor is connected to the second terminal of the fourth transistor, and the second terminal of the fifth transistor is connected to the first pull-down node. The second control circuit includes a sixth transistor, a seventh transistor, and an eighth transistor. The gate of the sixth transistor is connected to the first clock signal terminal, the first terminal of the sixth transistor is connected to the second control voltage terminal, and the second terminal of the sixth transistor is connected to the second pull-down node. The gate of the seventh transistor is connected to the pull-up node, the first terminal of the seventh transistor is connected to the first clock signal terminal, and the second terminal of the seventh transistor is connected to the second pull-down node via the eighth transistor. The gate of the eighth transistor is connected to the second control voltage terminal, the first terminal of the eighth transistor is connected to the second terminal of the seventh transistor, and the second terminal of the eighth transistor is connected to the second pull-down node.

10. The shift register unit according to any one of claims 1 to 9, wherein, The first pull-down circuit includes an isolation sub-circuit and a pull-down sub-circuit. in, The isolation sub-circuit is connected between the pull-down sub-circuit and the pull-up node, and is used to turn on or off under the control of the second clock signal terminal; The pull-down sub-circuit is connected between the isolation sub-circuit and the reference signal terminal, and is used to provide the signal from the reference signal terminal to the isolation sub-circuit under the control of the pull-down node.

11. The shift register unit according to claim 10, wherein, The isolation sub-circuit includes a ninth transistor, the gate of which is connected to the second clock signal terminal, the first terminal of which is connected to the pull-down sub-circuit, and the second terminal of which is connected to the pull-up node.

12. The shift register unit according to claim 11, wherein, The pull-down sub-circuit includes a tenth transistor, the gate of which is connected to the pull-down node, the first terminal of which is connected to the reference signal terminal, and the second terminal of which is connected to the first terminal of the ninth transistor.

13. The shift register unit according to claim 11, wherein, The pull-down node includes a first pull-down node and a second pull-down node, and the pull-down sub-circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor. The gates of the tenth transistor and the eleventh transistor are connected to the first pull-down node, the first terminal of the eleventh transistor is connected to the reference signal terminal, the second terminal of the eleventh transistor is connected to the first terminal of the tenth transistor, and the second terminal of the tenth transistor is connected to the first terminal of the ninth transistor. The gates of the twelfth transistor and the thirteenth transistor are connected to the second pull-down node. The first terminal of the thirteenth transistor is connected to the reference signal terminal. The second terminal of the thirteenth transistor is connected to the first terminal of the twelfth transistor. The second terminal of the twelfth transistor is connected to the first terminal of the ninth transistor.

14. The shift register unit according to any one of claims 1 to 13 further includes a second voltage regulator circuit, the second voltage regulator circuit being connected between the pull-down node and the reference signal terminal for stabilizing the potential of the pull-down node.

15. The shift register unit according to claim 14, wherein, The pull-down node includes a first pull-down node and a second pull-down node. The second voltage regulator circuit includes a second capacitor and a third capacitor. The first terminal of the second capacitor is connected to the reference signal terminal, the second terminal of the second capacitor is connected to the first pull-down node, the first terminal of the third capacitor is connected to the reference signal terminal, and the second terminal of the third capacitor is connected to the second pull-down node.

16. The shift register unit according to any one of claims 1 to 15, wherein, The output circuit includes a fourteenth transistor and a fourth capacitor. The gate of the fourteenth transistor is connected to the pull-up node, the first terminal of the fourteenth transistor is connected to the second clock signal terminal, and the second terminal of the fourteenth transistor is connected to the output signal terminal. The first terminal of the fourth capacitor is connected to the second terminal of the fourteenth transistor, and the second terminal of the fourth capacitor is connected to the gate of the fourteenth transistor.

17. The shift register unit according to claim 16, wherein, The output signal terminal includes a first output signal terminal and a second output signal terminal, wherein the second terminal of the fourteenth transistor is connected to the first output signal terminal; The output circuit also includes a fifteenth transistor and a fifth capacitor. The gate of the fifteenth transistor is connected to the pull-up node, the first terminal of the fifteenth transistor is connected to the second clock signal terminal, and the second terminal of the fifteenth transistor is connected to the second output signal terminal. The first terminal of the fifth capacitor is connected to the second terminal of the fifteenth transistor, and the second terminal of the fifth capacitor is connected to the gate of the fifteenth transistor.

18. The shift register unit according to any one of claims 1 to 17, further comprising: A reset circuit is connected to the reset signal terminal, pull-up node, and reference signal terminal of the shift register unit, and is used to provide the signal from the reference signal terminal to the pull-up node under the control of the reset signal terminal.

19. The shift register unit according to claim 18, wherein, The reset circuit includes a sixteenth transistor, the gate of which is connected to the reset signal terminal, the first terminal of which is connected to the reference signal terminal, and the second terminal of which is connected to the pull-up node.

20. The shift register unit according to claim 19, wherein, The reset circuit includes a sixteenth transistor and a seventeenth transistor. The gate of the sixteenth transistor is connected to the reset signal terminal, the first terminal of the sixteenth transistor is connected to the reference signal terminal via the seventeenth transistor, the second terminal of the sixteenth transistor is connected to the pull-up node, the gate of the seventeenth transistor is connected to the reset signal terminal, the first terminal of the seventeenth transistor is connected to the reference signal terminal, and the second terminal of the seventeenth transistor is connected to the first terminal of the sixteenth transistor.

21. The shift register unit according to claim 20, wherein, The reset circuit also includes an eighteenth transistor and a nineteenth transistor; The gate of the eighteenth transistor is connected to the total reset signal terminal of the shift register unit. The first terminal of the eighteenth transistor is connected to the reference signal terminal via the nineteenth transistor. The second terminal of the eighteenth transistor is connected to the pull-up node. The gate of the nineteenth transistor is connected to the total reset signal terminal. The first terminal of the nineteenth transistor is connected to the reference signal terminal. The second terminal of the nineteenth transistor is connected to the first terminal of the eighteenth transistor.

22. The shift register unit according to any one of claims 1 to 21, further comprising: The first leakage protection circuit is connected to the first leakage protection node, the power signal terminal and the output signal terminal of the shift register unit, and is used to provide the signal of the power signal terminal to the first leakage protection node under the control of the signal of the output signal terminal. Wherein, at least one of the input circuit, the first pull-down circuit, and the reset circuit is connected to the first leakage protection node.

23. The shift register unit according to claim 22, wherein, The first leakage protection circuit includes a twentieth transistor, the gate of which is connected to the output signal terminal, the first terminal of which is connected to the power signal terminal, and the second terminal of which is connected to the first leakage protection node.

24. The shift register unit according to claim 22, wherein, In the input circuit, the second terminal of the first transistor and the first terminal of the second transistor are connected to the first leakage protection node; In the reset circuit, the first terminal of the sixteenth transistor and the second terminal of the seventeenth transistor are connected to the first leakage protection node; In the first pull-down circuit, the second terminal of the tenth transistor and the first terminal of the eleventh transistor are connected to the first leakage protection node, and the second terminal of the twelfth transistor and the first terminal of the thirteenth transistor are connected to the first leakage protection node.

25. The shift register unit according to claim 22, further comprising: The second leakage protection circuit is connected to the second leakage protection node, the power signal terminal, and the output signal terminal of the shift register unit. It is used to provide the signal from the power signal terminal to the second leakage protection node under the control of the signal from the output signal terminal. The input circuit is connected to the first leakage protection node, and at least one of the first pull-down circuit and the reset circuit is connected to the second leakage protection node.

26. The shift register unit according to claim 25, wherein, The second leakage protection circuit includes a twenty-first transistor, the gate of which is connected to the output signal terminal, the first terminal of which is connected to the power signal terminal, and the second terminal of which is connected to the second leakage protection node.

27. The shift register unit according to claim 25, wherein, In the input circuit, the second terminal of the first transistor and the first terminal of the second transistor are connected to the first leakage protection node; In the reset circuit, the second terminal of the sixteenth transistor and the first terminal of the seventeenth transistor are connected to the second leakage protection node, and the first terminal of the eighteenth transistor and the second terminal of the nineteenth transistor are connected to the second leakage protection node. In the first pull-down circuit, the second terminal of the tenth transistor and the first terminal of the eleventh transistor are connected to the second leakage protection node, and the second terminal of the twelfth transistor and the first terminal of the thirteenth transistor are connected to the second leakage protection node.

28. The shift register unit according to any one of claims 1 to 27, further comprising a second pull-down circuit, the second pull-down circuit being connected to the pull-down node, the output signal terminal and the reference signal terminal of the shift register unit, for providing the signal of the reference signal terminal to the output signal terminal under the control of the pull-down node.

29. The shift register unit according to claim 28, wherein, The second pull-down circuit includes a twenty-second transistor, the gate of which is connected to the pull-down node, the first terminal of which is connected to the reference signal terminal, and the second terminal of which is connected to the output signal terminal.

30. The shift register unit according to claim 28, wherein, The drop-down node includes a first drop-down node and a second drop-down node, and the output signal terminal includes a first output signal terminal and a second output signal terminal; The second pull-down circuit includes a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, and a twenty-fifth transistor. The gate of the 22nd transistor is connected to the first pull-down node, the first terminal of the 22nd transistor is connected to the reference signal terminal, and the second terminal of the 22nd transistor is connected to the first output signal terminal. The gate of the 23rd transistor is connected to the second pull-down node, the first terminal of the 23rd transistor is connected to the reference signal terminal, and the second terminal of the 23rd transistor is connected to the first output signal terminal. The gate of the 24th transistor is connected to the first pull-down node, the first terminal of the 24th transistor is connected to the reference signal terminal, and the second terminal of the 24th transistor is connected to the second output signal terminal. The gate of the 25th transistor is connected to the second pull-down node, the first terminal of the 25th transistor is connected to the reference signal terminal, and the second terminal of the 25th transistor is connected to the second output signal terminal.

31. The shift register unit according to any one of claims 1 to 30, wherein, The control circuit, the input circuit, and the first pull-down circuit are arranged along a first direction. The shift register unit further includes a first clock signal connection line having a first branch and a second branch. The first clock signal terminal is electrically connected to the input circuit through the first branch and to the control circuit through the second branch. The first branch extends at least partially along the first direction, and the second branch extends at least partially along a second direction perpendicular to the first direction.

32. The shift register unit according to claim 31 further includes a second clock signal connection line, the second clock signal terminal being connected to the output circuit via the second clock signal connection line, wherein the second clock signal connection line extends at least partially along the first direction, and a first branch of the first clock signal line is located between the second clock signal connection line and the control circuit.

33. The shift register unit according to claim 32, wherein, The shift register unit further includes a first voltage regulator circuit and a second pull-down circuit. The second pull-down circuit is located along a second direction on the side of the first pull-down circuit away from the second clock signal connection line. At least a portion of the first voltage regulator circuit is located between the second pull-down circuit and the second clock signal connection line.

34. [Amended according to Rule 26 02.12.2024] The shift register unit according to claim 33, wherein, The first voltage regulator circuit includes a first capacitor, which includes a first portion and a second portion. The first portion is located between the first pull-down circuit and the second pull-down circuit and extends along a first direction. The second portion is located between the first portion and the output circuit and extends along a second direction.

35. The shift register unit according to claim 34, wherein, The shift register unit further includes a second capacitor and a third capacitor, wherein the third capacitor, the second capacitor, and the first capacitor are arranged along a first direction, and the first part of the first capacitor, the second capacitor, and the third capacitor have substantially the same size in a second direction.

36. A gate driving circuit comprising N shift register units according to any one of claims 1 to 35, wherein the N shift register units are cascaded, wherein the input signal terminal of the nth stage shift register unit is connected to the output signal terminal of the (n-1)th stage shift register unit, and the reset signal terminal of the nth stage shift register unit is connected to the output signal terminal of the (n+1)th stage shift register unit, wherein N is an integer greater than 1, and 1 < n < N.

37. The gate drive circuit according to claim 36, wherein, The gate drive circuit further includes a first clock signal line and a second clock signal line, wherein the first clock signal line is configured to receive a first clock signal and the second clock signal line is configured to receive a second clock signal. In one of the two adjacent shift register units, the first clock signal terminal of one shift register unit is connected to the first clock signal line, and the second clock signal terminal is connected to the second clock signal line; the first clock signal terminal of the other shift register unit is connected to the second clock signal line, and the second clock signal terminal is connected to the first clock signal line.

38. The gate drive circuit according to claim 37, wherein, During the period when the first clock signal is high, the second clock signal is low; during the period when the second clock signal is high, the first clock signal is low.

39. A control method for a shift register unit as described in any one of claims 1 to 35, comprising: During the input period, the input circuit provides the signal from the input signal terminal to the pull-up node under the control of the first clock signal terminal; The control circuit provides the signal from the control voltage terminal to the pull-down node under the control of the first clock signal terminal, and provides the signal from the first clock signal terminal to the pull-down node under the control of the pull-up node; During the output period, the output circuit provides the signal from the second clock signal terminal to the output signal terminal under the control of the pull-up node, and the control circuit provides the signal from the first clock signal terminal to the pull-down node under the control of the pull-up node, and disconnects the control voltage terminal from the pull-down node under the control of the first clock signal terminal. During the reset period, the reset circuit provides the signal from the reference signal terminal to the pull-up node under the control of the reset signal terminal. The control circuit disconnects the first clock signal terminal from the pull-down node under the control of the pull-up node, and provides the signal from the control voltage terminal to the pull-down node under the control of the first clock signal terminal. During the hold period, the first pull-down circuit, under the control of the pull-down node and the second clock signal terminal, provides the signal from the reference signal terminal to the pull-up node.

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