Display substrate and display device

Abstract

The present disclosure provides a display substrate and a display device. The display substrate comprises a substrate, a pixel circuit and a driving module, the substrate comprises a display area and a peripheral area, the pixel circuit is arranged in the display area, and the driving module is arranged in the peripheral area; the driving module comprises a multi-stage driving circuit; the peripheral area comprises a plurality of driving circuit areas; the driving circuit comprises a circuit element, a switching line and a signal line; the circuit element comprises at least one transistor and at least one capacitor; the at least two electrodes of the circuit element are electrically connected through the switching line; and the ratio between the area of the circuit element area where the circuit element is located and the area of the driving circuit area is greater than 0.56 and less than 1. The display substrate disclosed by the present disclosure can realize a narrow frame.

Description

Display substrate and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0002] In related technologies, the overall layout area of ​​the driving circuit is relatively large, and the bezel area formed on the substrate is relatively wide, which affects the user experience of the product. It is necessary to further reduce the layout space of the driving circuit and narrow the bezel.

[0003] Summary of the Invention

[0004] In one aspect, embodiments of this disclosure provide a display substrate, the display substrate including a substrate, pixel circuits, and a driving module, the substrate including a display area and a peripheral area, the pixel circuits being disposed in the display area, and the driving module being disposed in the peripheral area; the driving module including multi-level driving circuits; the peripheral area including multiple driving circuit areas;

[0005] The driving circuit includes circuit elements, adapter lines, and signal lines; the circuit elements include at least one transistor and at least one capacitor; at least two electrodes of the circuit elements are electrically connected through the adapter lines.

[0006] The ratio between the area of ​​the circuit element region where the circuit element is located and the area of ​​the driving circuit region is greater than 0.56 and less than 1.

[0007] Optionally, the contour line of the orthographic projection of the nth-level driving circuit on the substrate that is furthest from the display area is the first contour line, and the contour line of the orthographic projection of the nth-level driving circuit on the substrate that is closest to the display area is the second contour line.

[0008] The outline of the nth stage driving circuit's orthogonal projection onto the substrate that is closest to the (n-1)th stage driving circuit is the third outline.

[0009] The contour line furthest from the (n-1)th stage driving circuit in the orthographic projection of the nth stage driving circuit onto the substrate is the fourth contour line; n is a positive integer.

[0010] The area of ​​the quadrilateral formed by the extensions of the first contour line, the second contour line, the third contour line, and the fourth contour line is the area of ​​the nth-level driving circuit region.

[0011] The nth-level driving circuit is located within the nth-level driving circuit region.

[0012] Optionally, the signal line extends along a first direction;

[0013] The driving circuit includes at least two transistors arranged along a first direction.

[0014] Optionally, the active pattern of the first transistor included in the driving circuit is electrically connected to the active pattern of the second transistor included in the driving circuit through a via, and a first conductive pattern formed on the gate metal layer.

[0015] Optionally, the signal line extends along a first direction;

[0016] The driving circuit includes an active pattern of a third transistor that extends along a second direction, which intersects with the first direction.

[0017] The active patterns of the first transistor and the third transistor are arranged along a first direction.

[0018] Optionally, the driving circuit includes a first node control circuit, a second node control circuit, and a third node control circuit; the first node control circuit is used to control the potential of the first node; the second node control circuit is used to control the potential of the second node; and the third node control circuit is used to control the potential of the third node according to the potential of the second node.

[0019] The first node control circuit includes the first transistor and the second transistor; the active patterns of the first transistor and the second transistor are both electrically connected to the first node.

[0020] The third node control circuit includes the third transistor, and the active pattern of the third transistor is electrically connected to the third node.

[0021] Optionally, the driving circuit further includes an output reset circuit; the output reset circuit is electrically connected to the third node and the driving output terminal respectively, and is used to reset the driving signal provided by the driving output terminal under the control of the potential of the third node;

[0022] The output reset circuit includes a fourth transistor;

[0023] The active pattern of the third transistor is electrically connected to the gate of the fourth transistor through a via and a second conductive pattern formed on the gate metal layer.

[0024] Optionally, the second node control circuit includes a fifth transistor;

[0025] The gate of the first transistor and the gate of the fifth transistor are electrically connected through a third conductive pattern formed on the gate metal layer;

[0026] The third conductive pattern is electrically connected to the active pattern of the second transistor through a via.

[0027] Optionally, the second node control circuit includes a fifth transistor;

[0028] The signal line includes a first clock signal line; the second transistor is electrically connected to the first clock signal line.

[0029] The orthographic projection of the active pattern of the second transistor onto the substrate at least partially overlaps with the orthographic projection of the first clock signal line onto the substrate;

[0030] The orthographic projection of the active pattern of the third transistor onto the substrate at least partially overlaps with the orthographic projection of the first clock signal line onto the substrate.

[0031] Optionally, the signal line extends along a first direction; the first direction intersects with a second direction;

[0032] The gate of the first transistor and the gate of the fifth transistor both extend along the second direction;

[0033] The gates of the first transistor and the fifth transistor are arranged along a second direction.

[0034] Optionally, the gate of the second transistor is disposed on the side of the gate of the fifth transistor away from the gate of the third transistor.

[0035] Optionally, the signal line extends along a first direction; the second node control circuit further includes at least one transistor;

[0036] The second node control circuit includes at least a portion of transistors whose active patterns are arranged along a first direction.

[0037] Optionally, the signal line includes a second clock signal line;

[0038] The active pattern of at least some of the transistors in the second node control circuit is projected onto the substrate in a positive projection that at least partially overlaps with the positive projection of the second clock signal line onto the substrate.

[0039] Optionally, the capacitor includes a first plate and a second plate; the first plate of the capacitor includes a first plate portion and a second plate portion.

[0040] The first electrode portion, the second electrode portion, and the second electrode portion are arranged sequentially along a direction away from the substrate;

[0041] The orthographic projections of the first electrode portion onto the substrate, the orthographic projections of the second electrode portion onto the substrate, and the orthographic projections of the second electrode portion onto the substrate at least partially overlap.

[0042] Optionally, the signal line extends along a first direction; the signal line includes a first voltage line;

[0043] The driving circuit includes an output circuit and an output reset circuit; the output circuit is electrically connected to the first node, the driving output terminal, and the first voltage line respectively, and is used to control the connection between the driving output terminal and the first voltage line under the control of the potential of the first node; the output reset circuit is electrically connected to the third node and the driving output terminal respectively, and is used to reset the driving signal provided by the driving output terminal under the control of the potential of the third node.

[0044] The transistors included in the output circuit and the transistors included in the output reset circuit are arranged along a first direction.

[0045] Optionally, the driving circuit includes a first node control circuit, a second node control circuit, and a third node control circuit;

[0046] The first node control circuit is electrically connected to the first clock signal line;

[0047] The transistors included in the first node control circuit and the transistors included in the second node control circuit that are electrically connected to the first clock signal line are arranged along a first direction.

[0048] Optionally, the driving circuit includes a first node control circuit, a second node control circuit, and a third node control circuit;

[0049] The transistors included in the second node control circuit are arranged along a first direction with the transistors included in the third node control circuit.

[0050] Optionally, the orthographic projection of the active pattern of the transistors included in the output circuit onto the substrate at least partially overlaps with the orthographic projection of the first voltage line onto the substrate.

[0051] Optionally, the gate of the transistor is formed on a first gate metal layer; the connecting line is formed on a first source-drain metal layer; and the signal line is formed on a second source-drain metal layer.

[0052] Optionally, the gate of the transistor is formed on a first gate metal layer; the transition line is formed on a second gate metal layer;

[0053] The conductive pattern formed on the first gate metal layer can be electrically connected to the conductive pattern formed on the second gate metal layer through a via.

[0054] Optionally, the signal line is formed on a first source / drain metal layer or a second source / drain metal layer;

[0055] At least a portion of the orthographic projection of the signal line onto the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the driving circuit onto the substrate.

[0056] Optionally, the gate of the transistor is formed on a first gate metal layer; the transition line is formed on a second gate metal layer or a first source / drain metal layer;

[0057] The conductive pattern formed on the first gate metal layer can be electrically connected to the conductive pattern formed on the second gate metal layer through a via;

[0058] The signal line is formed in the second source / drain metal layer.

[0059] Optionally, the orthographic projection of at least one capacitor included in the driving circuit onto the substrate at least partially overlaps with the orthographic projection of at least one transistor included in the driving circuit onto the substrate.

[0060] Optionally, the signal line is formed on the second source / drain metal layer; the active pattern of the transistor is formed on the semiconductor layer; the active pattern can be directly electrically connected to the conductive pattern formed on the second source / drain metal layer through a via.

[0061] Optionally, the driving circuit includes a first node control circuit, a second node control circuit, a third node control circuit, a fourth node control circuit, and a fifth node control circuit.

[0062] The first node control circuit is electrically connected to the first node and the first clock signal line respectively, and is used to control the potential of the first node according to the first clock signal provided by the first clock signal line;

[0063] The second node control circuit is electrically connected to the first clock signal line and the second node respectively, and is used to control the potential of the second node under the control of the first clock signal;

[0064] The third node control circuit is electrically connected to the first node, the second node, the third node, the sixth node, and the second clock signal line, respectively. It is used to control the potential of the third node according to the potential of the second node, control the potential of the fourth node under the control of the potential of the first node, control the connection or disconnection between the sixth node and the second clock signal line under the control of the potential of the third node, and control the potential of the third node according to the potential of the sixth node.

[0065] The fourth node control circuit is electrically connected to both the first node and the fourth node, and is used to control the potential of the fourth node according to the potential of the first node.

[0066] The fifth node control circuit is electrically connected to the second clock signal line, the fourth node, the fifth node, the second node, and the first voltage line, respectively. It is used to control the potential of the fifth node according to the potential of the fourth node and the second clock signal provided by the second clock signal line, and to control the potential of the fifth node according to the first voltage signal provided by the first voltage line under the control of the second clock signal and the potential of the second node.

[0067] The transistors included in the first node control circuit are arranged along a first direction;

[0068] The transistors included in the first node control circuit and the transistors included in the second node are arranged along a first direction;

[0069] The transistors included in the third node control circuit are arranged along a first direction;

[0070] The transistors included in the fourth node control circuit are arranged along the first direction with the transistors included in the third node control circuit.

[0071] The transistors in the fifth node control circuit are arranged along a first direction.

[0072] Optionally, the active pattern of at least two transistors electrically connected to the second clock signal line is integrally formed in the fifth node control circuit; and / or, the active pattern of the transistors electrically connected to the first voltage line is integrally formed in the fifth node control circuit.

[0073] Optionally, the driving circuit includes a first node control circuit, a second node control circuit, a third node control circuit, a fourth node control circuit, and a fifth node control circuit.

[0074] The first node control circuit is electrically connected to the first node and the first clock signal line respectively, and is used to control the potential of the first node according to the first clock signal provided by the first clock signal line;

[0075] The second node control circuit is electrically connected to the first clock signal line, the second node, and the seventh node, respectively, and is used to control the potential of the second node and the potential of the seventh node under the control of the first clock signal.

[0076] The third node control circuit is electrically connected to the first node, the first voltage line, the second clock signal line, the sixth node, the seventh node, the eighth node, and the third node, respectively. It is used to control the potential of the third node according to the potential of the first node, control the potential of the eighth node according to the potential of the seventh node, control the potential of the third node according to the potential of the eighth node, control the potential of the sixth node under the control of the potential of the first node and the eighth node, control the potential of the eighth node according to the potential of the sixth node, and control the potential of the third node according to the potential of the eighth node.

[0077] The fourth node control circuit is electrically connected to the first node and the fourth node respectively, and is used to control the potential of the fourth node according to the potential of the first node;

[0078] The fifth node control circuit is electrically connected to the second clock signal line, the fourth node, the fifth node, the control voltage terminal, and the first node, respectively. It is used to control the potential of the fifth node under the control of the potential of the fourth node, according to the second clock signal provided by the second clock signal line, to control the potential of the second node under the control of the control voltage provided by the control voltage terminal, and to control the potential of the fifth node under the control of the potential of the first node.

[0079] The transistors included in the first node control circuit are arranged along a first direction, and the transistors included in the second node control circuit are arranged along a first direction. The transistors included in the first node control circuit and the transistors included in the second node control circuit are arranged along a first direction.

[0080] The transistors included in the third node control circuit are arranged along a first direction, and the transistors included in the fourth node control circuit and the transistors included in the third node control circuit are arranged along the first direction.

[0081] The transistors in the fifth node control circuit are arranged along a first direction.

[0082] Optionally, the driving circuit further includes an output circuit and an output reset circuit;

[0083] The output circuit is electrically connected to the fifth node and the drive output terminal respectively, and is used to control the drive output terminal to provide a drive signal under the control of the potential of the fifth node;

[0084] The output reset circuit is electrically connected to the third node and the drive output terminal respectively, and is used to reset the drive signal under the control of the potential of the third node;

[0085] The transistors included in the output circuit and the transistors included in the output reset circuit are arranged along a first direction.

[0086] Optionally, the driving circuit includes a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, an output circuit, and an output reset circuit; the first node control circuit includes a first transistor and a second transistor; the third node control circuit includes a third transistor; the output reset circuit includes a fourth transistor; the second node control circuit includes a fifth transistor; the second node control circuit includes a sixth transistor and a seventh transistor; and the output circuit includes an eighth transistor.

[0087] The active pattern of the third transistor extends along the second direction; the first direction intersects the second direction;

[0088] The second and third transistors are arranged along the first direction; the sixth and seventh transistors are arranged along the first direction; the eighth and fourth transistors are arranged along the first direction.

[0089] At least one of the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line has an orthogonal projection on the substrate that at least partially overlaps with the orthogonal projection of the circuit element on the substrate.

[0090] The ratio between the area of ​​the circuit element region and the area of ​​the drive circuit region is greater than or equal to 73% and less than or equal to 77%.

[0091] Optionally, the driving circuit includes a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, an output circuit, and an output reset circuit; the first node control circuit includes a first transistor and a second transistor; the third node control circuit includes a third transistor; the output reset circuit includes a fourth transistor; the second node control circuit includes a fifth transistor; the second node control circuit includes a sixth transistor and a seventh transistor; the output circuit includes an eighth transistor; the active pattern of the third transistor extends along a second direction.

[0092] The gate of the first transistor and the gate of the fifth transistor are electrically connected through a third conductive pattern formed on the gate metal layer; the third conductive pattern is electrically connected to the active pattern of the second transistor through a via.

[0093] The sixth and seventh transistors are arranged along the first direction; the eighth and fourth transistors are arranged along the first direction;

[0094] At least one of the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line has an orthogonal projection on the substrate that at least partially overlaps with the orthogonal projection of the circuit element on the substrate.

[0095] The ratio between the area of ​​the circuit element region and the area of ​​the drive circuit region is greater than or equal to 69% and less than or equal to 75%.

[0096] Optionally, the driving circuit includes a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, an output circuit, and an output reset circuit; the first node control circuit includes a first transistor and a second transistor; the third node control circuit includes a third transistor; the output reset circuit includes a fourth transistor; the second node control circuit includes a fifth transistor; the second node control circuit includes a sixth transistor and a seventh transistor; the output circuit includes an eighth transistor; the active pattern of the third transistor extends along a second direction.

[0097] The second and third transistors are arranged along the first direction; the fifth, sixth, and seventh transistors are arranged along the first square; the eighth and fourth transistors are arranged along the first direction.

[0098] The orthographic projection of at least one of the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line onto the substrate at least partially overlaps with the orthographic projection of the circuit element onto the substrate; the ratio between the area of ​​the circuit element region and the area of ​​the driving circuit region is greater than or equal to 68% and less than or equal to 72%.

[0099] Optionally, the driving circuit includes a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, an output circuit, and an output reset circuit; the first node control circuit includes a first transistor and a second transistor; the third node control circuit includes a third transistor; the output reset circuit includes a fourth transistor; the second node control circuit includes a fifth transistor; the second node control circuit includes a sixth transistor and a seventh transistor; and the output circuit includes an eighth transistor.

[0100] The first transistor, the second transistor, and the fifth transistor are arranged along the first direction; the sixth transistor, the seventh transistor, and the third transistor are arranged along the first direction; and the eighth transistor and the fourth transistor are arranged along the first direction.

[0101] The orthographic projection of at least one of the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line on the substrate at least partially overlaps with the orthographic projection of the circuit element on the substrate; the ratio between the area of ​​the circuit element region and the area of ​​the driving circuit region is greater than or equal to 74% and less than or equal to 80%.

[0102] Optionally, the driving circuit includes a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, an output circuit, and an output reset circuit; the first node control circuit includes a first transistor and a second transistor; the third node control circuit includes a third transistor; the output reset circuit includes a fourth transistor; the second node control circuit includes a fifth transistor; the second node control circuit includes a sixth transistor and a seventh transistor; and the output circuit includes an eighth transistor.

[0103] The sixth and seventh transistors are arranged along the first direction, and the eighth and fourth transistors are arranged along the first direction;

[0104] The orthographic projection of at least one of the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line on the substrate at least partially overlaps with the orthographic projection of the circuit element on the substrate; the ratio between the area of ​​the circuit element region and the area of ​​the driving circuit region is greater than or equal to 65% and less than or equal to 70%.

[0105] Optionally, the driving circuit includes a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, an output circuit, and an output reset circuit; the first node control circuit includes a first transistor and a second transistor; the third node control circuit includes a third transistor; the output reset circuit includes a fourth transistor; the second node control circuit includes a fifth transistor; the second node control circuit includes a sixth transistor and a seventh transistor; the output circuit includes an eighth transistor; the driving circuit further includes a first capacitor and a second capacitor;

[0106] At least one of the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line has an orthogonal projection on the substrate that at least partially overlaps with the orthogonal projection of the circuit element on the substrate.

[0107] A first voltage line, a second voltage line, a first clock signal line, and a second clock signal line are formed on a first source-drain metal layer; a fifth transistor and a third transistor are arranged along a first direction, a sixth transistor and a seventh transistor are arranged along a first direction, and an eighth transistor and a fourth transistor are arranged along a first direction; or, a first voltage line, a second voltage line, a first clock signal line, and a second clock signal line are formed on a second source-drain metal layer; a fifth transistor and a third transistor are arranged along a first direction, a sixth transistor and a seventh transistor are arranged along a first direction, and an eighth transistor and a fourth transistor are arranged along a first direction.

[0108] The ratio between the area of ​​the circuit element region and the area of ​​the drive circuit region is greater than or equal to 61% and less than or equal to 67%.

[0109] Optionally, the driving circuit includes a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, an output circuit, and an output reset circuit; the first node control circuit includes a first transistor and a second transistor; the third node control circuit includes a third transistor; the output reset circuit includes a fourth transistor; the second node control circuit includes a fifth transistor; the second node control circuit includes a sixth transistor and a seventh transistor; the output circuit includes an eighth transistor; the driving circuit further includes a first capacitor and a second capacitor;

[0110] The first voltage line, the second voltage line, the first clock signal line, and the second clock signal line are formed on the second source-drain metal layer;

[0111] The second and third transistors are arranged along the first direction, the fifth, sixth and seventh transistors are arranged along the first direction, and the eighth and fourth transistors are arranged along the first direction;

[0112] At least one of the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line has an orthogonal projection on the substrate that at least partially overlaps with the orthogonal projection of the circuit element on the substrate.

[0113] The ratio between the area of ​​the circuit element region and the area of ​​the drive circuit region is greater than or equal to 79% and less than or equal to 85%.

[0114] Optionally, the driving circuit includes a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, an output circuit, and an output reset circuit; the first node control circuit includes a first transistor and a second transistor; the third node control circuit includes a third transistor; the output reset circuit includes a fourth transistor; the second node control circuit includes a fifth transistor; the second node control circuit includes a sixth transistor and a seventh transistor; the output circuit includes an eighth transistor; the driving circuit further includes a first capacitor and a second capacitor;

[0115] The first voltage line, the second voltage line, the first clock signal line, and the second clock signal line are formed on the second source-drain metal layer;

[0116] The second and third transistors are arranged along the first direction, the fifth, sixth and seventh transistors are arranged along the first direction, and the eighth and fourth transistors are arranged along the first direction;

[0117] At least one of the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line has an orthogonal projection on the substrate that at least partially overlaps with the orthogonal projection of the circuit element on the substrate.

[0118] The ratio between the area of ​​the circuit element region and the area of ​​the drive circuit region is greater than or equal to 87% and less than or equal to 93%.

[0119] Optionally, the driving circuit includes a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, a fourth node control circuit, a fifth node control circuit, an output reset circuit, and an output circuit; the first node control circuit includes a first transistor and a second transistor, the second node control circuit includes a fifth transistor; the third node control circuit includes a ninth transistor, a tenth transistor, and an eleventh transistor; the fourth node control circuit includes a twelfth transistor, the fifth node control circuit includes a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor, the output circuit includes an eighth transistor, the output reset circuit includes a fourth transistor, and the driving circuit further includes a first capacitor, a second capacitor, and a third capacitor;

[0120] At least one of the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line has an orthogonal projection on the substrate that at least partially overlaps with the orthogonal projection of the circuit element on the substrate.

[0121] The first, second, and fifth transistors are arranged along a first direction; the twelfth, tenth, and eleventh transistors extend along the first direction; the third and second capacitors are arranged along the first direction; the fourteenth, fifteenth, and sixteenth transistors are arranged along the first direction; and the eighth and fourth transistors are arranged along the first direction. Alternatively, the first, second, and fifth transistors are arranged along the first direction; the twelfth, tenth, and eleventh transistors are arranged along the first direction; the third and second capacitors are arranged along the first direction; and the fourteenth,... The thirteenth, fifteenth, and sixteenth transistors are arranged along a first direction, and the eighth and fourth transistors are arranged along a first direction; the first plate of the second capacitor includes dissimilarly disposed and electrically connected portions of the first and second plates of the second capacitor, and the first plate of the third capacitor includes dissimilarly disposed and electrically connected portions of the first and second plates of the second capacitor; or, the first, second, seventeenth, and eighteenth transistors are arranged vertically; the twelfth, tenth, and eleventh transistors are arranged vertically, the nineteenth and twentyth transistors are arranged along a first direction, the fourteenth, fifteenth, sixteenth, and twenty-first transistors are arranged along a first direction, and the eighth and fourth transistors are arranged along a first direction;

[0122] The ratio between the area of ​​the circuit element region and the area of ​​the drive circuit region is greater than 56% and less than or equal to 63%.

[0123] In a second aspect, embodiments of this disclosure provide a display device including the display substrate described above. Attached Figure Description

[0124] Figure 1A is a structural diagram of at least one embodiment of the driving circuit;

[0125] Figure 1B is a structural diagram of at least one embodiment of the driving circuit;

[0126] Figure 1C is a circuit diagram of at least one embodiment of the driving circuit;

[0127] Figures 1D and 1E are layout diagrams of the nth stage drive circuit and the (n-1)th stage drive circuit;

[0128] Figure 2 is a layout diagram of at least one embodiment of the driving circuit in at least one embodiment of the present disclosure;

[0129] Figures 3A and 3B are layout diagrams of the semiconductor layer in Figure 2;

[0130] Figure 4 is a layout diagram of the first gate metal layer in Figure 2;

[0131] Figure 5 is a layout diagram of the second gate metal layer in Figure 2;

[0132] Figure 6 is a layout diagram of the third gate metal layer in Figure 2;

[0133] Figure 7 is a layout diagram of the first source / drain metal layer in Figure 2;

[0134] Figure 8A is a layout diagram of the second source / drain metal layer in Figure 2;

[0135] Figure 8B is a stack-up diagram of the semiconductor layer and the first gate metal layer in Figure 2;

[0136] Figure 8C is a stack-up diagram of the first gate metal layer and the second gate metal layer in Figure 2;

[0137] Figure 8D is a stack-up diagram of the second gate metal layer and the third gate metal layer in Figure 2;

[0138] Figure 8E is a stack-up diagram of the third gate metal layer and the first source / drain metal layer in Figure 2;

[0139] Figure 8F is a stack-up diagram of the first source / drain metal layer and the second source / drain metal layer in Figure 2;

[0140] Figure 9 is a layout diagram of at least one embodiment of the driving circuit in at least one embodiment of the present disclosure;

[0141] Figure 10 is a layout diagram of the semiconductor layer in Figure 9;

[0142] Figure 11 is a layout diagram of the first gate metal layer in Figure 9;

[0143] Figure 12 is a layout diagram of the second gate metal layer in Figure 9;

[0144] Figure 13 is a layout diagram of the third gate metal layer in Figure 9;

[0145] Figure 14 is a layout diagram of the first source / drain metal layer in Figure 9;

[0146] Figure 15A is a layout diagram of the second source / drain metal layer in Figure 9;

[0147] Figure 15B is a stack-up diagram of the semiconductor layer and the first gate metal layer in Figure 9;

[0148] Figure 15C is a stack-up diagram of the first gate metal layer and the second gate metal layer in Figure 9;

[0149] Figure 15D is a stack-up diagram of the second gate metal layer and the third gate metal layer in Figure 9;

[0150] Figure 15E is a stack-up diagram of the third gate metal layer and the first source / drain metal layer in Figure 9;

[0151] Figure 15F is a stack-up diagram of the first source / drain metal layer and the second source / drain metal layer in Figure 9;

[0152] Figure 16 is a layout diagram of at least one embodiment of the driving circuit in at least one embodiment of the present disclosure;

[0153] Figure 17 is a layout diagram of the semiconductor layer in Figure 16;

[0154] Figure 18 is a layout diagram of the first gate metal layer in Figure 16;

[0155] Figure 19 is a layout diagram of the second gate metal layer in Figure 16;

[0156] Figure 20 is a layout diagram of the third gate metal layer in Figure 16;

[0157] Figure 21 is a layout diagram of the first source / drain metal layer in Figure 16;

[0158] Figure 22A is a layout diagram of the second source / drain metal layer in Figure 16;

[0159] Figure 22B is a stack-up diagram of the semiconductor layer and the first gate metal layer in Figure 16;

[0160] Figure 22C is a stack-up diagram of the first gate metal layer and the second gate metal layer in Figure 16;

[0161] Figure 22D is a stack-up diagram of the second gate metal layer and the third gate metal layer in Figure 16;

[0162] Figure 22E is a stack-up diagram of the third gate metal layer and the first source / drain metal layer in Figure 16;

[0163] Figure 22F is a stack-up diagram of the first source / drain metal layer and the second source / drain metal layer in Figure 16;

[0164] Figure 23 is a layout diagram of at least one embodiment of the driving circuit in at least one embodiment of the present disclosure;

[0165] Figure 24 is a layout diagram of the semiconductor layer in Figure 23;

[0166] Figure 25 is a layout diagram of the first gate metal layer in Figure 23;

[0167] Figure 26 is a layout diagram of the second gate metal layer in Figure 23;

[0168] Figure 27 is a layout diagram of the third gate metal layer in Figure 23;

[0169] Figure 28 is a layout diagram of the first source / drain metal layer in Figure 23;

[0170] Figure 29A is a layout diagram of the second source / drain metal layer in Figure 23;

[0171] Figure 29B is a stack-up diagram of the semiconductor layer and the first gate metal layer in Figure 23;

[0172] Figure 29C is a stack-up diagram of the first gate metal layer and the second gate metal layer in Figure 23;

[0173] Figure 29D is a stack-up diagram of the second gate metal layer and the third gate metal layer in Figure 23;

[0174] Figure 29E is a stack-up diagram of the third gate metal layer and the first source / drain metal layer in Figure 23;

[0175] Figure 29F is a stack-up diagram of the first source / drain metal layer and the second source / drain metal layer in Figure 23;

[0176] Figure 30 is a layout diagram of at least one embodiment of the driving circuit in at least one embodiment of the present disclosure;

[0177] Figure 31 is a layout diagram of the semiconductor layer in Figure 30;

[0178] Figure 32 is a layout diagram of the first gate metal layer in Figure 30;

[0179] Figure 33 is a layout diagram of the second gate metal layer in Figure 30;

[0180] Figure 34 is a layout diagram of the first source / drain metal layer in Figure 30;

[0181] Figure 35A is a layout diagram of the second source / drain metal layer in Figure 30;

[0182] Figure 35B is a stack-up diagram of the semiconductor layer and the first gate metal layer in Figure 30;

[0183] Figure 35C is a stack-up diagram of the first gate metal layer and the second gate metal layer in Figure 30;

[0184] Figure 35D is a stack-up diagram of the second gate metal layer and the first source / drain metal layer in Figure 30;

[0185] Figure 35E is a stack-up diagram of the first source / drain metal layer and the second source / drain metal layer in Figure 30;

[0186] Figure 36 is a layout diagram of at least one embodiment of the driving circuit in at least one embodiment of the present disclosure;

[0187] Figure 37 is a layout diagram of the semiconductor layer in Figure 36;

[0188] Figure 38 is a layout diagram of the first gate metal layer in Figure 36;

[0189] Figure 39 is a layout diagram of the second gate metal layer in Figure 36;

[0190] Figure 40 is a layout diagram of the first source / drain metal layer in Figure 36;

[0191] Figure 41A is a layout diagram of the second source / drain metal layer in Figure 36;

[0192] Figure 41B is a stack-up diagram of the semiconductor layer and the first gate metal layer in Figure 36;

[0193] Figure 41C is a stack-up diagram of the first gate metal layer and the second gate metal layer in Figure 36;

[0194] Figure 41D is a stack-up diagram of the second gate metal layer and the first source / drain metal layer in Figure 36;

[0195] Figure 41E is a stack-up diagram of the first source / drain metal layer and the second source / drain metal layer in Figure 36;

[0196] Figure 42 is a layout diagram of at least one embodiment of the driving circuit in at least one embodiment of the present disclosure;

[0197] Figure 43 is a layout diagram of the semiconductor layer in Figure 42;

[0198] Figure 44 is a layout diagram of the first gate metal layer in Figure 42;

[0199] Figure 45 is a layout diagram of the second gate metal layer in Figure 42;

[0200] Figure 46 is a layout diagram of the first source / drain metal layer in Figure 42;

[0201] Figure 47A is a layout diagram of the second source / drain metal layer in Figure 42;

[0202] Figure 47B is a stack-up diagram of the semiconductor layer and the first gate metal layer in Figure 42;

[0203] Figure 47C is a stack-up diagram of the first gate metal layer and the second gate metal layer in Figure 42;

[0204] Figure 47D is a stack-up diagram of the second gate metal layer and the first source / drain metal layer in Figure 42;

[0205] Figure 47E is a stack-up diagram of the first source / drain metal layer and the second source / drain metal layer in Figure 42;

[0206] Figure 48A is a layout diagram of at least one embodiment of the driving circuit in at least one embodiment of this disclosure;

[0207] Figure 48B is a layout diagram of Figure 48A with the second source / drain metal layer removed;

[0208] Figure 49 is a layout diagram of the semiconductor layer in Figure 48A;

[0209] Figure 50 is a layout diagram of the first gate metal layer in Figure 48A;

[0210] Figure 51 is a layout diagram of the second gate metal layer in Figure 48A;

[0211] Figure 52 is a layout diagram of the first source / drain metal layer in Figure 48A;

[0212] Figure 53A is a layout diagram of the second source / drain metal layer in Figure 48A;

[0213] Figure 53B is a stack-up diagram of the semiconductor layer and the first gate metal layer in Figure 48A;

[0214] Figure 53C is a stack-up diagram of the first gate metal layer and the second gate metal layer in Figure 48A;

[0215] Figure 53D is a stack-up diagram of the second gate metal layer and the first source / drain metal layer in Figure 48A;

[0216] Figure 53E is a stack-up diagram of the first source / drain metal layer and the second source / drain metal layer in Figure 48A.

[0217] Figure 54A is a layout diagram of at least one embodiment of the driving circuit in at least one embodiment of this disclosure;

[0218] Figure 54B is a layout diagram based on Figure 54A, with the second source / drain metal layer removed.

[0219] Figure 55 is a layout diagram of the semiconductor layer in Figure 54A;

[0220] Figure 56 is a layout diagram of the first gate metal layer in Figure 54A;

[0221] Figure 57 is a layout diagram of the second gate metal layer in Figure 54A;

[0222] Figure 58 is a layout diagram of the first source / drain metal layer in Figure 54A;

[0223] Figure 59A is a layout diagram of the second source / drain metal layer in Figure 54A;

[0224] Figure 59B is a stack-up diagram of the semiconductor layer and the first gate metal layer in Figure 54A;

[0225] Figure 59C is a stack-up diagram of the first gate metal layer and the second gate metal layer in Figure 54A;

[0226] Figure 59D is a stack-up diagram of the second gate metal layer and the first source / drain metal layer in Figure 54A;

[0227] Figure 59E is a stack-up diagram of the first source / drain metal layer and the second source / drain metal layer in Figure 54A.

[0228] Figure 60A is a layout diagram of at least one embodiment of the driving circuit in at least one embodiment of the present disclosure;

[0229] Figure 60B is a layout diagram based on Figure 60A with the second source / drain metal layer removed;

[0230] Figure 61 is a layout diagram of the semiconductor layer in Figure 60A;

[0231] Figure 62 is a layout diagram of the first gate metal layer in Figure 60A;

[0232] Figure 63 is a layout diagram of the second gate metal layer in Figure 60A;

[0233] Figure 64 is a layout diagram of the first source / drain metal layer in Figure 60A;

[0234] Figure 65A is a layout diagram of the second source / drain metal layer in Figure 60A;

[0235] Figure 65B is a stack-up diagram of the semiconductor layer and the first gate metal layer in Figure 60A;

[0236] Figure 65C is a stack-up diagram of the first gate metal layer and the second gate metal layer in Figure 60A;

[0237] Figure 65D is a stack-up diagram of the second gate metal layer and the first source / drain metal layer in Figure 60A;

[0238] Figure 65E is a stack-up diagram of the first source / drain metal layer and the second source / drain metal layer in Figure 60A.

[0239] Figure 66 is a structural diagram of at least one embodiment of the driving circuit;

[0240] Figure 67 is a circuit diagram of at least one embodiment of the driving circuit;

[0241] Figure 68A is a layout diagram of at least one embodiment of the driving circuit shown in Figure 67;

[0242] Figures 68B and 68C are layout diagrams of Figure 68A with the second source / drain metal layer removed.

[0243] Figure 69 is a layout diagram of the semiconductor layer in Figure 68A;

[0244] Figure 70 is a layout diagram of the first gate metal layer in Figure 68A;

[0245] Figure 71 is a layout diagram of the second gate metal layer in Figure 68A;

[0246] Figure 72 is a layout diagram of the third gate metal layer in Figure 68A;

[0247] Figure 73 is a layout diagram of the first source / drain metal layer in Figure 68A;

[0248] Figure 74A is a layout diagram of the second source / drain metal layer in Figure 68A;

[0249] Figure 74B is a stack-up diagram of the semiconductor layer and the first gate metal layer in Figure 68A;

[0250] Figure 74C is a stack-up diagram of the first gate metal layer and the second gate metal layer in Figure 68A;

[0251] Figure 74D is a stack-up diagram of the second gate metal layer and the third gate metal layer in Figure 68A;

[0252] Figure 74E is a stack-up diagram of the third gate metal layer and the first source / drain metal layer in Figure 68A;

[0253] Figure 74F is a stack-up diagram of the first source / drain metal layer and the second source / drain metal layer in Figure 68A;

[0254] Figure 75A is a layout diagram of at least one embodiment of the driving circuit shown in Figure 67;

[0255] Figure 75B is a layout diagram of Figure 75A with the second source / drain metal layer removed;

[0256] Figure 76 is a layout diagram of the semiconductor layer in Figure 75A;

[0257] Figure 77 is a layout diagram of the first gate metal layer in Figure 75A;

[0258] Figure 78 is a layout diagram of the second gate metal layer in Figure 75A;

[0259] Figure 79 is a layout diagram of the third gate metal layer in Figure 75A;

[0260] Figure 80 is a layout diagram of the first source / drain metal layer in Figure 75A;

[0261] Figure 81A is a layout diagram of the second source / drain metal layer in Figure 75A;

[0262] Figure 81B is a stack-up diagram of the semiconductor layer and the first gate metal layer in Figure 75A;

[0263] Figure 81C is a stack-up diagram of the first gate metal layer and the second gate metal layer in Figure 75A;

[0264] Figure 81D is a stack-up diagram of the second gate metal layer and the third gate metal layer in Figure 75A;

[0265] Figure 81E is a stack-up diagram of the third gate metal layer and the first source / drain metal layer in Figure 75A;

[0266] Figure 81F is a stack-up diagram of the first source / drain metal layer and the second source / drain metal layer in Figure 75A;

[0267] Figure 82 is a structural diagram of at least one embodiment of the driving circuit;

[0268] Figure 83 is a circuit diagram of at least one embodiment of the driving circuit;

[0269] Figure 84A is a layout diagram of at least one embodiment of the driving circuit shown in Figure 83;

[0270] Figure 84B is a layout diagram of Figure 84A with the second source / drain metal layer removed;

[0271] Figure 85 is a layout diagram of the semiconductor layer in Figure 84A;

[0272] Figure 86 is a layout diagram of the first gate metal layer in Figure 84A;

[0273] Figure 87 is a layout diagram of the second gate metal layer in Figure 84A;

[0274] Figure 88 is a layout diagram of the third gate metal layer in Figure 84A;

[0275] Figure 89 is a layout diagram of the first source / drain metal layer in Figure 84A;

[0276] Figure 90A is a layout diagram of the second source / drain metal layer in Figure 84A;

[0277] Figure 90B is a stack-up diagram of the semiconductor layer and the first gate metal layer in Figure 84A;

[0278] Figure 90C is a stack-up diagram of the first gate metal layer and the second gate metal layer in Figure 84A;

[0279] Figure 90D is a stack-up diagram of the second gate metal layer and the third gate metal layer in Figure 84A;

[0280] Figure 90E is a stack-up diagram of the third gate metal layer and the first source / drain metal layer in Figure 84A;

[0281] Figure 90F is a stack-up diagram of the first source / drain metal layer and the second source / drain metal layer in Figure 84A. Detailed Implementation

[0282] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0283] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0284] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0285] The display substrate described in this embodiment includes a substrate, pixel circuits, and a driving module. The substrate includes a display area and a peripheral area. The pixel circuits are disposed in the display area, and the driving module is disposed in the peripheral area. The driving module includes multi-level driving circuits, and the peripheral area includes multiple driving circuit areas.

[0286] The driving circuit includes circuit elements, adapter lines, and signal lines; the circuit elements include at least one transistor and at least one capacitor; at least two electrodes of the circuit elements are electrically connected through the adapter lines.

[0287] The ratio between the area of ​​the circuit element region where the circuit element is located and the area of ​​the driving circuit region is greater than 0.56 and less than 1.

[0288] In at least one embodiment of this disclosure, the ratio between the area of ​​the circuit element region where the circuit element of the driving circuit is located and the area of ​​the driving circuit region is set to be greater than 0.56 and less than 1, so as to reduce the area of ​​the driving circuit and facilitate the realization of a narrow bezel.

[0289] In at least one embodiment of this disclosure, the contour line of the orthographic projection of the nth-level driving circuit on the substrate that is furthest from the display area is the first contour line, and the contour line of the orthographic projection of the nth-level driving circuit on the substrate that is closest to the display area is the second contour line.

[0290] The outline of the nth stage driving circuit's orthogonal projection onto the substrate that is closest to the (n-1)th stage driving circuit is the third outline.

[0291] The contour line furthest from the (n-1)th stage driving circuit in the orthographic projection of the nth stage driving circuit onto the substrate is the fourth contour line; n is a positive integer.

[0292] The area of ​​the quadrilateral formed by the extensions of the first contour line, the second contour line, the third contour line, and the fourth contour line is the area of ​​the nth-level driving circuit region.

[0293] The nth-level driving circuit is located within the nth-level driving circuit region.

[0294] In at least one embodiment of this disclosure, the circuit element region in which the circuit elements included in the driving circuit are located includes: the circuit element region in which the transistors included in the driving circuit are located, and the circuit element region in which the capacitors included in the driving circuit are located.

[0295] The area of ​​the circuit element region where the circuit elements of the driving circuit are located is the sum of the area of ​​the circuit element region where each transistor of the driving circuit is located and the area of ​​the circuit element region where each capacitor of the driving circuit is located.

[0296] Wherein, the contour line of the active pattern of the transistor in the nth stage driving circuit that is furthest from the display area is the fifth contour line, and the contour line of the active pattern of the transistor in the nth stage driving circuit that is closest to the display area is the sixth contour line; the contour line of the active pattern of the transistor in the nth stage driving circuit that is closest to the (n-1)th stage driving circuit is the seventh contour line, and the contour line of the active pattern of the transistor in the nth stage driving circuit that is furthest from the (n-1)th stage driving circuit is the eighth contour line; the area of ​​the quadrilateral formed by the extension lines of the fifth, sixth, seventh, and eighth contour lines is the area of ​​the circuit region in which the transistor is located.

[0297] The relative area of ​​the two plates of the capacitor in the driving circuit is the area of ​​the circuit region in which the capacitor is located.

[0298] In at least one embodiment of this disclosure, the relative area of ​​the two plates of the capacitor refers to the overlapping area between the orthographic projection of the first plate of the capacitor onto the substrate and the orthographic projection of the second plate of the capacitor onto the substrate.

[0299] In Figure 1D, the circuit labeled Sn is the nth stage drive circuit, and the circuit labeled Sn-1 is the (n-1)th stage drive circuit.

[0300] In Figure 1E, Y1 is the extension of the first contour line, Y2 is the extension of the second contour line, Y3 is the extension of the third contour line, and Y4 is the extension of the fourth contour line. The area of ​​the quadrilateral formed by Y1, Y2, Y3, and Y4 is the area of ​​the nth stage drive circuit region.

[0301] In at least one embodiment shown in Figures 1D and 1E, the layout of the driving circuit is shown in Figure 2.

[0302] Optionally, the signal line extends along a first direction;

[0303] The driving circuit includes at least two transistors arranged along a first direction.

[0304] In at least one embodiment of this disclosure, the driving circuit includes at least two transistors that can be arranged along a first direction, such as a vertical direction, to save the lateral space occupied by the driving circuit and facilitate the realization of a narrow bezel.

[0305] Optionally, the active pattern of the first transistor included in the driving circuit is electrically connected to the active pattern of the second transistor included in the driving circuit through a via, and a first conductive pattern formed on the gate metal layer.

[0306] In at least one embodiment of this disclosure, by providing an additional gate insulating layer mask, the semiconductor layer and the second gate metal layer can be directly electrically connected through vias, and the semiconductor layer and the third gate metal layer can be directly electrically connected through vias.

[0307] In at least one embodiment shown in Figures 2-22, a mask for the second gate insulating layer can be added. The semiconductor layer and the first gate metal layer can be connected via vias penetrating the first gate insulating layer (for LTPO (Low Temperature Polycrystalline Oxide) and LTPS (Low Temperature Polycrystalline Silicon) products); the semiconductor layer and the second gate metal layer can be connected via vias penetrating the first gate insulating layer and the first interlayer dielectric layer (for LTPO products); the semiconductor layer and the second gate metal layer can be connected via vias penetrating the first and second gate insulating layers (for LTPS products); the semiconductor layer and the third gate metal layer can be connected via vias penetrating the first gate insulating layer, the first interlayer dielectric layer, the second interlayer dielectric layer, the second buffer layer, and the second gate insulating layer (for LTPO products); additionally, following related technologies, the first source / drain metal layer and the semiconductor layer... The electrical connection is a via formed by using a third interlayer dielectric layer mask to penetrate the first gate insulating layer, the first interlayer dielectric layer, the second interlayer dielectric layer, the second buffer layer, the second gate insulating layer, and the third interlayer dielectric layer (for LTPO products); or, the electrical connection between the first source / drain metal layer and the semiconductor layer is a via formed by using an interlayer dielectric layer mask to penetrate the first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer (for LTPS products); or, the connection between the first source / drain metal layer and the semiconductor layer is a via formed by using a second gate insulating layer mask to penetrate the first gate insulating layer, the first interlayer dielectric layer, the second interlayer dielectric layer, the second buffer layer, and the second gate insulating layer, and a second via formed by using a third interlayer dielectric layer mask to penetrate the third interlayer dielectric layer (for LTPO products); or, the connection between the first source / drain metal layer and the semiconductor layer is a via formed by using a second gate insulating layer mask to penetrate the first gate insulating layer and the second gate insulating layer, and a second via formed by using an interlayer dielectric layer mask to penetrate the interlayer dielectric layer (for LTPS products).

[0308] In at least one embodiment of this disclosure, the signal line extends along a first direction;

[0309] The driving circuit includes an active pattern of a third transistor that extends along a second direction, which intersects with the first direction.

[0310] The active patterns of the first transistor and the third transistor are arranged along a first direction.

[0311] Optionally, the second direction can be a horizontal direction.

[0312] In specific implementation, the active pattern of the third transistor can be set to extend horizontally, and the active patterns of the first transistor and the third transistor can be arranged in a vertical square. The active pattern of the third transistor can be reversed by 90 degrees, so that the active pattern of the third transistor can be set below the active pattern of the first transistor, which helps to save horizontal space and achieve a narrow bezel.

[0313] In at least one embodiment of this disclosure, the driving circuit includes a first node control circuit, a second node control circuit, and a third node control circuit; the first node control circuit is used to control the potential of a first node; the second node control circuit is used to control the potential of a second node; and the third node control circuit is used to control the potential of a third node according to the potential of the second node.

[0314] The first node control circuit includes the first transistor and the second transistor; the active patterns of the first transistor and the second transistor are both electrically connected to the first node.

[0315] The third node control circuit includes the third transistor, and the active pattern of the third transistor is electrically connected to the third node.

[0316] In at least one embodiment of this disclosure, the driving circuit further includes an output circuit and an output reset circuit;

[0317] The output circuit is electrically connected to the fifth node and the drive output terminal respectively, and is used to control the drive output terminal to provide a drive signal under the control of the potential of the fifth node;

[0318] The output reset circuit is electrically connected to the third node and the drive output terminal respectively, and is used to reset the drive signal under the control of the potential of the third node;

[0319] The transistors included in the output circuit and the transistors included in the output reset circuit are arranged along a first direction to save the lateral space occupied by the drive circuit and facilitate the realization of a narrow bezel.

[0320] As shown in Figure 1A, at least one embodiment of the driving circuit includes a first node control circuit 11, a second node control circuit 12, and a third node control circuit 13.

[0321] The first node control circuit 11 is electrically connected to the first node N1 and is used to control the potential of the first node N1;

[0322] The second node control circuit 12 is electrically connected to the second node N2 and is used to control the potential of the second node N2;

[0323] The third node control circuit 13 is electrically connected to the second node N2 and the third node N3 respectively, and is used to control the potential of the third node N3 according to the potential of the second node N2.

[0324] Figure 2 is a layout diagram of at least one embodiment of the driving circuit in at least one embodiment of this disclosure. Figures 3A and 3B are layout diagrams of the semiconductor layers in Figure 2, Figure 4 is a layout diagram of the first gate metal layer in Figure 2, Figure 5 is a layout diagram of the second gate metal layer in Figure 2, Figure 6 is a layout diagram of the third gate metal layer in Figure 2, Figure 7 is a layout diagram of the first source / drain metal layer in Figure 2, and Figure 8 is a layout diagram of the second source / drain metal layer in Figure 2. In Figure 2, the circuit diagram of at least one embodiment of the driving circuit can be as shown in Figure 1C.

[0325] As shown in Figures 2-8, in at least one embodiment of the driving circuit, the first node control circuit includes a first transistor T1 and a second transistor T2; the active pattern A1 of the first transistor T1 and the active pattern A2 of the second transistor T2 are both electrically connected to the first node.

[0326] The third node control circuit includes a third transistor T3, and the active pattern A3 of the third transistor T3 is electrically connected to the third node.

[0327] Optionally, the driving circuit further includes an output reset circuit; the output reset circuit is electrically connected to the third node and the driving output terminal respectively, and is used to reset the driving signal provided by the driving output terminal under the control of the potential of the third node;

[0328] The output reset circuit includes a fourth transistor;

[0329] The active pattern of the third transistor is electrically connected to the gate of the fourth transistor through a via and a second conductive pattern formed on the gate metal layer.

[0330] As shown in Figure 1B, in at least one embodiment of the driving circuit shown in Figure 1A, the driving circuit further includes an output reset circuit 10 and an output circuit 20.

[0331] The output reset circuit 10 is electrically connected to the third node N3 and the drive output terminal OT, respectively, and is used to reset the drive signal provided by the drive output terminal OT under the control of the potential of the third node N3.

[0332] The output circuit 20 is electrically connected to the first node N1 and the drive output terminal OT, respectively, and is used to control the drive output terminal OT to output a drive signal under the control of the potential of the first node N1.

[0333] As shown in Figure 1C, based on at least one embodiment of the driving circuit shown in Figure 1B, the first node control circuit includes a first transistor T1 and a second transistor T2; the third node control circuit includes a third transistor T3; the output reset circuit includes a fourth transistor T4; the second node control circuit includes a fifth transistor T5; the second node control circuit includes a sixth transistor T6 and a seventh transistor T7; and the output circuit may include an eighth transistor T8.

[0334] At least one embodiment of the driving circuit further includes a high voltage line VGH, a second voltage line VGL, a first clock signal line CK, and a second clock signal line CB;

[0335] The gate of T1 is electrically connected to the first clock signal line CK, the first electrode of T1 is electrically connected to the low voltage line VGL, and the second electrode of T1 is electrically connected to the first node N1.

[0336] The gate of T2 is electrically connected to the second node N2, and the first electrode of T2 is electrically connected to the first clock signal line CK.

[0337] The gate of T3 is electrically connected to the low voltage line VGL, the first electrode of T3 is electrically connected to the second node N2, and the second electrode of T3 is electrically connected to the third node N3.

[0338] The gate of T4 is electrically connected to the third node N3, the first electrode of T4 is electrically connected to the drive output terminal OT, and the second electrode of T4 is electrically connected to the second clock signal line CB.

[0339] The gate of T5 is electrically connected to the first clock signal line CK, the first electrode of T5 is electrically connected to the input terminal I1, and the second electrode of T5 is electrically connected to the second node N2.

[0340] The gate of T6 is electrically connected to the first node N1, the first electrode of T6 is electrically connected to the high voltage line VGH, and the second electrode of T6 is electrically connected to the first electrode of T7.

[0341] The gate of T7 is electrically connected to the second clock signal line CB, and the second electrode of T7 is electrically connected to the gate of T2.

[0342] The gate of T8 is electrically connected to the first node N1, the first electrode of T8 is electrically connected to the high voltage line VGH, and the second electrode of T8 is electrically connected to the drive output terminal OT.

[0343] At least one embodiment of the driving circuit further includes a first capacitor C1 and a second capacitor C2;

[0344] The first plate of C1 is electrically connected to the first node N1, and the second plate of C1 is electrically connected to the high voltage line VGH.

[0345] The first electrode of C2 is electrically connected to the third node N3, and the second electrode of C2 is electrically connected to the drive output terminal OT.

[0346] In at least one embodiment shown in Figure 1C, all transistors are p-type transistors, but this is not a limitation.

[0347] As shown in Figures 2-8, in at least one embodiment of this disclosure, the driving circuit includes a first transistor T1 and a second transistor T2;

[0348] The active pattern A1 of the first transistor T1 is electrically connected to the active pattern A2 of the second transistor T2 through the first via H1 and the first conductive pattern DX1 formed on the third gate metal layer.

[0349] The output reset circuit includes a fourth transistor T4;

[0350] The active pattern A3 of the third transistor T3 is electrically connected to the gate G4 of the fourth transistor T4 through the second via H2 and the second conductive pattern DX2 formed on the third gate metal layer.

[0351] In at least one embodiment shown in Figures 2-8, the third gate metal layer is a third gate metal layer, and the third node can be transferred through the third gate metal layer.

[0352] In Figure 7, the part labeled LB1 is the first connecting part, the part labeled LB2 is the second connecting part, and the part labeled LB3 is the third connecting part.

[0353] As shown in Figures 2-8, VGL, CK, CB and VGH all extend in the vertical direction;

[0354] VGH, CK, CB, and VGH are arranged sequentially along the direction closest to the display area;

[0355] The orthographic projections of the active graphic A1 on the substrate of T1 at least partially overlap with the orthographic projections of VGL on the substrate; the orthographic projections of the active graphic A2 on the substrate of T2 at least partially overlap with the orthographic projections of CK on the substrate; the orthographic projections of the active graphic A3 on the substrate of T3 at least partially overlap with the orthographic projections of CK on the substrate; the orthographic projections of the active graphic A4 on the substrate of T4 at least partially overlap with the orthographic projections of VGH on the substrate; the orthographic projections of the active graphic A5 on the substrate of T5 at least partially overlap with the orthographic projections of CK on the substrate; the orthographic projections of the active graphic A6 on the substrate of T6 at least partially overlap with the orthographic projections of CB on the substrate; the orthographic projections of the active graphic A7 on the substrate of T7 at least partially overlap with the orthographic projections of CB on the substrate; the orthographic projections of the active graphic A8 on the substrate of T8 at least partially overlap with the orthographic projections of VGH on the substrate; this allows for narrowing the lateral space of the driving circuit, facilitating the implementation of a narrow bezel;

[0356] T5 is a dual-gate transistor. The first gate of T5 is marked as G51, and the second gate of T5 is marked as G52.

[0357] T2 and T3 are arranged vertically;

[0358] The active graphic A6 of T6 and the active graphic A7 of T7 are integrally formed, and T6 and T7 are arranged in the vertical direction;

[0359] The active graphic A8 of T8 and the active image A4 of T4 are integrally formed, and T8 and T4 are arranged in the vertical direction;

[0360] The first electrode plate of C1 includes a first electrode plate portion C1a1 formed on a first gate metal layer, the second electrode plate of C1 is formed on a second gate metal layer, and the second electrode plate portion C1a2 of the first electrode plate of C1 is formed on a third gate metal layer; the orthographic projections of C1a1, C1a2, and C1b on the substrate at least partially overlap.

[0361] The first electrode plate of C2 includes a first electrode plate portion C2a1 formed on a first gate metal layer, the second electrode plate of C2 is formed on a second gate metal layer, and the second electrode plate portion C2a2 of the first electrode plate of C2 is formed on a third gate metal layer; the orthographic projections of C2a1, C2a2, and C2b on the substrate at least partially overlap.

[0362] By setting C1 and C2 as a three-layer electrode structure, the area of ​​C1 and the area of ​​C2 can be reduced to half that in related technologies.

[0363] In at least one embodiment shown in Figures 2-8, the ratio between the area of ​​the circuit element (including T1, T2, T3, T4, T5, T6, T7, T8, C1, and C2) in the circuit element region and the area of ​​the driving circuit region is 75.78%.

[0364] As shown in at least one embodiment of Figures 2-8, the circuit element region in which the circuit elements of the driving circuit are located includes: the circuit element region in which T1, T2, T3, T4, T5, T6, T7 and T8 of the driving circuit are located, and the circuit region in which C1 and C2 of the driving circuit are located.

[0365] The area of ​​the circuit element region where the circuit element included in the driving circuit is located is the sum of the areas of the circuit element regions where T1, T2, T3, T4, T5, T6, T7, T8, C1, and C2.

[0366] In at least one embodiment shown in Figures 2-8, the area of ​​the circuit element region where T1 is located is the area of ​​A1, the area of ​​the circuit element region where T2 is located is the area of ​​A2, the area of ​​the circuit element region where T3 is located is the area of ​​A3, the area of ​​the circuit element region where T4 is located is the area of ​​A2, the area of ​​the circuit element region where T6 is located is the area of ​​A6, the area of ​​the circuit element region where T7 is located is the area of ​​A7, and the area of ​​the circuit element region where T8 is located is the area of ​​A8.

[0367] As shown in Figure 3B, the area of ​​the circuit region where T5 is located is the area of ​​the quadrilateral formed by the extensions of the fifth contour line Y5, the sixth contour line Y6, the seventh contour line Y7, and the eighth contour line Y8.

[0368] As in at least one embodiment of this disclosure, the circuit element region where C1 is located is the overlapping area between the orthographic projection of the first electrode plate of C1 on the substrate and the orthographic projection of the second electrode plate of C1 on the substrate.

[0369] The circuit element region where C2 is located is the overlapping area between the orthographic projection of the first plate of C2 on the substrate and the orthographic projection of the second plate of C2 on the substrate.

[0370] In at least one embodiment shown in Figures 2-8, the first electrode portion of the first electrode plate of C1 is designated as C1a1, the second electrode portion of the first electrode plate of C1 is designated as C1a2, and the second electrode plate of C1 is designated as C1b; the overlapping area of ​​the orthographic projection of C1a1 onto the substrate and the orthographic projection of C1b onto the substrate is the first overlapping area, the overlapping area of ​​the orthographic projection of C1a2 onto the substrate and the orthographic projection of C1b onto the substrate is the second overlapping area, and the area of ​​the circuit element region where C1 is located is the larger of the first overlapping area and the second overlapping area;

[0371] The first electrode portion of C2 is designated as C2a1, the second electrode portion of C2 is designated as C2a2, and the second electrode portion of C2 is designated as C2b. The overlapping area of ​​the orthographic projections of C2a1 and C2b on the substrate is the third overlapping area, the overlapping area of ​​the orthographic projections of C2a2 and C2b on the substrate is the fourth overlapping area, and the area of ​​the circuit element region where C2 is located is the larger of the third and fourth overlapping areas.

[0372] Optionally, the second node control circuit includes a fifth transistor;

[0373] The gate of the first transistor and the gate of the fifth transistor are electrically connected through a third conductive pattern formed on the gate metal layer;

[0374] The third conductive pattern is electrically connected to the active pattern of the second transistor through a via.

[0375] In practical implementation, the gates of the first transistor and the fifth transistor can be electrically connected to the active pattern of the second transistor through the third conductive pattern formed on the gate metal layer, which can alleviate the layout pressure in the vertical direction.

[0376] Figure 9 is a layout diagram of at least one embodiment of the driving circuit in at least one embodiment of the present disclosure. Figure 10 is a layout diagram of the semiconductor layer in Figure 9, Figure 11 is a layout diagram of the first gate metal layer in Figure 9, Figure 12 is a layout diagram of the second gate metal layer in Figure 9, Figure 13 is a layout diagram of the third gate metal layer in Figure 9, Figure 14 is a layout diagram of the first source / drain metal layer in Figure 9, and Figure 15 is a layout diagram of the second source / drain metal layer in Figure 9.

[0377] Compared to the at least one embodiment shown in FIG2, the at least one embodiment shown in FIG9 reduces the vertically arranged conductive portion DJ (shown in FIG7) formed on the first source-drain metal layer for the active pattern A2 used to electrically connect the gate G1 and T2 of T1. This reduces the vertical space, facilitates the inversion of the active pattern A3 of T3 by 90 degrees, and makes it easier to place the active pattern A3 of the third transistor T3 below the active pattern A1 of the first transistor T1, thereby saving horizontal space and achieving a narrow bezel.

[0378] As shown in Figures 9-15, in at least one embodiment of the driving circuit, the second node control circuit may include a fifth transistor T5;

[0379] The gate G1 of T1 and the gate G5 of T5 are electrically connected through a third conductive pattern DX3 formed on the third gate metal layer.

[0380] The third conductive pattern DX3 is electrically connected to the active pattern A2 of the second transistor T2 through the third via H3.

[0381] Optionally, the second node control circuit includes a fifth transistor;

[0382] The signal line includes a first clock signal line; the second transistor is electrically connected to the first clock signal line.

[0383] The orthographic projection of the active pattern of the second transistor onto the substrate at least partially overlaps with the orthographic projection of the first clock signal line onto the substrate;

[0384] The orthographic projection of the active pattern of the third transistor onto the substrate at least partially overlaps with the orthographic projection of the first clock signal line onto the substrate.

[0385] In a specific implementation, the orthographic projection of the active pattern of the second transistor onto the substrate at least partially overlaps with the orthographic projection of the first clock signal line onto the substrate; the orthographic projection of the active pattern of the third transistor onto the substrate at least partially overlaps with the orthographic projection of the first clock signal line onto the substrate, which helps to reduce the lateral space occupied by the driving circuit and facilitates the realization of a narrow bezel.

[0386] As shown in Figures 2-8, the orthographic projection of the active pattern A2 of the second transistor T2 onto the substrate at least partially overlaps with the orthographic projection of the first clock signal line CK onto the substrate, and the orthographic projection of the active pattern A3 of the third transistor T3 onto the substrate at least partially overlaps with the orthographic projection of the first clock signal line CK onto the substrate.

[0387] As shown in Figures 9-15, the orthographic projection of the active pattern A2 of the second transistor T2 onto the substrate at least partially overlaps with the orthographic projection of the first clock signal line CK onto the substrate, and the orthographic projection of the active pattern A3 of the third transistor T3 onto the substrate at least partially overlaps with the orthographic projection of the first clock signal line CK onto the substrate.

[0388] In at least one embodiment of this disclosure, the signal line extends along a first direction; the first direction intersects with a second direction;

[0389] The gate of the first transistor and the gate of the fifth transistor both extend along the second direction;

[0390] The gates of the first transistor and the fifth transistor are arranged along a second direction.

[0391] Optionally, the first direction can be vertical, and the second direction can be horizontal.

[0392] As shown in Figures 9-15, the first clock signal line CK extends vertically, and the gates G1 of T1 and G5 of T5 both extend horizontally. The gates G1 of T1 and G5 of T5 are arranged horizontally.

[0393] In Figures 9-15, the active pattern labeled A1 is T1, the active pattern labeled A2 is T2, the active pattern labeled A3 is T3, the active pattern labeled A4 is T4, the active pattern labeled A5 is T5, the active pattern labeled A6 is T6, the active pattern labeled A7 is T7, and the active pattern labeled A8 is T8.

[0394] The part labeled LB4 is the fourth connecting part, the part labeled LB5 is the fifth connecting part, and the part labeled LB6 is the sixth connecting part.

[0395] In at least one embodiment shown in Figures 9-15, T5 and T3 are arranged in the vertical direction, T6 and T7 are arranged in the vertical direction, and T8 and T4 are arranged in the vertical direction, so as to narrow the lateral space of the driving circuit and facilitate the realization of a narrow bezel.

[0396] The orthographic projection of A1 onto the substrate at least partially overlaps with the orthographic projection of VGL onto the substrate; the orthographic projection of A3 onto the substrate at least partially overlaps with the orthographic projection of CK onto the substrate; the orthographic projection of A6 onto the substrate at least partially overlaps with the orthographic projection of CB onto the substrate; the orthographic projection of A7 onto the substrate at least partially overlaps with the orthographic projection of CB onto the substrate; the orthographic projection of A8 onto the substrate at least partially overlaps with the orthographic projection of VGH onto the substrate; the orthographic projection of A4 onto the substrate at least partially overlaps with the orthographic projection of VGH onto the substrate; This allows transistors to be placed using the signal line area, narrowing the lateral space of the drive circuit and facilitating the implementation of a narrow bezel;

[0397] The plate labeled C1a is the first plate of C1, and the plate labeled C1b is the second plate of C1.

[0398] The plate labeled C2a is the first plate of C2, and the plate labeled C2b is the second plate of C2.

[0399] The orthographic projection of C1a onto the substrate at least partially overlaps with the orthographic projection of C1b onto the substrate, and the orthographic projection of C2a onto the substrate at least partially overlaps with the orthographic projection of C2b onto the substrate.

[0400] C1a and C2a are formed in the first gate metal layer, and C1b and C2b are formed in the second gate metal layer.

[0401] In at least one embodiment shown in Figures 9-15, the ratio between the area of ​​the orthographic projection of the circuit element region where the circuit element (including circuit elements T1, T2, T3, T4, T5, T6, T7, T8, C1, and C2) is located and the area of ​​the driving circuit region is 72.91%.

[0402] Figure 16 is a layout diagram of at least one embodiment of the driving circuit in at least one embodiment of this disclosure. Figure 17 is a layout diagram of the semiconductor layer in Figure 16, Figure 19 is a layout diagram of the first gate metal layer in Figure 16, Figure 20 is a layout diagram of the third gate metal layer in Figure 16, Figure 21 is a layout diagram of the first source / drain metal layer in Figure 16, and Figure 22 is a layout diagram of the second source / drain metal layer in Figure 16.

[0403] As shown in Figures 16-22, the first clock signal line CK extends vertically, and the gates G1 of T1 and G5 of T5 both extend horizontally. The gates G1 of T1 and G5 of T5 are arranged horizontally.

[0404] Optionally, the gate of the second transistor is disposed on the side of the gate of the fifth transistor away from the gate of the third transistor.

[0405] As shown in Figures 16-22, the gate G2 of T2 is located on the side of the gate G1 of T1 away from the gate G5 of T5, so that T2 is positioned above T1. The space below T5 saved is used to set the sixth transistor T6 and the seventh transistor T7 of the second node control circuit, which helps to save horizontal space and achieve a narrow bezel.

[0406] As shown in Figures 16-22, T3, T6, and T7 are placed directly below T5, T2, and T1.

[0407] In at least one embodiment of this disclosure, the signal line extends along a first direction; the second node control circuit further includes at least one transistor;

[0408] The second node control circuit includes at least a portion of transistors whose active patterns are arranged along a first direction.

[0409] As shown in Figures 16-22, the first clock signal line CK extends vertically, and T3, T6 and T7 are arranged vertically, which is beneficial for achieving a narrow bezel.

[0410] In Figures 16-22, the seventh connecting part is labeled LB7, the eighth connecting part is labeled LB8, the ninth connecting part is labeled LB9, the tenth connecting part is labeled LB10, and the eleventh connecting part is labeled LB11.

[0411] As shown in Figures 16-22, the orthographic projection of A1 onto the substrate and the orthographic projection of VGL onto the substrate at least partially overlap;

[0412] The orthographic projection of A2 onto the substrate at least partially overlaps with the orthographic projection of CK onto the substrate;

[0413] The orthographic projection of A3 onto the substrate at least partially overlaps with the orthographic projection of CK onto the substrate;

[0414] The orthographic projection of A8 onto the substrate at least partially overlaps with the orthographic projection of VGH onto the substrate;

[0415] The orthographic projection of A4 onto the substrate at least partially overlaps with the orthographic projection of VGH onto the substrate;

[0416] This reduces the lateral space occupied by the drive circuit, making it easier to achieve a narrow bezel.

[0417] In Figures 16-22, the first plate of C1 is labeled C1a, the first plate of C2 is labeled C2a, the second plate of C1 is labeled C1b, and the second plate of C2b is labeled C2b.

[0418] The orthographic projection of C1a onto the substrate at least partially overlaps with the orthographic projection of C1b onto the substrate;

[0419] The orthographic projection of C2a onto the substrate at least partially overlaps with the orthographic projection of C2b onto the substrate.

[0420] In at least one embodiment shown in Figures 16-22, T1 and T3 are arranged vertically, T2 and T3 are arranged vertically, T5, T6 and T7 are arranged vertically, and T8 and T4 are arranged vertically to narrow the horizontal space occupied by the driving circuit, which is beneficial to achieving a narrow bezel.

[0421] In at least one embodiment shown in Figures 16-22, the ratio between the area of ​​the orthographic projection of the circuit element region where the circuit element (including circuit elements T1, T2, T3, T4, T5, T6, T7, T8, C1, and C2) is located and the area of ​​the driving circuit region is 70.66%.

[0422] In at least one embodiment of this disclosure, the signal line includes a second clock signal line;

[0423] The active pattern of at least some of the transistors in the second node control circuit is projected onto the substrate in a positive projection that at least partially overlaps with the positive projection of the second clock signal line onto the substrate.

[0424] As shown in Figures 9-15, the second clock signal line CB extends in the vertical direction;

[0425] The second node control circuit includes a sixth transistor T6 and a seventh transistor T7;

[0426] The orthographic projection of the active graphic A6 on the substrate of T6 at least partially overlaps with the orthographic projection of CB on the substrate, and the orthographic projection of the active graphic A7 on the substrate of T7 at least partially overlaps with the orthographic projection of CB on the substrate, which is beneficial for achieving a narrow bezel.

[0427] In at least one embodiment of this disclosure, the capacitor includes a first plate and a second plate; the first plate of the capacitor includes a first plate portion and a second plate portion.

[0428] The first electrode portion, the second electrode portion, and the second electrode portion are arranged sequentially along a direction away from the substrate;

[0429] The orthographic projections of the first electrode portion onto the substrate, the orthographic projections of the second electrode portion onto the substrate, and the orthographic projections of the second electrode portion onto the substrate at least partially overlap.

[0430] In a specific implementation, the capacitor includes a first plate and a second plate; the first plate of the capacitor includes a first plate portion and a second plate portion.

[0431] The circuit element region where the capacitor is located is the larger of the following: the overlapping area between the orthographic projection of the first plate portion of the capacitor on the substrate and the orthographic projection of the second plate portion of the capacitor on the substrate, and the overlapping area between the orthographic projection of the second plate portion of the capacitor on the substrate and the orthographic projection of the second plate portion of the capacitor on the substrate.

[0432] As shown in Figures 2 to 8, the first plate portion of the first electrode of the first capacitor C1 is marked as C1a1, the second plate portion of the first electrode of the first capacitor C1 is marked as C1a2, and the second plate of the first capacitor C1 is marked as C1b.

[0433] C1a1 is formed in the first gate metal layer, C1a2 is formed in the third gate metal layer, and C1b is formed in the second gate metal layer. C1a1, C1b and C1a2 are arranged sequentially in a direction away from the substrate.

[0434] The orthographic projections of C1a1, C1b, and C1a2 on the substrate at least partially overlap. A three-layer capacitor structure is adopted, and the capacitor area is half that of related technologies, which is beneficial for achieving a narrow bezel.

[0435] In at least one embodiment of this disclosure, the signal line extends along a first direction; the signal line includes a first voltage line;

[0436] The driving circuit includes an output circuit and an output reset circuit; the output circuit is electrically connected to the first node, the driving output terminal, and the first voltage line respectively, and is used to control the connection between the driving output terminal and the first voltage line under the control of the potential of the first node; the output reset circuit is electrically connected to the third node and the driving output terminal respectively, and is used to reset the driving signal provided by the driving output terminal under the control of the potential of the third node.

[0437] The transistors included in the output circuit and the transistors included in the output reset circuit are arranged along a first direction.

[0438] In a specific implementation, the first voltage line can be a high voltage line, which can extend vertically. The driving circuit can include an output circuit and an output reset circuit. The output reset circuit includes a fourth transistor. The output circuit can include an eighth transistor, which is arranged vertically with the fourth transistor to facilitate the realization of a narrow bezel.

[0439] As shown in Figures 2-8, at least one embodiment of the driving circuit includes a fourth transistor T4 and an eighth transistor T8;

[0440] T8 and T4 are arranged vertically, and the high-voltage line VGH extends vertically.

[0441] As shown in Figures 9-15, at least one embodiment of the driving circuit includes a fourth transistor T4 and an eighth transistor T8;

[0442] T8 and T4 are arranged vertically, and the high-voltage line VGH extends vertically.

[0443] As shown in Figures 16-22, at least one embodiment of the driving circuit includes a fourth transistor T4 and an eighth transistor T8;

[0444] T8 and T4 are arranged vertically, and the high-voltage line VGH extends vertically.

[0445] Optionally, the driving circuit includes a first node control circuit, a second node control circuit, and a third node control circuit;

[0446] The first node control circuit is electrically connected to the first clock signal line;

[0447] The transistors included in the first node control circuit and the transistors included in the second node control circuit that are electrically connected to the first clock signal line are arranged along a first direction.

[0448] Figure 23 is a layout diagram of at least one embodiment of the driving circuit in at least one embodiment of this disclosure. Figure 24 is a layout diagram of the semiconductor layer in Figure 23, Figure 25 is a layout diagram of the first gate metal layer in Figure 23, Figure 26 is a layout diagram of the second gate metal layer in Figure 23, Figure 27 is a layout diagram of the third gate metal layer in Figure 23, Figure 28 is a layout diagram of the first source / drain metal layer in Figure 23, and Figure 29 is a layout diagram of the second source / drain metal layer in Figure 23.

[0449] As shown in Figures 23-29, at least one embodiment of the driving circuit includes a first node control circuit, a second node control circuit, and a third node control circuit; the first node control circuit includes a first transistor T1 and a second transistor T2, and the second node control circuit includes a fifth transistor T5 (T1);

[0450] T1, T2, and T5 are arranged vertically, and the first clock signal line CK extends vertically.

[0451] Optionally, the driving circuit includes a first node control circuit, a second node control circuit, and a third node control circuit;

[0452] The transistors included in the second node control circuit are arranged along a first direction with the transistors included in the third node control circuit.

[0453] As shown in Figures 23-29, at least one embodiment of the driving circuit includes a first node control circuit, a second node control circuit, and a third node control circuit;

[0454] The second node control circuit includes the sixth transistor T6 and the seventh transistor T7, and the third node control circuit includes the third transistor T3.

[0455] The low-voltage line VGL extends vertically;

[0456] T6, T7, and T3 are arranged vertically, which helps to achieve a narrow bezel.

[0457] As shown in Figures 23-29, at least one embodiment of the driving circuit includes a fourth transistor T4 and an eighth transistor T8;

[0458] T8 and T4 are arranged vertically, and the high-voltage line VGH extends vertically.

[0459] As shown in Figures 23-29, the orthographic projection of A1 on the substrate at least partially overlaps with the orthographic projection of CK on the substrate, the orthographic projection of A2 on the substrate at least partially overlaps with the orthographic projection of CK on the substrate, the orthographic projection of A5 on the substrate at least partially overlaps with the orthographic projection of CK on the substrate, and the orthographic projection of A8 on the substrate at least partially overlaps with the orthographic projection of VGH on the substrate. The orthographic projection of A8 on the substrate at least partially overlaps with the orthographic projection of VGH on the substrate, so as to utilize the space for setting signal lines to set transistors, which is beneficial to achieve a narrow bezel.

[0460] T6, T7 and T3 are set between VGL and CB;

[0461] T1, T2, and T5 are arranged vertically, as are T6, T7, and T3, and T8 and T4, in order to save the horizontal space occupied by the drive circuit and to achieve a narrow bezel.

[0462] In Figures 23-29, the part labeled LB12 is the twelfth connecting part, the part labeled LB13 is the thirteenth connecting part, the part labeled LB14 is the fourteenth connecting part, the part labeled LB15 is the fifteenth connecting part, and the part labeled LB16 is the sixteenth connecting part.

[0463] The plate labeled C1a is the first plate of C1, the plate labeled C1b is the second plate of C1, the plate labeled C2a is the first plate of C2, and the plate labeled C2b is the second plate of C2.

[0464] The orthographic projection of C1a onto the substrate at least partially overlaps with the orthographic projection of C1b onto the substrate, and the orthographic projection of C2a onto the substrate at least partially overlaps with the orthographic projection of C2b onto the substrate.

[0465] In at least one embodiment shown in Figures 23-29, the ratio between the area of ​​the circuit element region where the circuit elements (including T1, T2, T3, T4, T5, T6, T7, T8, C1, and C2) are located and the area of ​​the driving circuit region is 77.3%.

[0466] In at least one embodiment of this disclosure, the orthographic projection of the active pattern of the transistors included in the output circuit onto the substrate at least partially overlaps with the orthographic projection of the first voltage line onto the substrate.

[0467] As shown in Figures 2-29, the orthographic projection of the active pattern A8 of T8 onto the substrate at least partially overlaps with the orthographic projection of the high-voltage line VGH onto the substrate, in order to achieve a narrow bezel.

[0468] In at least one embodiment shown in Figures 23-29, by adding a mask that penetrates the gate insulating layer, direct electrical connection between the semiconductor layer and the second source / drain metal layer can be achieved. The connection between the second source / drain metal layer and the semiconductor layer is formed by using via 1 made with GI2 (GI2 is the second gate insulating layer) mask that penetrates the first gate insulating layer, the first interlayer dielectric layer, the second interlayer dielectric layer, the second buffer layer, and the second gate insulating layer, via 2 made with ILD2 (ILD2 is the third interlayer dielectric layer) mask that penetrates the third interlayer dielectric layer, and via 3 made with PLN1 (PLN1 is the first planarization layer) mask that penetrates the first planarization layer (for LTPO products); or, via 1 made with GI2 mask that penetrates the first gate insulating layer and the second gate insulating layer, via 2 made with ILD (ILD is the interlayer dielectric layer) mask that penetrates the interlayer dielectric layer, and via 3 made with PLN1 mask that penetrates the passivation layer and the first planarization layer (for LTPS products), avoiding excessively deep vias.

[0469] In at least one embodiment of this disclosure, the connection between the second source / drain metal layer and the semiconductor layer can be achieved through vias that penetrate the interlayer dielectric layer (ILD) and the planarization layer (PLN). These vias are formed by via 1, which is made using an ILD2 mask and penetrates the first gate insulating layer, the first interlayer dielectric layer, the second interlayer dielectric layer, the second buffer layer, the second gate insulating layer, and the third interlayer dielectric layer, and via 2, which is made using a PLN1 mask and penetrates the first planarization layer (for LTPO products). Alternatively, the connection between the semiconductor layer and the second source / drain metal layer can also be achieved by via 1, which is made using an ILD mask and penetrates the first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer, and via 2, which is made using a PLN1 mask and penetrates the passivation layer and the first planarization layer (for LTPS products).

[0470] Optionally, the gate of the transistor is formed on a first gate metal layer; the adapter line is formed on a first source-drain metal layer; and the signal line is formed on a second source-drain metal layer.

[0471] Figure 30 is a layout diagram of at least one embodiment of the driving circuit in at least one embodiment of the present disclosure. Figure 31 is a layout diagram of the semiconductor layer in Figure 30, Figure 32 is a layout diagram of the first gate metal layer in Figure 30, Figure 33 is a layout diagram of the second gate metal layer in Figure 30, Figure 34 is a layout diagram of the first source / drain metal layer in Figure 30, and Figure 35 is a layout diagram of the second source / drain metal layer in Figure 30.

[0472] As shown in Figures 30-35, the first clock signal line CK, the low voltage line VGL, the second clock signal line CB, and the high voltage line VGH are all formed in the second source-drain metal layer, and CK, VGL, CB, and VGH all extend in the vertical direction.

[0473] T6 and T7 are arranged vertically, and T8 and T4 are arranged vertically, which helps to achieve a narrow bezel;

[0474] The orthographic projection of the active graphic A8 of T8 onto the substrate at least partially overlaps with the orthographic projection of VGH onto the substrate, and the orthographic projection of the active graphic A4 of T4 onto the substrate at least partially overlaps with the orthographic projection of VGH onto the substrate.

[0475] The orthographic projection of the active pattern A6 of T6 onto the substrate at least partially overlaps with the orthographic projection of the second clock signal line CB onto the substrate, and the orthographic projection of the active pattern A7 of T7 onto the substrate at least partially overlaps with the orthographic projection of CB onto the substrate.

[0476] The orthographic projection of the active pattern A3 of T3 onto the substrate at least partially overlaps with the orthographic projection of the low voltage line VGL onto the substrate.

[0477] This facilitates the achievement of narrow bezels.

[0478] In Figure 32, the plate labeled C1a is the first plate of C1, and the plate labeled C2a is the first plate of C2.

[0479] In Figure 33, the plate labeled C1b is the second plate of C1, and the plate labeled C2b is the second plate of C2.

[0480] In Figure 34, the part labeled LB17 is the seventeenth connecting part, the part labeled LB18 is the eighteenth connecting part, and the part labeled LB19 is the nineteenth connecting part.

[0481] As shown in Figures 30-35, T5 and T3 are arranged vertically; T8 and T4 are arranged vertically; T6 and T7 are arranged vertically; in order to save the horizontal space occupied by the drive circuit and facilitate the realization of a narrow bezel;

[0482] The orthographic projections of A1 and VGL on the substrate at least partially overlap; the orthographic projections of A5 and CK on the substrate at least partially overlap; the orthographic projections of A6 and CB on the substrate at least partially overlap; the orthographic projections of A7 and CB on the substrate at least partially overlap; the orthographic projections of A8 and VGH on the substrate at least partially overlap; and the orthographic projections of A4 and VGH on the substrate at least partially overlap; this saves the lateral space occupied by the driving circuit and facilitates the implementation of a narrow bezel.

[0483] The orthographic projection of T2 onto the substrate is positioned between the orthographic projections of T1 and T5 onto the substrate.

[0484] In at least one embodiment shown in Figures 30-35, the ratio between the area of ​​the circuit element region where the circuit elements (including T1, T2, T3, T4, T5, T6, T7, T8, C1, and C2) are located and the area of ​​the driving circuit region is 68.06%.

[0485] Optionally, the gate of the transistor is formed on a first gate metal layer; the transition line is formed on a second gate metal layer;

[0486] The conductive pattern formed on the first gate metal layer can be electrically connected to the conductive pattern formed on the second gate metal layer through a via.

[0487] In practical implementation, the conductive pattern formed on the first gate metal layer can be electrically connected to the conductive pattern formed on the second gate metal layer through a via, and the first gate metal layer can be directly connected to the second gate metal layer.

[0488] In at least one embodiment of Figures 36-65, the second gate metal layer is used as a transition line, and an ILD0 (ILD0 is the first interlayer dielectric layer) mask (for LTPO products) or a GI2 (GI2 is the second gate insulating layer) mask (for LTPS products) is added, so that the first gate metal layer and the second gate metal layer can be directly connected.

[0489] Figure 36 is a layout diagram of at least one embodiment of the driving circuit in at least one embodiment of the present disclosure. Figure 37 is a layout diagram of the semiconductor layer in Figure 36, Figure 38 is a layout diagram of the first gate metal layer in Figure 36, Figure 39 is a layout diagram of the second gate metal layer in Figure 36, Figure 40 is a layout diagram of the first source / drain metal layer in Figure 36, and Figure 41 is a layout diagram of the second source / drain metal layer in Figure 36.

[0490] As shown in Figures 36-41, the high voltage line VGH, the low voltage line VGL, the first clock signal line CK, and the second clock signal line CB are all formed in the first source-drain metal layer.

[0491] The gate G8 of T8 is electrically connected to the fourth conductive pattern DX4 through the fourth via H4.

[0492] The gate of T8 is formed in the first gate metal layer, and DX4 is formed in the second gate metal layer;

[0493] DX4 is electrically connected to the gate G6 of T6 through the fifth via H5, so that the gate G8 of T8 is electrically connected to the gate G6 of T6.

[0494] The gate G6 of T6 is electrically connected to the fifth conductive pattern DX5 formed on the second gate metal layer through the sixth via H6.

[0495] The gate G7 of T7 is electrically connected to the sixth conductive pattern DX6 through the seventh via H7. DX6 is formed on the second gate metal layer.

[0496] T8 and T4 are arranged vertically; T6 and T7 are arranged vertically, which helps to achieve a narrow bezel.

[0497] As shown in Figures 36-41, the orthographic projection of A8 on the substrate and the orthographic projection of VGH on the substrate at least partially overlap;

[0498] The orthographic projection of A4 onto the substrate at least partially overlaps with the orthographic projection of VGH onto the substrate;

[0499] T8 and T4 are arranged vertically.

[0500] In Figure 40, the plate labeled C1a is the first plate of C1, and the plate labeled C2a is the first plate of C2.

[0501] In Figure 41, the first plate of C1 is labeled C1a, and the first plate of C2 is labeled C2a.

[0502] The orthographic projection of C1a onto the substrate at least partially overlaps with the orthographic projection of C1b onto the substrate, and the orthographic projection of C2a onto the substrate at least partially overlaps with the orthographic projection of C2b onto the substrate.

[0503] The orthographic projection of C1a on the substrate at least partially overlaps with the orthographic projection of A8 on the substrate; the orthographic projection of C1b on the substrate at least partially overlaps with the orthographic projection of A8 on the substrate; the orthographic projection of C2a on the substrate at least partially overlaps with the orthographic projection of A4 on the substrate; the orthographic projection of C2b on the substrate at least partially overlaps with the orthographic projection of A4 on the substrate; this reduces the lateral space occupied by the driving circuit and facilitates the realization of a narrow bezel.

[0504] In at least one embodiment shown in Figures 36-41, the ratio between the area of ​​the circuit element region where the circuit elements (including T1, T2, T3, T4, T5, T6, T7, T8, C1, and C2) are located and the area of ​​the driving circuit region is 54.42%.

[0505] In at least one embodiment shown in Figures 36-41, the orthographic projection of VGH on the substrate at least partially overlaps with the orthographic projection of the active pattern A8 of T8 on the substrate, and the orthographic projection of VGH on the substrate at least partially overlaps with the orthographic projection of the active pattern A4 of T4 on the substrate.

[0506] In practice, the orthographic projection of VGH onto the substrate may not overlap with the orthographic projection of A8 onto the substrate, and the orthographic projection of VGH onto the substrate may not overlap with the orthographic projection of A4 onto the substrate.

[0507] In at least one embodiment of this disclosure, the orthographic projection of each signal line may or may not overlap with the orthographic projection of any circuit element on the substrate.

[0508] In at least one embodiment of this disclosure, the signal line is formed on a first source / drain metal layer or a second source / drain metal layer;

[0509] At least a portion of the orthographic projection of the signal line onto the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the driving circuit onto the substrate.

[0510] In a specific implementation, the signal line can be formed on a first source-drain metal layer or a second source-drain metal layer. At least a portion of the orthographic projection of the signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the driving circuit on the substrate, which is beneficial for achieving a narrow bezel.

[0511] Figure 42 is a layout diagram of at least one embodiment of the driving circuit in at least one embodiment of the present disclosure. Figure 43 is a layout diagram of the semiconductor layer in Figure 42, Figure 44 is a layout diagram of the first gate metal layer in Figure 42, Figure 45 is a layout diagram of the second gate metal layer in Figure 42, Figure 46 is a layout diagram of the first source / drain metal layer in Figure 42, and Figure 47 is a layout diagram of the second source / drain metal layer in Figure 42.

[0512] As shown in Figures 42-47, the first clock signal line CK, the second clock signal line CB, the high voltage line VGH, and the low voltage line VGL extend in the vertical direction; CK, CB, VGH, and VGL are all formed in the first source-drain metal layer;

[0513] T1, the second transistor T2, and T5 are positioned between the orthogonal projection of the low voltage line VGL onto the substrate and the orthogonal projection of the first clock signal line CK onto the substrate.

[0514] T6 and T7 are arranged vertically, and T8 and T4 are arranged vertically.

[0515] The orthographic projection of the active graphic A6 on the substrate of T6 at least partially overlaps with the orthographic projection of the second clock signal line CB on the substrate, and the orthographic projection of the active graphic A7 on the substrate of T7 at least partially overlaps with the orthographic projection of the second clock signal line CB on the substrate, which is beneficial for achieving a narrow bezel.

[0516] The orthographic projection of the active graphic A3 of T3 onto the substrate at least partially overlaps with the orthographic projection of the first clock signal line CK onto the substrate, which is beneficial for achieving a narrow bezel.

[0517] The orthographic projection of the active graphic A8 on the substrate of T8 at least partially overlaps with the orthographic projection of the high voltage line VGH on the substrate, which is beneficial for achieving a narrow bezel.

[0518] The orthographic projection of the active pattern A4 on the substrate of T4 at least partially overlaps with the orthographic projection of the high voltage line VGH on the substrate, which is beneficial for achieving a narrow bezel.

[0519] In Figure 44, the gate labeled G8 is the gate of T8, and the gate labeled G4 is the gate of T4.

[0520] In Figure 45, the part labeled LB20 is the twentieth connecting part, the part labeled LB22 is the twenty-first connecting part, and the part labeled LB22 is the twenty-second connecting part.

[0521] In Figure 46, the first plate of C1 is labeled C1a, and the first plate of C2 is labeled C2a.

[0522] In Figure 47, the plate labeled C1b is the second plate of C1, and the plate labeled C2b is the second plate of C2.

[0523] As shown in Figures 42-47, the orthographic projection of C1a on the substrate at least partially overlaps with the orthographic projection of C1b on the substrate, and the orthographic projection of C2a on the substrate at least partially overlaps with the orthographic projection of C2b on the substrate.

[0524] The orthographic projection of C1a onto the substrate at least partially overlaps with the orthographic projection of A8 onto the substrate, and the orthographic projection of C1b onto the substrate at least partially overlaps with the orthographic projection of A8 onto the substrate.

[0525] The orthographic projection of C2a onto the substrate at least partially overlaps with the orthographic projection of A4 onto the substrate, and the orthographic projection of C2b onto the substrate at least partially overlaps with the orthographic projection of A4 onto the substrate;

[0526] This reduces the lateral space occupied by the drive circuit, making it easier to achieve a narrow bezel.

[0527] In at least one embodiment shown in Figures 42-47, the ratio between the area of ​​the circuit element region where the circuit elements (including T1, T2, T3, T4, T5, T6, T7, T8, C1, and C2) are located and the area of ​​the driving circuit region is 64.7%.

[0528] Figure 48A is a layout diagram of at least one embodiment of the driving circuit in at least one embodiment of this disclosure. Figure 49 is a layout diagram of the semiconductor layer in Figure 48A, Figure 50 is a layout diagram of the first gate metal layer in Figure 48A, Figure 51 is a layout diagram of the second gate metal layer in Figure 48A, Figure 52 is a layout diagram of the first source / drain metal layer in Figure 48A, and Figure 53 is a layout diagram of the second source / drain metal layer in Figure 48A.

[0529] Figure 48B is a layout diagram of Figure 48A with the second source / drain metal layer removed.

[0530] As shown in Figures 48A-53, the first clock signal line CK, the second clock signal line CB, the high voltage line VGH, and the low voltage line VGL extend in the vertical direction; CK, CB, VGH, and VGL are all formed in the second source / drain metal layer;

[0531] T1, the second transistor T2, and T5 are positioned between the orthogonal projection of the low voltage line VGL onto the substrate and the orthogonal projection of the first clock signal line CK onto the substrate.

[0532] T6 and T7 are arranged vertically, and T8 and T4 are arranged vertically.

[0533] The orthographic projection of the active graphic A6 on the substrate of T6 at least partially overlaps with the orthographic projection of the second clock signal line CB on the substrate, and the orthographic projection of the active graphic A7 on the substrate of T7 at least partially overlaps with the orthographic projection of the second clock signal line CB on the substrate, which is beneficial for achieving a narrow bezel.

[0534] The orthographic projection of the active graphic A3 of T3 onto the substrate at least partially overlaps with the orthographic projection of the first clock signal line CK onto the substrate, which is beneficial for achieving a narrow bezel.

[0535] The orthographic projection of the active graphic A8 on the substrate of T8 at least partially overlaps with the orthographic projection of the high voltage line VGH on the substrate, which is beneficial for achieving a narrow bezel.

[0536] The orthographic projection of the active pattern A4 on the substrate of T4 at least partially overlaps with the orthographic projection of the high voltage line VGH on the substrate, which is beneficial for achieving a narrow bezel.

[0537] In Figure 50, the active pattern labeled G8 is T8, and the active pattern labeled G4 is T4.

[0538] In Figure 51, the part labeled LB23 is the twenty-third connecting part, the part labeled LB24 is the twenty-fourth connecting part, and the part labeled LB25 is the twenty-fifth connecting part.

[0539] In Figure 52, the first plate of C1 is labeled C1a, and the first plate of C2 is labeled C2a.

[0540] In Figure 53, the plate labeled C1b is the second plate of C1, and the plate labeled C2b is the second plate of C2.

[0541] As shown in Figures 48A-53, the orthographic projection of C1a on the substrate at least partially overlaps with the orthographic projection of C1b on the substrate, and the orthographic projection of C2a on the substrate at least partially overlaps with the orthographic projection of C2b on the substrate.

[0542] The orthographic projection of C1a on the substrate at least partially overlaps with the orthographic projection of A8 on the substrate; the orthographic projection of C1b on the substrate at least partially overlaps with the orthographic projection of A8 on the substrate; the orthographic projection of C2a on the substrate at least partially overlaps with the orthographic projection of A4 on the substrate; the orthographic projection of C2b on the substrate at least partially overlaps with the orthographic projection of A4 on the substrate; this is to reduce the lateral space occupied by the driving circuit and to facilitate the realization of a narrow bezel.

[0543] In at least one embodiment shown in Figures 48A-53, the ratio between the area of ​​the circuit element region where the circuit elements (including T1, T2, T3, T4, T5, T6, T7, T8, C1, and C2) are located and the area of ​​the driving circuit region is 64.16%.

[0544] In at least one embodiment of this disclosure, the gate of the transistor is formed on a first gate metal layer; the transition line is formed on a second gate metal layer or a first source / drain metal layer;

[0545] The conductive pattern formed on the first gate metal layer can be electrically connected to the conductive pattern formed on the second gate metal layer through a via;

[0546] The signal line is formed in the second source / drain metal layer.

[0547] In a specific implementation, the gate of the transistor can be formed on the first gate metal layer, the adapter line can be formed on the second gate metal layer or the first source-drain metal layer, the signal line can be formed on the second source-drain metal layer, and the pattern formed on the first gate metal layer can be electrically connected to the conductive pattern formed on the second gate metal layer through a via.

[0548] Figure 54A is a layout diagram of at least one embodiment of the driving circuit in at least one embodiment of this disclosure. Figure 55 is a layout diagram of the semiconductor layer in Figure 54A, Figure 56 is a layout diagram of the first gate metal layer in Figure 54A, Figure 57 is a layout diagram of the second gate metal layer in Figure 54A, Figure 58 is a layout diagram of the first source / drain metal layer in Figure 54A, and Figure 59 is a layout diagram of the second source / drain metal layer in Figure 54A.

[0549] Figure 54B is a layout diagram based on Figure 54A, with the second source / drain metal layer removed.

[0550] As shown in Figures 54A-59, the low-voltage line VGL, the first clock signal line CK, the second clock signal line CB, and the high-voltage line VGH extend in the vertical direction;

[0551] The gate G8 of T8 is electrically connected to the seventh conductive pattern DX7 formed on the first source-drain metal layer through the eighth via H8, and the seventh conductive pattern DX7 is electrically connected to the gate G6 of the sixth transistor T6 through the ninth via H9.

[0552] The gate G2 of T2 is electrically connected to the eighth conductive pattern DX8 formed on the second gate metal layer through the tenth via H10. The eighth conductive pattern DX8 is electrically connected to the active pattern A5 of T5.

[0553] The gate G6 of T6 is electrically connected to the ninth conductive pattern DX9 formed on the first source-drain metal layer through the eleventh via H11. DX9 is electrically connected to the tenth conductive pattern DX10 formed on the second gate metal layer through the twelfth via H12. DX10 is electrically connected to the first electrode of T2.

[0554] DX9 is electrically connected to the eleventh conductive pattern DX11 formed on the second gate metal layer through the thirteenth via H13, and DX11 is electrically connected to the active pattern A3 of T1.

[0555] The gate G4 of T4 is electrically connected to the twelfth conductive pattern DX12 formed on the first source / drain metal layer through the fourteenth via H14.

[0556] DX12 is electrically connected to the thirteenth conductive pattern DX13 formed on the second gate metal layer through the fifteenth via H15, and DX13 is electrically connected to the active pattern A3 of T3.

[0557] T5, T6 and T7 extend vertically, which helps to achieve a narrow bezel;

[0558] T8 and T4 extend vertically, which helps to achieve a narrow bezel;

[0559] T2 and T3 extend vertically, which helps to achieve a narrow bezel;

[0560] The orthographic projection of the active pattern A8 of T8 onto the substrate at least partially overlaps with the orthographic projection of the high-voltage line VGH onto the substrate.

[0561] The orthographic projection of the active pattern A4 of T4 onto the substrate at least partially overlaps with the orthographic projection of the second clock signal line CB onto the substrate;

[0562] The orthographic projection of the active pattern A6 of T6 onto the substrate at least partially overlaps with the orthographic projection of the second clock signal line CB onto the substrate;

[0563] The orthographic projection of the active pattern A2 of T2 onto the substrate at least partially overlaps with the orthographic projection of the second clock signal line CB onto the substrate;

[0564] The orthographic projection of the active pattern A3 of T3 onto the substrate at least partially overlaps with the orthographic projection of the second clock signal line CB onto the substrate;

[0565] The orthographic projection of the active pattern A5 of T5 onto the substrate at least partially overlaps with the orthographic projection of the second clock signal line CB onto the substrate.

[0566] The orthographic projection of the active pattern A1 of T1 onto the substrate at least partially overlaps with the orthographic projection of the low voltage line VGL onto the substrate;

[0567] This facilitates the achievement of narrow bezels.

[0568] As shown in Figures 54A-59, the orthographic projection of C1a on the substrate at least partially overlaps with the orthographic projection of C1b on the substrate, and the orthographic projection of C2a on the substrate at least partially overlaps with the orthographic projection of C2b on the substrate.

[0569] The orthographic projection of C1a on the substrate at least partially overlaps with the orthographic projection of A8 on the substrate; the orthographic projection of C1b on the substrate at least partially overlaps with the orthographic projection of A8 on the substrate; the orthographic projection of C2a on the substrate at least partially overlaps with the orthographic projection of A4 on the substrate; the orthographic projection of C2b on the substrate at least partially overlaps with the orthographic projection of A4 on the substrate; this is to reduce the lateral space occupied by the driving circuit and to facilitate the realization of a narrow bezel.

[0570] In at least one embodiment shown in Figures 54A-59, the ratio between the area of ​​the circuit element region where the circuit elements (including T1, T2, T3, T4, T5, T6, T7, T8, C1, and C2) are located and the area of ​​the driving circuit region is 82.73%.

[0571] Optionally, the orthographic projection of at least one capacitor included in the driving circuit onto the substrate at least partially overlaps with the orthographic projection of at least one transistor included in the driving circuit onto the substrate, which is beneficial for achieving a narrow bezel.

[0572] Figure 60A is a layout diagram of at least one embodiment of the driving circuit in at least one embodiment of this disclosure. Figure 61 is a layout diagram of the semiconductor layer in Figure 60A, Figure 62 is a layout diagram of the first gate metal layer in Figure 60A, Figure 63 is a layout diagram of the second gate metal layer in Figure 60A, Figure 64 is a layout diagram of the first source / drain metal layer in Figure 60A, and Figure 65 is a layout diagram of the second source / drain metal layer in Figure 60A.

[0573] Figure 60B is a layout diagram based on Figure 60A, with the second source / drain metal layer removed.

[0574] As shown in Figures 60A-65, the first electrode C1a of C1 is formed in the first source / drain metal layer, and the second electrode C1b of C1 is formed in the second source / drain metal layer.

[0575] The first electrode C2a of C2 is formed in the first source / drain metal layer, and the second electrode C2b of C2 is formed in the second source / drain metal layer;

[0576] The orthographic projection of C1a onto the substrate at least partially overlaps with the orthographic projection of C1b onto the substrate, and the orthographic projection of C2a onto the substrate at least partially overlaps with the orthographic projection of C2b onto the substrate.

[0577] The orthographic projection of the active graphic A8 of T8 onto the substrate at least partially overlaps with the orthographic projection of C1a onto the substrate;

[0578] The orthographic projection of the active graphic A8 of T8 onto the substrate at least partially overlaps with the orthographic projection of C1b onto the substrate;

[0579] The orthographic projection of the active pattern A4 of T4 onto the substrate at least partially overlaps with the orthographic projection of C2a onto the substrate;

[0580] The orthographic projection of the active pattern A4 of T4 onto the substrate at least partially overlaps with the orthographic projection of C2b onto the substrate;

[0581] This helps save lateral space in the drive circuit and facilitates the achievement of a narrow bezel.

[0582] As shown in Figures 60A-65, the orthographic projection of A4 onto the substrate covers the orthographic projection of the first plate C2a of C2 onto the substrate, and the orthographic projection of A4 onto the substrate covers the orthographic projection of the second plate C2b of C2 onto the substrate.

[0583] As shown in Figures 60A-65, T5, T6, and T7 are arranged vertically, T2 and T3 are arranged vertically, and T8 and T4 are arranged vertically to reduce the horizontal space occupied by the driving circuit, for example, to achieve a narrow bezel.

[0584] The orthographic projection of A1 onto the substrate at least partially overlaps with the orthographic projection of VGL onto the substrate; the orthographic projection of A2 onto the substrate at least partially overlaps with the orthographic projection of CK onto the substrate; the orthographic projection of A3 onto the substrate at least partially overlaps with the orthographic projection of VGL onto the substrate; and the orthographic projection of A5 onto the substrate at least partially overlaps with the orthographic projection of VGL onto the substrate.

[0585] The orthographic projection of A5 onto the substrate at least partially overlaps with the orthographic projection of CB onto the substrate; the orthographic projection of A6 onto the substrate at least partially overlaps with the orthographic projection of CB onto the substrate; the orthographic projection of A7 onto the substrate at least partially overlaps with the orthographic projection of CB onto the substrate.

[0586] The orthographic projection of A8 onto the substrate at least partially overlaps with the orthographic projection of VGH onto the substrate; the orthographic projection of A4 onto the substrate at least partially overlaps with the orthographic projection of VGH onto the substrate;

[0587] To reduce the lateral space occupied by the driving circuit, for example, to achieve a narrow bezel.

[0588] In at least one embodiment shown in Figures 60A-65, the ratio between the area of ​​the circuit element region where the circuit elements (including T1, T2, T3, T4, T5, T6, T7, T8, C1, and C2) are located and the area of ​​the driving circuit region is 91.27%.

[0589] In at least one embodiment shown in Figures 2-65, the structure of at least one embodiment of the driving circuit is shown in Figure 1C.

[0590] Optionally, the driving circuit includes a first node control circuit, a second node control circuit, a third node control circuit, a fourth node control circuit, and a fifth node control circuit.

[0591] The first node control circuit is electrically connected to the first node and the first clock signal line respectively, and is used to control the potential of the first node according to the first clock signal provided by the first clock signal line;

[0592] The second node control circuit is electrically connected to the first clock signal line and the second node respectively, and is used to control the potential of the second node under the control of the first clock signal;

[0593] The third node control circuit is electrically connected to the first node, the second node, the third node, and the sixth node, respectively, and is used to control the potential of the third node according to the potential of the second node, control the potential of the fourth node under the control of the potential of the first node, control the potential of the sixth node under the control of the potential of the third node, and control the potential of the third node according to the potential of the sixth node.

[0594] The fourth node control circuit is electrically connected to both the first node and the fourth node, and is used to control the potential of the fourth node according to the potential of the first node.

[0595] The fifth node control circuit is electrically connected to the second clock signal line, the fourth node, the fifth node, the second node, and the first voltage line, respectively. It is used to control the potential of the fifth node according to the potential of the fourth node and the second clock signal provided by the second clock signal line, and to control the potential of the fifth node according to the first voltage signal provided by the first voltage line under the control of the second clock signal and the potential of the second node.

[0596] The transistors included in the first node control circuit are arranged along a first direction;

[0597] The transistors included in the first node control circuit and the transistors included in the second node are arranged along a first direction;

[0598] The transistors included in the third node control circuit are arranged along a first direction;

[0599] The transistors included in the fourth node control circuit are arranged along the first direction with the transistors included in the third node control circuit.

[0600] The transistors in the fifth node control circuit are arranged along a first direction.

[0601] As shown in Figure 66, at least one embodiment of the driving circuit includes a first node control circuit 1, a second node control circuit 12, a third node control circuit 13, a fourth node control circuit 14, a fifth node control circuit 15, an output reset circuit 10, and an output circuit 20.

[0602] The first node control circuit 11 is electrically connected to the first node N1 and the first clock signal line CK respectively, and is used to control the potential of the first node N1 according to the first clock signal provided by the first clock signal line CK.

[0603] The second node control circuit 12 is electrically connected to the first clock signal line CK and the second node N2 respectively, and is used to control the potential of the second node N2 under the control of the first clock signal;

[0604] The third node control circuit 13 is electrically connected to the first node N1, the second node N2, the third node N3, the sixth node N6, and the second clock signal line CB, respectively. It is used to control the potential of the third node N3 according to the potential of the second node N2, control the potential of the fourth node N4 under the control of the potential of the first node N1, control the connection or disconnection between the sixth node N6 and the second clock signal line CB under the control of the potential of the third node N3, and control the potential of the third node N3 according to the potential of the sixth node N6.

[0605] The fourth node control circuit 14 is electrically connected to the first node N1 and the fourth node N4 respectively, and is used to control the potential of the fourth node N4 according to the potential of the first node N1.

[0606] The fifth node control circuit 15 is electrically connected to the second clock signal line CB, the fourth node N4, the fifth node N5, the second node N2 and the first voltage line V1, respectively. It is used to control the potential of the fifth node N5 according to the potential of the fourth node N4 and the second clock signal provided by the second clock signal line CB, and under the control of the second clock signal and the potential of the second node N2, to control the potential of the fifth node N5 according to the first voltage signal provided by the first voltage line V1.

[0607] The output circuit 20 is electrically connected to the fifth node N5, the first voltage line V1 and the drive output terminal OT respectively, and is used to control the connection or disconnection between the drive output terminal OT and the first voltage line V1 under the control of the potential of the fifth node N5.

[0608] The output reset circuit 10 is electrically connected to the third node N3, the drive output terminal OT, and the second voltage line V2, respectively, and is used to control the connection or disconnection between the drive output terminal OT and the second voltage line V2 under the control of the potential of the third node N3.

[0609] Optionally, the first voltage line can be a high voltage line, and the second voltage line can be a low voltage line.

[0610] As shown in Figure 67, based on at least one embodiment of the driving circuit shown in Figure 66, the first node control circuit includes a first transistor T1 and a second transistor T2; the second node control circuit includes a fifth transistor T5; the third node control circuit includes a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11; the fourth node control circuit includes a twelfth transistor T12; the fifth node control circuit includes a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a sixteenth transistor T16; the output circuit includes an eighth transistor T8; the output reset circuit includes a fourth transistor T4; and the driving circuit further includes a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0611] The gate of T1 is electrically connected to the first clock signal line CK, the first electrode of T1 is electrically connected to the low voltage line VGL, and the second electrode of T1 is electrically connected to the first node N1.

[0612] The gate of T2 is electrically connected to the second node N2, the first electrode of T2 is electrically connected to the second electrode of T1, and the second electrode of T2 is electrically connected to the first clock signal line CK.

[0613] The gate of T5 is electrically connected to the first clock signal line CK, the first electrode of T5 is electrically connected to the input terminal I1, and the second electrode of T5 is electrically connected to the second node N2.

[0614] The gate of T9 is electrically connected to the low voltage line VGL, the first electrode of T9 is electrically connected to the second node N2, and the second electrode of T9 is electrically connected to the third node N3.

[0615] The gate of T10 is electrically connected to the first node N1, the first electrode of T10 is electrically connected to the high voltage line VGH, and the second electrode of T10 is electrically connected to the sixth node N6.

[0616] The gate of T11 is electrically connected to the third node N3, the first electrode of T11 is electrically connected to the sixth node N6, and the second electrode of T11 is electrically connected to the second clock signal line CB.

[0617] The gate of T12 is electrically connected to the low voltage line VGL, the first electrode of T12 is electrically connected to the first node N1, and the second electrode of T12 is electrically connected to the gate of T13.

[0618] The first electrode of T13 is electrically connected to the second clock signal line CB, and the second electrode of T13 is electrically connected to the first electrode of T14.

[0619] The gate of T14 is electrically connected to the second clock signal line CB, and the gate of T15 is electrically connected to the gate of T8.

[0620] The gate of T15 is electrically connected to the second node N2, the first electrode of T15 is electrically connected to the fifth node N5, and the second electrode of T15 is electrically connected to the high voltage line VGH.

[0621] The gate of T16 is electrically connected to the second clock signal line CB, the first electrode of T16 is electrically connected to the high voltage line VGH, and the second electrode of T16 is electrically connected to the second node N2.

[0622] The gate of T8 is electrically connected to the fifth node N5, the first electrode of T8 is electrically connected to the high voltage line VGH, and the second electrode of T8 is electrically connected to the drive output terminal OT.

[0623] The gate of T4 is electrically connected to the third node N3, the first electrode of T4 is electrically connected to the drive output terminal OT, and the second electrode of T4 is electrically connected to the low voltage line VGL.

[0624] The first plate of C1 is electrically connected to the fifth node N5, and the second plate of C1 is electrically connected to the high voltage line VGH.

[0625] The first electrode of C2 is electrically connected to the third node N3, and the second electrode of C2 is electrically connected to the sixth node N6.

[0626] The first electrode of C3 is electrically connected to the gate of T13, and the second electrode of C3 is electrically connected to the second electrode of T13.

[0627] In at least one embodiment shown in Figure 67, all transistors are p-type transistors, but this is not a limitation.

[0628] In at least one embodiment of this disclosure, the signal line is formed on a second source-drain metal layer; the active pattern of the transistor is formed on a semiconductor layer; and the active pattern can be directly electrically connected to the conductive pattern formed on the second source-drain metal layer through a via.

[0629] In a specific implementation, the signal line can be formed on the second source / drain metal layer. It can be masked by the gate insulating layer, and the semiconductor layer and the second source / drain metal layer can be directly electrically connected through vias that penetrate the gate insulating layer and the planarization layer, avoiding excessively deep vias.

[0630] In at least one embodiment shown in Figures 68A-90, by adding a via through the gate insulating layer GI, the semiconductor layer and the second source / drain metal layer can be directly electrically connected through the via through the gate insulating layer and the planarization layer, avoiding excessively deep vias.

[0631] In at least one embodiment of this disclosure, the active pattern of at least two transistors electrically connected to the second clock signal line is integrally formed in the fifth node control circuit; and / or, the active pattern of the transistors electrically connected to the first voltage line is integrally formed in the fifth node control circuit.

[0632] Figure 68A is a layout diagram of at least one embodiment of the drive circuit shown in Figure 67.

[0633] Figures 68B and 68C are layout diagrams of Figure 68A with the second source / drain metal layer removed.

[0634] Figure 69 is a layout diagram of the semiconductor layer in Figure 68A, Figure 70 is a layout diagram of the first gate metal layer in Figure 68A, Figure 71 is a layout diagram of the second gate metal layer in Figure 68A, Figure 72 is a layout diagram of the third gate metal layer in Figure 68A, Figure 73 is a layout diagram of the first source / drain metal layer in Figure 68A, and Figure 74 is a layout diagram of the second source / drain metal layer in Figure 68A.

[0635] In at least one embodiment shown in Figures 68A-74, the signal line can be formed on the second source / drain metal layer. It can be directly electrically connected to the semiconductor layer and the second source / drain metal layer through a via that penetrates the gate insulating layer and the planarization layer by a masking layer, thus avoiding excessively deep vias.

[0636] As shown in Figures 68A-74, the active pattern A1 of T1 and the active pattern A2 of T2 are integrally formed.

[0637] The first clock signal line CK is formed on the second source-drain metal layer; the low voltage line VGL, the second clock signal line CB, and the high voltage line VGH are formed on the second source-drain metal layer;

[0638] The active pattern A2 of T2 is electrically connected to CK through the sixteenth via H16 and the fourteenth conductive pattern DX14 formed on the first source / drain metal layer.

[0639] The active pattern A5 of T5 is electrically connected to the fifteenth conductive pattern DX15 formed on the first source / drain metal layer through the seventeenth via H17. DX15 is electrically connected to the active pattern A9 of T9 through the eighteenth via H18. DX15 is electrically connected to the active pattern A16 of T16 through the twenty-fifth via H25.

[0640] The active pattern A1 of T1 is electrically connected to the sixteenth conductive pattern DX16 formed on the third gate metal layer through the nineteenth via H19; DX16 is electrically connected to the active pattern A12 of T12 through the twentieth via H20.

[0641] The active pattern A11 of T11 is electrically connected to the seventeenth conductive pattern DX17 formed on the third gate metal layer through the twentieth via H21, and DX17 is electrically connected to the second clock signal line CB through the twenty-second via H22.

[0642] The active pattern A10 of T10 is electrically connected to the eighteenth conductive pattern DX18 formed on the third gate metal layer through the twenty-third via H23. DX18 is electrically connected to the first plate C2a of the second capacitor C2 formed on the second gate metal layer through the twenty-fourth via H24.

[0643] The active pattern A13 of T13 is electrically connected to the second clock signal line CB through the twenty-fifth via H25 and the nineteenth conductive pattern DX19 formed on the first source / drain metal layer.

[0644] The active pattern A13 of T13 is electrically connected to the twentieth conductive pattern DX20 formed on the first source / drain metal layer through the twenty-sixth via H26, and DX20 is electrically connected to the active pattern A14 of T14 through the twenty-seventh via H27.

[0645] DX19 is electrically connected to the second plate C3b of the third capacitor C3 through the twenty-eighth via H28; C3b is formed in the second gate metal layer; the first plate of C3 is labeled C3a, which is formed in the first gate metal layer;

[0646] The gate G4 of T4 is electrically connected to the 21st conductive pattern DX21 formed on the third gate metal layer through the 29th via H29. DX21 is electrically connected to the active pattern A9 of T9 through the 30th via H30.

[0647] DX21 is electrically connected to the gate G11 of T11 through the thirty-first via H31.

[0648] The active pattern A8 of T8 is electrically connected to the 22nd conductive pattern DX22 formed on the first source / drain metal layer through the 32nd via H32. DX22 is electrically connected to the high voltage line VGH through the 33rd via H33. DX22 is electrically connected to the second plate C1b of the first capacitor C1 through the 34th via H34. C1b is formed on the second gate metal layer.

[0649] The first plate C1a of the first capacitor C1 is integrally formed with the gate G8 of T8; both G8 and C1a are formed on the first gate metal layer;

[0650] The active graphic A8 of T8 and the active graphic A4 of T4 are integrally formed;

[0651] T8's active pattern A8 is electrically connected to the 23rd conductive pattern DX23 via the 35th via H35.

[0652] The active pattern A4 of T4 is electrically connected to DX23 through the thirty-sixth via H36; DX23 is formed in the first source / drain metal layer;

[0653] The gate G8 of T8 is electrically connected to the 24th conductive pattern DX24 formed on the third gate metal layer through the 37th via H37. DX24 is electrically connected to the active pattern A14 of T14 through the 38th via H38.

[0654] As shown in Figures 68A-74, T1, T2, and T5 are arranged in sequence along the vertical direction, T12, T10, and T11 are arranged in sequence along the vertical direction, T14, T15, and T16 are arranged in sequence along the vertical direction, and T8 and T4 are arranged in sequence along the vertical direction, which is conducive to achieving a narrow bezel.

[0655] The orthographic projection of the active graphic A1 on the substrate of T1 at least partially overlaps with the orthographic projection of CK on the substrate; the orthographic projection of the active graphic A2 on the substrate of T2 at least partially overlaps with the orthographic projection of CK on the substrate; the orthographic projection of the active graphic A5 on the substrate of T5 at least partially overlaps with the orthographic projection of CK on the substrate.

[0656] The orthographic projection of the active graphic A12 of T12 onto the substrate at least partially overlaps with the orthographic projection of VGL onto the substrate; the orthographic projection of the active graphic A10 of T10 onto the substrate at least partially overlaps with the orthographic projection of VGL onto the substrate; the orthographic projection of the active graphic A11 of T11 onto the substrate at least partially overlaps with the orthographic projection of VGL onto the substrate.

[0657] The orthographic projection of the active graphic A8 of T8 onto the substrate at least partially overlaps with the orthographic projection of VGH onto the substrate; the orthographic projection of the active graphic A4 of T4 onto the substrate at least partially overlaps with the orthographic projection of VGH onto the substrate.

[0658] This reduces the lateral space occupied by the drive circuit, making it easier to achieve a narrow bezel.

[0659] As shown in Figures 68A-74, the orthographic projection of the first plate C3a of C3 onto the substrate at least partially overlaps with the orthographic projection of CB onto the substrate; the orthographic projection of the second plate C3b of C3 onto the substrate at least partially overlaps with the orthographic projection of CB onto the substrate; the orthographic projection of the first plate C2a of C2 onto the substrate at least partially overlaps with the orthographic projection of CB onto the substrate; the orthographic projection of the second plate C2b of C2 onto the substrate at least partially overlaps with the orthographic projection of CB onto the substrate; the orthographic projection of the first plate C1a of C1 onto the substrate at least partially overlaps with the orthographic projection of VGH onto the substrate; the orthographic projection of the second plate C1b of C1 onto the substrate at least partially overlaps with the orthographic projection of VGH onto the substrate.

[0660] This reduces the lateral space occupied by the drive circuit, making it easier to achieve a narrow bezel.

[0661] In Figure 69, A1 is the first active pattern of T1, A2 is the first active pattern of T1, A5 is the first active pattern of T5, A9 is the first active pattern of T9, A10 is the first active pattern of T10, A11 is the first active pattern of T11, A12 is the first active pattern of T12, A13 is the first active pattern of T13, A14 is the first active pattern of T14, A15 is the first active pattern of T15, A16 is the first active pattern of T16, A8 is the first active pattern of T8, and A4 is the first active pattern of T4.

[0662] In at least one embodiment shown in Figures 68A-74, the ratio between the area of ​​the circuit element region where the circuit elements (including T1, T2, T5, T4, T8, T9, T10, T11, T12, T13, T14, T15, T16, C1, C2, and C3) are located and the area of ​​the driving circuit region is 60.69%.

[0663] Figure 75A is a layout diagram of at least one embodiment of the drive circuit shown in Figure 67.

[0664] Figure 75B is a layout diagram of Figure 75A with the second source / drain metal layer removed.

[0665] Figure 76 is a layout diagram of the semiconductor layer in Figure 75A, Figure 77 is a layout diagram of the first gate metal layer in Figure 75A, Figure 78 is a layout diagram of the second gate metal layer in Figure 75A, Figure 79 is a layout diagram of the third gate metal layer in Figure 75A, Figure 80 is a layout diagram of the first source / drain metal layer in Figure 75A, and Figure 81 is a layout diagram of the second source / drain metal layer in Figure 75A.

[0666] In at least one embodiment shown in Figures 75A-81, the signal line can be formed on the second source / drain metal layer. It can be directly electrically connected to the semiconductor layer and the second source / drain metal layer through a via that penetrates the gate insulating layer and the planarization layer through a mask, thus avoiding excessively deep vias.

[0667] Compared with the at least one embodiment shown in FIG68A, in the at least one embodiment shown in FIG75A, T13 is disposed below T14, and T13 is disposed in the space below T14, which helps to save horizontal space.

[0668] Furthermore, C3 and C2 are configured as a three-layer structure, which helps to reduce the area of ​​the electrode plates of C3 and C2, thus facilitating the achievement of a narrow bezel.

[0669] In Figure 76, A1 is the first active pattern of T1, A2 is the first active pattern of T1, A5 is the first active pattern of T5, A9 is the first active pattern of T9, A10 is the first active pattern of T10, A11 is the first active pattern of T11, A12 is the first active pattern of T12, A13 is the first active pattern of T13, A14 is the first active pattern of T14, A15 is the first active pattern of T15, A16 is the first active pattern of T16, A8 is the first active pattern of T8, and A4 is the first active pattern of T4.

[0670] In Figure 77, the part labeled C3a1 is the first electrode plate portion included in the first electrode plate of C3, the part labeled C2a1 is the first electrode plate portion included in the first electrode plate of C2, and the part labeled C1a is the first electrode plate of C1.

[0671] In Figure 78, the plate labeled C3b is the second plate of C3, the plate labeled C2b is the second plate of C2, and the plate labeled C1b is the second plate of C1.

[0672] In Figure 79, the part labeled C3a2 is the second electrode portion included in the first electrode plate of C3, and the part labeled C2a2 is the second electrode portion included in the first electrode plate of C2.

[0673] In at least one embodiment as shown in Figures 75A-81, C3a1 and C3a2 are electrically connected, and C2a1 and C2a2 are electrically connected.

[0674] The orthographic projections of C3a1, C3b, and C3a2 onto the substrate at least partially overlap.

[0675] The orthographic projections of C2a1, C2b, and C2a2 onto the substrate at least partially overlap.

[0676] The orthographic projection of C1a onto the substrate at least partially overlaps with the orthographic projection of C1b onto the substrate.

[0677] In Figure 80, the 22nd conductive pattern is labeled DX22, and the 23rd conductive pattern is labeled DX23.

[0678] In at least one embodiment shown in Figures 75A-81, A1 and A2 are integrally formed, A10 and A11 are integrally formed, A15 and A16 are integrally formed, A14 and A13 are integrally formed, and A8 and A4 are integrally formed.

[0679] T1, T2, and T5 are arranged vertically; T12, T10, T11, and T9 are arranged vertically; C3 and C2 are arranged vertically; T14, T13, T15, and T16 are arranged vertically; and T8 and T4 are arranged vertically. This arrangement saves horizontal space occupied by the drive circuit and facilitates the achievement of a narrow bezel.

[0680] As shown in Figures 75A-81, the orthographic projection of the first electrode C3a on the substrate of C3 at least partially overlaps with the orthographic projection of CB on the substrate; the orthographic projection of the second electrode C3b on the substrate of C3 at least partially overlaps with the orthographic projection of CB on the substrate; the orthographic projection of the first electrode C1a on the substrate of C1 at least partially overlaps with the orthographic projection of VGH on the substrate; the orthographic projection of the second electrode C1b on the substrate of C1 at least partially overlaps with the orthographic projection of VGH on the substrate, so as to save the lateral space occupied by the driving circuit and facilitate the realization of a narrow bezel.

[0681] In at least one embodiment shown in Figures 75A-81, the ratio between the area of ​​the circuit element region where the circuit elements (including T1, T2, T5, T4, T8, T9, T10, T11, T12, T13, T14, T15, T16, C1, C2, and C3) are located and the area of ​​the driving circuit region is 59.16%.

[0682] Optionally, the driving circuit includes a first node control circuit, a second node control circuit, a third node control circuit, a fourth node control circuit, and a fifth node control circuit.

[0683] The first node control circuit is electrically connected to the first node and the first clock signal line respectively, and is used to control the potential of the first node according to the first clock signal provided by the first clock signal line;

[0684] The second node control circuit is electrically connected to the first clock signal line, the second node, and the seventh node, respectively, and is used to control the potential of the second node and the potential of the seventh node under the control of the first clock signal.

[0685] The third node control circuit is electrically connected to the first node, the first voltage line, the second clock signal line, the sixth node, the seventh node, the eighth node, and the third node, respectively. It is used to control the potential of the third node according to the potential of the first node, control the potential of the eighth node according to the potential of the seventh node, control the potential of the third node according to the potential of the eighth node, control the potential of the sixth node under the control of the potential of the first node and the eighth node, control the potential of the eighth node according to the potential of the sixth node, and control the potential of the third node according to the potential of the eighth node.

[0686] The fourth node control circuit is electrically connected to the first node and the fourth node respectively, and is used to control the potential of the fourth node according to the potential of the first node;

[0687] The fifth node control circuit is electrically connected to the second clock signal line, the fourth node, the fifth node, the control voltage terminal, and the first node, respectively. It is used to control the potential of the fifth node under the control of the potential of the fourth node, according to the second clock signal provided by the second clock signal line, to control the potential of the second node under the control of the control voltage provided by the control voltage terminal, and to control the potential of the fifth node under the control of the potential of the first node.

[0688] The transistors included in the first node control circuit are arranged along a first direction, and the transistors included in the second node control circuit are arranged along a first direction. The transistors included in the first node control circuit and the transistors included in the second node control circuit are arranged along a first direction.

[0689] The transistors included in the third node control circuit are arranged along a first direction, and the transistors included in the fourth node control circuit and the transistors included in the third node control circuit are arranged along the first direction.

[0690] The transistors in the fifth node control circuit are arranged along a first direction.

[0691] Optionally, the first direction can be a vertical direction. By arranging the transistors included in the first node control circuit along the first direction, arranging the transistors included in the second node control circuit along the first direction, and arranging the transistors included in the first node control circuit and the second node control circuit along the first direction; arranging the transistors included in the third node control circuit and the fourth node control circuit along the first direction; and arranging the transistors included in the fifth node control circuit along the first direction, the horizontal space occupied by the driving circuit can be saved, which is beneficial for achieving a narrow bezel.

[0692] As shown in Figure 82, at least one embodiment of the driving circuit includes a first node control circuit 11, a second node control circuit 12, a third node control circuit 13, a fourth node control circuit 14 and a fifth node control circuit 15, an output reset circuit 10 and an output circuit 20.

[0693] The first node control circuit 11 is electrically connected to the first node N1 and the first clock signal line CK respectively, and is used to control the potential of the first node N1 according to the first clock signal provided by the first clock signal line CK.

[0694] The second node control circuit 12 is electrically connected to the first clock signal line CK, the second node N2 and the seventh node N7 respectively, and is used to control the potential of the second node N2 and the potential of the seventh node N7 under the control of the first clock signal.

[0695] The third node control circuit 13 is electrically connected to the first node N1, the first voltage line V1, the second clock signal line CB, the sixth node N6, the seventh node N7, the eighth node N8, and the third node N3, respectively. It is used to control the potential of the third node N3 according to the potential of the first node N1, control the potential of the eighth node N8 according to the potential of the seventh node N7, control the potential of the third node N3 according to the potential of the eighth node N8, control the potential of the sixth node N6 according to the potential of the sixth node N6, control the potential of the eighth node N8 according to the potential of the eighth node N8, and control the potential of the third node N3 according to the potential of the eighth node N8.

[0696] The fourth node control circuit 14 is electrically connected to the first node N1 and the fourth node N4 respectively, and is used to control the potential of the fourth node N4 according to the potential of the first node N1.

[0697] The fifth node control circuit 15 is electrically connected to the second clock signal line CB, the fourth node N4, the fifth node N5, the control voltage terminal VEL, and the first node N1, respectively. It is used to control the potential of the fifth node N5 under the control of the potential of the fourth node N4 and according to the second clock signal provided by the second clock signal line CB, control the potential of the second node N2 under the control of the control voltage provided by the control voltage terminal VEL, and control the potential of the fifth node N5 under the control of the potential of the first node N1.

[0698] The output circuit 20 is electrically connected to the fifth node N5, the first voltage line V1 and the drive output terminal OT respectively, and is used to control the connection or disconnection between the drive output terminal OT and the first voltage line V1 under the control of the potential of the fifth node N5.

[0699] The output reset circuit 10 is electrically connected to the third node N3, the drive output terminal OT, and the second voltage line V2, respectively, and is used to control the connection or disconnection between the drive output terminal OT and the second voltage line V2 under the control of the potential of the third node N3.

[0700] As shown in Figure 83, based on at least one embodiment of the driving circuit shown in Figure 82, the first node control circuit includes a first transistor T1 and a second transistor T2; the second node control circuit includes a seventeenth transistor T17 and an eighteenth transistor T18; the third node control circuit includes a nineteenth transistor T19, a twentieth transistor T20, a tenth transistor T10, an eleventh transistor T11, and a twenty-first transistor T21; the fourth node control circuit includes a twelfth transistor T12; the fifth node control circuit includes a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a sixteenth transistor T16; the output circuit includes an eighth transistor T8; the output reset circuit includes a fourth transistor T4; and the driving circuit further includes a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0701] The gate of T1 is electrically connected to the first clock signal line CK, the first electrode of T1 is electrically connected to the low voltage line VGL, and the second electrode of T1 is electrically connected to the first node N1.

[0702] The gate of T2 is electrically connected to the second node N2, the first electrode of T2 is electrically connected to the second electrode of T1, and the second electrode of T2 is electrically connected to the first clock signal line CK.

[0703] The gate of T17 is electrically connected to the first clock signal line CK, the first electrode of T17 is electrically connected to the input terminal I1, and the second electrode of T17 is electrically connected to the second node N2.

[0704] The gate of T18 is electrically connected to the first clock signal line CK, the first electrode of T18 is electrically connected to the input terminal I1, and the second electrode of T18 is electrically connected to the seventh node N7.

[0705] The gate of T19 is electrically connected to the low voltage line VGL, the first electrode of T19 is electrically connected to the second node N2, and the second electrode of T19 is electrically connected to the third node N3.

[0706] The gate of T20 is electrically connected to the low voltage line VGL, the first electrode of T20 is electrically connected to the seventh node N7, and the second electrode of T20 is electrically connected to the eighth node N8.

[0707] The gate and the first electrode of T21 are both electrically connected to the eighth node N8, and the second electrode of T21 is electrically connected to the third node N3.

[0708] The gate of T10 is electrically connected to the first node N1, the first electrode of T10 is electrically connected to the high voltage line VGH, and the second electrode of T10 is electrically connected to the sixth node N6.

[0709] The gate of T11 is electrically connected to the eighth node N8, the first electrode of T11 is electrically connected to the sixth node N6, and the second electrode of T11 is electrically connected to the second clock signal line CB.

[0710] The gate of T12 is electrically connected to the low voltage line VGL, the first electrode of T12 is electrically connected to the first node N1, and the second electrode of T12 is electrically connected to the gate of T13.

[0711] The first electrode of T13 is electrically connected to the second clock signal line CB, and the second electrode of T13 is electrically connected to the first electrode of T14.

[0712] The gate of T14 is electrically connected to the second clock signal line CB, and the gate of T15 is electrically connected to the gate of T8.

[0713] The gate of T15 is electrically connected to the second node N2, the first electrode of T15 is electrically connected to the high voltage line VGH, and the second electrode of T15 is electrically connected to the fifth node N5.

[0714] The gate of T16 is electrically connected to the control voltage terminal VEL, the first electrode of T16 is electrically connected to the high voltage line VGH, and the second electrode of T16 is electrically connected to the second node N2.

[0715] The gate of T8 is electrically connected to the fifth node N5, the first electrode of T8 is electrically connected to the high voltage line VGH, and the second electrode of T8 is electrically connected to the drive output terminal OT.

[0716] The gate of T4 is electrically connected to the third node N3, the first electrode of T4 is electrically connected to the drive output terminal OT, and the second electrode of T4 is electrically connected to the low voltage line VGL.

[0717] The first plate of C1 is electrically connected to the fifth node N5, and the second plate of C1 is electrically connected to the high voltage line VGH.

[0718] The first electrode of C2 is electrically connected to the third node N3, and the second electrode of C2 is electrically connected to the sixth node N6.

[0719] The first electrode of C3 is electrically connected to the gate of T13, and the second electrode of C3 is electrically connected to the second electrode of T13.

[0720] In at least one embodiment of the driving circuit shown in Figure 83, all transistors are p-type transistors, but this is not a limitation.

[0721] Figure 84A is a layout diagram of at least one embodiment of the drive circuit shown in Figure 83.

[0722] Figure 84B is a layout diagram of Figure 84A with the second source / drain metal layer removed.

[0723] Figure 85 is a layout diagram of the semiconductor layer in Figure 84A, Figure 86 is a layout diagram of the first gate metal layer in Figure 84A, Figure 87 is a layout diagram of the second gate metal layer in Figure 84A, Figure 88 is a layout diagram of the third gate metal layer in Figure 84A, Figure 80 is a layout diagram of the first source / drain metal layer in Figure 84A, and Figure 90 is a layout diagram of the second source / drain metal layer in Figure 84A.

[0724] In at least one embodiment shown in Figures 84A-90, the signal line can be formed on the second source / drain metal layer. It can be directly electrically connected to the semiconductor layer and the second source / drain metal layer through a via that penetrates the gate insulating layer and the planarization layer through a masking layer, thus avoiding excessively deep vias.

[0725] In Figure 85, the active pattern labeled A1 is T1, the active pattern labeled A2 is T2, the active pattern labeled A17 is T17, the active pattern labeled A18 is T18, the active pattern labeled A12 is T12, the active pattern labeled A10 is T10, the active pattern labeled A11 is T11, and the active pattern labeled A19 is T19. The diagrams are labeled as follows: A20 is the active diagram of T20, A13 is the active diagram of T13, A14 is the active diagram of T14, A15 is the active diagram of T15, A16 is the active diagram of T16, A21 is the active diagram of T21, A8 is the active diagram of T8, and A9 is the active diagram of T9.

[0726] A1 and A2 are integrally formed, A10 and A11 are integrally formed, A15 and A16 are integrally formed, and A8 and A4 are integrally formed.

[0727] As shown in Figure 86, the first plate of C1 is labeled C1a, the first plate of C2 is labeled C2a, and the first plate of C3 is labeled C3a.

[0728] As shown in Figure 87, the plate labeled C1b is the second plate of C1, the plate labeled C2b is the second plate of C2, and the plate labeled C3b is the second plate of C3.

[0729] The orthographic projection of C1a onto the substrate at least partially overlaps with the orthographic projection of C1b onto the substrate, and the orthographic projection of C2a onto the substrate at least partially overlaps with the orthographic projection of C2b onto the substrate.

[0730] In Figure 88, the sixteenth conductive pattern is labeled DX16, the seventeenth conductive pattern is labeled DX17, the eighteenth conductive pattern is labeled DX18, the twenty-first conductive pattern is labeled DX21, and the twenty-fourth conductive pattern is labeled DX24.

[0731] In Figure 89, the 22nd conductive pattern is labeled DX22, and the 23rd conductive pattern is labeled DX23.

[0732] As shown in Figures 84A-90, T1, T2, T17 and T18 are arranged in sequence along the vertical direction, T12, T10 and T11 are arranged in sequence along the vertical direction, T19 and T20 are arranged in sequence along the vertical direction, T14, T15, T16 and T21 are arranged in sequence along the vertical direction, and T8 and T4 are arranged in sequence along the vertical direction to reduce the horizontal space occupied by the driving circuit and facilitate the realization of a narrow bezel.

[0733] As shown in Figures 84A-90, the orthographic projection of A1 on the base overlaps at least partially with the orthographic projection of CK on the base, the orthographic projection of A2 on the base overlaps at least partially with the orthographic projection of CK on the base, the orthographic projection of A17 on the base overlaps at least partially with the orthographic projection of CK on the base, and the orthographic projection of A18 on the base overlaps at least partially with the orthographic projection of CK on the base.

[0734] The orthographic projection of A12 on the substrate at least partially overlaps with the orthographic projection of VGL on the substrate; the orthographic projection of A10 on the substrate at least partially overlaps with the orthographic projection of VGL on the substrate; the orthographic projection of A11 on the substrate at least partially overlaps with the orthographic projection of VGL on the substrate; the orthographic projection of A19 on the substrate at least partially overlaps with the orthographic projection of VGL on the substrate; the orthographic projection of A20 on the substrate at least partially overlaps with the orthographic projection of VGL on the substrate.

[0735] The orthographic projection of A15 on the substrate at least partially overlaps with the orthographic projection of CB on the substrate; the orthographic projection of A16 on the substrate at least partially overlaps with the orthographic projection of CB on the substrate; the orthographic projection of A21 on the substrate at least partially overlaps with the orthographic projection of CB on the substrate.

[0736] The orthographic projection of A8 onto the substrate at least partially overlaps with the orthographic projection of VGH onto the substrate, and the orthographic projection of A4 onto the substrate at least partially overlaps with the orthographic projection of VGH onto the substrate.

[0737] This reduces the lateral space occupied by the drive circuit, making it easier to achieve a narrow bezel.

[0738] As shown in Figures 84A-90, the orthographic projection of the first plate C3a of C3 onto the substrate at least partially overlaps with the orthographic projection of CB onto the substrate; the orthographic projection of the second plate C3b of C3 onto the substrate at least partially overlaps with the orthographic projection of CB onto the substrate; the orthographic projection of the first plate C2a of C2 onto the substrate at least partially overlaps with the orthographic projection of CB onto the substrate; the orthographic projection of the second plate C2b of C2 onto the substrate at least partially overlaps with the orthographic projection of CB onto the substrate; the orthographic projection of the first plate C1a of C1 onto the substrate at least partially overlaps with the orthographic projection of VGH onto the substrate; the orthographic projection of the second plate C1b of C1 onto the substrate at least partially overlaps with the orthographic projection of VGH onto the substrate;

[0739] This reduces the lateral space occupied by the drive circuit, making it easier to achieve a narrow bezel.

[0740] In at least one embodiment shown in Figures 84A-90, the ratio between the area of ​​the circuit element region (including circuit elements T1, T2, T4, T8, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, T21, C1, C2, and C3) and the area of ​​the driving circuit region is 59.08%.

[0741] In at least one embodiment of this disclosure, the driving circuit includes a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, an output circuit, and an output reset circuit; the first node control circuit includes a first transistor and a second transistor; the third node control circuit includes a third transistor; the output reset circuit includes a fourth transistor; the second node control circuit includes a fifth transistor; the second node control circuit includes a sixth transistor and a seventh transistor; and the output circuit includes an eighth transistor.

[0742] The active pattern of the third transistor extends along the second direction; the first direction intersects the second direction;

[0743] The second and third transistors are arranged along the first direction; the sixth and seventh transistors are arranged along the first direction; the eighth and fourth transistors are arranged along the first direction.

[0744] At least one of the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line has an orthogonal projection on the substrate that at least partially overlaps with the orthogonal projection of the circuit element on the substrate.

[0745] The ratio between the area of ​​the orthographic projection of the circuit element on the substrate and the area of ​​the driving circuit region is greater than or equal to 73% and less than or equal to 77%; for example, the ratio can be 73%, 73.5%, 74%, 74.5%, 75%, 75.5%, 75.78%, 76%, 76.5%, or 77%.

[0746] In at least one embodiment of this disclosure, the driving circuit includes a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, an output circuit, and an output reset circuit; the first node control circuit includes a first transistor and a second transistor; the third node control circuit includes a third transistor; the output reset circuit includes a fourth transistor; the second node control circuit includes a fifth transistor; the second node control circuit includes a sixth transistor and a seventh transistor; the output circuit includes an eighth transistor; the active pattern of the third transistor extends along a second direction;

[0747] The gate of the first transistor and the gate of the fifth transistor are electrically connected through a third conductive pattern formed on the gate metal layer; the third conductive pattern is electrically connected to the active pattern of the second transistor through a via.

[0748] The sixth and seventh transistors are arranged along the first direction; the eighth and fourth transistors are arranged along the first direction;

[0749] The orthographic projection of at least one of the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line onto the substrate at least partially overlaps with the orthographic projection of the circuit element onto the substrate; the ratio between the area of ​​the orthographic projection of the circuit element onto the substrate and the area of ​​the driving circuit region is greater than or equal to 69% and less than or equal to 75%; for example, the ratio may be 69%, 69.5%, 70%, 70.5%, 71%, 71.5%, 72%, 72.5%, 72.91%, 73%, 73.5%, 74%, 74.5%, or 75%.

[0750] In at least one embodiment of this disclosure, the driving circuit includes a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, an output circuit, and an output reset circuit; the first node control circuit includes a first transistor and a second transistor; the third node control circuit includes a third transistor; the output reset circuit includes a fourth transistor; the second node control circuit includes a fifth transistor; the second node control circuit includes a sixth transistor and a seventh transistor; the output circuit includes an eighth transistor; the active pattern of the third transistor extends along a second direction;

[0751] The second and third transistors are arranged along the first direction; the fifth, sixth, and seventh transistors are arranged along the first square; the eighth and fourth transistors are arranged along the first direction.

[0752] The orthographic projection of at least one of the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line onto the substrate at least partially overlaps with the orthographic projection of the circuit element onto the substrate; the ratio between the area of ​​the orthographic projection of the circuit element onto the substrate and the area of ​​the driving circuit region is greater than or equal to 68% and less than or equal to 72%; for example, the ratio may be 68%, 68.5%, 69%, 69.5%, 70%, 70.5%, 70.66%, 71%, 71.5%, or 72%.

[0753] In at least one embodiment of this disclosure, the driving circuit includes a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, an output circuit, and an output reset circuit; the first node control circuit includes a first transistor and a second transistor; the third node control circuit includes a third transistor; the output reset circuit includes a fourth transistor; the second node control circuit includes a fifth transistor; the second node control circuit includes a sixth transistor and a seventh transistor; and the output circuit includes an eighth transistor.

[0754] The first transistor, the second transistor, and the fifth transistor are arranged along the first direction; the sixth transistor, the seventh transistor, and the third transistor are arranged along the first direction; and the eighth transistor and the fourth transistor are arranged along the first direction.

[0755] The orthographic projection of at least one of the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line onto the substrate at least partially overlaps with the orthographic projection of the circuit element onto the substrate; the ratio between the area of ​​the orthographic projection of the circuit element onto the substrate and the area of ​​the driving circuit region is greater than or equal to 74% and less than or equal to 80%; for example, the ratio may be 74%, 74.5%, 75%, 75.5%, 76%, 76.5%, 77%, 77.3%, 77.5%, 78%, 78.5%, 79%, 79.5%, or 80%.

[0756] In at least one embodiment of this disclosure, the driving circuit includes a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, an output circuit, and an output reset circuit; the first node control circuit includes a first transistor and a second transistor; the third node control circuit includes a third transistor; the output reset circuit includes a fourth transistor; the second node control circuit includes a fifth transistor; the second node control circuit includes a sixth transistor and a seventh transistor; and the output circuit includes an eighth transistor.

[0757] The sixth and seventh transistors are arranged along the first direction, and the eighth and fourth transistors are arranged along the first direction;

[0758] The orthographic projection of at least one of the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line onto the substrate at least partially overlaps with the orthographic projection of the circuit element onto the substrate; the ratio between the area of ​​the orthographic projection of the circuit element onto the substrate and the area of ​​the driving circuit region is greater than or equal to 65% and less than or equal to 70%; for example, the ratio may be 65%, 65.5%, 66%, 66.5%, 67%, 67.5%, 68%, 68.06%, 68.5%, 69%, 69.5%, or 70%.

[0759] In at least one embodiment of this disclosure, the driving circuit includes a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, an output circuit, and an output reset circuit; the first node control circuit includes a first transistor and a second transistor; the third node control circuit includes a third transistor; the output reset circuit includes a fourth transistor; the second node control circuit includes a fifth transistor; the second node control circuit includes a sixth transistor and a seventh transistor; the output circuit includes an eighth transistor; the driving circuit further includes a first capacitor and a second capacitor;

[0760] The first voltage line, the second voltage line, the first clock signal line, and the second clock signal line are formed in the first source-drain metal layer;

[0761] The sixth and seventh transistors are arranged along the first direction, the eighth and fourth transistors are arranged along the first direction; the fifth transistor and the third transistor are arranged along the first direction;

[0762] The orthographic projection of at least one of the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line onto the substrate at least partially overlaps with the orthographic projection of the circuit element onto the substrate; the ratio between the area of ​​the orthographic projection of the circuit element onto the substrate and the area of ​​the driving circuit region is greater than or equal to 52% and less than or equal to 57%; for example, the ratio may be 52%, 52.5%, 53%, 53.5%, 54%, 54.42%, 54.5%, 55%, 55.5%, 56%, 56.5%, or 57%.

[0763] In at least one embodiment of this disclosure, the driving circuit includes a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, an output circuit, and an output reset circuit; the first node control circuit includes a first transistor and a second transistor; the third node control circuit includes a third transistor; the output reset circuit includes a fourth transistor; the second node control circuit includes a fifth transistor; the second node control circuit includes a sixth transistor and a seventh transistor; the output circuit includes an eighth transistor; the driving circuit further includes a first capacitor and a second capacitor;

[0764] At least one of the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line has an orthogonal projection on the substrate that at least partially overlaps with the orthogonal projection of the circuit element on the substrate.

[0765] A first voltage line, a second voltage line, a first clock signal line, and a second clock signal line are formed on a first source-drain metal layer; a fifth transistor and a third transistor are arranged along a first direction, a sixth transistor and a seventh transistor are arranged along a first direction, and an eighth transistor and a fourth transistor are arranged along a first direction; or, a first voltage line, a second voltage line, a first clock signal line, and a second clock signal line are formed on a second source-drain metal layer; a fifth transistor and a third transistor are arranged along a first direction, a sixth transistor and a seventh transistor are arranged along a first direction, and an eighth transistor and a fourth transistor are arranged along a first direction.

[0766] The ratio between the area of ​​the orthographic projection of the circuit element on the substrate and the area of ​​the driving circuit region is greater than or equal to 61% and less than or equal to 67%; for example, the ratio can be 61%, 61.5%, 62%, 62.5%, 63%, 63.5%, 64%, 64.16%, 64.5%, 64.7%, 65%, 65.5%, 66%, 66.5%, or 67%.

[0767] In at least one embodiment of this disclosure, the driving circuit includes a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, an output circuit, and an output reset circuit; the first node control circuit includes a first transistor and a second transistor; the third node control circuit includes a third transistor; the output reset circuit includes a fourth transistor; the second node control circuit includes a fifth transistor; the second node control circuit includes a sixth transistor and a seventh transistor; the output circuit includes an eighth transistor; the driving circuit further includes a first capacitor and a second capacitor;

[0768] The first voltage line, the second voltage line, the first clock signal line, and the second clock signal line are formed on the second source-drain metal layer;

[0769] The second and third transistors are arranged along the first direction, the fifth, sixth and seventh transistors are arranged along the first direction, and the eighth and fourth transistors are arranged along the first direction;

[0770] The orthographic projection of at least one of the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line onto the substrate at least partially overlaps with the orthographic projection of the circuit element onto the substrate; the ratio between the area of ​​the orthographic projection of the circuit element onto the substrate and the area of ​​the driving circuit region is greater than or equal to 79% and less than or equal to 85%; for example, the ratio may be 79%, 79.5%, 80%, 80.5%, 81%, 81.5%, 82%, 82.5%, 82.73%, 83%, 83.5%, 84%, 84.5%, or 85%.

[0771] In at least one embodiment of this disclosure, the driving circuit includes a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, an output circuit, and an output reset circuit; the first node control circuit includes a first transistor and a second transistor; the third node control circuit includes a third transistor; the output reset circuit includes a fourth transistor; the second node control circuit includes a fifth transistor; the second node control circuit includes a sixth transistor and a seventh transistor; the output circuit includes an eighth transistor; the driving circuit further includes a first capacitor and a second capacitor;

[0772] At least one of the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line has an orthogonal projection on the substrate that at least partially overlaps with the orthogonal projection of the circuit element on the substrate.

[0773] The first voltage line, the second voltage line, the first clock signal line, and the second clock signal line are formed on the second source-drain metal layer;

[0774] The second and third transistors are arranged along the first direction, the fifth, sixth and seventh transistors are arranged along the first direction, and the eighth and fourth transistors are arranged along the first direction;

[0775] The ratio between the area of ​​the orthographic projection of the circuit element on the substrate and the area of ​​the driving circuit region is greater than or equal to 87% and less than or equal to 93%; for example, the ratio can be 87%, 87.5%, 88%, 88.5%, 89%, 89.5%, 90%, 90.5%, 91%, 91.27%, 91.5%, 92%, 92.5%, or 93%.

[0776] In at least one embodiment of this disclosure, the driving circuit includes a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, a fourth node control circuit, a fifth node control circuit, an output reset circuit, and an output circuit; the first node control circuit includes a first transistor and a second transistor, the second node control circuit includes a fifth transistor; the third node control circuit includes a ninth transistor, a tenth transistor, and an eleventh transistor; the fourth node control circuit includes a twelfth transistor, the fifth node control circuit includes a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor, the output circuit includes an eighth transistor, the output reset circuit includes a fourth transistor, and the driving circuit further includes a first capacitor, a second capacitor, and a third capacitor;

[0777] The first, second, and fifth transistors are arranged along a first direction; the twelfth, tenth, and eleventh transistors extend along a first direction; the third and second capacitors are arranged along a first direction; the fourteenth, fifteenth, and sixteenth transistors are arranged along a first direction; and the eighth and fourth transistors are arranged along a first direction. Alternatively, the first, second, and fifth transistors are arranged along a first direction; the twelfth, tenth, and eleventh transistors are arranged along a first direction; the third and second capacitors are arranged along a first direction; the fourteenth, thirteenth, fifteenth, and sixteenth transistors are arranged along a first direction; and the eighth and fourth transistors extend along a first direction. The first electrode of the second capacitor is arranged in one direction; the first electrode of the second capacitor includes layers that are electrically connected to each other and are disposed in different layers; the first electrode of the second capacitor and the second electrode of the second capacitor are arranged in the same direction; the first electrode of the third capacitor includes layers that are electrically connected to each other and are disposed in different layers; or, the first transistor, the second transistor, the seventeenth transistor and the eighteenth transistor are arranged in a vertical direction; the twelfth transistor, the tenth transistor and the eleventh transistor are arranged in a vertical direction; the nineteenth transistor and the twentieth transistor are arranged in a first direction; the fourteenth transistor, the fifteenth transistor, the sixteenth transistor and the twenty-first transistor are arranged in a first direction; the eighth transistor and the fourth transistor are arranged in a first direction.

[0778] The ratio between the area of ​​the orthographic projection of the circuit element onto the substrate and the area of ​​the driving circuit region is greater than 56% and less than or equal to 63%; for example, the ratio can be 56.1%, 56.5%, 57%, 57.5%, 58%, 58.5%, 59%, 59.08%, 59.16%, 59.5%, 60%, 60.5%, 60.69%, 61%, 61.5%, 62%, 62.5%, or 63%.

[0779] In at least one embodiment of this disclosure, when the display substrate includes an LTPS (Low Temperature Polycrystalline Silicon) driving circuit, a buffer layer, a semiconductor layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an interlayer dielectric layer, a first source / drain metal layer, a passivation layer, a first planarization layer, a second source / drain metal layer, a second planarization layer, an anode layer, and a pixel defining layer may be sequentially disposed along a direction away from the substrate.

[0780] In at least one embodiment of this disclosure, when the display substrate includes an LTPO (Low Temperature Polycrystalline Oxide) driving circuit, a shielding layer, a first buffer layer, a first semiconductor layer, a first gate insulating layer, a first gate metal layer, a first interlayer dielectric layer, a second gate metal layer, a second interlayer dielectric layer, a second buffer layer, a second semiconductor layer, a second gate insulating layer, a third gate metal layer, a third interlayer dielectric layer, a first source / drain metal layer, a first planarization layer, a second source / drain metal layer, a second planarization layer, an anode layer, and a pixel defining layer may be provided sequentially along the direction away from the substrate. The second semiconductor layer may be made of IGZO (Indium Gallium Zinc Oxide).

[0781] The display device described in this disclosure includes the display substrate described above.

[0782] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

A display substrate includes a substrate, pixel circuits, and a driving module. The substrate includes a display area and a peripheral area. The pixel circuits are disposed in the display area, and the driving module is disposed in the peripheral area. The driving module includes multi-level driving circuits, and the peripheral area includes multiple driving circuit areas. The driving circuit includes circuit elements, adapter lines, and signal lines; the circuit elements include at least one transistor and at least one capacitor; at least two electrodes of the circuit elements are electrically connected through the adapter lines. The ratio between the area of ​​the circuit element region where the circuit element is located and the area of ​​the driving circuit region is greater than 0.56 and less than 1. The display substrate of claim 1, wherein, The outline of the nth-level driving circuit's orthographic projection on the substrate that is furthest from the display area is the first outline, and the outline of the nth-level driving circuit's orthographic projection on the substrate that is closest to the display area is the second outline. The outline of the nth stage driving circuit's orthogonal projection onto the substrate that is closest to the (n-1)th stage driving circuit is the third outline. The contour line furthest from the (n-1)th stage driving circuit in the orthographic projection of the nth stage driving circuit onto the substrate is the fourth contour line; n is a positive integer. The area of ​​the quadrilateral formed by the extensions of the first contour line, the second contour line, the third contour line, and the fourth contour line is the area of ​​the nth-level driving circuit region. The nth-level driving circuit is located within the nth-level driving circuit region. The display substrate of claim 1, wherein, The signal line extends along a first direction; The driving circuit includes at least two transistors arranged along a first direction. The display substrate of claim 1, wherein, The active pattern of the first transistor in the driving circuit is electrically connected to the active pattern of the second transistor in the driving circuit through a via, and a first conductive pattern formed on the gate metal layer. The display substrate of claim 4, wherein, The signal line extends along a first direction; The driving circuit includes an active pattern of a third transistor that extends along a second direction, which intersects with the first direction. The active patterns of the first transistor and the third transistor are arranged along a first direction. The display substrate of claim 5, wherein The driving circuit includes a first node control circuit, a second node control circuit, and a third node control circuit; the first node control circuit is used to control the potential of the first node. The second node control circuit is used to control the potential of the second node; The third node control circuit is used to control the potential of the third node according to the potential of the second node; The first node control circuit includes the first transistor and the second transistor; the active patterns of the first transistor and the second transistor are both electrically connected to the first node. The third node control circuit includes the third transistor, and the active pattern of the third transistor is consistent with that of the third node. Electrical connection. The display substrate of claim 6, wherein, The driving circuit further includes an output reset circuit; the output reset circuit is electrically connected to the third node and the driving output terminal respectively, and is used to reset the driving signal provided by the driving output terminal under the control of the potential of the third node. The output reset circuit includes a fourth transistor; The active pattern of the third transistor is electrically connected to the gate of the fourth transistor through a via and a second conductive pattern formed on the gate metal layer. The display substrate of claim 6, wherein, The second node control circuit includes a fifth transistor; The gate of the first transistor and the gate of the fifth transistor are electrically connected through a third conductive pattern formed on the gate metal layer; The third conductive pattern is electrically connected to the active pattern of the second transistor through a via. The display substrate of claim 6, wherein, The second node control circuit includes a fifth transistor; The signal line includes a first clock signal line; the second transistor is electrically connected to the first clock signal line. The orthographic projection of the active pattern of the second transistor onto the substrate at least partially overlaps with the orthographic projection of the first clock signal line onto the substrate; The orthographic projection of the active pattern of the third transistor onto the substrate at least partially overlaps with the orthographic projection of the first clock signal line onto the substrate. The display substrate of claim 8, wherein, The signal line extends along a first direction; the first direction intersects with a second direction; The gate of the first transistor and the gate of the fifth transistor both extend along the second direction; The gates of the first transistor and the fifth transistor are arranged along a second direction. The display substrate of claim 5, wherein, The gate of the second transistor is disposed on the side of the gate of the fifth transistor away from the gate of the third transistor. The display substrate of claim 8, wherein, The signal line extends along a first direction; the second node control circuit further includes at least one transistor; The second node control circuit includes at least a portion of transistors whose active patterns are arranged along a first direction. The display substrate of claim 12, wherein, The signal line includes a second clock signal line; The active pattern of at least some of the transistors in the second node control circuit is projected onto the substrate in a positive projection that at least partially overlaps with the positive projection of the second clock signal line onto the substrate. The display substrate according to any one of claims 1 to 13, wherein The capacitor includes a first plate and a second plate; the first plate of the capacitor includes a first plate portion and a second plate portion. The first electrode portion, the second electrode portion, and the second electrode portion are arranged sequentially along a direction away from the substrate; The orthographic projections of the first electrode portion onto the substrate, the orthographic projections of the second electrode portion onto the substrate, and the orthographic projections of the second electrode portion onto the substrate at least partially overlap. The display substrate according to any one of claims 1 to 13, wherein The signal line extends along a first direction; the signal line includes a first voltage line. The driving circuit includes an output circuit and an output reset circuit; the output circuit is electrically connected to the first node, the driving output terminal, and the first voltage line respectively, and is used to control the connection between the driving output terminal and the first voltage line under the control of the potential of the first node; the output reset circuit is electrically connected to the third node and the driving output terminal respectively, and is used to reset the driving signal provided by the driving output terminal under the control of the potential of the third node. The transistors included in the output circuit and the transistors included in the output reset circuit are arranged along a first direction. The display substrate of claim 15, wherein, The driving circuit includes a first node control circuit, a second node control circuit, and a third node control circuit. The first node control circuit is electrically connected to the first clock signal line; The transistors included in the first node control circuit and the transistors included in the second node control circuit that are electrically connected to the first clock signal line are arranged along a first direction. The display substrate of claim 15, wherein, The driving circuit includes a first node control circuit, a second node control circuit, and a third node control circuit. The transistors included in the second node control circuit are arranged along a first direction with the transistors included in the third node control circuit. The display substrate of claim 15, wherein, The orthographic projection of the active pattern of the transistors included in the output circuit onto the substrate at least partially overlaps with the orthographic projection of the first voltage line onto the substrate. The display substrate of claim 1, wherein, The gate of the transistor is formed on a first gate metal layer; the connecting line is formed on a first source-drain metal layer; and the signal line is formed on a second source-drain metal layer. The display substrate of claim 1, wherein, The gate of the transistor is formed on the first gate metal layer; the adapter line is formed on the second gate metal layer; The conductive pattern formed on the first gate metal layer can be electrically connected to the conductive pattern formed on the second gate metal layer through a via. The display substrate of claim 20, wherein, The signal line is formed in a first source / drain metal layer or a second source / drain metal layer; At least a portion of the orthographic projection of the signal line onto the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the driving circuit onto the substrate. The display substrate of claim 1, wherein, The gate of the transistor is formed on the first gate metal layer; the transition line is formed on the second gate metal layer or the first source / drain metal layer; The conductive pattern formed on the first gate metal layer can be electrically connected to the conductive pattern formed on the second gate metal layer through a via; The signal line is formed in the second source / drain metal layer. The display substrate according to any one of claims 1-13, 19-22, wherein, The orthographic projection of at least one capacitor included in the driving circuit onto the substrate and the orthographic projection of at least one transistor included in the driving circuit onto the substrate. The orthographic projections of the two objects at least partially overlap. The display substrate as claimed in claim 1, wherein, The signal line is formed on the second source-drain metal layer; the active pattern of the transistor is formed on the semiconductor layer; the active pattern can be directly electrically connected to the conductive pattern formed on the second source-drain metal layer through vias. The display substrate of claim 24, wherein, The driving circuit includes a first node control circuit, a second node control circuit, a third node control circuit, a fourth node control circuit, and a fifth node control circuit. The first node control circuit is electrically connected to the first node and the first clock signal line respectively, and is used to control the potential of the first node according to the first clock signal provided by the first clock signal line; The second node control circuit is electrically connected to the first clock signal line and the second node respectively, and is used to control the potential of the second node under the control of the first clock signal; The third node control circuit is electrically connected to the first node, the second node, the third node, the sixth node, and the second clock signal line, respectively. It is used to control the potential of the third node according to the potential of the second node, control the potential of the fourth node under the control of the potential of the first node, control the connection or disconnection between the sixth node and the second clock signal line under the control of the potential of the third node, and control the potential of the third node according to the potential of the sixth node. The fourth node control circuit is electrically connected to both the first node and the fourth node, and is used to control the potential of the fourth node according to the potential of the first node. The fifth node control circuit is electrically connected to the second clock signal line, the fourth node, the fifth node, the second node, and the first voltage line, respectively. It is used to control the potential of the fifth node according to the potential of the fourth node and the second clock signal provided by the second clock signal line, and to control the potential of the fifth node according to the first voltage signal provided by the first voltage line under the control of the second clock signal and the potential of the second node. The transistors included in the first node control circuit are arranged along a first direction; The transistors included in the first node control circuit and the transistors included in the second node are arranged along a first direction; The transistors included in the third node control circuit are arranged along a first direction; The transistors included in the fourth node control circuit are arranged along the first direction with the transistors included in the third node control circuit. The transistors in the fifth node control circuit are arranged along a first direction. The display substrate of claim 25, wherein, The fifth node control circuit includes an active pattern of at least two transistors electrically connected to the second clock signal line integrally formed; and / or, the fifth node control circuit includes an active pattern of a transistor electrically connected to the first voltage line integrally formed. The display substrate of claim 24, wherein, The driving circuit includes a first node control circuit, a second node control circuit, a third node control circuit, a fourth node control circuit, and a fifth node control circuit. The first node control circuit is electrically connected to the first node and the first clock signal line respectively, and is used to control the potential of the first node according to the first clock signal provided by the first clock signal line; The second node control circuit is electrically connected to the first clock signal line, the second node, and the seventh node, respectively. Used to control the potential of the second node and the potential of the seventh node under the control of the first clock signal; The third node control circuit is electrically connected to the first node, the first voltage line, the second clock signal line, the sixth node, the seventh node, the eighth node, and the third node, respectively. It is used to control the potential of the third node according to the potential of the first node, control the potential of the eighth node according to the potential of the seventh node, control the potential of the third node according to the potential of the eighth node, control the potential of the sixth node under the control of the potential of the first node and the eighth node, control the potential of the eighth node according to the potential of the sixth node, and control the potential of the third node according to the potential of the eighth node. The fourth node control circuit is electrically connected to the first node and the fourth node respectively, and is used to control the potential of the fourth node according to the potential of the first node; The fifth node control circuit is electrically connected to the second clock signal line, the fourth node, the fifth node, the control voltage terminal, and the first node, respectively. It is used to control the potential of the fifth node under the control of the potential of the fourth node, according to the second clock signal provided by the second clock signal line, to control the potential of the second node under the control of the control voltage provided by the control voltage terminal, and to control the potential of the fifth node under the control of the potential of the first node. The transistors included in the first node control circuit are arranged along a first direction, and the transistors included in the second node control circuit are arranged along a first direction. The transistors included in the first node control circuit and the transistors included in the second node control circuit are arranged along a first direction. The transistors included in the third node control circuit are arranged along a first direction, and the transistors included in the fourth node control circuit and the transistors included in the third node control circuit are arranged along the first direction. The transistors in the fifth node control circuit are arranged along a first direction. The display substrate according to any one of claims 25 to 27, wherein The driving circuit also includes an output circuit and an output reset circuit; The output circuit is electrically connected to the fifth node and the drive output terminal respectively, and is used to control the drive output terminal to provide a drive signal under the control of the potential of the fifth node; The output reset circuit is electrically connected to the third node and the drive output terminal respectively, and is used to reset the drive signal under the control of the potential of the third node; The transistors included in the output circuit and the transistors included in the output reset circuit are arranged along a first direction. The display substrate of claim 1, wherein, The driving circuit includes a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, an output circuit, and an output reset circuit; the first node control circuit includes a first transistor and a second transistor; the third node control circuit includes a third transistor; the output reset circuit includes a fourth transistor; the second node control circuit includes a fifth transistor; the second node control circuit includes a sixth transistor and a seventh transistor; and the output circuit includes an eighth transistor. The active pattern of the third transistor extends along the second direction; the first direction intersects the second direction; The second and third transistors are arranged along the first direction; the sixth and seventh transistors are arranged along the first direction; the eighth and fourth transistors are arranged along the first direction. At least one of the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line has an orthogonal projection on the substrate that at least partially overlaps with the orthogonal projection of the circuit element on the substrate. The ratio between the area of ​​the circuit element region and the area of ​​the drive circuit region is greater than or equal to 73% and less than or equal to 77%. The display substrate of claim 1, wherein, The driving circuit includes a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, an output circuit, and an output reset circuit; the first node control circuit includes a first transistor and a second transistor; the third node control circuit includes a third transistor; the output reset circuit includes a fourth transistor; the second node control circuit includes a fifth transistor; the second node control circuit includes a sixth transistor and a seventh transistor; the output circuit includes an eighth transistor; the active pattern of the third transistor extends along a second direction; The gate of the first transistor and the gate of the fifth transistor are electrically connected through a third conductive pattern formed on the gate metal layer; the third conductive pattern is electrically connected to the active pattern of the second transistor through a via. The sixth and seventh transistors are arranged along the first direction; the eighth and fourth transistors are arranged along the first direction; At least one of the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line has an orthogonal projection on the substrate that at least partially overlaps with the orthogonal projection of the circuit element on the substrate. The ratio between the area of ​​the circuit element region and the area of ​​the drive circuit region is greater than or equal to 69% and less than or equal to 75%. The display substrate of claim 1, wherein, The driving circuit includes a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, an output circuit, and an output reset circuit; the first node control circuit includes a first transistor and a second transistor; the third node control circuit includes a third transistor; the output reset circuit includes a fourth transistor; the second node control circuit includes a fifth transistor; the second node control circuit includes a sixth transistor and a seventh transistor; the output circuit includes an eighth transistor; the active pattern of the third transistor extends along a second direction; The second and third transistors are arranged along the first direction; the fifth, sixth, and seventh transistors are arranged along the first square; the eighth and fourth transistors are arranged along the first direction. At least one of the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line has an orthogonal projection on the substrate that at least partially overlaps with the orthogonal projection of the circuit element on the substrate. The ratio between the area of ​​the circuit element region and the area of ​​the drive circuit region is greater than or equal to 68% and less than or equal to 72%. The display substrate of claim 1, wherein, The driving circuit includes a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, an output circuit, and an output reset circuit; the first node control circuit includes a first transistor and a second transistor; the third node control circuit includes a third transistor; the output reset circuit includes a fourth transistor; the second node control circuit includes a fifth transistor; the second node control circuit includes a sixth transistor and a seventh transistor; and the output circuit includes an eighth transistor. The first transistor, the second transistor, and the fifth transistor are arranged along the first direction; the sixth transistor, the seventh transistor, and the third transistor are arranged along the first direction; and the eighth transistor and the fourth transistor are arranged along the first direction. At least one of the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line has an orthogonal projection on the substrate that at least partially overlaps with the orthogonal projection of the circuit element on the substrate. The ratio between the area of ​​the circuit element region and the area of ​​the drive circuit region is greater than or equal to 74% and less than or equal to 80%. The display substrate of claim 1, wherein, The driving circuit includes a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, an output circuit, and an output reset circuit; the first node control circuit includes a first transistor and a second transistor; the third node control circuit includes a third transistor; the output reset circuit includes a fourth transistor; the second node control circuit includes a fifth transistor; the second node control circuit includes a sixth transistor and a seventh transistor; and the output circuit includes an eighth transistor. The sixth and seventh transistors are arranged along the first direction, and the eighth and fourth transistors are arranged along the first direction; At least one of the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line has an orthogonal projection on the substrate that at least partially overlaps with the orthogonal projection of the circuit element on the substrate. The ratio between the area of ​​the circuit element region and the area of ​​the drive circuit region is greater than or equal to 65% and less than or equal to 70%. The display substrate of claim 1, wherein, The driving circuit includes a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, an output circuit, and an output reset circuit. The first node control circuit includes a first transistor and a second transistor. The third node control circuit includes a third transistor. The output reset circuit includes a fourth transistor. The second node control circuit includes a fifth transistor. The second node control circuit includes a sixth transistor and a seventh transistor. The output circuit includes an eighth transistor. The driving circuit also includes a first capacitor and a second capacitor. At least one of the first voltage line, the second voltage line, the first clock signal line, and the second clock signal line has an orthogonal projection on the substrate that at least partially overlaps with the orthogonal projection of the circuit element on the substrate. The first voltage line, the second voltage line, the first clock signal line, and the second clock signal line are formed in the first source-drain metal layer; The fifth transistor and the third transistor are arranged along the first direction, the sixth transistor and the seventh transistor are arranged along the first direction, and the eighth transistor and the fourth transistor are arranged along the first direction; or, the first voltage line, the second voltage line, the first clock signal line and the second clock signal line are formed on the second source-drain metal layer; the fifth transistor and the third transistor are arranged along the first direction, the sixth transistor and the seventh transistor are arranged along the first direction, and the eighth transistor and the fourth transistor are arranged along the first direction. The ratio between the area of the circuit element region and the area of the driving circuit region is greater than or equal to 61% and less than or equal to 67%. The display substrate of claim 1, wherein, The driving circuit comprises a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, an output circuit and an output reset circuit; the first node control circuit comprises a first transistor and a second transistor; the third node control circuit comprises a third transistor, and the output reset circuit comprises a fourth transistor; the second node control circuit comprises a fifth transistor; the second node control circuit comprises a sixth transistor and a seventh transistor; the output circuit comprises an eighth transistor; and the driving circuit further comprises a first capacitor and a second capacitor. The first voltage line, the second voltage line, the first clock signal line and the second clock signal line are formed in the second source-drain metal layer. The second transistor and the third transistor are arranged along a first direction, the fifth transistor, the sixth transistor and the seventh transistor are arranged along the first direction, and the eighth transistor and the fourth transistor are arranged along the first direction. At least one of the first voltage line, the second voltage line, the first clock signal line and the second clock signal line has a normal projection on the substrate which at least partially overlaps with the normal projection of the circuit element on the substrate. The ratio between the area of the circuit element region and the area of the driving circuit region is greater than or equal to 79% and less than or equal to 85%. The driving circuit comprises a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, an output circuit and an output reset circuit; the first node control circuit comprises a first transistor and a second transistor; the third node control circuit comprises a third transistor, and the output reset circuit comprises a fourth transistor; the second node control circuit comprises a fifth transistor; the second node control circuit comprises a sixth transistor and a seventh transistor; the output circuit comprises an eighth transistor; and the driving circuit further comprises a first capacitor and a second capacitor. The display substrate of claim 1, wherein, The first voltage line, the second voltage line, the first clock signal line and the second clock signal line are formed in the second source-drain metal layer. The second transistor and the third transistor are arranged along a first direction, the fifth transistor, the sixth transistor and the seventh transistor are arranged along the first direction, and the eighth transistor and the fourth transistor are arranged along the first direction. At least one of the first voltage line, the second voltage line, the first clock signal line and the second clock signal line has a normal projection on the substrate which at least partially overlaps with the normal projection of the circuit element on the substrate. The ratio between the area of the circuit element region and the area of the driving circuit region is greater than or equal to 87% and less than or equal to 93%. ​ The display substrate of claim 1, wherein, The driving circuit comprises a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, a first node control circuit, a second node control circuit, a third node control circuit, a fourth node control circuit, a fifth node control circuit, an output reset circuit and an output circuit; the first node control circuit comprises a first transistor and a second transistor, the second node control circuit comprises a fifth transistor; the third node control circuit comprises a ninth transistor, a tenth transistor and an eleventh transistor; the fourth node control circuit comprises a twelfth transistor, the fifth node control circuit comprises a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a sixteenth transistor, the output circuit comprises an eighth transistor, the output reset circuit comprises a fourth transistor, and the driving circuit further comprises a first capacitor, a second capacitor and a third capacitor; At least one of the first voltage line, the second voltage line, the first clock signal line and the second clock signal line has a projection on the substrate that at least partially overlaps with the projection of the circuit element on the substrate; The first transistor, the second transistor and the fifth transistor are arranged along a first direction, the twelfth transistor, the tenth transistor and the eleventh transistor extend along the first direction, the third capacitor and the second capacitor are arranged along the first direction, the fourteenth transistor, the fifteenth transistor and the sixteenth transistor are arranged along the first direction, and the eighth transistor and the fourth transistor are arranged along the first direction; Alternatively, the first transistor, the second transistor and the fifth transistor are arranged along a first direction, the twelfth transistor, the tenth transistor and the eleventh transistor are arranged along the first direction, the third capacitor and the second capacitor are arranged along the first direction, the fourteenth transistor, the thirteenth transistor, the fifteenth transistor and the sixteenth transistor are arranged along the first direction, and the eighth transistor and the fourth transistor are arranged along the first direction; the first plate of the second capacitor comprises a first plate part of the second capacitor and a second plate part of the second capacitor which are arranged in different layers and are electrically connected to each other, and the first plate of the third capacitor comprises a first plate part of the second capacitor and a second plate part of the second capacitor which are arranged in different layers and are electrically connected to each other; or the first transistor, the second transistor, a seventeenth transistor and an eighteenth transistor are arranged along a vertical direction; the twelfth transistor, the tenth transistor and the eleventh transistor are arranged along the vertical direction, a nineteenth transistor and a twentieth transistor are arranged along a first direction, the fourteenth transistor, the fifteenth transistor, the sixteenth transistor and a twenty-first transistor are arranged along the first direction, and the eighth transistor and the fourth transistor are arranged along the first direction; The ratio between the area of the circuit element region and the area of the driving circuit region is greater than 56% and less than or equal to 63%. A display device comprises a display substrate as claimed in any one of claims 1 to 37.

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