Display substrate and display device

Abstract

A display substrate and a display device, wherein the display substrate comprises a display area (AA) and a non-display area surrounding at least one side of the display area (AA), the non-display area is provided with a gate drive circuit, the gate drive circuit (GOA) comprises a plurality of cascaded shift registers, at least two stages of shift registers in the plurality of cascaded shift registers are at least partially symmetrically arranged with respect to a straight line extending along a first direction (D1), a second direction is the arrangement direction of the at least two stages of shift registers in the plurality of cascaded shift registers, and the display substrate further comprises two fourth power supply lines, a first fourth power supply line (VL4-1) is located between the orthographic projection of at least one transistor in at least one stage of shift registers on a base and the orthographic projection of at least one transistor in at least one stage of shift registers on the base, and the orthographic projection of a second fourth power supply line (VL4-2) on the base is located on a side close to the display area of the orthographic projection of a plurality of transistors in at least one stage of shift registers on the base.

Description

Display substrate and display device Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and specifically to a display substrate and a display device. Background Technology

[0002] Liquid crystal displays (LCDs) have seen rapid development due to their small size, low power consumption, and lack of radiation. An LCD panel consists of a thin-film transistor array (TFT) substrate (cells) and a color filter (CF) substrate. Liquid crystal (LC) molecules are disposed between the TFT and CF substrates. By controlling the common electrode and pixel electrode, an electric field is formed to drive the liquid crystal deflection, achieving grayscale display.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, this disclosure provides a display substrate, comprising: a substrate having a display area and a non-display area surrounding at least one side of the display area, the non-display area comprising: a transistor device area having a gate driving circuit disposed thereon, the gate driving circuit comprising: a plurality of cascaded shift registers, at least one shift register comprising: a plurality of transistors and a fourth power supply terminal;

[0006] At least two of the multiple cascaded shift registers are arranged at least partially symmetrically with respect to a straight line extending along a first direction, and the second direction is the arrangement direction of at least two of the multiple cascaded shift registers. The first direction and the second direction are located in the same plane and intersect.

[0007] The display substrate further includes: two fourth power lines located in the transistor device area, the fourth power lines extending at least partially along the second direction; the fourth power lines are electrically connected to the fourth power terminal of at least one level shift register;

[0008] The first fourth power line and its orthographic projection on the substrate are located between the orthographic projections of at least two transistors in at least one level shift register on the substrate, and the second fourth power line and its orthographic projection on the substrate are located on the side of the orthographic projections of multiple transistors in at least one level shift register closer to the display area.

[0009] In an exemplary embodiment, it further includes: a first power connection line and a second power connection line located in the non-display area, wherein at least one of the first power connection line and the second power connection line extends at least partially along a first direction;

[0010] The first power connection line is electrically connected to the first end of the first fourth power line and the first end of the second fourth power line, respectively.

[0011] The second power connection line is electrically connected to the second end of the first fourth power line and the second end of the second fourth power line, respectively.

[0012] In an exemplary embodiment, the at least one shift register includes: a sixth transistor, a fifteenth transistor, an eighteenth transistor, a second reset signal terminal, a drive signal output terminal, a first pull-down node, and a second pull-down node, wherein the control electrode of the sixth transistor is electrically connected to the second reset signal terminal, the first electrode of the sixth transistor is electrically connected to the drive signal output terminal, the second electrode of the sixth transistor is electrically connected to the fourth power supply terminal, the control electrode of the fifteenth transistor is electrically connected to the first pull-down node, the first electrode of the fifteenth transistor is electrically connected to the drive signal output terminal, the second electrode of the fifteenth transistor is electrically connected to the fourth power supply terminal, the control electrode of the eighteenth transistor is electrically connected to the second pull-down node, the first electrode of the eighteenth transistor is electrically connected to the drive signal output terminal, and the second electrode of the eighteenth transistor is electrically connected to the fourth power supply terminal;

[0013] The orthographic projection of the sixth transistor on the substrate is located between the orthographic projection of the second fourth power line on the substrate and the orthographic projection of the first fourth power line on the substrate, and the distance between the orthographic projection of the sixth transistor on the substrate and the orthographic projection of the second fourth power line on the substrate is less than the distance between the orthographic projection of the sixth transistor on the substrate and the orthographic projection of the first fourth power line on the substrate.

[0014] The orthographic projection of at least one of the fifteenth and eighteenth transistors on the substrate is located on the side of the first fourth power line away from the display area, and the distance between the orthographic projection of at least one of the fifteenth and eighteenth transistors on the substrate and the orthographic projection of the first fourth power line on the substrate is less than the distance between the orthographic projection of the sixth transistor on the substrate and the orthographic projection of the first fourth power line on the substrate.

[0015] In an exemplary embodiment, the display area is further provided with a plurality of sub-pixels, at least one of the plurality of sub-pixels including: a first electrode and a second electrode, wherein the first electrode and the second electrode are transparent electrodes, and at least one of the plurality of transistors including: a control electrode, an active pattern, a first electrode and a second electrode;

[0016] The display substrate further includes: a circuit structure layer disposed on the substrate; the circuit structure layer includes: a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially stacked on the substrate;

[0017] The first conductive layer includes: a fourth power line and a control electrode of at least one transistor among a plurality of transistors located in at least one level shift register;

[0018] The semiconductor layer includes: an active pattern of at least one transistor among a plurality of transistors located in at least one level shift register;

[0019] The second conductive layer includes: a first terminal and a second terminal of at least one of a plurality of transistors located in at least one level shift register;

[0020] The third conductive layer includes: one of the first electrode and the second electrode located in at least one sub-pixel;

[0021] The fourth conductive layer includes another electrode located in the first electrode and the second electrode of at least one sub-pixel.

[0022] In an exemplary embodiment, it further includes: a first power connection line and a second power connection line located in the non-display area;

[0023] At least one of the first power connection line and the second power connection line is located in the first conductive layer.

[0024] In an exemplary embodiment, at least one of the plurality of cascaded shift registers includes: a capacitor, a pull-up node, and a drive signal output terminal, wherein the first terminal of the capacitor is electrically connected to the pull-up node, and the second terminal of the capacitor is electrically connected to the drive signal output terminal.

[0025] At least one of the multiple cascaded shift registers includes: a first plate, a second plate, and a third plate, wherein at least two of the first plate, the second plate, and the third plate are disposed in different layers, and the orthographic projections of the first plate, the second plate, and the third plate onto the substrate at least partially overlap.

[0026] The first electrode plate is electrically connected to the third electrode plate and serves as the first electrode of the capacitor, while the second electrode plate serves as the second electrode of the capacitor.

[0027] In an exemplary embodiment, at least one of the plurality of cascaded shift registers further includes: a first connection portion and a second connection portion, wherein the first electrode plate and the third electrode plate are connected through the first connection portion, and the second electrode plate is connected to the second connection portion;

[0028] The first electrode plate is located in the first conductive layer, the second electrode plate and the first connecting portion are located in the second conductive layer, and the third electrode plate and the second connecting portion are disposed in the same layer and are located in the third conductive layer or the fourth conductive layer.

[0029] In an exemplary embodiment, at least one of the plurality of cascaded shift registers includes: a capacitor, a pull-up node, and a drive signal output terminal, wherein the first terminal of the capacitor is electrically connected to the pull-up node, and the second terminal of the capacitor is electrically connected to the drive signal output terminal.

[0030] At least one of the multiple cascaded shift registers includes: a first plate, a second plate, a third plate, and a fourth plate, wherein at least two of the first plate, the second plate, the third plate, and the fourth plate are arranged in different layers, and the orthographic projections of at least two of the first plate, the second plate, the third plate, and the fourth plate on the substrate at least partially overlap.

[0031] The first electrode plate is electrically connected to the fourth electrode plate and serves as the first electrode of the capacitor. The second electrode plate is electrically connected to the third electrode plate and serves as the second electrode of the capacitor.

[0032] In an exemplary embodiment, at least one of the plurality of cascaded shift registers further includes: a first connection portion and a second connection portion, wherein the first electrode plate and the fourth electrode plate are connected through the first connection portion, and the second electrode plate and the third electrode plate are connected through the second connection portion;

[0033] The first electrode plate is located in the first conductive layer, the second electrode plate and the first connecting portion are located in the second conductive layer, the third electrode plate is located in the third conductive layer, and the fourth electrode plate and the second connecting portion are located in the fourth conductive layer.

[0034] In an exemplary embodiment, at least one of the plurality of cascaded shift registers includes: a capacitor, a pull-up node, and a drive signal output terminal, wherein the first terminal of the capacitor is electrically connected to the pull-up node, and the second terminal of the capacitor is electrically connected to the drive signal output terminal.

[0035] At least one of the multiple cascaded shift registers includes: a first plate, a second plate, a third plate, a fourth plate, and a fifth plate, wherein at least two of the first plate, the second plate, the third plate, the fourth plate, and the fifth plate are arranged in different layers, and the orthographic projections of at least two of the first plate, the second plate, the third plate, the fourth plate, and the fifth plate onto the substrate at least partially overlap;

[0036] The first electrode plate is electrically connected to the third electrode plate and the fifth electrode plate respectively, and serves as the first electrode of the capacitor. The second electrode plate is electrically connected to the fourth electrode plate, and serves as the second electrode of the capacitor.

[0037] In an exemplary embodiment, the circuit structure layer further includes a fifth conductive layer, which is located between the semiconductor layer and the third conductive layer;

[0038] The first electrode plate is located in the first conductive layer, the second electrode plate is located in the second conductive layer, the third electrode plate is located in the fifth conductive layer, the fourth electrode plate is located in the third conductive layer, and the fifth electrode plate is located in the fourth conductive layer.

[0039] In an exemplary embodiment, it further includes: a plurality of third power lines located in the transistor device region, at least one of the plurality of third power lines extending at least partially along a first direction; the third power line is located in the second conductive layer;

[0040] The at least one shift register further includes: a fourth transistor, a fifth transistor, an eighth transistor, a ninth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a sixteenth transistor, a seventeenth transistor, and a third power supply terminal, wherein the second terminals of the fourth transistor, the fifth transistor, the eighth transistor, the ninth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the sixteenth transistor, and the seventeenth transistor are respectively electrically connected to the third power supply terminal;

[0041] At least one third power supply line is electrically connected to the third power supply terminal in at least one shift register.

[0042] In an exemplary embodiment, the plurality of cascaded shift registers include: a first shift register, a second shift register, and a third shift register, wherein the first shift register is at least one of the plurality of cascaded shift registers, the second shift register is a shift register of one adjacent level of the first shift register, and the third shift register is a shift register of another adjacent level of the first shift register.

[0043] At least one third power line is located between the first shift register and the second shift register, and is electrically connected to the third power supply terminal of the first shift register and the third power supply terminal of the second shift register. The center line of the at least one third power line extending in the first direction is the same as the center line of the first shift register and the second shift register extending in the first direction.

[0044] At least one third power line is integrally structured with the second terminals of the fourth, fifth, eighth, ninth, eleventh, twelfth, thirteenth, fourteenth, sixteenth, and seventeenth transistors in at least one of the first and second shift registers.

[0045] In an exemplary embodiment, the at least one shift register further includes: a fifteenth transistor and an eighteenth transistor; the control electrode of the fourth transistor is electrically connected to the blanking reset signal terminal; the first electrode of the fourth transistor is electrically connected to the pull-up node; and the second electrode of the fourth transistor is electrically connected to the third power supply terminal; the control electrode of the fifth transistor is electrically connected to the first reset signal terminal; the first electrode of the fifth transistor is electrically connected to the pull-up node; and the second electrode of the fifth transistor is electrically connected to the third power supply terminal; the control electrode of the eighth transistor is electrically connected to the signal input terminal; the first electrode of the eighth transistor is electrically connected to the first pull-down node; and the second electrode of the eighth transistor is electrically connected to the third power supply terminal; the control electrode of the ninth transistor is electrically connected to the pull-up node; the first electrode of the ninth transistor is electrically connected to the first pull-down node; and the second electrode of the ninth transistor is electrically connected to the third power supply terminal; the control electrode of the eleventh transistor is electrically connected to the signal input terminal; the first electrode of the eleventh transistor is electrically connected to the second pull-down node; and the second electrode of the eleventh transistor is electrically connected to the third power supply terminal; the control electrode of the twelfth transistor is electrically connected to the pull-up node; the first electrode of the twelfth transistor is electrically connected to the second pull-down node; and the second electrode of the twelfth transistor is electrically connected to the third power supply terminal; and the control electrode of the twelfth transistor is electrically connected to the pull-up node; and ... The third power supply terminal is electrically connected; the control electrode of the thirteenth transistor is electrically connected to the first pull-down node; the first electrode of the thirteenth transistor is electrically connected to the pull-up node; the second electrode of the thirteenth transistor is electrically connected to the third power supply terminal; the control electrode of the fourteenth transistor is electrically connected to the first pull-down node; the first electrode of the fourteenth transistor is electrically connected to the cascade signal output terminal; the second electrode of the fourteenth transistor is electrically connected to the third power supply terminal; the control electrode of the fifteenth transistor is electrically connected to the second pull-down node; the first electrode of the fifteenth transistor is electrically connected to the drive signal output terminal; the second electrode of the fifteenth transistor is electrically connected to the fourth power supply terminal; the control electrode of the sixteenth transistor is electrically connected to the second pull-down node; the first electrode of the sixteenth transistor is electrically connected to the pull-up node; the second electrode of the sixteenth transistor is electrically connected to the third power supply terminal; the control electrode of the seventeenth transistor is electrically connected to the second pull-down node; the first electrode of the seventeenth transistor is electrically connected to the cascade signal output terminal; the second electrode of the seventeenth transistor is electrically connected to the third power supply terminal; the control electrode of the eighteenth transistor is electrically connected to the second pull-down node; the first electrode of the eighteenth transistor is electrically connected to the drive signal output terminal; the second electrode of the eighteenth transistor is electrically connected to the third power supply terminal.

[0046] The fourth transistor, the ninth transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the fifteenth transistor, and the eighth transistor are arranged sequentially along the first direction;

[0047] The eighth and eleventh transistors are arranged along the second direction, the thirteenth and sixteenth transistors are arranged along the second direction, the fourteenth and seventeenth transistors are arranged along the second direction, and the fifteenth and eighteenth transistors are arranged along the second direction.

[0048] In an exemplary embodiment, the control electrode of the ninth transistor and the control electrode of the twelfth transistor are the same electrode, and the active pattern of the ninth transistor and the active pattern of the twelfth transistor are the same active pattern.

[0049] The ninth transistor has two electrodes, and the twelfth transistor has two electrodes. The electrodes of the ninth and twelfth transistors are arranged along the first direction, and one of the electrodes of the ninth transistor and one of the electrodes of the twelfth transistor are the same electrode.

[0050] The first terminal of the ninth transistor is located between the second terminals of the two ninth transistors, and the first terminal of the twelfth transistor is located between the second terminals of the two twelfth transistors;

[0051] The second terminals of the ninth transistor and the twelfth transistor of at least one shift register are each connected to at least one third power supply line.

[0052] In an exemplary embodiment, the control electrode of the eighth transistor and the control electrode of the eleventh transistor are the same electrode, and the active pattern of the eighth transistor and the active pattern of the eleventh transistor are the same active pattern.

[0053] The second electrode of the eighth transistor is the same as the second electrode of the eleventh transistor.

[0054] In an exemplary embodiment, the control electrodes of the thirteenth transistor, the fourteenth transistor, and the fifteenth transistor are on the same electrode;

[0055] The control electrodes of the sixteenth transistor, the seventeenth transistor, and the eighteenth transistor are on the same electrode. In an exemplary embodiment, the non-display area further includes a first signal line area and a second signal line area, and at least one shift register includes a clock signal terminal, a first power supply terminal, and a second power supply terminal;

[0056] The first signal line area is located on the side of the transistor device area away from the display area, and the second signal line area is located on the side of the transistor device area closer to the display area.

[0057] The first signal line area includes: multiple clock signal lines, a first power line, and a second power line; at least one of the multiple clock signal lines, the first power line, and the second power line extends at least partially along the second direction;

[0058] The clock signal terminal of the at least one level shift register is electrically connected to one of the multiple clock signal lines, the first power line is electrically connected to the first power supply terminal of the at least one level shift register, and the second power supply line is electrically connected to the second power supply terminal of the at least one level shift register.

[0059] The second signal line area includes a common signal line group, which includes at least one common signal line that extends at least partially along the second direction.

[0060] In an exemplary embodiment, the non-display area is further provided with multiple drive signal output lines located in the second conductive layer and multiple scan lines located in the first conductive layer. At least one of the multiple drive signal output lines is electrically connected to the drive signal output terminal of at least one level shift register and one of the multiple scan lines, respectively.

[0061] The drive signal output line includes: a first output section, a second output section and a third output section, wherein the second output section is connected to the first output section and the third output section respectively, the first output section extends along a first direction, and the second output section and the third output section extend along a second direction, wherein the first output section and the second output section are arranged at right angles.

[0062] The second output and the third output in the drive signal output line connected to at least one shift register are located on the side of the first output that is away from the first adjacent shift register;

[0063] The orthographic projection of the first output unit on the substrate at least partially overlaps with the orthographic projection of the at least one common signal line on the substrate, the orthographic projection of the third output unit on the substrate at least partially overlaps with the orthographic projection of the scan line on the substrate, and the orthographic projection of the second output unit on the substrate does not overlap with the orthographic projection of the scan line on the substrate.

[0064] In an exemplary embodiment, the plurality of cascaded shift registers include: a first shift register, a second shift register, and a third shift register, wherein the first shift register is at least one of the plurality of cascaded shift registers, the second shift register is a shift register of one adjacent level of the first shift register, and the third shift register is a shift register of another adjacent level of the first shift register.

[0065] The scan line connected to the first shift register and the scan line connected to the second shift register are at least partially symmetrical with respect to an axis of symmetry extending along a first direction between the first shift register and the second shift register;

[0066] The spacing between the scan line connected to the first shift register and the scan line connected to the second shift register is greater than the spacing between the scan line connected to the first shift register and the scan line connected to the third shift register, and is greater than the length of at least one shift register extending along the second direction;

[0067] At least one of the multiple cascaded shift registers includes: a first transistor to the Mth transistor and a first capacitor to the Nth capacitor;

[0068] The m-th transistor in the first shift register and the m-th transistor in the second shift register are symmetrically arranged with respect to the midline extending along the first direction of the first shift register and the second shift register, where m is any value from 1 to M.

[0069] The nth capacitor in the first shift register and the nth capacitor in the second shift register are symmetrically arranged with respect to the midline extending along the first direction of the first shift register and the second shift register, where n is any value from 1 to N.

[0070] In an exemplary embodiment, the display area is provided with an array of pixel driving circuits;

[0071] At least one row of sub-pixels is electrically connected to a first scan line and a second scan line, respectively. The first scan line connected to the at least one row of sub-pixels is located on the side of the at least one row of sub-pixels closer to the previous row of sub-pixels, and the second scan line connected to the at least one row of sub-pixels is located on the side of the at least one row of sub-pixels closer to the next row of sub-pixels.

[0072] At least one row of subpixels is connected to the first scan line, which is electrically connected to the third shift register, and at least one row of subpixels is connected to the second scan line, which is electrically connected to the first shift register.

[0073] In an exemplary embodiment, the distance between the third output portion of the drive signal output line connected to at least one level shift register and the common signal line group along the first direction is greater than 30 micrometers;

[0074] The distance between the third output portion of the drive signal output line connected to at least one shift register and the third output portion of the drive signal output line connected to the first adjacent shift register along the second direction is greater than the distance between the third output portion of the drive signal output line connected to at least one shift register and the third output portion of the drive signal output line connected to the second adjacent shift register along the second direction, and the distance between the third output portion of the drive signal output line connected to at least one shift register and the third output portion of the drive signal output line connected to the second adjacent shift register along the second direction is greater than 5 micrometers;

[0075] The length of the second output section of the drive signal output line connected to at least one shift register along the second direction is greater than 30 micrometers.

[0076] In an exemplary embodiment, at least one common signal line includes: a first common connection portion and a plurality of spaced-apart second common connection portions, wherein the first common connection portion and the second common connection portions extend along the second direction;

[0077] The first common connection portion is located in the first conductive layer, and the second common connection portion is located in the second conductive layer;

[0078] At least one of the multiple spaced second common connection portions has its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first common connection portion on the substrate, and is electrically connected to the first common connection portion.

[0079] In an exemplary embodiment, it further includes: an initial signal line and multiple cascaded signal lines located in the transistor device area; at least one shift register includes: a first transistor, a fifth transistor, a signal input terminal and a first reset signal terminal; the control electrode and the first electrode of the first transistor are electrically connected to the signal input terminal; the second electrode of the first transistor is electrically connected to the pull-up node; the control electrode of the fifth transistor is electrically connected to the first reset signal terminal; the control electrode of the fifth transistor is electrically connected to the pull-up node; and the second electrode of the fifth transistor is electrically connected to the third power supply terminal.

[0080] At least one of the initial signal line and the plurality of cascaded signal lines extends at least partially along the second direction and is located in the first conductive layer;

[0081] At least one cascaded signal line is electrically connected to the signal input terminal of at least one shift register and the first reset signal terminal of at least one shift register, respectively;

[0082] The orthographic projection of at least one of the initial signal lines and multiple cascaded signal lines on the substrate is located between the orthographic projection of the first transistor on the substrate and the orthographic projection of the fifth transistor on the substrate, and between the orthographic projection of the first fourth power line on the substrate and the orthographic projection of the second fourth power line on the substrate.

[0083] The first electrode of the first transistor is electrically connected to the control electrode of the first transistor through a via.

[0084] In an exemplary embodiment, it further includes: multiple reset signal lines located in the transistor device region, and at least one level shift register includes: a second reset signal terminal, and at least one reset signal line is electrically connected to the second reset signal terminal in the at least one level shift register;

[0085] At least one of the plurality of reset signal lines extends at least partially along a second direction, and the reset signal line is located in a first conductive layer;

[0086] At least one of the multiple reset signal lines has its orthographic projection on the substrate located between the orthographic projection of the sixth transistor on the substrate and the orthographic projection of the second fourth power supply line on the substrate.

[0087] In an exemplary embodiment, at least one of the plurality of cascaded shift registers includes: a first transistor, a signal input terminal, and a pull-up node, wherein the control electrode and the first electrode of the first transistor are electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the pull-up node.

[0088] The active pattern of the first transistor includes: a plurality of first active portions and a second active portion, at least one of the plurality of first active portions and the second active portion extends along a second direction, and the plurality of first active portions are arranged along a first direction, and the second active portion is located on the side of at least one of the plurality of first active portions close to the display area.

[0089] At least one of the plurality of first active portions has a length in the second direction that is greater than the length of the second active portion in the second direction;

[0090] The aspect ratio of the channel region of at least one of the plurality of first active parts is in the range of 5 / 6 to 20 / 4, and the spacing between two adjacent active parts is in the range of 3 micrometers to 7 micrometers.

[0091] In an exemplary embodiment, at least one of the multiple cascaded shift registers includes: a third transistor, a pull-up node, a clock signal terminal, and a drive signal output terminal. The control electrode of the third transistor is electrically connected to the pull-up node, the first electrode of the third transistor is electrically connected to the clock signal terminal, and the second electrode of the third transistor is electrically connected to the drive signal output terminal.

[0092] The active pattern of the third transistor includes: a plurality of third active portions, at least one of the plurality of third active portions extending along a second direction, and the plurality of third active portions arranged along a first direction;

[0093] The aspect ratio of the channel region of at least one of the plurality of third active parts is in the range of 5 / 6 to 20 / 4, and the spacing between two adjacent active parts is in the range of 3 micrometers to 7 micrometers.

[0094] Secondly, this disclosure also provides a display device, including: the aforementioned display substrate.

[0095] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0096] Overview of the attached figures

[0097] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0098] Figure 1 is a schematic diagram of the planar structure of the display device;

[0099] Figure 2A is an equivalent circuit diagram of a shift register;

[0100] Figure 2B is the timing diagram of the shift register provided in Figure 2A;

[0101] Figure 3 is a schematic diagram of the display substrate structure;

[0102] Figure 4 is a top view of the display substrate;

[0103] Figure 5 is a top view of the display substrate (second view);

[0104] Figure 6 is a top view of the display substrate;

[0105] Figure 7 is a schematic diagram of the wiring of the display substrate;

[0106] Figure 8 is a cross-sectional schematic diagram of the display substrate;

[0107] Figure 9 is an enlarged schematic diagram of the capacitor in the display substrate provided in Figure 4;

[0108] Figure 10 is an enlarged schematic diagram of the capacitor in the display substrate provided in Figure 5;

[0109] Figure 11 is an enlarged schematic diagram of the capacitor in the display substrate shown in Figure 6;

[0110] Figure 12 is a partial schematic diagram of the display substrates provided in Figures 4 to 6;

[0111] Figure 13A is a partial structural schematic diagram of the display substrate;

[0112] Figure 13B is a schematic diagram of the connection relationship between the scan line and the pixel driving circuit;

[0113] Figure 14 is an enlarged schematic diagram of the ninth and twelfth transistors;

[0114] Figure 15 is an enlarged schematic diagram of the eighth and eleventh transistors;

[0115] Figure 16 is an enlarged schematic diagram of transistors thirteen through eighteen;

[0116] Figure 17 is a schematic diagram of the active pattern of the first transistor;

[0117] Figure 18 is an enlarged schematic diagram of the first transistor;

[0118] Figure 19 is a schematic diagram of the active pattern of the third transistor;

[0119] Figure 20 is a schematic diagram after the first conductive layer pattern in Figure 4 is formed;

[0120] Figure 21 is a schematic diagram of the semiconductor layer pattern in Figure 5;

[0121] Figure 22 is a schematic diagram after the semiconductor layer pattern is formed in Figure 4;

[0122] Figure 23 is a schematic diagram after the first insulating layer pattern is formed in Figure 4;

[0123] Figure 24 is a schematic diagram of the pattern of the second conductive layer in Figure 4;

[0124] Figure 25 is a schematic diagram after the second conductive layer pattern is formed in Figure 4;

[0125] Figure 26 is a schematic diagram after the first planarization layer pattern in Figure 4 is formed;

[0126] Figure 27 is a schematic diagram of the third conductive layer pattern in Figure 4;

[0127] Figure 28 is a schematic diagram after the formation of the third conductive layer pattern in Figure 4;

[0128] Figure 29 is a schematic diagram of the third conductive layer pattern in Figure 5;

[0129] Figure 30 is a schematic diagram of the formation of the third conductive layer pattern in Figure 5;

[0130] Figure 31 is a schematic diagram after the second flattening layer pattern is formed in Figure 5;

[0131] Figure 32 is a schematic diagram of the fourth conductive layer pattern in Figure 5;

[0132] Figure 33 is a schematic diagram after the fourth conductive layer pattern is formed in Figure 5;

[0133] Figure 34 is a schematic diagram after the third insulating layer pattern is formed in Figure 6;

[0134] Figure 35 is a schematic diagram of the fifth conductive layer pattern in Figure 6;

[0135] Figure 36 is a schematic diagram after the fifth conductive layer pattern is formed in Figure 6;

[0136] Figure 37 is a schematic diagram of the third conductive layer pattern in Figure 6;

[0137] Figure 38 is a schematic diagram of the formation of the third conductive layer pattern in Figure 6;

[0138] Figure 39 is a schematic diagram after the second flattening layer pattern is formed in Figure 6;

[0139] Figure 40 is a schematic diagram of the fourth conductive layer pattern in Figure 6;

[0140] Figure 41 is a schematic diagram of the fourth conductive layer pattern formed in Figure 6.

[0141] Detailed Explanation

[0142] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0143] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the length and spacing of each signal line along the first direction can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are merely structural schematic diagrams, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0144] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0145] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0146] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0147] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0148] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0149] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0150] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0151] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0152] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0153] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0154] Figure 1 is a schematic diagram of the planar structure of the display device. As shown in Figure 1, the display device includes a display substrate, which includes a display area AA and a non-display area BB. The display area AA is provided with sub-pixels P arranged in an array, multiple scan lines S and multiple data lines D.

[0155] At least one sub-pixel includes: a transistor and a first electrode and a second electrode for driving liquid crystal molecules to deflect, wherein the control electrode of the transistor is electrically connected to at least one scan line, the first electrode of the transistor is electrically connected to a data line, the second electrode of the transistor is electrically connected to the first electrode, and the second electrode of multiple sub-pixels may be the same electrode.

[0156] In an exemplary embodiment, at least one of the first electrode and the second electrode may be a transparent electrode.

[0157] In an exemplary embodiment, multiple scan lines can extend horizontally and be arranged sequentially vertically, and multiple data lines can extend vertically and be arranged sequentially horizontally. The intersecting scan lines and data lines define multiple regularly arranged sub-pixels.

[0158] In an exemplary embodiment, the display substrate may further include: a gate driving circuit that provides signals to multiple scan lines, and a source driving circuit that provides signals to multiple data lines.

[0159] In an exemplary embodiment, the display device may further include a timing controller connected to a gate driving circuit and a source driving circuit. The timing controller can provide grayscale values ​​and control signals of specifications suitable for the source driving circuit to the source driving circuit, and can provide clock signals, scan start signals, etc., of specifications suitable for the gate driving circuit to the gate driving circuit. The source driving circuit can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data lines. For example, the source driving circuit can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to the data lines on a pixel-by-pixel basis. The gate driving circuit can generate scan signals to be provided to scan lines by receiving clock signals, scan start signals, etc., from the timing controller. For example, the gate driving circuit can sequentially provide scan signals with on-level pulses to the scan lines. For example, the gate driving circuit can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal.

[0160] In an exemplary embodiment, the display substrate may include a plurality of pixel units arranged in a matrix. At least one of the plurality of pixel units includes a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light. Each of the first, second, and third sub-pixels includes a transistor, a first electrode, and a second electrode. The transistors in the first, second, and third sub-pixels are respectively connected to a scan line and a data line. The transistors are configured to provide a data line signal to the first electrode under the control of the scan line signal.

[0161] In an exemplary embodiment, the first sub-pixel can be a red sub-pixel emitting red light, the second sub-pixel can be a blue sub-pixel emitting blue light, and the third sub-pixel can be a green sub-pixel emitting green light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged horizontally side by side, vertically side by side, or in a triangular arrangement; this disclosure does not limit the specific arrangement.

[0162] In an exemplary embodiment, a pixel unit may include three sub-pixels, which may be arranged in a horizontal, vertical, or triangular manner, etc., and this disclosure does not limit the arrangement.

[0163] In other exemplary embodiments, a pixel unit may include four sub-pixels, which may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the arrangement.

[0164] In an exemplary embodiment, the shape of the sub-pixel can be rectangular, rhomboid, pentagonal, or hexagonal, etc., and this disclosure does not limit it.

[0165] In an exemplary embodiment, the gate drive circuit includes a plurality of cascaded shift registers.

[0166] In an exemplary embodiment, at least one shift register may include: an input sub-circuit, an output sub-circuit, a blanking reset sub-circuit, a display reset sub-circuit, a pull-down control sub-circuit, and a noise reduction sub-circuit.

[0167] Figure 2A is an equivalent circuit diagram of a shift register. As shown in Figure 2A, the input sub-circuit includes: a first transistor T1; the output sub-circuit includes: a second transistor T2, a third transistor T3 and a capacitor C; the blanking reset sub-circuit includes: a fourth transistor T4; the display reset sub-circuit includes: a fifth transistor T5 and a sixth transistor T6; the pull-down control sub-circuit includes: a seventh transistor T7 to a twelfth transistor T12; and the noise reduction sub-circuit includes: a thirteenth transistor T13 to an eighteenth transistor T18.

[0168] As shown in Figure 2A, the control electrode and first electrode of the first transistor T1 are electrically connected to the signal input terminal INPUT, and the second electrode of the first transistor T1 is electrically connected to the pull-up node PU; the control electrode of the second transistor T2 is electrically connected to the pull-up node PU, the first electrode of the second transistor T2 is electrically connected to the clock signal terminal CLK, and the second electrode of the second transistor T2 is electrically connected to the cascaded signal output terminal OUTC; the control electrode of the third transistor T3 is electrically connected to the pull-up node PU, the first electrode of the third transistor T3 is electrically connected to the clock signal terminal CLK, and the second electrode of the third transistor T3 is electrically connected to the drive signal output terminal GOUT; the control electrode of the fourth transistor T4 is electrically connected to the blanking reset signal terminal TRST. The first terminal of the fourth transistor T4 is electrically connected to the pull-up node PU, and the second terminal of the fourth transistor T4 is electrically connected to the third power supply terminal LVGL; the control terminal of the fifth transistor T5 is electrically connected to the first reset signal terminal RST1, the first terminal of the fifth transistor T5 is electrically connected to the pull-up node PU, and the second terminal of the fifth transistor T5 is electrically connected to the third power supply terminal LVGL; the control terminal of the sixth transistor T6 is electrically connected to the second reset signal terminal RST2, the first terminal of the sixth transistor T6 is electrically connected to the drive signal output terminal GOUT, and the second terminal of the sixth transistor T6 is electrically connected to the fourth power supply terminal VGL; the control terminal and the first terminal of the seventh transistor T7 are respectively electrically connected to the first high-level power supply terminal VDD1, and the seventh... The second terminal of transistor T7 is electrically connected to the first pull-down node PD1; the control terminal of the eighth transistor T8 is electrically connected to the signal input terminal INPUT, the first terminal of the eighth transistor T8 is electrically connected to the first pull-down node PD1, and the second terminal of the eighth transistor T8 is electrically connected to the third power supply terminal LVGL; the control terminal of the ninth transistor T9 is electrically connected to the pull-up node PU, the first terminal of the ninth transistor T9 is electrically connected to the first pull-down node PD1, and the second terminal of the ninth transistor T9 is electrically connected to the third power supply terminal LVGL; the control terminal and the first terminal of the tenth transistor T10 are respectively electrically connected to the second high-level power supply terminal VDD2, and the second terminal of the tenth transistor T10 is electrically connected to the second pull-down node PD2; the eleventh... The control electrode of transistor T11 is electrically connected to the signal input terminal INPUT; the first electrode of the eleventh transistor T11 is electrically connected to the second pull-down node PD2; and the second electrode of the eleventh transistor T11 is electrically connected to the third power supply terminal LVGL. The control electrode of the twelfth transistor T12 is electrically connected to the pull-up node PU; the first electrode of the twelfth transistor T12 is electrically connected to the second pull-down node PD2; and the second electrode of the twelfth transistor T12 is electrically connected to the third power supply terminal LVGL. The control electrode of the thirteenth transistor T13 is electrically connected to the first pull-down node PD1; the first electrode of the thirteenth transistor T13 is electrically connected to the pull-up node PU; and the second electrode of the thirteenth transistor T13 is electrically connected to the third power supply terminal LVGL.The control electrode of the fourteenth transistor T14 is electrically connected to the first pull-down node PD1, the first electrode of the fourteenth transistor T14 is electrically connected to the cascaded signal output terminal OUTC, and the second electrode of the fourteenth transistor T14 is electrically connected to the third power supply terminal LVGL; the control electrode of the fifteenth transistor T15 is electrically connected to the first pull-down node PD1, the first electrode of the fifteenth transistor T15 is electrically connected to the drive signal output terminal GOUT, and the second electrode of the fifteenth transistor T15 is electrically connected to the fourth power supply terminal VGL; the control electrode of the sixteenth transistor T16 is electrically connected to the second pull-down node PD2, the first electrode of the sixteenth transistor T16 is electrically connected to the pull-up node PU, and the second electrode of the sixteenth transistor T16 is electrically connected to the third power supply terminal LVGL. The first transistor T17 is electrically connected to the third power supply terminal LVGL; the control terminal of the seventeenth transistor T17 is electrically connected to the second pull-down node PD2; the first terminal of the seventeenth transistor T17 is electrically connected to the cascaded signal output terminal OUTC; and the second terminal of the seventeenth transistor T17 is electrically connected to the third power supply terminal LVGL. The control terminal of the eighteenth transistor T18 is electrically connected to the second pull-down node PD2; the first terminal of the eighteenth transistor T18 is electrically connected to the drive signal output terminal GOUT; and the second terminal of the eighteenth transistor T18 is electrically connected to the fourth power supply terminal VGL. The first terminal of the first capacitor C1 is electrically connected to the pull-up node PU; and the second terminal of the first capacitor C1 is electrically connected to the drive signal output terminal GOUT.

[0169] In an exemplary embodiment, the cascaded signal output terminal of at least one shift register is electrically connected to the first reset signal terminal and the second reset signal terminal of the at least one shift register, and is also electrically connected to the signal input terminal of the at least one shift register. Exemplarily, the cascaded signal output terminal of the at least one shift register is electrically connected to the first reset signal terminal and the second reset signal terminal of the previous shift register, and to the signal input terminal of the next shift register.

[0170] In an exemplary embodiment, the operation of the display substrate includes a display phase and a power-off phase. During the power-off phase, the display substrate has an Xon function to promptly release the charge from the pixel units in the display substrate.

[0171] In an exemplary embodiment, the display phase includes multiple display frames, with a silencing period set between adjacent display frames.

[0172] In an exemplary embodiment, in at least one display frame, the signal received by the signal input terminal INPUT is a single pulse signal.

[0173] In an exemplary embodiment, in at least one display frame, the cascade signal output terminal OUTC and the drive signal output terminal GOUT have the same signal. The cascade signal output terminal OUTC of at least one shift register is configured to provide an output cascade signal to the signal input terminal of at least one shift register and the first reset signal terminal and the second reset signal terminal of at least one shift register. The drive signal output terminal OUT of at least one shift register is configured to provide a drive signal to the scan signal line connected to the pixel drive circuit located in the display area.

[0174] In an exemplary embodiment, during the display phase, the signals of the third power terminal LVGL and the fourth power terminal VGL remain at a low level, and the absolute value of the voltage value of the signal of the third power terminal LVGL is greater than the absolute value of the voltage value of the signal of the fourth power terminal VGL.

[0175] In an exemplary embodiment, during the power-off phase, the signal of the fourth power supply terminal VGL is a high-level signal to pull up the signal of the drive signal output terminal OUT of at least one shift register, thereby discharging the pixel unit. The signal of the third power supply terminal LVGL is a low-level signal to pull down the signal of the pull-up node PU to prevent charge accumulation in the pull-up node PU of at least one shift register, so as to ensure that at least one shift register can work normally during the display phase.

[0176] In an exemplary embodiment, during the display phase, the signal at at least one of the first power supply terminal VDD1 and the second power supply terminal VDD2 is a periodic signal.

[0177] In an exemplary embodiment, during the display phase, the signals of the first power supply terminal VDD1 and the second power supply terminal VDD2 are at least partially inverted signals. When the signal of the first power supply terminal VDD1 is a high-level signal, the signal of the second power supply terminal VDD2 is a low-level signal, and when the signal of the second power supply terminal VDD2 is a high-level signal, the signal of the first power supply terminal VDD1 is a low-level signal.

[0178] In an exemplary embodiment, the display frame includes: a first display frame and a second display frame. In at least one first display frame, the signal of the first power terminal VDD1 is a high-level signal and the signal of the second power terminal VDD2 is a low-level signal. In at least one second display frame, the signal of the second power terminal VDD2 is a high-level signal and the signal of the first power terminal VDD1 is a low-level signal.

[0179] In an exemplary embodiment, the blanking reset signal terminal RST is an active level signal during the blanking period and an inactive level signal during the timing phase. An active level signal means that the signal terminal is electrically connected to the control electrode of the transistor, causing the transistor connected to the signal terminal to conduct; an inactive level signal means that the signal terminal is electrically connected to the control electrode of the transistor, causing the transistor connected to the signal terminal to disconnect.

[0180] In an exemplary embodiment, the signal of the first reset signal terminal RST1 is an active level signal for a portion of at least one display frame.

[0181] In an exemplary embodiment, the signal of the second reset signal terminal RST2 is an invalid level signal in at least one display frame and an valid level signal during a portion of the time period between display frames.

[0182] In an exemplary embodiment, this disclosure reduces noise in the shift register by alternately changing the first power supply terminal VDD1 and the second power supply terminal VDD2 to high-level signals, which can reduce the stress on at least one transistor in the shift register and thus improve the lifespan of the shift register.

[0183] Figure 2B is a timing diagram of the shift register shown in Figure 2A. Figure 2B is illustrated using the example of N-type transistors, from the first transistor T1 to the eighteenth transistor T18. The embodiments provided in this disclosure are further illustrated below through the operation of the shift register shown in Figure 2A.

[0184] In the first display frame, the fourth transistor T4, the sixth transistor T6, and the tenth transistor T10 are turned off, and the seventh transistor T7 is turned on.

[0185] In the first display frame, the operation of at least one shift register includes the following steps:

[0186] In the first stage, S1, the input stage, the signal at the INPUT terminal is high, while the clock signal CLK and the first reset signal RST1 are low. The first transistor T1, the eighth transistor T8, and the eleventh transistor T11 are turned on, and the fifth transistor T5 is turned off.

[0187] The first transistor T1 is turned on, and the high-level signal at the signal input terminal INPUT is written to the pull-up node PU. The second transistor T2, the third transistor T3, the ninth transistor T9, and the twelfth transistor T12 are turned on, and the low-level signal at the clock signal terminal CLK is written to the cascaded signal output terminal OUTC and the drive signal output terminal GOUT. The eighth transistor T8 and the ninth transistor T9 are turned on, and the low-level signal at the third power supply terminal LVGL is written to the first pull-down node PD1. The thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are turned off. The eleventh transistor T11 and the twelfth transistor T12 are turned on, and the low-level signal at the third power supply terminal LVGL is written to the second pull-down node PD2. The sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18 are turned off.

[0188] During this phase, the signal of the pull-up node PU is a high-level signal, the signals of the first pull-down node PD1 and the second pull-down node PD2 are low-level signals, and the signals of the cascade signal output terminal OUTC and the drive signal output terminal GOUT are low-level signals.

[0189] In the second stage, S2, the output stage, the clock signal CLK is high, while the signal input INPUT and the first reset signal RST1 are low. The first transistor T1, the fifth transistor T5, the eighth transistor T8, and the eleventh transistor T11 are disconnected.

[0190] The first transistor T1 is off, and the low-level signal at the signal input terminal INPUT cannot be written to the pull-up node PU. The voltage value of the signal at the pull-up node PU increases under the bootstrap effect of the capacitor C. The second transistor T2 and the third transistor T3 are fully turned on, and the high-level signal at the clock signal terminal CLK is written to the cascaded signal output terminal OUTC and the drive signal output terminal GOUT. The ninth transistor T9 and the twelfth transistor T12 are turned on, and the low-level signal at the third power supply terminal LVGL is written to the first pull-down node PD1. The thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are off, and the low-level signal at the third power supply terminal LVGL is written to the second pull-down node PD2. The sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18 are off.

[0191] During this phase, the signal of the pull-up node PU is a high-level signal, the signals of the first pull-down node PD1 and the second pull-down node PD2 are low-level signals, and the signals of the cascade signal output terminal OUTC and the drive signal output terminal GOUT are high-level signals.

[0192] In the third stage, the signals at the signal input terminal INPUT, the clock signal terminal CLK, and the first reset signal terminal RST1 are all low-level signals. The first transistor T1, the fifth transistor T5, the eighth transistor T8, and the eleventh transistor T11 are disconnected.

[0193] The signal at the pull-up node PU is a high-level signal. The second transistor T2 and the third transistor T3 are continuously turned on. The low-level signal of the clock signal terminal CLK is written to the cascade signal output terminal OUTC and the drive signal output terminal GOUT. The ninth transistor T9 and the twelfth transistor T12 are turned on. The low-level signal of the third power supply terminal LVGL is written to the first pull-down node PD1. The thirteenth transistor T13, the fourteenth transistor T14 and the fifteenth transistor T15 are turned off. The low-level signal of the third power supply terminal LVGL is written to the second pull-down node PD2. The sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned off.

[0194] During this phase, the signal of the pull-up node PU is a high-level signal, the signals of the first pull-down node PD1 and the second pull-down node PD2 are low-level signals, and the signals of the cascade signal output terminal OUTC and the drive signal output terminal GOUT are high-level signals.

[0195] In the fourth stage (S4), the reset stage, the clock signal terminal CLK and the first reset signal terminal RST1 are high-level signals, while the signal input terminal INPUT is low-level. The fifth transistor T5 is turned on, while the first transistor T1, the eighth transistor T8, and the eleventh transistor T11 are turned off.

[0196] The fifth transistor T5 is turned on, and the low-level signal of the third power supply terminal LVGL is written to the pull-up node PU. The sixth transistor T6 is turned on, and the low-level signal of the fourth power supply terminal VGL is written to the drive signal output terminal GOUT. The ninth transistor T9 and the twelfth transistor T12 are turned off, and the high-level signal of the first power supply terminal VDD1 is written to the first pull-down node PD1. The thirteenth transistor T13 is turned on, and the low-level signal of the third power supply terminal LVGL is continuously written to the pull-up node PU. The fourteenth transistor T14 is turned on, and the low-level signal of the third power supply terminal LVGL is written to the cascade signal output terminal OUTC. The fifteenth transistor T15 is turned on, and the low-level signal of the fourth power supply terminal VGL is continuously written to the drive signal output terminal GOUT. The second pull-down node PD2 maintains the low-level signal of the previous stage. The sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18 are turned off.

[0197] During this phase, the signal of the first pull-down node PD1 is a high-level signal, the signals of the pull-up node PU and the second pull-down node PD2 are low-level signals, and the signals of the cascade signal output terminal OUTC and the drive signal output terminal GOUT are low-level signals.

[0198] In the fifth stage, the clock signal CLK at S5 is high, while the signals at the signal input INPUT and the first reset signal RST1 are low. The first transistor T1, the fifth transistor T5, the eighth transistor T8, and the eleventh transistor T11 are disconnected.

[0199] Under the action of capacitor C, the signal of pull-up node PU remains at a low level. The ninth transistor T9 and the twelfth transistor T12 are turned off. The high level signal of the first power supply terminal VDD1 is written to the first pull-down node PD1. The thirteenth transistor T13 is turned on. The low level signal of the third power supply terminal LVGL is continuously written to pull-up node PU. The fourteenth transistor T14 is turned on. The low level signal of the third power supply terminal LVGL is written to the cascaded signal output terminal OUTC. The fifteenth transistor T15 is turned on. The low level signal of the fourth power supply terminal VGL is continuously written to the drive signal output terminal GOUT. The second pull-down node PD2 maintains the low level signal of the previous stage. The sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned off.

[0200] In the sixth stage, the signals at the signal input terminal INPUT, the clock signal terminal CLK, and the first reset signal terminal RST1 are all low-level signals. The first transistor T1, the fifth transistor T5, the eighth transistor T8, and the eleventh transistor T11 are disconnected.

[0201] Under the action of capacitor C, the signal of pull-up node PU remains at a low level. The ninth transistor T9 and the twelfth transistor T12 are turned off. The high level signal of the first power supply terminal VDD1 is written to the first pull-down node PD1. The thirteenth transistor T13 is turned on. The low level signal of the third power supply terminal LVGL is continuously written to pull-up node PU. The fourteenth transistor T14 is turned on. The low level signal of the third power supply terminal LVGL is written to the cascaded signal output terminal OUTC. The fifteenth transistor T15 is turned on. The low level signal of the fourth power supply terminal VGL is continuously written to the drive signal output terminal GOUT. The second pull-down node PD2 maintains the low level signal of the previous stage. The sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned off.

[0202] The fifth stage (S5) and the sixth stage (S6) occur in a loop until the signal at the signal input terminal (INPUT) is a high-level signal.

[0203] In the second display frame, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are turned off, while the tenth transistor T10 is turned on.

[0204] In the second display frame, the operation of at least one shift register includes the following steps:

[0205] In the first stage, S1, the input stage, the signal at the INPUT terminal is high, while the clock signal CLK and the first reset signal RST1 are low. The first transistor T1, the eighth transistor T8, and the eleventh transistor T11 are turned on, and the fifth transistor T5 is turned off.

[0206] The first transistor T1 is turned on, and the high-level signal at the signal input terminal INPUT is written to the pull-up node PU. The second transistor T2, the third transistor T3, the ninth transistor T9, and the twelfth transistor T12 are turned on, and the low-level signal at the clock signal terminal CLK is written to the cascaded signal output terminal OUTC and the drive signal output terminal GOUT. The eighth transistor T8 and the ninth transistor T9 are turned on, and the low-level signal at the third power supply terminal LVGL is written to the first pull-down node PD1. The thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are turned off. The eleventh transistor T11 and the twelfth transistor T12 are turned on, and the low-level signal at the third power supply terminal LVGL is written to the second pull-down node PD2. The sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18 are turned off.

[0207] During this phase, the signal of the pull-up node PU is a high-level signal, the signals of the first pull-down node PD1 and the second pull-down node PD2 are low-level signals, and the signals of the cascade signal output terminal OUTC and the drive signal output terminal GOUT are low-level signals.

[0208] In the second stage, S2, the output stage, the clock signal CLK is high, while the signal input INPUT and the first reset signal RST1 are low. The first transistor T1, the fifth transistor T5, the eighth transistor T8, and the eleventh transistor T11 are disconnected.

[0209] The first transistor T1 is off, and the low-level signal at the signal input terminal INPUT cannot be written to the pull-up node PU. The voltage value of the signal at the pull-up node PU increases under the bootstrap effect of the capacitor C. The second transistor T2 and the third transistor T3 are fully turned on, and the high-level signal at the clock signal terminal CLK is written to the cascaded signal output terminal OUTC and the drive signal output terminal GOUT. The ninth transistor T9 and the twelfth transistor T12 are turned on, and the low-level signal at the third power supply terminal LVGL is written to the first pull-down node PD1. The thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are off, and the low-level signal at the third power supply terminal LVGL is written to the second pull-down node PD2. The sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18 are off.

[0210] During this phase, the signal of the pull-up node PU is a high-level signal, the signals of the first pull-down node PD1 and the second pull-down node PD2 are low-level signals, and the signals of the cascade signal output terminal OUTC and the drive signal output terminal GOUT are high-level signals.

[0211] In the third stage, the signals at the signal input terminal INPUT, the clock signal terminal CLK, and the first reset signal terminal RST1 are all low-level signals. The first transistor T1, the fifth transistor T5, the eighth transistor T8, and the eleventh transistor T11 are disconnected.

[0212] The signal at the pull-up node PU is a high-level signal. The second transistor T2 and the third transistor T3 are continuously turned on. The low-level signal of the clock signal terminal CLK is written to the cascade signal output terminal OUTC and the drive signal output terminal GOUT. The ninth transistor T9 and the twelfth transistor T12 are turned on. The low-level signal of the third power supply terminal LVGL is written to the first pull-down node PD1. The thirteenth transistor T13, the fourteenth transistor T14 and the fifteenth transistor T15 are turned off. The low-level signal of the third power supply terminal LVGL is written to the second pull-down node PD2. The sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned off.

[0213] During this phase, the signal of the pull-up node PU is a high-level signal, the signals of the first pull-down node PD1 and the second pull-down node PD2 are low-level signals, and the signals of the cascade signal output terminal OUTC and the drive signal output terminal GOUT are high-level signals.

[0214] In the fourth stage (S4), the reset stage, the clock signal terminal CLK and the first reset signal terminal RST1 are high-level signals, while the signal input terminal INPUT is low-level. The fifth transistor T5 is turned on, while the first transistor T1, the eighth transistor T8, and the eleventh transistor T11 are turned off.

[0215] The fifth transistor T5 is turned on, and the low-level signal of the third power supply terminal LVGL is written to the pull-up node PU. The sixth transistor T6 is turned on, and the low-level signal of the fourth power supply terminal VGL is written to the drive signal output terminal GOUT. The ninth transistor T9 and the twelfth transistor T12 are turned off, and the high-level signal of the second high-level power supply terminal VDD2 is written to the second pull-down node PD2. The sixteenth transistor T16 is turned on, and the low-level signal of the third power supply terminal LVGL is continuously written to the pull-up node PU. The seventeenth transistor T17 is turned on, and the low-level signal of the third power supply terminal LVGL is written to the cascade signal output terminal OUTC. The eighteenth transistor T18 is turned on, and the low-level signal of the fourth power supply terminal VGL is continuously written to the drive signal output terminal GOUT. The first pull-down node PD1 maintains the low-level signal of the previous stage. The thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are turned off.

[0216] During this phase, the signal of the second pull-down node PD2 is a high-level signal, the signals of the pull-up node PU and the first pull-down node PD1 are low-level signals, and the signals of the cascade signal output terminal OUTC and the drive signal output terminal GOUT are low-level signals.

[0217] In the fifth stage, the clock signal CLK at S5 is high, while the signals at the signal input INPUT and the first reset signal RST1 are low. The first transistor T1, the fifth transistor T5, the eighth transistor T8, and the eleventh transistor T11 are disconnected.

[0218] Under the action of capacitor C, the signal of pull-up node PU remains at a low level. The ninth transistor T9 and the twelfth transistor T12 are turned off. The high-level signal of the second high-level power supply terminal VDD2 is written to the second pull-down node PD2. The sixteenth transistor T16 is turned on. The low-level signal of the third power supply terminal LVGL is continuously written to pull-up node PU. The seventeenth transistor T17 is turned on. The low-level signal of the third power supply terminal LVGL is written to the cascaded signal output terminal OUTC. The eighteenth transistor T18 is turned on. The low-level signal of the fourth power supply terminal VGL is continuously written to the drive signal output terminal GOUT. The first pull-down node PD1 maintains the low-level signal of the previous stage. The thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are turned off.

[0219] In the sixth stage, the signals at the signal input terminal INPUT, the clock signal terminal CLK, and the first reset signal terminal RST1 are all low-level signals. The first transistor T1, the fifth transistor T5, the eighth transistor T8, and the eleventh transistor T11 are disconnected.

[0220] Under the action of capacitor C, the signal of pull-up node PU remains at a low level. The ninth transistor T9 and the twelfth transistor T12 are turned off. The high-level signal of the second high-level power supply terminal VDD2 is written to the second pull-down node PD2. The sixteenth transistor T16 is turned on. The low-level signal of the third power supply terminal LVGL is continuously written to pull-up node PU. The seventeenth transistor T17 is turned on. The low-level signal of the third power supply terminal LVGL is written to the cascaded signal output terminal OUTC. The eighteenth transistor T18 is turned on. The low-level signal of the fourth power supply terminal VGL is continuously written to the drive signal output terminal GOUT. The second pull-down node PD2 maintains the low-level signal of the previous stage. The thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are turned off.

[0221] The fifth stage (S5) and the sixth stage (S6) occur in a loop until the signal at the signal input terminal (INPUT) is a high-level signal.

[0222] As can be seen from the above analysis, the gate drive circuit in the display device uses two power supply terminals (the first power supply terminal VDD1 and the second power supply terminal VDD2) to alternately perform DC noise reduction. The setting of two power supply terminals leads to a tight space layout for the gate drive circuit, and the gate drive circuit occupies a large space, which cannot meet the requirements of narrow bezel.

[0223] Therefore, this disclosure provides a display substrate.

[0224] Figure 3 is a schematic diagram of the display substrate structure, Figure 4 is a top view of the display substrate (first view), Figure 5 is a top view of the display substrate (second view), and Figure 6 is a top view of the display substrate (third view). As shown in Figures 3 to 6, the display substrate provided in this embodiment includes: a display area AA and a non-display area surrounding at least one side of the display area AA. The non-display area includes: a transistor device area TR, and the transistor device area TR is provided with a gate driving circuit GOA. The gate driving circuit includes: a plurality of cascaded shift registers. Figures 4 to 6 show two adjacent shift registers GOA1 and GOA2.

[0225] As shown in Figures 4 to 6, at least two stages of the multiple cascaded shift registers are arranged at least partially symmetrically with respect to a straight line extending along the first direction D1, and the second direction D2 is the arrangement direction of at least two stages of the multiple cascaded shift registers.

[0226] As shown in Figures 4 to 6, the display substrate further includes: two fourth power lines located in the transistor device area, the fourth power lines VL4 extending at least partially along the second direction D2; the fourth power lines VL4 are electrically connected to the fourth power supply terminal of at least one level shift register.

[0227] In an exemplary embodiment, as shown in Figures 4 to 6, the first fourth power line VL4-1 and its orthographic projection on the substrate are located between the orthographic projections of at least two transistors in at least one level shift register on the substrate, and the second fourth power line VL4-2 and its orthographic projection on the substrate are located on the side of the orthographic projections of multiple transistors in at least one level shift register on the substrate that are closer to the display area.

[0228] In an exemplary embodiment, at least one shift register includes a plurality of transistors and a capacitor C. The plurality of transistors includes a first transistor T1 to an eighteenth transistor T18. The plurality of transistors in Figures 4 to 6 have the same structure, the difference being the structure of the capacitor C.

[0229] In an exemplary embodiment, the first direction D1 and the second direction D2 are located in the same plane and intersect. For example, the first direction D1 and the second direction D2 can be perpendicular.

[0230] In an exemplary embodiment, the non-display area includes: a first border area BB1, a second border area BB2, a third border area BB3, and a fourth border area BB4. The first border area BB1 may be located to the left of the display area AA, and may also be referred to as the left border area; the second border area BB2 may be located to the right of the display area AA, and may also be referred to as the right border area; the third border area BB3 may be located at the top of the display area AA, and may also be referred to as the top border area; and the fourth border area BB4 may be located at the bottom of the display area AA, and may also be referred to as the bottom border area. Exemplarily, the gate driving circuit GOA may be disposed in at least one area of ​​the first border area BB1 and the second border area BB2.

[0231] This disclosure enables at least two stages of cascaded shift registers to be at least partially symmetrically arranged with respect to a straight line extending along a first direction, thereby allowing at least two stages of cascaded shift registers to share some signal lines, thus achieving a narrow bezel.

[0232] In an exemplary embodiment, as shown in FIG3, the non-display area is further provided with a first signal line area LR1 and a second signal line area LR2. At least one shift register includes: a clock signal terminal, a blanking reset signal terminal, a first power supply terminal, and a second power supply terminal. The first signal line area LR1 is located on the side of the transistor device area TR away from the display area AA, and the second signal line area LR2 is located on the side of the transistor device area TR closer to the display area AA.

[0233] In an exemplary embodiment, the first signal line region includes: a plurality of clock signal lines, a blanking reset signal line, a first power supply line, and a second power supply line. At least one of the plurality of clock signal lines, the blanking reset signal line, the first power supply line, and the second power supply line extends at least partially along a second direction.

[0234] In an exemplary embodiment, the clock signal terminal of at least one level shift register is electrically connected to one of a plurality of clock signal lines, the first power supply line is electrically connected to the first power supply terminal of at least one level shift register, the second power supply line is electrically connected to the second power supply terminal of at least one level shift register, and the blanking reset signal line is electrically connected to the blanking reset signal terminal of at least one level shift register.

[0235] In an exemplary embodiment, the second signal line area may include a common signal line group, which includes at least one common signal line that extends at least partially along a second direction.

[0236] In an exemplary embodiment, FIG7 is a schematic diagram of the wiring of a display substrate. As shown in FIG7, the display substrate may further include: a first power connection line VCL1 and a second power connection line VCL2 located in a non-display area, wherein at least one of the first power connection line VCL1 and the second power connection line VCL2 extends at least partially along a first direction D1; the first power connection line VCL1 is electrically connected to the first end of the first fourth power line VL4-1 and the first end of the second fourth power line VL4-2, respectively; the second power connection line VCL2 is electrically connected to the second end of the first fourth power line VL4-1 and the second end of the second fourth power line VL4-2, respectively.

[0237] In an exemplary embodiment, as shown in Figures 4 to 6, the orthographic projection of the sixth transistor T6 on the substrate is located between the orthographic projection of the second fourth power line VL4-2 on the substrate and the orthographic projection of the first fourth power line VL4-1 on the substrate, and the distance between the orthographic projection of the sixth transistor T6 on the substrate and the orthographic projection of the second fourth power line VL4-2 on the substrate is less than the distance between the orthographic projection of the sixth transistor T6 on the substrate and the orthographic projection of the first fourth power line VL4-1 on the substrate.

[0238] In an exemplary embodiment, as shown in Figures 4 to 6, the orthographic projection of at least one of the fifteenth transistor T15 and the eighteenth transistor T18 onto the substrate is located on the side of the first fourth power line VL4-1 away from the display area, and the distance between the orthographic projection of at least one of the fifteenth transistor T15 and the eighteenth transistor T18 onto the substrate and the orthographic projection of the first fourth power line VL4-1 onto the substrate is less than the distance between the orthographic projection of the sixth transistor T6 onto the substrate and the orthographic projection of the first fourth power line VL4-1 onto the substrate.

[0239] In an exemplary embodiment, the sixth transistor T6, fifteenth transistor T15, and eighteenth transistor T18 connected to the fourth power line VL4 are used to provide a low-level signal to the drive signal output terminal during the switching between display frames to reduce noise at the drive signal terminal. The fifteenth transistor T15 provides a low-level signal to the drive signal output terminal under the control of the signal from the first pull-down node within a display frame to reduce noise at the drive signal terminal. The eighteenth transistor T18 provides a low-level signal to the drive signal output terminal under the control of the signal from the second pull-down node within a display frame to reduce noise at the drive signal terminal. Therefore, the usage of the sixth transistor T6 is completely different from that of at least one of the fifteenth and eighteenth transistors T18. Therefore, this invention... Two fourth power lines VL4 are configured. The fifteenth transistor T15 and the eighteenth transistor T18 are close to and electrically connected to the first fourth power line VL4-1. The sixth transistor T6 is close to and electrically connected to the second fourth power line VL4-2. The first fourth power line VL4-1 and the second fourth power line VL4-2 are connected end to end through the first power connection line VCL1 and the second power connection line VCL2. This avoids the need to set a horizontal trace from at least one of the fifteenth transistor T15 and the eighteenth transistor T18 to connect to the sixth transistor T6 if only one fourth power line is configured. This can save the space occupied by at least one shift register along the second direction and achieve a high PPI of the display substrate.

[0240] In an exemplary embodiment, at least one of the plurality of transistors includes: a control electrode, an active pattern, a first electrode, and a second electrode.

[0241] In an exemplary embodiment, FIG8 is a schematic cross-sectional view of the display substrate. As shown in FIG8, the display substrate further includes a circuit structure layer disposed on the substrate 100. The circuit structure layer includes a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially stacked on the substrate 100. At least one level shift register and at least one transistor in a sub-pixel, a first electrode, and a second electrode are disposed in the circuit structure layer. The at least one level shift register includes a plurality of transistors. In FIG8, GT refers to one of the transistors in the at least one level shift register, GC refers to one of the capacitors in the at least one level shift register, PT refers to the transistor in at least one sub-pixel, PE1 refers to the first electrode in at least one sub-pixel, and PE2 refers to the second electrode in at least one sub-pixel. FIG8 is illustrated using GT and PT as an example of a bottom gate structure.

[0242] As shown in Figure 8, the circuit structure layer further includes: a first insulating layer 200 located between the first conductive layer and the semiconductor layer; a second insulating layer 300 located between the second conductive layer and the third conductive layer; and a third insulating layer 400 located between the third conductive layer and the fourth conductive layer.

[0243] In an exemplary embodiment, the first conductive layer includes: a fourth power line, and the control electrode of at least one transistor among a plurality of transistors located in at least one level shift register, and the control electrode of a transistor located in at least one sub-pixel.

[0244] In an exemplary embodiment, the first power connection line and the second power connection line may be located in the first conductive layer.

[0245] In an exemplary embodiment, the semiconductor layer includes: an active pattern of at least one transistor among a plurality of transistors in at least one level shift register and a control electrode of a transistor in at least one sub-pixel.

[0246] In an exemplary embodiment, the second conductive layer includes: a first pole and a second pole of at least one transistor of a plurality of transistors located in at least one level shift register, and a first pole and a second pole of a transistor located in at least one sub-pixel.

[0247] In an exemplary embodiment, the third conductive layer includes one of a first electrode and a second electrode located in at least one sub-pixel.

[0248] In an exemplary embodiment, the fourth conductive layer includes another electrode located in the first electrode and the second electrode of at least one sub-pixel.

[0249] In an exemplary embodiment, as shown in Figures 4 to 6, the display substrate may further include: an initial signal line (not shown) located in the transistor device region and a plurality of cascaded signal lines OUTCL. At least one of the initial signal line and the plurality of cascaded signal lines OUTCL extends at least partially along a second direction and is located in the first conductive layer.

[0250] In an exemplary embodiment, at least one cascaded signal line OUTCL is electrically connected to the signal input terminal of at least one shift register and the first reset signal terminal of at least one shift register, respectively.

[0251] In an exemplary embodiment, the orthographic projection of at least one of the initial signal line and the plurality of cascaded signal lines on the substrate is located between the orthographic projection of the first transistor T1 on the substrate and the orthographic projection of the fifth transistor T5 on the substrate, and between the orthographic projection of the first fourth power line VL4-1 on the substrate and the orthographic projection of the second fourth power line VL4-2 on the substrate.

[0252] In this disclosure, since both the first transistor T1 and the fifth transistor T5 are electrically connected to the pull-up node, the first transistor T1 and the fifth transistor T5 are placed on both sides of the cascaded signal line, which can save the area occupied by the shift register and thus achieve a narrow bezel.

[0253] In an exemplary embodiment, as shown in Figures 4 to 6, the display substrate further includes: a plurality of reset signal lines RL2 located in the transistor device area, and at least one level shift register includes: a second reset signal terminal, and at least one reset signal line RL2 is electrically connected to the second reset signal terminal in the at least one level shift register.

[0254] In an exemplary embodiment, as shown in Figures 4 to 6, at least one of the plurality of reset signal lines RL2 extends at least partially along the second direction D2, and the reset signal line is located in the first conductive layer.

[0255] In an exemplary embodiment, as shown in Figures 4 to 6, the orthographic projection of at least one of the multiple reset signal lines RL2 onto the substrate lies between the orthographic projection of the sixth transistor T6 onto the substrate and the orthographic projection of the second fourth power supply line VL4-2 onto the substrate.

[0256] In an exemplary embodiment, FIG9 is an enlarged schematic diagram of the capacitor in the display substrate provided in FIG4. As shown in FIG9, at least one stage of the multiple cascaded shift registers includes: a first electrode C1, a second electrode C2, and a third electrode C3. At least two of the first electrode C1, the second electrode C2, and the third electrode C3 are disposed in different layers. The orthographic projections of at least two of the first electrode C1, the second electrode C2, and the third electrode C3 on the substrate at least partially overlap. The first electrode C1 is electrically connected to the third electrode C3 and serves as the first electrode of the capacitor, and the second electrode C2 serves as the second electrode of the capacitor.

[0257] In an exemplary embodiment, the first electrode C1 is located in the first conductive layer, the second electrode C2 is located in the second conductive layer, and the third electrode C3 is located in the third or fourth conductive layer.

[0258] As shown in Figure 9, the display substrate further includes a first connecting portion CL1 and a second connecting portion CL2. The first connecting portion CL1 is located in the second conductive layer, and the second connecting portion CL2 is located in the same film layer as the third electrode plate C3, and is located in either the third or fourth conductive layer. The first electrode plate C1 and the third electrode plate C3 are connected through the first connecting portion CL1, and the second electrode plate C2 is connected to the second connecting portion CL2.

[0259] In the capacitor shown in Figure 9, the second connecting part CL2 and the third plate C3 are located on the top layer of the multiple film layers in which the capacitor is located, and are connected to different plates respectively. For example, the second connecting part CL2 is connected to the second plate C2, and the third plate C3 is connected to the first plate C1. This arrangement is beneficial for testing the capacitor in the shift register and can improve the reliability of the shift register.

[0260] In an exemplary embodiment, FIG10 is an enlarged schematic diagram of the capacitor in the display substrate provided in FIG5. As shown in FIG10, at least one stage of the multiple cascaded shift registers includes: a first electrode C1, a second electrode C2, a third electrode C3, and a fourth electrode C4. At least two of the first electrode C1, second electrode C2, third electrode C3, and fourth electrode C4 are disposed in different layers, and the orthographic projections of at least two of the first electrode C1, second electrode C2, third electrode C3, and fourth electrode C4 on the substrate at least partially overlap. The first electrode C1 is electrically connected to the fourth electrode C4 and serves as the first electrode of the capacitor, and the second electrode C2 is electrically connected to the third electrode C3 and serves as the second electrode of the capacitor.

[0261] In an exemplary embodiment, the first electrode C1 is located in the first conductive layer, the second electrode C2 is located in the second conductive layer, the third electrode C3 is located in the third conductive layer, and the fourth electrode C4 is located in the fourth conductive layer.

[0262] As shown in Figure 10, the display substrate further includes a first connecting portion CL1 and a second connecting portion CL2. The first connecting portion CL1 is located in the second conductive layer, and the second connecting portion CL2 is located in the fourth conductive layer. The first electrode plate C1 and the fourth electrode plate C4 are connected through the first connecting portion, and the second electrode plate C2 and the third electrode plate C3 are connected through the second connecting portion.

[0263] In the capacitor shown in Figure 10, the second connecting part CL2 and the fourth plate C4 are located on the top layer of the multiple film layers in which the capacitor is located, and are connected to different plates respectively. For example, the second connecting part CL2 is connected to the second plate C2 and the third plate C3, and the fourth plate C4 is connected to the first plate C1. This arrangement is beneficial for testing the capacitor in the shift register and can improve the reliability of the shift register.

[0264] In an exemplary embodiment, FIG11 is an enlarged schematic diagram of the capacitor in the display substrate provided in FIG6. As shown in FIG11, at least one stage of the multiple cascaded shift registers includes: a first electrode C1, a second electrode C2, a third electrode C3, a fourth electrode C4, and a fifth electrode C5. At least two of the first electrode C1, second electrode C2, third electrode C3, fourth electrode C4, and fifth electrode C5 are disposed in different layers, and the orthographic projections of at least two of the first electrode C1, second electrode C2, third electrode C3, fourth electrode C4, and fifth electrode C5 on the substrate at least partially overlap. The first electrode C1 is electrically connected to the third electrode C3 and the fifth electrode C5 respectively, and serves as the first electrode of the capacitor. The second electrode C2 is electrically connected to the fourth electrode C4, and serves as the second electrode of the capacitor.

[0265] In an exemplary embodiment, the circuit structure layer further includes a fifth conductive layer, which is located between the semiconductor layer and the third conductive layer. A first electrode C1 is located in the first conductive layer, a second electrode C2 is located in the second conductive layer, a third electrode C3 is located in the fifth conductive layer, a fourth electrode C4 is located in the third conductive layer, and a fifth electrode C5 is located in the fourth conductive layer.

[0266] As shown in Figure 11, the display substrate further includes a first connecting portion CL1 and a second connecting portion CL2. The first connecting portion CL1 is located in the second conductive layer, and the second connecting portion CL2 is located in the fourth conductive layer. The second electrode plate C2 and the fourth electrode plate C4 are connected through the second connecting portion CL2. The first electrode plate C1 and the third electrode plate C3 are connected through a via. The first electrode plate C1 and the fifth electrode plate C5 are connected through the first connecting portion CL1.

[0267] In exemplary embodiments, the capacitor in Figure 4 of this disclosure has a three-layer structure, the capacitor in Figure 5 has a four-layer structure, and the capacitor in Figure 6 has a five-layer structure. By employing a multi-layer capacitor structure, this disclosure can save the area occupied by the capacitor while ensuring the capacitance, thereby achieving a narrow bezel. The more layers the capacitor includes, the greater the area saved. Figure 8 illustrates this with an example of a three-layer capacitor structure.

[0268] In an exemplary embodiment, as shown in Figures 4 to 6, the fourth transistor T4, the ninth transistor T9, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, and the eighteenth transistor T18 are arranged sequentially along the first direction D1.

[0269] In an exemplary embodiment, the fourth transistor T4, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, and the eighteenth transistor T18 in at least one level shift register are all electrically connected to the third power supply terminal. This disclosure avoids signal line winding by arranging the fourth transistor T4, the ninth transistor T9, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, and the eighteenth transistor T18 in at least one level shift register in the same direction, thereby saving the space occupied by the shift register.

[0270] In an exemplary embodiment, as shown in Figures 4 to 6, the eighth transistor T8 and the eleventh transistor T11 are arranged along the second direction D2, the thirteenth transistor T13 and the sixteenth transistor T16 are arranged along the second direction D2, the fourteenth transistor and the seventeenth transistor T17 are arranged along the second direction D2, and the fifteenth transistor T15 and the eighteenth transistor T18 are arranged along the second direction D2.

[0271] In an exemplary embodiment, FIG12 is a partial schematic diagram of the display substrate provided in FIGS. 4 to 6. As shown in FIGS. 4 to 6 and FIG12, the display substrate further includes: a plurality of third power lines VL3 located in the transistor device region, at least one of the plurality of third power lines VL3 extending at least partially along the first direction D3.

[0272] In an exemplary embodiment, the third power line VL3 is located in the second conductive layer.

[0273] In an exemplary embodiment, the second terminals of the fourth transistor, the fifth transistor, the eighth transistor, the ninth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the sixteenth transistor, and the seventeenth transistor are each electrically connected to a third power supply terminal. At least one third power supply line is electrically connected to a third power supply terminal in at least one level of a shift register.

[0274] In an exemplary embodiment, the multiple cascaded shift registers include: a first shift register, a second shift register, and a third shift register. The first shift register is at least one stage of the cascaded shift registers, the second shift register is a shift register of one adjacent stage of the first shift register, and the third shift register is a shift register of another adjacent stage of the first shift register. Taking the nth stage shift register as the first shift register as an example, the (n-1)th stage shift register is the second shift register corresponding to the nth stage shift register, the (n+1)th stage shift register is the third shift register corresponding to the nth stage shift register, the (n+2)th stage shift register is the first shift register, the (n+1)th stage shift register is the second shift register corresponding to the (n+2)th stage shift register, and the (n+3)th stage shift register is the third shift register corresponding to the (n+2)th stage shift register. That is, the third shift register corresponding to the nth stage shift register and the second shift register corresponding to the (n+2)th stage shift register are the same shift register.

[0275] In an exemplary embodiment, at least one third power line is located between the first shift register and the second shift register, and is electrically connected to the third power supply terminals of the first shift register and the second shift register. The center line of the at least one third power line extending along the first direction is the same as the center line of the first shift register and the second shift register extending along the first direction.

[0276] In an exemplary embodiment, at least one of the multiple cascaded shift registers includes: a first transistor to an Mth transistor and a first capacitor to an Nth capacitor.

[0277] In an exemplary embodiment, the m-th transistor in the first shift register and the m-th transistor in the second shift register are symmetrically arranged with respect to the midline extending along a first direction between the first and second shift registers, where m is any value from 1 to M. Exemplarily, the first transistor in the first shift register and the first transistor in the second shift register are symmetrically arranged with respect to the midline extending along the first direction between the first and second shift registers, the second transistor in the first shift register and the second transistor in the second shift register are symmetrically arranged with respect to the midline extending along the first direction between the first and second shift registers, and so on.

[0278] In an exemplary embodiment, the nth capacitor in the first shift register and the nth capacitor in the second shift register are symmetrically arranged with respect to the midline extending along the first direction of the first and second shift registers, where n is any value from 1 to N. Exemplarily, the first capacitor in the first shift register and the first capacitor in the second shift register are symmetrically arranged with respect to the midline extending along the first direction of the first and second shift registers, the second capacitor in the first shift register and the second capacitor in the second shift register are symmetrically arranged with respect to the midline extending along the first direction of the first and second shift registers, and so on.

[0279] In an exemplary embodiment, at least one third power line VL3 is integrally structured with the second poles 44 of the fourth transistor, 54 of the fifth transistor, 84 of the eighth transistor, 94 of the ninth transistor, 114 of the eleventh transistor, 124 of the twelfth transistor, 134 of the thirteenth transistor, 144 of the fourteenth transistor, 164 of the sixteenth transistor, and 175 of the seventeenth transistor in at least one of the first and second shift registers.

[0280] In an exemplary embodiment, at least one third power line VL3 is integrated with the second terminals 44, 54, 84, 94, 114, 124, 134, 144, 164, and 175 of the fourth transistor, fifth transistor, eighth transistor, ninth transistor, eleventh transistor, twelfth transistor, thirteenth transistor, fourteenth transistor, sixteenth transistor, and seventeenth transistor in at least one shift register and at least one first adjacent shift register. That is, at least one shift register and the first adjacent shift register share a third power line, which can save the area occupied by at least two shift registers along the second direction and achieve high PPI.

[0281] Figure 13A is a partial structural schematic diagram of the display substrate. As shown in Figure 13A, the non-display area is further provided with multiple drive signal output lines OUTL located on the second conductive layer and multiple scan lines GL located on the first conductive layer. At least one of the multiple drive signal output lines is electrically connected to the drive signal output terminal of at least one level shift register and one of the multiple scan lines, respectively. Figure 13A shows the at least one level shift register and the second adjacent shift register. Figure 13A is illustrated using a common signal line group including: a first common signal line COML1 and a second common signal line COML2 as an example.

[0282] As shown in Figure 13A, the drive signal output line includes: a first output section OUTLA, a second output section OUTLB, and a third output section OUTLC. The second output section OUTLB is connected to the first output section OUTLA and the third output section OUTLC respectively. The first output section OUTLA extends along the first direction D1, and the second output section OUTLB and the third output section OUTLC extend along the second direction D2. The first output section OUTLA and the second output section OUTLB are set at right angles.

[0283] As shown in Figure 13A, the second output section OUTLB and the third output section OUTLC in the drive signal output line OUTL connected to at least one shift register are located on the side of the first output section OUTLA that is away from the first adjacent shift register, that is, on the side that is close to the second adjacent shift register.

[0284] As shown in Figure 13A, the orthographic projection of the first output unit OUTLA onto the substrate at least partially overlaps with the orthographic projection of at least one common signal line onto the substrate. The orthographic projection of the third output unit OUTLC onto the substrate at least partially overlaps with the orthographic projection of the scan line GL onto the substrate, while the orthographic projection of the second output unit OUTLB onto the substrate does not overlap with the orthographic projection of the scan line GL onto the substrate.

[0285] In an exemplary embodiment, the configuration of the drive signal output line in this disclosure ensures that the area where the third output unit overlaps with the scan line GL and the area where the first output unit overlaps with at least one common signal line are not on the same straight line. This avoids the situation where a short circuit occurs in the area where the third output unit overlaps with the scan line, which would break down the area where the first output unit overlaps with at least one common signal line, causing a short circuit between the drive signal output line and the common signal line. This can prevent display abnormalities on the display substrate.

[0286] In an exemplary embodiment, as shown in FIG13A, the distance W1 between the third output section OUTLC of the drive signal output line connected to at least one shift register and the common signal line group along the first direction D1 is greater than 30 micrometers.

[0287] In an exemplary embodiment, as shown in FIG13A, the distance between the third output portion OUTLC of the drive signal output line OUTL connected to at least one shift register and the third output portion OUTLC of the drive signal output line connected to the first adjacent shift register along the second direction D2 is greater than the distance between the third output portion OUTLC of the drive signal output line connected to at least one shift register and the third output portion OUTLC of the drive signal output line connected to the second adjacent shift register along the second direction D2, and the distance W3 between the third output portion OUTLC of the drive signal output line OUTL connected to at least one shift register and the third output portion OUTLC of the drive signal output line connected to the second adjacent shift register along the second direction D2 is greater than 5 micrometers.

[0288] In an exemplary embodiment, as shown in FIG13A, the length W2 of the second output portion OUTLB of the drive signal output line connected to at least one shift register along the second direction D2 is greater than 30 micrometers.

[0289] In an exemplary embodiment, as shown in FIG13A, at least one common signal line COML includes: a first common connection portion COMLA and a plurality of spaced second common connection portions COMLB, wherein the first common connection portion COMLA and the second common connection portion COMLB extend along a second direction.

[0290] In an exemplary embodiment, the first common connection portion COMLA is located in the first conductive layer, and the second common connection portion COMLB is located in the second conductive layer.

[0291] In an exemplary embodiment, at least one of the multiple spaced second common connection portions COMLB has its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first common connection portion COMLA on the substrate, and is electrically connected to the first common connection portion COMLA.

[0292] In an exemplary embodiment, the scan line GL1 connected to the first shift register and the scan line GL2 connected to the second shift register are at least partially symmetrical with respect to the axis of symmetry O extending along a first direction between the first shift register and the second shift register.

[0293] In an exemplary embodiment, the distance W4 between the scan line GL1 connected to the first shift register and the scan line GL2 connected to the second shift register is greater than the distance W5 between the scan line GL1 connected to the first shift register and the scan line GL3 connected to the third shift register, and is greater than the length L of at least one shift register extending along the second direction.

[0294] Figure 13B is a schematic diagram of the connection relationship between the scan lines and the pixel driving circuit. As shown in Figure 13B, the display area is provided with sub-pixels P arranged in an array. At least one row of sub-pixels is electrically connected to the first scan line GL1 and the second scan line GL2, respectively. The first scan line GL1 connected to the at least one row of sub-pixels is located on the side of the at least one row of sub-pixels closer to the previous row of sub-pixels, and the second scan line GL2 connected to the at least one row of sub-pixels is located on the side of the at least one row of sub-pixels closer to the next row of sub-pixels.

[0295] In an exemplary embodiment, a first scan line GL1 connected to at least one row of subpixels is electrically connected to a third shift register, and a second scan line GL2 connected to at least one row of subpixels is electrically connected to a first shift register.

[0296] Figure 14 is an enlarged schematic diagram of the ninth transistor and the twelfth transistor. As shown in Figure 14, in an exemplary embodiment, the control electrode 91 of the ninth transistor T9 and the control electrode 121 of the twelfth transistor T12 are the same electrode, and the active pattern 92 of the ninth transistor T9 and the active pattern 122 of the twelfth transistor T12 are the same active pattern.

[0297] As shown in Figure 14, the ninth transistor T9 has two second electrodes 94, and the twelfth transistor T12 has two second electrodes 124 94. The second electrodes 124 of the ninth transistor T9 and the twelfth transistor T12 are arranged along the first direction D1. One of the second electrodes 94 of the ninth transistor T9 and one of the second electrodes 124 94 of the twelfth transistor T12 are the same electrode.

[0298] As shown in Figure 14, the first terminal 93 of the ninth transistor T9 is located between the second terminals of the two ninth transistors T9, and the first terminal 123 of the twelfth transistor T12 is located between the second terminals 124 of the two twelfth transistors T12; the second terminals 94 of the ninth transistor T9 and the second terminals 124 of the twelfth transistor T12 of at least one shift register are respectively connected to at least one third power supply line VL3.

[0299] In this disclosure, the control electrode and the second electrode of the ninth transistor and the twelfth transistor are connected in the same way. Therefore, this disclosure makes the control electrode of the ninth transistor T9 and the control electrode of the twelfth transistor T12 the same electrode. The active pattern of the ninth transistor T9 and the active pattern of the twelfth transistor T12 are the same active pattern, which can save the area occupied by the shift register and achieve a narrow bezel.

[0300] Figure 15 is an enlarged schematic diagram of the eighth and eleventh transistors. As shown in Figure 15, the control electrode 82 of the eighth transistor T8 and the control electrode 112 of the eleventh transistor T11 are the same electrode; the active pattern 81 of the eighth transistor T8 and the active pattern 1111 of the eleventh transistor T11 are the same active pattern; the second electrode 84 of the eighth transistor T8 and the second electrode 114 of the eleventh transistor are the same electrode.

[0301] In this disclosure, the control electrode and the second electrode of the eighth and eleventh transistors are connected in the same way. Therefore, the arrangement of the eighth and eleventh transistors in this disclosure can save the area occupied by the shift register and achieve a narrow bezel.

[0302] Figure 16 is an enlarged schematic diagram of transistors 13 to 18 in Figures 4 to 6. As shown in Figure 16, the control electrode 131 of the 13th transistor, the control electrode 141 of the 14th transistor, and the control electrode 151 of the 15th transistor are the same electrode.

[0303] As shown in Figure 16, the control electrode 161 of the sixteenth transistor, the control electrode 171 of the seventeenth transistor, and the control electrode 181 of the eighteenth transistor are the same electrode.

[0304] In an exemplary embodiment, FIG17 is a schematic diagram of the active pattern of the first transistor. As shown in FIG17, the active pattern 12 of the first transistor includes: a plurality of first active portions 121 and a second active portion 122, at least one of the plurality of first active portions 121 and the second active portion 122 extends along a second direction, and the plurality of first active portions 121 are arranged along a first direction, and the second active portion 122 is located on the side of at least one of the plurality of first active portions 121 that is close to the display area.

[0305] In an exemplary embodiment, at least one of the plurality of first active portions 121 has a length along the second direction D2 that is greater than the length of the second active portion 122 along the second direction D1.

[0306] In an exemplary embodiment, the width of the channel region of at least one of the plurality of first active portions 121 is in the range of 5 micrometers to 20 micrometers, the length of the channel region of at least one of the plurality of first active portions 121 is in the range of 4 micrometers to 6 micrometers, and the width-to-length ratio of the channel region of at least one of the plurality of first active portions is in the range of 5 / 6 to 20 / 4.

[0307] In an exemplary embodiment, at least one of the plurality of first active portions 121 has a length L11 along the second direction D2 ranging from 15 micrometers to 25 micrometers, and the spacing W11 between two adjacent active portions ranges from 3 micrometers to 7 micrometers. For example, at least one of the plurality of first active portions 121 has a length L11 along the second direction D2 of 20 micrometers, and the spacing W11 between two adjacent active portions is 5 micrometers.

[0308] The active pattern arrangement of the first transistor in this disclosure reduces the area of ​​the first transistor without affecting functional output and process capability, thereby reducing the area occupied by the shift register and enabling a narrow bezel.

[0309] In an exemplary embodiment, FIG18 is an enlarged schematic diagram of a first transistor. As shown in FIG18, the first transistor includes: a control electrode 11, an active pattern 12, a first electrode 13, and a second electrode 14. The first electrode 13 of the first transistor is electrically connected to the control electrode 11 of the first transistor through a via V.

[0310] In this disclosure, the first electrode 13 of the first transistor is electrically connected to the control electrode 11 of the first transistor through a via V. That is, the signals of the control electrode and the first electrode of the first transistor are the same, which can avoid the characteristic drift of the first transistor under high temperature and high humidity environment, improve the life of the first transistor, and ensure the normal output of the shift register.

[0311] In an exemplary embodiment, FIG19 is a schematic diagram of the active pattern of the third transistor. As shown in FIG19, the active pattern 32 of the third transistor includes: a plurality of third active portions 320, at least one of the plurality of third active portions 320 extending along a second direction, and the plurality of third active portions 320 arranged along a first direction D1.

[0312] In an exemplary embodiment, the width of the channel region of at least one of the plurality of third active portions 320 is in the range of 5 micrometers to 20 micrometers, the length of the channel region of at least one of the plurality of third active portions 320 is in the range of 4 micrometers to 6 micrometers, and the width-to-length ratio of the channel region of at least one of the plurality of third active portions 320 is in the range of 5 / 6 to 20 / 4.

[0313] In an exemplary embodiment, as shown in FIG19, at least one of the plurality of third active portions 320 has a length L21 along the second direction D2 ranging from 15 micrometers to 25 micrometers, and the spacing W21 between two adjacent active portions ranges from 3 micrometers to 7 micrometers. For example, at least one of the plurality of third active portions 320 has a length L21 along the second direction D2 of 20 micrometers, and the spacing W21 between two adjacent active portions is 5 micrometers.

[0314] After rigorous reliability testing, the characteristics of the first transistor and the first reference transistor in this disclosure are not significantly different, and the characteristics of the third transistor and the third reference transistor are not significantly different. The first reference transistor includes multiple active portions, the length of which along the second direction is less than the length of which along the second direction is the same as the length of which along the second direction is the same as the length of which along the first direction is 5 micrometers. Similarly, the length of which along the second direction is 5 micrometers, and the length of which along the first direction is also 5 micrometers. The third reference transistor also includes multiple active portions, the length of which along the second direction is less than the length of which along the second direction is the same as the length of which along the second direction is the same as the length of which along the first direction is 5 micrometers.

[0315] In an exemplary embodiment, the ratio of the length of the control electrode of at least one transistor in a plurality of transistors in at least one level shift register along a first direction to the length along a second direction is in the range of 1:1 to 7:1.

[0316] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0317] The display substrate provided in the embodiments of this disclosure will be further described below with reference to the display substrate shown in FIG5.

[0318] (1) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: depositing a first conductive thin film on a substrate, and patterning the first conductive thin film using a patterning process to form a first conductive layer pattern. As shown in FIG20, FIG20 is a schematic diagram after the formation of the first conductive layer pattern in FIG4. In an exemplary embodiment, the first conductive layer may be referred to as a gate metal (GATE) layer.

[0319] In an exemplary embodiment, as shown in FIG20, the first conductive layer pattern may include at least: a first fourth power line VL4-1, a second fourth power line VL4-2, multiple cascaded signal lines OUTCL, multiple reset signal lines RL2, and the control electrode 11 of the first transistor to the control electrode 181 of the eighteenth transistor located in at least one level shift register, a first electrode plate C, and a connecting electrode E1.

[0320] In an exemplary embodiment, at least one of the following signal lines extends at least partially along the second direction D2: the first fourth power line VL4-1, the second fourth power line VL4-2, the cascaded signal line OUTCL, and the reset signal line RL2. The width of at least one of the following signal lines is greater than the width of at least one of the cascaded signal line OUTCL and the reset signal line RL2.

[0321] In an exemplary embodiment, the first fourth power line VL4-1, multiple cascaded signal lines OUTCL, multiple reset signal lines RL2, and the second fourth power line VL4-2 are arranged sequentially along the direction close to the display area.

[0322] In an exemplary embodiment, the control electrodes 41 of the fourth transistor, 71 of the seventh transistor, 81 of the eighth transistor, 91 of the ninth transistor, 101 of the tenth transistor, 111 of the eleventh transistor, 121 of the twelfth transistor, 131 of the thirteenth transistor, 141 of the fourteenth transistor, 151 of the fifteenth transistor, 161 of the sixteenth transistor, 171 of the seventeenth transistor, and 181 of the eighteenth transistor are located on the side of the first fourth power line VL4-1 away from the display area. The control electrode 51 of the fifth transistor is located between the first fourth power line VL4-1 and the multiple cascaded signal lines OUTCL. The control electrodes 11 of the first transistor, 21 of the second transistor, 31 of the third transistor, 61 of the sixth transistor, and the first electrode C1 are located between the multiple cascaded signal lines OUTCL and the multiple reset signal lines RL2.

[0323] In an exemplary embodiment, the control electrodes 41 of the fourth transistor, 91 of the ninth transistor, 121 of the twelfth transistor, 131 of the thirteenth transistor, 141 of the fourteenth transistor, and 151 of the fifteenth transistor are arranged along the first direction D1 and sequentially along the direction closest to the display area. The control electrodes 161 of the sixteenth transistor, 171 of the seventeenth transistor, and 181 of the eighteenth transistor are arranged along the first direction D1 and sequentially along the direction closest to the display area. The control electrodes 131 of the thirteenth transistor and 161 of the sixteenth transistor are arranged along the second direction D2. The control electrodes 141 of the fourteenth transistor and 171 of the seventeenth transistor are arranged along the second direction D2. The control electrodes 151 of the fifteenth transistor and 181 of the eighteenth transistor are arranged along the second direction D2. The control electrodes 41 of the fourth transistor, 71 of the seventh transistor, and 101 of the tenth transistor are arranged along the second direction D2. The control electrodes 81 of the eighth transistor and 111 of the eleventh transistor are arranged along the second direction D2, and are located on the side of the control electrodes 151 of the fifteenth transistor and 181 of the eighteenth transistor closer to the display area. The control electrodes 51 of the fifth transistor, 11 of the first transistor, 21 of the second transistor, 31 of the third transistor, the first plate C1, and 61 of the sixth transistor are arranged along the first direction D1, and are arranged sequentially towards the display area.

[0324] In an exemplary embodiment, the control electrode 91 of the ninth transistor and the control electrode 121 of the twelfth transistor are integrated. The control electrodes 131, 141, and 151 of the thirteenth, fourteenth, and fifteenth transistors are integrated. The control electrodes 161, 171, and 181 of the sixteenth, seventeenth, and eighteenth transistors are integrated. The control electrode 81 of the eighth transistor and the control electrode 111 of the eleventh transistor are integrated. The control electrodes 21 of the second transistor, 31 of the third transistor, and the first electrode C1 are integrated. The control electrodes 11 of the first transistor, 41 of the fourth transistor, 51 of the fifth transistor, 61 of the sixth transistor, 71 of the seventh transistor, and 101 of the tenth transistor are individually disposed.

[0325] In an exemplary embodiment, the main body portion of at least one control electrode of the first transistor's control 11 to the eighteenth transistor's control 181 may be rectangular in shape.

[0326] (2) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a first insulating film and a semiconductor film on the aforementioned pattern, patterning the semiconductor film using a patterning process to form a first insulating layer covering the first conductive layer pattern, and forming a semiconductor layer pattern disposed on the first insulating layer. As shown in Figures 21 and 22, Figure 21 is a schematic diagram of the semiconductor layer pattern in Figure 4, and Figure 22 is a schematic diagram of Figure 4 after the semiconductor layer pattern has been formed.

[0327] In an exemplary embodiment, as shown in Figures 21 and 22, the semiconductor layer pattern may include at least: an active pattern 12 of the first transistor to an active pattern 182 of the eighteenth transistor located in at least one level shift register.

[0328] In an exemplary embodiment, the active pattern 12 of the first transistor is disposed separately. The active pattern 12 of the first transistor includes: a plurality of first active portions 121 and a second active portion 122, at least one of the plurality of first active portions 121 and the second active portion 122 extends along a second direction D2, and the plurality of first active portions 121 are arranged along a first direction D1, and the second active portion 122 is located on the side of at least one of the plurality of first active portions 121 that is close to the display area.

[0329] In an exemplary embodiment, at least one of the plurality of first active portions 121 has a length along the second direction D2 that is greater than the length of the second active portion 122 along the second direction D1. In another exemplary embodiment, the length of at least one of the plurality of first active portions 121 along the second direction D2 is in the range of 15 micrometers to 25 micrometers, and the spacing between two adjacent active portions is in the range of 3 micrometers to 7 micrometers. For example, at least one of the plurality of first active portions 121 has a length of 20 micrometers along the second direction D2, and the spacing between two adjacent active portions is 5 micrometers.

[0330] In an exemplary embodiment, the active pattern 22 of the second transistor is disposed separately. The active pattern 22 of the second transistor includes a plurality of fourth active portions 220 arranged along a first direction D1. At least one fourth active portion 220 extends along a second direction D2.

[0331] In an exemplary embodiment, at least one of the plurality of fourth active portions 220 has a length along the second direction D2 that is greater than the length of the first active portion 121 along the first direction D1, and at least one of the plurality of fourth active portions 220 has a length along the first direction D1 that is less than the length of the first active portion 121 along the first direction D1.

[0332] In an exemplary embodiment, the active pattern 32 of the third transistor is separately provided and includes: a plurality of third active portions 320, at least one of the plurality of third active portions 320 extending along the second direction D2, and the plurality of third active portions 320 arranged along the first direction D1.

[0333] In an exemplary embodiment, at least one of the plurality of third active portions 320 has a length along the second direction D2 ranging from 15 micrometers to 25 micrometers, and the spacing between two adjacent active portions ranges from 3 micrometers to 7 micrometers. For example, at least one of the plurality of third active portions 320 has a length along the second direction D2 of 20 micrometers, and the spacing between two adjacent active portions is 5 micrometers. The length of at least one of the plurality of third active portions 320 along the first direction D1 is less than the length of the first active portion 121 along the first direction D1.

[0334] In an exemplary embodiment, the active pattern 42 of the fourth transistor is provided separately, and the shape of the active pattern 42 of the fourth transistor is rectangular. The length of the active pattern 42 of the fourth transistor along the second direction is less than the length of the second active portion 122 along the second direction D2, and the length of the active pattern 42 of the fourth transistor along the first direction D1 is less than the length of the first active portion 121 along the first direction D1.

[0335] In an exemplary embodiment, the active pattern 52 of the fifth transistor is separately disposed and includes a plurality of fifth active portions 520. At least one of the plurality of fifth active portions 520 extends along a second direction D2, and the plurality of fifth active portions 520 are arranged along a first direction D1.

[0336] In an exemplary embodiment, at least one of the plurality of fifth active portions 520 has a length along the second direction D2 that is greater than the length of the second active portion 122 along the second direction D2 and less than the length of the first active portion 121 along the second direction D2. At least one of the plurality of fifth active portions 520 has a length along the first direction D1 that is less than the length of the first active portion 121 along the first direction D1.

[0337] In an exemplary embodiment, the active pattern 62 of the sixth transistor is provided separately, and the active pattern 62 of the sixth transistor is rectangular in shape. The length of the active pattern 62 of the sixth transistor along the second direction D2 is greater than the length of the first active portion 121 along the second direction D2. The length of the active pattern 62 of the sixth transistor along the first direction D1 is greater than the length of the third active portion 320 along the first direction D1.

[0338] In an exemplary embodiment, the active pattern 72 of the seventh transistor is provided separately, and the shape of the active pattern 72 of the seventh transistor is rectangular. The length of the active pattern 72 of the seventh transistor along the second direction D2 is less than the length of the active pattern 42 of the fourth transistor along the second direction D2. The length of the active pattern 72 of the seventh transistor along the first direction D1 is less than the length of the third active portion 320 along the first direction D1.

[0339] In an exemplary embodiment, the active pattern 82 of the eighth transistor and the active pattern 112 of the eleventh transistor are an integral structure. The integral structure of the active pattern 82 of the eighth transistor and the active pattern 112 of the eleventh transistor is rectangular and extends along the second direction D2.

[0340] In an exemplary embodiment, the length of the integrated structure of the active pattern 82 of the eighth transistor and the active pattern 112 of the eleventh transistor along the second direction D2 is less than the length of the first active portion 121 along the second direction D2. The length of the integrated structure of the active pattern 82 of the eighth transistor and the active pattern 112 of the eleventh transistor along the first direction D1 is greater than the length of the third active portion 320 along the second direction D2.

[0341] In an exemplary embodiment, the active pattern 92 of the ninth transistor and the active pattern 122 of the twelfth transistor are an integral structure. The integral structure of the active pattern 92 of the ninth transistor and the active pattern 122 of the twelfth transistor is rectangular and extends along the second direction D2.

[0342] In an exemplary embodiment, the length of the integrated structure of the active pattern 92 of the ninth transistor and the active pattern 122 of the twelfth transistor along the second direction D2 is less than the length of the first active portion 121 along the second direction D2, and the length of the integrated structure of the active pattern 92 of the ninth transistor and the active pattern 122 of the twelfth transistor along the first direction D1 is greater than the length of the first active portion 121 along the first direction D1.

[0343] In an exemplary embodiment, the active pattern 132 of the thirteenth transistor is separately disposed and includes a plurality of sixth active portions 1320. At least one of the plurality of sixth active portions 1320 extends along a second direction D2, and the plurality of sixth active portions 1320 are arranged along a first direction D1.

[0344] In an exemplary embodiment, at least one of the plurality of sixth active portions 1320 has a length along the second direction D2 that is less than the length of the first active portion 121 along the second direction D2, and at least one of the plurality of sixth active portions 1320 has a length along the first direction D1 that is less than the length of the first active portion 121 along the first direction D1.

[0345] In an exemplary embodiment, the active pattern 142 of the fourteenth transistor is provided separately, and the active pattern 142 of the fourteenth transistor is rectangular in shape. The length of the active pattern 142 of the fourteenth transistor along the second direction is less than the length of the second active portion 122 along the second direction D2, and the length of the active pattern 142 of the fourteenth transistor along the first direction D1 is less than the length of the first active portion 121 along the first direction D1.

[0346] In an exemplary embodiment, the active pattern 152 of the fifteenth transistor is separately provided and includes a plurality of seventh active portions 1520. At least one of the plurality of seventh active portions 1520 extends along a second direction D2, and the plurality of seventh active portions 1520 are arranged along a first direction D1.

[0347] In an exemplary embodiment, at least one of the plurality of seventh active portions 1520 has a length along the second direction D2 that is less than the length of the first active portion 121 along the second direction D2, and at least one of the plurality of seventh active portions 1520 has a length along the first direction D1 that is greater than the length of the third active portion 320 along the first direction D1.

[0348] In an exemplary embodiment, the active pattern 162 of the sixteenth transistor is separately provided and includes a plurality of eighth active portions 1620. At least one of the plurality of eighth active portions 1620 extends along a second direction D2, and the plurality of eighth active portions 1620 are arranged along a first direction D1.

[0349] In an exemplary embodiment, at least one of the plurality of eighth active portions 1620 has a length along the second direction D2 that is less than the length of the first active portion 121 along the second direction D2, and at least one of the plurality of eighth active portions 1620 has a length along the first direction D1 that is less than the length of the first active portion 121 along the first direction D1.

[0350] In an exemplary embodiment, the active pattern 172 of the seventeenth transistor is provided separately, and the active pattern 172 of the seventeenth transistor is rectangular in shape. The length of the active pattern 172 of the seventeenth transistor along the second direction is less than the length of the second active portion 122 along the second direction D2, and the length of the active pattern 172 of the seventeenth transistor along the first direction D1 is less than the length of the first active portion 121 along the first direction D1.

[0351] In an exemplary embodiment, the active pattern 182 of the eighteenth transistor is provided separately, and the active pattern 182 of the eighteenth transistor is rectangular in shape. The length of the active pattern 182 of the eighteenth transistor along the second direction D2 is greater than the length of the second active portion 121 along the second direction D2. The length of the active pattern 182 of the eighteenth transistor along the first direction D1 is greater than the length of the third active portion 320 along the first direction D1.

[0352] In an exemplary embodiment, the active pattern 12 of the first transistor is disposed on the control electrode of the first transistor; the active pattern 22 of the second transistor and the active pattern 32 of the third transistor are disposed on the control electrode of the second transistor (which is also the control electrode of the third transistor and the first electrode plate); the active pattern 32 of the third transistor is disposed on the control electrode of the third transistor; the active pattern 42 of the fourth transistor is disposed on the control electrode of the fourth transistor; the active pattern 52 of the fifth transistor is disposed on the control electrode of the fifth transistor; the active pattern 62 of the sixth transistor is disposed on the control electrode of the sixth transistor; the active pattern 72 of the seventh transistor is disposed on the control electrode of the seventh transistor; and the active patterns 82 of the eighth transistor and 112 of the eleventh transistor are disposed on the control electrode of the eighth transistor (which is also the control electrode of the third transistor and the first electrode plate). The active patterns 92 of the ninth transistor and 122 of the twelfth transistor are located on the control electrode of the ninth transistor (which is also the control electrode of the twelfth transistor). The active pattern 102 of the tenth transistor is located on the control electrode of the tenth transistor. The active patterns 132 of the thirteenth transistor, 142 of the fourteenth transistor, and 152 of the fifteenth transistor are located on the control electrode of the thirteenth transistor (which is also the control electrode of the fourteenth and fifteenth transistors). The active patterns 162 of the sixteenth transistor, 172 of the seventeenth transistor, and 182 of the eighteenth transistor are located on the control electrode of the sixteenth transistor (which is also the control electrode of the seventeenth and eighteenth transistors).

[0353] (3) Forming a first insulating layer pattern. In an exemplary embodiment, forming a first insulating layer pattern may include: on a substrate on which the aforementioned pattern is formed, patterning the first insulating layer by a patterning process to form a first insulating layer pattern including a plurality of vias, as shown in FIG23, FIG23 being a schematic diagram of FIG4 after the formation of the first insulating layer pattern.

[0354] In an exemplary embodiment, as shown in FIG23, the plurality of vias in the first insulating layer pattern include: a first via V1 to a tenth via V10.

[0355] In an exemplary embodiment, the orthogonal projection of the first via V1 onto the substrate is within the range of the orthogonal projection of the control electrode of the first transistor onto the substrate. The first via V1 exposes the surface of the control electrode of the first transistor. The first via V1 is configured to allow the first electrode of the subsequently formed first transistor to be connected to the control electrode of the first transistor through the via.

[0356] In an exemplary embodiment, the orthogonal projection of the second via V2 onto the substrate lies within the range of the orthogonal projection of the control electrode of the second transistor (which is also the control electrode of the third transistor and the first electrode plate) onto the substrate. The second via V2 exposes the surface of the control electrode of the second transistor (which is also the control electrode of the third transistor and the first electrode plate). The second via V2 is configured to allow the subsequently formed first connection portion and the second electrode of the first transistor (which is also the first electrode of the fifth transistor) to be connected to the control electrode of the second transistor (which is also the control electrode of the third transistor and the first electrode plate) through the via.

[0357] In an exemplary embodiment, the orthographic projection of the third via V3 on the substrate is within the range of the orthographic projection of the control electrode of the eighth transistor (which is also the control electrode of the eleventh transistor) on the substrate. The third via V3 exposes the surface of the control electrode of the eighth transistor (which is also the control electrode of the eleventh transistor). The third via V3 is configured to allow the first electrode of the subsequently formed first transistor to be connected to the control electrode of the eighth transistor (which is also the control electrode of the eleventh transistor) through the via.

[0358] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate lies within the range of the orthographic projection of the control electrode of the ninth transistor (which is also the control electrode of the twelfth transistor) onto the substrate. The fourth via V4 exposes the surface of the control electrode of the ninth transistor (which is also the control electrode of the twelfth transistor). The fourth via V4 is configured to allow the first electrode of the subsequently formed fourth transistor to be connected to the control electrode of the ninth transistor (which is also the control electrode of the twelfth transistor) through the via.

[0359] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate lies within the range of the orthographic projection of the control electrode of the thirteenth transistor (which is also the control electrode of the fourteenth transistor and the fifteenth transistor) onto the substrate. The fifth via V5 exposes the surface of the control electrode of the thirteenth transistor (which is also the control electrode of the fourteenth transistor and the fifteenth transistor). The fifth via V5 is configured to allow the first electrode of the subsequently formed eighth transistor to be connected to the control electrode of the thirteenth transistor (which is also the control electrode of the fourteenth transistor and the fifteenth transistor) through the via.

[0360] In an exemplary embodiment, the orthogonal projection of the sixth via V6 onto the substrate lies within the range of the orthogonal projection of the control electrode of the sixteenth transistor (which is also the control electrode of the seventeenth and eighteenth transistors) onto the substrate. The sixth via V6 exposes the surface of the control electrode of the sixteenth transistor (which is also the control electrode of the seventeenth and eighteenth transistors). The sixth via V6 is configured to allow the first electrode of the subsequently formed eleventh transistor to be connected to the control electrode of the sixteenth transistor (which is also the control electrode of the seventeenth and eighteenth transistors) through the via.

[0361] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is within the range of the orthographic projection of the connection electrode on the substrate. The seventh via V7 exposes the surface of the connection electrode. The seventh via V7 is configured to allow the second electrode of the subsequently formed first transistor (which is also the first electrode of the fifth transistor) and the first electrode of the thirteenth transistor (which is also the first electrode of the sixteenth transistor) to be connected to the connection electrode through the via.

[0362] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is within the range of the orthographic projection of the first fourth power line on the substrate. The eighth via V8 exposes the surface of the first fourth power line. The eighth via V8 is configured to allow the second terminal of the subsequently formed fifteenth transistor (which is also the second terminal of the eighteenth transistor) to be connected to the first fourth power line through the via.

[0363] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate lies within the range of the orthographic projection of the cascaded signal line onto the substrate. The ninth via V9 exposes the surface of the cascaded signal line. The ninth via V9 is configured to connect the second terminal of the subsequently formed second transistor (which is also the first terminal of the fourteenth transistor and the first terminal of the seventeenth transistor) to the cascaded signal line.

[0364] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is within the range of the orthographic projection of the second fourth power line on the substrate. The tenth via V10 exposes the surface of the second fourth power line. The tenth via V10 is configured to allow the second terminal of the subsequently formed sixth transistor to be connected to the second fourth power line through the via.

[0365] (4) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: depositing a second conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the second conductive thin film using a patterning process to form a second conductive layer pattern disposed on the semiconductor layer pattern, as shown in Figures 24 and 25. Figure 24 is a schematic diagram of the second conductive layer pattern in Figure 4, and Figure 25 is a schematic diagram of the second conductive layer pattern after it has been formed in Figure 4. In an exemplary embodiment, the second conductive layer may be referred to as a source / drain metal (SD) layer.

[0366] In an exemplary embodiment, as shown in Figures 24 and 25, the second conductive layer pattern may include at least: a third power line VL3, a drive signal output line OUTL, a first pole 13 and a second pole 14 of a first transistor located in at least one level shift register, a first pole 183 and a second pole 184 of an eighteenth transistor, a second electrode plate C2, and a first connection portion CL1.

[0367] In an exemplary embodiment, the first electrode 13 of the first transistor is provided separately. The first electrode 13 of the first transistor is zigzag-shaped and extends at least partially along the first direction D1. The first electrode 13 of the first transistor is connected to the control electrode of the first transistor through a first via and to the control electrode of the eighth transistor (which is also the control electrode of the eleventh transistor) through a third via.

[0368] In an exemplary embodiment, the first electrode 14 of the first transistor and the first electrode 53 of the fifth transistor are integral structures. The second electrode 14 of the first transistor (which is also the first electrode 53 of the fifth transistor) is connected to the control electrode of the second transistor (which is also the control electrode of the third transistor and the first electrode plate) through a second via, and is configured through a seventh via V7 to connect the second electrode of the subsequently formed first transistor (which is also the first electrode of the fifth transistor) to the connection electrode.

[0369] In an exemplary embodiment, the first electrode 23 of the second transistor and the first electrode 33 of the third transistor are an integral structure.

[0370] In an exemplary embodiment, the second terminal 24 of the second transistor, the first terminal 143 of the fourteenth transistor, and the first terminal 173 of the seventeenth transistor are integrally formed. The second terminal of the subsequently formed second transistor (which is also the first terminal of the fourteenth and seventeenth transistors) is configured to be connected to the cascaded signal line via a ninth via.

[0371] In an exemplary embodiment, the second electrode 34 of the third transistor, the first electrode 63 of the sixth transistor, the first electrode 153 of the fifteenth transistor, the first electrode 183 of the eighteenth transistor, the second electrode plate C2, and the cascaded signal line OUTL are integrated into a single structure.

[0372] In an exemplary embodiment, the first electrode 43 of the fourth transistor is provided separately. The first electrode 43 of the fourth transistor is connected to the control electrode of the ninth transistor (which is also the control electrode of the twelfth transistor) through a fourth via.

[0373] In an exemplary embodiment, the second terminals 44 of the fourth transistor, 54 of the fifth transistor, 84 of the eighth transistor, 94 of the ninth transistor, 114 of the eleventh transistor, 124 of the twelfth transistor, 134 of the thirteenth transistor, 144 of the fourteenth transistor, 164 of the sixteenth transistor, and 174 of the seventeenth transistor are integrated with the third power line VL3.

[0374] In an exemplary embodiment, the second electrode 64 of the sixth transistor is provided separately. The second electrode 64 of the sixth transistor is connected to the second fourth power line through a tenth via.

[0375] In an exemplary embodiment, the first electrode 73 of the seventh transistor is provided separately, while the second electrode 74 of the seventh transistor and the first electrode 93 of the ninth transistor are an integral structure.

[0376] In an exemplary embodiment, the first electrode 83 of the eighth transistor is provided separately. The first electrode 83 of the eighth transistor is connected to the control electrode of the thirteenth transistor (which is also the control electrode of the fourteenth and fifteenth transistors) through a fifth via V5.

[0377] In an exemplary embodiment, the first electrode 103 of the tenth transistor is provided separately, while the second electrode 104 of the tenth transistor and the first electrode 123 of the twelfth transistor are an integral structure.

[0378] In an exemplary embodiment, the first electrode 113 of the eleventh transistor is provided separately. The first electrode 113 of the eleventh transistor is connected to the control electrode of the sixteenth transistor (which is also the control electrode of the seventeenth and eighteenth transistors) through a sixth via V6.

[0379] In an exemplary embodiment, the first electrode 133 of the thirteenth transistor and the first electrode 163 of the sixteenth transistor are integrally formed. The first electrode 133 of the thirteenth transistor (which is also the first electrode 163 of the sixteenth transistor) is connected to the connection electrode through a seventh via.

[0380] In an exemplary embodiment, the first electrode 153 of the fifteenth transistor and the first electrode 183 of the eighteenth transistor are an integral structure.

[0381] In an exemplary embodiment, the second terminal 154 of the fifteenth transistor and the second terminal 184 of the eighteenth transistor are integrally formed. The second terminal of the fifteenth transistor (which is also the second terminal of the eighteenth transistor) is connected to the first fourth power line through an eighth via.

[0382] In an exemplary embodiment, the first connecting portion CL1 is provided separately and is rectangular in shape. The first connecting portion CL1 is electrically connected to the control electrode of the second transistor (which is also the control electrode of the third transistor and the first electrode plate) through a second via.

[0383] (5) Forming a first planarization layer pattern. In an exemplary embodiment, forming a first planarization layer pattern may include: depositing a second insulating film on a substrate on which the aforementioned pattern has been formed, then coating a first planarization film, and patterning the second insulating film and the first planarization film by a patterning process to form a second insulating layer covering the aforementioned structure and a first planarization layer pattern disposed on the second insulating layer. The first planarization layer pattern has a plurality of via patterns, as shown in FIG26, FIG26 being a schematic diagram of FIG4 after the formation of the first planarization layer pattern.

[0384] In an exemplary embodiment, as shown in FIG26, the first planarization layer pattern may include at least an eleventh via V11 and a twelfth via V12 located in at least one level shift register.

[0385] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate lies within the range of the orthographic projection of the second electrode plate (which is also the second electrode of the third transistor, the first electrode of the sixth transistor, and the cascaded signal line) onto the substrate. The second insulating layer within the eleventh via V11 is etched away, exposing the surface of the second electrode plate (which is also the second electrode of the third transistor, the first electrode of the sixth transistor, and the cascaded signal line). The eleventh via V11 is configured to allow a subsequently formed second connection portion to connect to the second electrode plate (which is also the second electrode of the third transistor, the first electrode of the sixth transistor, and the cascaded signal line) through the via.

[0386] In an exemplary embodiment, the orthographic projection of the twelfth via V12 onto the substrate lies within the range of the orthographic projection of the first connection portion onto the substrate. The second insulating layer within the twelfth via V12 is etched away, exposing the surface of the first connection portion. The twelfth via V12 is configured such that a subsequently formed third electrode plate is connected to the first connection portion through this via.

[0387] (6) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the first planarization layer pattern, as shown in Figures 27 and 28. Figure 27 is a schematic diagram of the third conductive layer pattern in Figure 4, and Figure 28 is a schematic diagram of Figure 4 after the third conductive layer pattern has been formed.

[0388] In an exemplary embodiment, as shown in Figures 27 and 28, the third conductive layer pattern may include at least: a second connection portion CL2 located on the third plate C3 of at least one level shift register and a first electrode located on at least one sub-pixel.

[0389] In an exemplary embodiment, the main body of the third electrode C3 is rectangular in shape, and the third electrode C3 is connected to the first connecting portion through the twelfth through hole. The third electrode is connected to the first electrode through the first connecting portion, serving as the first electrode of the capacitor.

[0390] In an exemplary embodiment, the second connecting part CL2 is rectangular in shape and is connected to the second electrode plate through the eleventh through hole, serving as the second electrode plate of the capacitor.

[0391] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: coating a second planar thin film on a substrate on which the aforementioned pattern is formed, then depositing a fourth conductive thin film, and patterning the fourth conductive thin film using a patterning process to form a second planar layer covering the aforementioned structure and a fourth conductive layer pattern disposed on the second planar layer.

[0392] In an exemplary embodiment, the fourth conductive layer pattern may include at least a first electrode located at at least one sub-pixel.

[0393] The display substrate provided in the embodiments of this disclosure will be further described below with reference to the display substrate shown in FIG6.

[0394] The first conductive layer, semiconductor layer and second conductive layer in the display substrate shown in Figure 6 are the same as the first conductive layer, semiconductor layer and second conductive layer in the display substrate shown in Figure 5, and will not be described again in this disclosure.

[0395] (1) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: depositing a second insulating film on a substrate on which the aforementioned pattern has been formed, coating a first planarization film, patterning the second insulating film and the first planarization film using a patterning process to form a second insulating layer covering the aforementioned structure and a first planarization layer disposed on the second insulating layer, depositing a third conductive film on the first planarization layer, and patterning the third conductive film using a patterning process to form a third conductive layer pattern disposed on the pattern of the first planarization layer. FIG29 is a schematic diagram of the third conductive layer pattern in FIG5, and FIG30 is a schematic diagram of the formation of the third conductive layer pattern in FIG5.

[0396] In an exemplary embodiment, as shown in Figures 29 and 30, the third conductive layer pattern may include at least: a third electrode C3 located in at least one level shift register and a first electrode located in at least one sub-pixel.

[0397] In an exemplary embodiment, the main body of the third electrode plate C3 is rectangular in shape, and the orthographic projection of the third electrode plate C3 on the substrate at least partially overlaps with the orthographic projections of the second electrode plate and the first connecting portion on the substrate.

[0398] (2) Forming a second planarization layer pattern. In an exemplary embodiment, forming a second planarization layer pattern may include: coating a second planarization film on a substrate on which the aforementioned pattern has been formed, and patterning the second planarization film using a patterning process to form a second planarization layer pattern covering the aforementioned structure. The second planarization layer pattern has multiple via patterns, as shown in FIG31, which is a schematic diagram of FIG5 after the second planarization layer pattern has been formed.

[0399] In an exemplary embodiment, the plurality of vias in the second planarization layer pattern include: an eleventh via V11, a twelfth via V12, and a thirteenth via V13.

[0400] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate lies within the range of the orthographic projection of the second electrode plate (which is also the second electrode of the third transistor, the first electrode of the sixth transistor, and the cascaded signal line) onto the substrate. The second insulating layer and the first planarization layer within the eleventh via V11 are etched away, exposing the surface of the second electrode plate (which is also the second electrode of the third transistor, the first electrode of the sixth transistor, and the cascaded signal line). The eleventh via V11 is configured such that the subsequently formed second connection portion is connected to the second electrode plate (which is also the second electrode of the third transistor, the first electrode of the sixth transistor, and the cascaded signal line).

[0401] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is within the range of the orthographic projection of the first connection portion on the substrate. The second insulating layer and the first planarization layer within the twelfth via V12 are etched away, exposing the surface of the first connection portion. The twelfth via V12 is configured such that the subsequently formed fourth electrode plate is connected to the first connection portion.

[0402] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 onto the substrate lies within the range of the orthographic projection of the third electrode plate onto the substrate, and the thirteenth via V13 exposes the surface of the third electrode plate. The thirteenth via V13 is configured to connect a subsequently formed second connection portion to the third electrode plate.

[0403] (3) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the second planarization layer pattern, as shown in Figures 32 and 33. Figure 32 is a schematic diagram of the fourth conductive layer pattern in Figure 5, and Figure 33 is a schematic diagram of Figure 5 after the fourth conductive layer pattern has been formed.

[0404] In an exemplary embodiment, as shown in Figures 32 and 33, the fourth conductive layer pattern may include at least: a fourth electrode C4 located in at least one level shift register and a second connection portion CL2, and a second electrode located in at least one sub-pixel.

[0405] In an exemplary embodiment, the main body of the fourth electrode C4 is rectangular in shape, and the fourth electrode C4 is connected to the first connecting portion through the twelfth through hole. The fourth electrode is connected to the first electrode through the first connecting portion, serving as the first electrode of the capacitor.

[0406] In an exemplary embodiment, the second connecting part CL2 is rectangular in shape. The second connecting part CL2 is connected to the second electrode plate through the eleventh through hole and to the third electrode plate through the thirteenth through hole. The second electrode plate is connected to the second electrode plate, which serves as a capacitor, through the third electrode plate and the second connecting part.

[0407] The first conductive layer, semiconductor layer and second conductive layer in the display substrate shown in Figure 7 are the same as the first conductive layer, semiconductor layer and second conductive layer in the display substrate shown in Figure 5, and will not be described again in this disclosure.

[0408] (1) Forming a third insulating layer pattern. In an exemplary embodiment, forming a third insulating layer pattern may include: depositing a third insulating film on a substrate on which the aforementioned pattern has been formed, and patterning the third insulating film using a patterning process to form a third insulating layer pattern covering the aforementioned structure. As shown in FIG34, FIG34 is a schematic diagram of FIG6 after the third insulating layer pattern has been formed.

[0409] In an exemplary embodiment, as shown in FIG34, the third insulating layer pattern may include at least an eleventh via V11.

[0410] In an exemplary embodiment, the orthographic projection of the eleventh via V11 on the substrate is within the range of the orthographic projection of the first connection portion on the substrate. The eleventh via V11 exposes the surface of the first connection portion. The eleventh via V11 is configured to connect the subsequently formed third electrode plate to the first connection portion.

[0411] (2) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming a fifth conductive layer pattern may include: depositing a fifth conductive thin film on a substrate on which the aforementioned pattern has been formed, and patterning the fifth conductive thin film using a patterning process to form a fifth conductive layer pattern covering the aforementioned structure, as shown in Figures 35 and 36. Figure 35 is a schematic diagram of the fifth conductive layer pattern in Figure 6, and Figure 36 is a schematic diagram of the fifth conductive layer pattern after it has been formed in Figure 6.

[0412] In an exemplary embodiment, as shown in Figures 35 and 36, the fifth conductive layer pattern may include at least a third plate C3 located in at least one level shift register.

[0413] In an exemplary embodiment, the main body of the third electrode plate C3 is rectangular in shape, and the orthographic projection of the third electrode plate C3 on the substrate at least partially overlaps with the orthographic projections of the second electrode plate and the first connecting portion on the substrate. The third electrode plate C3 is connected to the first connecting portion through an eleventh through hole.

[0414] (3) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: depositing a second insulating film on a substrate on which the aforementioned pattern has been formed, coating a first planarization film, patterning the second insulating film and the first planarization film using a patterning process to form a second insulating layer covering the aforementioned structure and a first planarization layer disposed on the second insulating layer, depositing a third conductive film on the first planarization layer, and patterning the third conductive film using a patterning process to form a third conductive layer pattern disposed on the pattern of the first planarization layer. FIG37 is a schematic diagram of the third conductive layer pattern in FIG6, and FIG38 is a schematic diagram of the formation of the third conductive layer pattern in FIG6.

[0415] In an exemplary embodiment, as shown in Figures 37 and 38, the third conductive layer pattern may include at least a fourth electrode C4 located in at least one level shift register and a first electrode located in at least one sub-pixel.

[0416] In an exemplary embodiment, the main body of the fourth electrode plate C4 is rectangular in shape and similar in shape to the third electrode plate C3. The orthographic projection of the fourth electrode plate C4 onto the substrate at least partially overlaps with the orthographic projection of the third electrode plate onto the substrate.

[0417] (4) Forming a second planarization layer pattern. In an exemplary embodiment, forming a second planarization layer pattern may include: coating a second planarization film on a substrate on which the aforementioned pattern has been formed, and patterning the second planarization film using a patterning process to form a second planarization layer pattern covering the aforementioned structure. The second planarization layer pattern has multiple via patterns, as shown in FIG39, which is a schematic diagram of FIG6 after the second planarization layer pattern has been formed.

[0418] In an exemplary embodiment, the plurality of vias in the second planarization layer pattern include: a twelfth via V12, a thirteenth via V13, and a fourteenth via V14.

[0419] In an exemplary embodiment, the orthographic projection of the twelfth via V12 onto the substrate lies within the range of the orthographic projection of the second electrode plate (which is also the second electrode of the third transistor, the first electrode of the sixth transistor, and the cascaded signal line) onto the substrate. The second insulating layer, the first planarization layer, and the third insulating layer within the twelfth via V12 are etched away, exposing the surface of the second electrode plate (which is also the second electrode of the third transistor, the first electrode of the sixth transistor, and the cascaded signal line). The twelfth via V12 is configured such that the subsequently formed second connection portion is connected to the second electrode plate (which is also the second electrode of the third transistor, the first electrode of the sixth transistor, and the cascaded signal line).

[0420] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the substrate is within the range of the orthographic projection of the first connection portion on the substrate. The third insulating layer, the second insulating layer, and the first planarization layer within the thirteenth via V13 are etched away, exposing the surface of the first connection portion. The thirteenth via V13 is configured to connect the subsequently formed fifth electrode plate to the first connection portion.

[0421] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is within the range of the orthographic projection of the fourth electrode plate on the substrate, the fourteenth via V14 exposes the surface of the fourth electrode plate, and the fourteenth via V14 is configured to connect the subsequently formed second connection portion to the fourth electrode plate.

[0422] (5) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the second planarization layer pattern, as shown in Figures 40 and 41. Figure 40 is a schematic diagram of the fourth conductive layer pattern in Figure 7, and Figure 41 is a schematic diagram of the fourth conductive layer pattern after it is formed in Figure 6.

[0423] In an exemplary embodiment, as shown in Figures 40 and 41, the fourth conductive layer pattern may include at least: a fifth electrode C5 located in at least one level shift register and a second connection portion CL2, as well as a second electrode located in at least one sub-pixel.

[0424] In an exemplary embodiment, the main body of the fifth electrode C5 is rectangular in shape, and the orthographic projection of the fifth electrode C5 onto the substrate at least partially overlaps with the orthographic projection of the fourth electrode onto the substrate. The fifth electrode C5 is connected to the first connecting portion through a thirteenth through-hole. The fifth electrode is connected to the first electrode and the third electrode respectively through the first connecting portion, serving as the first electrode of the capacitor.

[0425] In an exemplary embodiment, the second connecting part CL2 is rectangular in shape. The second connecting part CL2 is connected to the second electrode plate through the twelfth through hole and to the fourth electrode plate through the fourteenth through hole. The second electrode plate and the fourth electrode plate are connected through the second connecting part to serve as the second electrode plate of the capacitor.

[0426] At this point, the circuit structure layer on the substrate is complete. In a plane parallel to the display substrate, the circuit structure layer may include multiple shift registers. In a plane perpendicular to the display substrate, the circuit structure layer may be disposed on the substrate.

[0427] In an exemplary embodiment, the substrate can be a rigid substrate or a flexible substrate. The rigid substrate can be, but is not limited to, one or more of glass and metal sheets; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0428] In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The first and second flexible material layers may be made of materials such as polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films. The first and second inorganic material layers may be made of materials such as silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers. The semiconductor layer may be made of amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: firstly, coating a layer of polyimide on a glass substrate, curing it into a film to form a first flexible (PI1) layer; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating another layer of polyimide on the amorphous silicon layer, curing it into a film to form a second flexible (PI2) layer; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thus completing the substrate preparation.

[0429] In an exemplary embodiment, the semiconductor layer can be an amorphous silicon layer or a polycrystalline silicon layer, or it can be a metal oxide layer. The metal oxide layer can be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer can be a single layer, a double layer, or a multilayer.

[0430] In an exemplary embodiment, the first conductive layer, the second conductive layer, and the fifth conductive layer may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They may be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo.

[0431] In an exemplary embodiment, the third and fourth conductive layers may be made of transparent conductive materials, such as indium tin oxide or zinc tin oxide.

[0432] In an exemplary embodiment, the first insulating layer, the second insulating layer, and the third insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0433] This disclosure also provides a display device, which includes: the display substrate provided in any of the foregoing embodiments.

[0434] In an exemplary embodiment, the display device may further include: a cell substrate disposed in conjunction with the display substrate, and a liquid crystal layer disposed between the display substrate and the cell substrate.

[0435] In an exemplary embodiment, the substrate may include a second substrate and a black matrix layer and a filter layer disposed on the second substrate.

[0436] In an exemplary embodiment, the second substrate can be a rigid substrate or a flexible substrate. The rigid substrate can be, but is not limited to, one or more of glass and metal sheets; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. Exemplarily, the second substrate can be a glass substrate.

[0437] In an exemplary embodiment, the black matrix layer and the filter layer can be disposed on the same layer. The black matrix layer has vias, and the filter layer fills the vias in the black matrix layer.

[0438] In an exemplary embodiment, the orthographic projection of the black matrix layer on the second substrate and the orthographic projection of the filter layer on the second substrate may or may not overlap, and this disclosure does not limit this.

[0439] In one exemplary embodiment, the filter layer may include: multiple filters of different colors, with a filter disposed on a region corresponding to each pixel region on the color filter substrate.

[0440] In an exemplary embodiment, the filter may include a red filter, a green filter, and a blue filter.

[0441] In an exemplary embodiment, the display device may further include a backlight module located on the side of the display substrate away from the counter substrate, wherein the backlight module is configured to emit light toward the display substrate.

[0442] In an exemplary embodiment, the display device can be any product or component with display function, such as a liquid crystal display (LCD), electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0443] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0444] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0445] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising: A substrate having a display area and a non-display area surrounding at least one side of the display area, the non-display area including: a transistor device area, the transistor device area being provided with a gate driving circuit, the gate driving circuit including: a plurality of cascaded shift registers, at least one shift register including: a plurality of transistors and a fourth power supply terminal; At least two of the multiple cascaded shift registers are arranged at least partially symmetrically with respect to a straight line extending along a first direction, and the second direction is the arrangement direction of at least two of the multiple cascaded shift registers. The first direction and the second direction are located in the same plane and intersect. The display substrate further includes: two fourth power lines located in the transistor device area, the fourth power lines extending at least partially along the second direction; the fourth power lines are electrically connected to the fourth power terminal of at least one level shift register; The first fourth power line and its orthographic projection on the substrate are located between the orthographic projections of at least two transistors in at least one level shift register on the substrate, and the second fourth power line and its orthographic projection on the substrate are located on the side of the orthographic projections of multiple transistors in at least one level shift register closer to the display area.

2. The display substrate according to claim 1, further comprising: A first power connection line and a second power connection line located in the non-display area, wherein at least one of the first power connection line and the second power connection line extends at least partially along a first direction; The first power connection line is electrically connected to the first end of the first fourth power line and the first end of the second fourth power line, respectively. The second power connection line is electrically connected to the second end of the first fourth power line and the second end of the second fourth power line, respectively.

3. The display substrate according to claim 1, wherein, The at least one shift register includes: a sixth transistor, a fifteenth transistor, an eighteenth transistor, a second reset signal terminal, a drive signal output terminal, a first pull-down node, and a second pull-down node, wherein the control electrode of the sixth transistor is electrically connected to the second reset signal terminal, the first electrode of the sixth transistor is electrically connected to the drive signal output terminal, and the second electrode of the sixth transistor is electrically connected to the fourth power supply terminal; the control electrode of the fifteenth transistor is electrically connected to the first pull-down node, the first electrode of the fifteenth transistor is electrically connected to the drive signal output terminal, and the second electrode of the fifteenth transistor is electrically connected to the fourth power supply terminal; the control electrode of the eighteenth transistor is electrically connected to the second pull-down node, the first electrode of the eighteenth transistor is electrically connected to the drive signal output terminal, and the second electrode of the eighteenth transistor is electrically connected to the fourth power supply terminal. The orthographic projection of the sixth transistor on the substrate is located between the orthographic projection of the second fourth power line on the substrate and the orthographic projection of the first fourth power line on the substrate, and the distance between the orthographic projection of the sixth transistor on the substrate and the orthographic projection of the second fourth power line on the substrate is less than the distance between the orthographic projection of the sixth transistor on the substrate and the orthographic projection of the first fourth power line on the substrate. The orthographic projection of at least one of the fifteenth and eighteenth transistors on the substrate is located on the side of the first fourth power line away from the display area, and the distance between the orthographic projection of at least one of the fifteenth and eighteenth transistors on the substrate and the orthographic projection of the first fourth power line on the substrate is less than the distance between the orthographic projection of the sixth transistor on the substrate and the orthographic projection of the first fourth power line on the substrate.

4. The display substrate according to claim 3, wherein, The display area is further provided with a plurality of sub-pixels, at least one of the plurality of sub-pixels including: a first electrode and a second electrode, wherein the first electrode and the second electrode are transparent electrodes, and at least one of the plurality of transistors including: a control electrode, an active pattern, a first electrode and a second electrode; The display substrate further includes: a circuit structure layer disposed on the substrate; the circuit structure layer includes: a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially stacked on the substrate; The first conductive layer includes: a fourth power line and a control electrode of at least one transistor among a plurality of transistors located in at least one level shift register; The semiconductor layer includes: an active pattern of at least one transistor among a plurality of transistors located in at least one level shift register; The second conductive layer includes: a first terminal and a second terminal of at least one of a plurality of transistors located in at least one level shift register; The third conductive layer includes: one of the first electrode and the second electrode located in at least one sub-pixel; The fourth conductive layer includes another electrode located in the first electrode and the second electrode of at least one sub-pixel.

5. The display substrate according to claim 4, further comprising: The first power connection line and the second power connection line are located in the non-display area; At least one of the first power connection line and the second power connection line is located in the first conductive layer.

6. The display substrate according to claim 4, wherein, At least one of the multiple cascaded shift registers includes: a capacitor, a pull-up node, and a drive signal output terminal, wherein the first terminal of the capacitor is electrically connected to the pull-up node, and the second terminal of the capacitor is electrically connected to the drive signal output terminal. At least one of the multiple cascaded shift registers includes: a first plate, a second plate, and a third plate, wherein at least two of the first plate, the second plate, and the third plate are disposed in different layers, and the orthographic projections of the first plate, the second plate, and the third plate onto the substrate at least partially overlap. The first electrode plate is electrically connected to the third electrode plate and serves as the first electrode of the capacitor, while the second electrode plate serves as the second electrode of the capacitor.

7. The display substrate according to claim 6, wherein, At least one of the multiple cascaded shift registers further includes: a first connection part and a second connection part, wherein the first electrode plate and the third electrode plate are connected through the first connection part, and the second electrode plate is connected to the second connection part; The first electrode plate is located in the first conductive layer, the second electrode plate and the first connecting portion are located in the second conductive layer, and the third electrode plate and the second connecting portion are disposed in the same layer and are located in the third conductive layer or the fourth conductive layer.

8. The display substrate according to claim 4, wherein, At least one of the multiple cascaded shift registers includes: a capacitor, a pull-up node, and a drive signal output terminal, wherein the first terminal of the capacitor is electrically connected to the pull-up node, and the second terminal of the capacitor is electrically connected to the drive signal output terminal. At least one of the multiple cascaded shift registers includes: a first plate, a second plate, a third plate, and a fourth plate, wherein at least two of the first plate, the second plate, the third plate, and the fourth plate are arranged in different layers, and the orthographic projections of at least two of the first plate, the second plate, the third plate, and the fourth plate on the substrate at least partially overlap. The first electrode plate is electrically connected to the fourth electrode plate and serves as the first electrode of the capacitor. The second electrode plate is electrically connected to the third electrode plate and serves as the second electrode of the capacitor.

9. The display substrate according to claim 8, wherein, At least one of the multiple cascaded shift registers further includes: a first connection part and a second connection part, wherein the first electrode plate and the fourth electrode plate are connected through the first connection part, and the second electrode plate and the third electrode plate are connected through the second connection part; The first electrode plate is located in the first conductive layer, the second electrode plate and the first connecting portion are located in the second conductive layer, the third electrode plate is located in the third conductive layer, and the fourth electrode plate and the second connecting portion are located in the fourth conductive layer.

10. The display substrate according to claim 4, wherein, At least one of the multiple cascaded shift registers includes: a capacitor, a pull-up node, and a drive signal output terminal, wherein the first terminal of the capacitor is electrically connected to the pull-up node, and the second terminal of the capacitor is electrically connected to the drive signal output terminal. At least one of the multiple cascaded shift registers includes: a first plate, a second plate, a third plate, a fourth plate, and a fifth plate, wherein at least two of the first plate, the second plate, the third plate, the fourth plate, and the fifth plate are arranged in different layers, and the orthographic projections of at least two of the first plate, the second plate, the third plate, the fourth plate, and the fifth plate onto the substrate at least partially overlap; The first electrode plate is electrically connected to the third electrode plate and the fifth electrode plate respectively, and serves as the first electrode of the capacitor. The second electrode plate is electrically connected to the fourth electrode plate, and serves as the second electrode of the capacitor.

11. The display substrate according to claim 10, wherein, The circuit structure layer further includes: a fifth conductive layer, which is located between the semiconductor layer and the third conductive layer; The first electrode plate is located in the first conductive layer, the second electrode plate is located in the second conductive layer, the third electrode plate is located in the fifth conductive layer, the fourth electrode plate is located in the third conductive layer, and the fifth electrode plate is located in the fourth conductive layer.

12. The display substrate according to claim 1, further comprising: Multiple third power lines located in the transistor device region, at least one of the multiple third power lines extending at least partially along a first direction; The at least one shift register further includes: a fourth transistor, a fifth transistor, an eighth transistor, a ninth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a sixteenth transistor, a seventeenth transistor, and a third power supply terminal, wherein the second terminals of the fourth transistor, the fifth transistor, the eighth transistor, the ninth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the sixteenth transistor, and the seventeenth transistor are respectively electrically connected to the third power supply terminal; At least one third power supply line is electrically connected to the third power supply terminal in at least one shift register.

13. The display substrate according to claim 12, wherein, The plurality of cascaded shift registers include: a first shift register, a second shift register, and a third shift register, wherein the first shift register is at least one of the plurality of cascaded shift registers, the second shift register is a shift register of one adjacent level of the first shift register, and the third shift register is a shift register of another adjacent level of the first shift register; At least one third power line is located between the first shift register and the second shift register, and is electrically connected to the third power supply terminal of the first shift register and the third power supply terminal of the second shift register. The center line of the at least one third power line extending in the first direction is the same as the center line of the first shift register and the second shift register extending in the first direction. At least one third power line is integrally structured with the second terminals of the fourth, fifth, eighth, ninth, eleventh, twelfth, thirteenth, fourteenth, sixteenth, and seventeenth transistors in at least one of the first and second shift registers.

14. The display substrate according to claim 1, wherein, The at least one shift register further includes: a fifteenth transistor and an eighteenth transistor; the control electrode of the fourth transistor is electrically connected to the blanking reset signal terminal; the first electrode of the fourth transistor is electrically connected to the pull-up node; and the second electrode of the fourth transistor is electrically connected to the third power supply terminal; the control electrode of the fifth transistor is electrically connected to the first reset signal terminal; the first electrode of the fifth transistor is electrically connected to the pull-up node; and the second electrode of the fifth transistor is electrically connected to the third power supply terminal; the control electrode of the eighth transistor is electrically connected to the signal input terminal; the first electrode of the eighth transistor is electrically connected to the first pull-down node; and the second electrode of the eighth transistor is electrically connected to the third power supply terminal; the control electrode of the ninth transistor is electrically connected to the pull-up node; the first electrode of the ninth transistor is electrically connected to the first pull-down node; and the second electrode of the ninth transistor is electrically connected to the third power supply terminal; the control electrode of the eleventh transistor is electrically connected to the signal input terminal; the first electrode of the eleventh transistor is electrically connected to the second pull-down node; and the second electrode of the eleventh transistor is electrically connected to the third power supply terminal; the control electrode of the twelfth transistor is electrically connected to the pull-up node; the first electrode of the twelfth transistor is electrically connected to the second pull-down node; and the second electrode of the twelfth transistor is electrically connected to the third power supply terminal; Electrical connections: The control electrode of the thirteenth transistor is electrically connected to the first pull-down node; the first electrode of the thirteenth transistor is electrically connected to the pull-up node; the second electrode of the thirteenth transistor is electrically connected to the third power supply terminal; the control electrode of the fourteenth transistor is electrically connected to the first pull-down node; the first electrode of the fourteenth transistor is electrically connected to the cascaded signal output terminal; the second electrode of the fourteenth transistor is electrically connected to the third power supply terminal; the control electrode of the fifteenth transistor is electrically connected to the second pull-down node; the first electrode of the fifteenth transistor is electrically connected to the drive signal output terminal; the second electrode of the fifteenth transistor is electrically connected to the fourth power supply terminal; the control electrode of the sixteenth transistor is electrically connected to the second pull-down node; the first electrode of the sixteenth transistor is electrically connected to the pull-up node; the second electrode of the sixteenth transistor is electrically connected to the third power supply terminal; the control electrode of the seventeenth transistor is electrically connected to the second pull-down node; the first electrode of the seventeenth transistor is electrically connected to the cascaded signal output terminal; the second electrode of the seventeenth transistor is electrically connected to the third power supply terminal; the control electrode of the eighteenth transistor is electrically connected to the second pull-down node; the first electrode of the eighteenth transistor is electrically connected to the drive signal output terminal; the second electrode of the eighteenth transistor is electrically connected to the third power supply terminal. The fourth transistor, the ninth transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the fifteenth transistor, and the eighth transistor are arranged sequentially along the first direction; The eighth and eleventh transistors are arranged along the second direction, the thirteenth and sixteenth transistors are arranged along the second direction, the fourteenth and seventeenth transistors are arranged along the second direction, and the fifteenth and eighteenth transistors are arranged along the second direction.

15. The display substrate according to claim 14, wherein, The control electrode of the ninth transistor and the control electrode of the twelfth transistor are the same electrode, and the active pattern of the ninth transistor and the active pattern of the twelfth transistor are the same active pattern. The ninth transistor has two electrodes, and the twelfth transistor has two electrodes. The electrodes of the ninth and twelfth transistors are arranged along the first direction, and one of the electrodes of the ninth transistor and one of the electrodes of the twelfth transistor are the same electrode. The first terminal of the ninth transistor is located between the second terminals of the two ninth transistors, and the first terminal of the twelfth transistor is located between the second terminals of the two twelfth transistors; The second terminals of the ninth transistor and the twelfth transistor of at least one shift register are each connected to at least one third power supply line.

16. The display substrate according to claim 14, wherein, The control electrode of the eighth transistor and the control electrode of the eleventh transistor are the same electrode, and the active pattern of the eighth transistor and the active pattern of the eleventh transistor are the same active pattern. The second electrode of the eighth transistor is the same as the second electrode of the eleventh transistor.

17. The display substrate according to claim 14, wherein, The control electrodes of the thirteenth transistor, the fourteenth transistor, and the fifteenth transistor are on the same electrode; The control electrodes of the sixteenth, seventeenth, and eighteenth transistors are on the same electrode.

18. The display substrate according to claim 1, wherein, The non-display area further includes: a first signal line area and a second signal line area, and at least one level of shift register includes: a clock signal terminal, a first power supply terminal and a second power supply terminal; The first signal line area is located on the side of the transistor device area away from the display area, and the second signal line area is located on the side of the transistor device area closer to the display area. The first signal line area includes: multiple clock signal lines, a first power line, and a second power line; at least one of the multiple clock signal lines, the first power line, and the second power line extends at least partially along the second direction; The clock signal terminal of the at least one level shift register is electrically connected to one of the multiple clock signal lines, the first power line is electrically connected to the first power supply terminal of the at least one level shift register, and the second power supply line is electrically connected to the second power supply terminal of the at least one level shift register. The second signal line area includes a common signal line group, which includes at least one common signal line that extends at least partially along the second direction.

19. The display substrate according to claim 18, wherein, The non-display area is also provided with multiple drive signal output lines located on the second conductive layer and multiple scan lines located on the first conductive layer. At least one of the multiple drive signal output lines is electrically connected to the drive signal output terminal of at least one level shift register and one of the multiple scan lines, respectively. The drive signal output line includes: a first output section, a second output section and a third output section, wherein the second output section is connected to the first output section and the third output section respectively, the first output section extends along a first direction, and the second output section and the third output section extend along a second direction, wherein the first output section and the second output section are arranged at right angles. The second output and the third output in the drive signal output line connected to at least one shift register are located on the side of the first output that is away from the first adjacent shift register; The orthographic projection of the first output unit on the substrate at least partially overlaps with the orthographic projection of the at least one common signal line on the substrate, the orthographic projection of the third output unit on the substrate at least partially overlaps with the orthographic projection of the scan line on the substrate, and the orthographic projection of the second output unit on the substrate does not overlap with the orthographic projection of the scan line on the substrate.

20. The display substrate according to claim 19, wherein, The plurality of cascaded shift registers include: a first shift register, a second shift register, and a third shift register, wherein the first shift register is at least one of the plurality of cascaded shift registers, the second shift register is a shift register of one adjacent level of the first shift register, and the third shift register is a shift register of another adjacent level of the first shift register; The scan line connected to the first shift register and the scan line connected to the second shift register are at least partially symmetrical with respect to an axis of symmetry extending along a first direction between the first shift register and the second shift register; The spacing between the scan line connected to the first shift register and the scan line connected to the second shift register is greater than the spacing between the scan line connected to the first shift register and the scan line connected to the third shift register, and is greater than the length of at least one shift register extending along the second direction; At least one of the multiple cascaded shift registers includes: a first transistor to the Mth transistor and a first capacitor to the Nth capacitor; The m-th transistor in the first shift register and the m-th transistor in the second shift register are symmetrically arranged with respect to the midline extending along the first direction of the first shift register and the second shift register, where m is any value from 1 to M. The nth capacitor in the first shift register and the nth capacitor in the second shift register are symmetrically arranged with respect to the midline extending along the first direction of the first shift register and the second shift register, where n is any value from 1 to N.

21. The display substrate according to claim 20, wherein, The display area is provided with sub-pixels arranged in an array; At least one row of sub-pixels is electrically connected to a first scan line and a second scan line, respectively. The first scan line connected to the at least one row of sub-pixels is located on the side of the at least one row of sub-pixels closer to the previous row of sub-pixels, and the second scan line connected to the at least one row of sub-pixels is located on the side of the at least one row of sub-pixels closer to the next row of sub-pixels. At least one row of subpixels is connected to the first scan line, which is electrically connected to the third shift register, and at least one row of subpixels is connected to the second scan line, which is electrically connected to the first shift register.

22. The display substrate according to claim 19, wherein, The distance between the third output section of the drive signal output line connected to at least one shift register and the common signal line group along the first direction is greater than 30 micrometers; The distance between the third output portion of the drive signal output line connected to at least one shift register and the third output portion of the drive signal output line connected to the first adjacent shift register along the second direction is greater than the distance between the third output portion of the drive signal output line connected to at least one shift register and the third output portion of the drive signal output line connected to the second adjacent shift register along the second direction, and the distance between the third output portion of the drive signal output line connected to at least one shift register and the third output portion of the drive signal output line connected to the second adjacent shift register along the second direction is greater than 5 micrometers; The length of the second output section of the drive signal output line connected to at least one shift register along the second direction is greater than 30 micrometers.

23. The display substrate according to claim 18, wherein, At least one common signal line includes: a first common connection portion and a plurality of spaced second common connection portions, wherein the first common connection portion and the second common connection portions extend along the second direction; The first common connection portion is located in the first conductive layer, and the second common connection portion is located in the second conductive layer; At least one of the multiple spaced second common connection portions has its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first common connection portion on the substrate, and is electrically connected to the first common connection portion.

24. The display substrate according to claim 4, further comprising: The initial signal line and multiple cascaded signal lines located in the transistor device area, at least one shift register includes: a first transistor, a fifth transistor, a signal input terminal and a first reset signal terminal, the control electrode and the first electrode of the first transistor are electrically connected to the signal input terminal, the second electrode of the first transistor is electrically connected to the pull-up node, the control electrode of the fifth transistor is electrically connected to the first reset signal terminal, the control electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the third power supply terminal; At least one of the initial signal line and the plurality of cascaded signal lines extends at least partially along the second direction and is located in the first conductive layer; At least one cascaded signal line is electrically connected to the signal input terminal of at least one shift register and the first reset signal terminal of at least one shift register, respectively; The orthographic projection of at least one of the initial signal lines and multiple cascaded signal lines on the substrate is located between the orthographic projection of the first transistor on the substrate and the orthographic projection of the fifth transistor on the substrate, and between the orthographic projection of the first fourth power line on the substrate and the orthographic projection of the second fourth power line on the substrate. The first electrode of the first transistor is electrically connected to the control electrode of the first transistor through a via.

25. The display substrate according to claim 4, further comprising: The transistor device region has multiple reset signal lines, and at least one shift register includes: a second reset signal terminal, and at least one reset signal line is electrically connected to the second reset signal terminal in the at least one shift register; At least one of the multiple reset signal lines extends at least partially along a second direction, and the reset signal line is located in a first conductive layer; At least one of the multiple reset signal lines has its orthographic projection on the substrate located between the orthographic projection of the sixth transistor on the substrate and the orthographic projection of the second fourth power supply line on the substrate.

26. The display substrate according to claim 1, wherein, At least one of the multiple cascaded shift registers includes: a first transistor, a signal input terminal, and a pull-up node, wherein the control electrode and the first electrode of the first transistor are electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the pull-up node. The active pattern of the first transistor includes: a plurality of first active portions and a second active portion, at least one of the plurality of first active portions and the second active portion extends along a second direction, and the plurality of first active portions are arranged along a first direction, and the second active portion is located on the side of at least one of the plurality of first active portions close to the display area. At least one of the plurality of first active portions has a length in the second direction that is greater than the length of the second active portion in the second direction; The aspect ratio of the channel region of at least one of the plurality of first active parts is in the range of 5 / 6 to 20 / 4, and the spacing between two adjacent active parts is in the range of 3 micrometers to 7 micrometers.

27. The display substrate according to claim 1, wherein, At least one of the multiple cascaded shift registers includes: a third transistor, a pull-up node, a clock signal terminal, and a drive signal output terminal. The control electrode of the third transistor is electrically connected to the pull-up node, the first electrode of the third transistor is electrically connected to the clock signal terminal, and the second electrode of the third transistor is electrically connected to the drive signal output terminal. The active pattern of the third transistor includes: a plurality of third active portions, at least one of the plurality of third active portions extending along a second direction, and the plurality of third active portions arranged along a first direction; The aspect ratio of the channel region of at least one of the plurality of third active parts is in the range of 5 / 6 to 20 / 4, and the spacing between two adjacent active parts is in the range of 3 micrometers to 7 micrometers.

28. A display device, comprising: The display substrate as described in any one of claims 1 to 27.

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