Method and apparatus for synchronizing a multi-phase converter

Abstract

An example apparatus (206A) for controlling a power stage circuit (204A) includes programmable circuitry configured to, in response to an instruction from an external controller (206B), generate a pulse in a first local clock signal (226A) that is generated when a flying capacitor in the power stage circuit has discharged for a discharge period that is less than a threshold amount of time, and generate a pulse in a second local clock signal (228A) after the flying capacitor has charged for a charge period, where a length of the charge period is based on a length of the discharge period.

Description

Technical Field

[0001] This specification generally relates to power converters, and more specifically, to methods and apparatus for synchronizing multiphase converters. Background Technology

[0002] Power management is a critical design component of all electronic devices. Generally, a power management circuit system refers to the hardware within an electronic device that converts a first amount of power received from a source into a second amount of power that can be consumed by the load within the device. The power source may include, but is not limited to, 120-volt AC (VAC) or 240-VAC outlets, batteries, generators, solar energy, etc. Typically, the power management circuit system can further convert the power from the first type (e.g., AC) to a second type (e.g., DC) usable by the load. Summary of the Invention

[0003] For methods and apparatus for synchronizing multiphase converters, one example apparatus includes: a programmable circuit system configured to: generate pulses in a first local clock signal in response to an instruction from an external controller, the pulses in the first local clock signal being generated when a flying capacitor in a power stage circuit has discharged for a discharge cycle of less than a threshold time; and generate pulses in a second local clock signal after the flying capacitor has been charged for a charging cycle, wherein the length of the charging cycle is based on the length of the discharge cycle. Attached Figure Description

[0004] Figure 1 This is an example of power delivery in a system containing a multiphase buck regulator circuit.

[0005] Figure 2 yes Figure 1 Example block diagram of a multiphase buck regulator circuit system.

[0006] Figure 3 yes Figure 2 Example block diagram of the local controller circuit system.

[0007] Figure 4 yes Figure 2 Example block diagram of a power stage circuit system.

[0008] Figure 5 It is by Figure 2 Example timing diagrams of signals generated by the local controller circuitry and power stage circuitry.

[0009] Figure 6 It contains by Figure 3 An example of a timing diagram of the signals generated by the ramp generator circuit system and the clock manager circuit system.

[0010] Figure 7 yes Figure 3 A first example block diagram of a clock manager circuit system.

[0011] Figure 8 yes Figure 3 The second example block diagram of the clock manager circuit system.

[0012] Figure 9 It is by Figure 7 and 8 Example timing diagram of signals generated by the clock manager circuit system.

[0013] Figure 10 It means that it can be used. Figure 2 The flowchart illustrates the example machine-readable instructions and / or example operations performed, instantiated, and / or executed in an example programmable circuit system implementation of the local controller circuit.

[0014] Figure 11 It means that it can be used. Figure 3 The flowchart illustrates the example programmable circuit system implementation of the clock manager circuit system, including example machine-readable instructions and / or example operations performed, instantiated, and / or executed.

[0015] Figure 12 This is a block diagram of an example processing platform containing a programmable circuit system configured to perform, instantiate, and / or execute example machine-readable instructions and / or perform... Figure 10 and 11 Example operations to implement Figure 2 The local controller circuit system 206A and / or more generally the controller circuit system 202.

[0016] The same reference numerals or other reference indicators are used in the accompanying drawings to indicate (functionally and / or structurally) the same or similar features. Detailed Implementation

[0017] The accompanying drawings are not necessarily drawn to scale. Generally, the same reference numerals in the drawings and this specification refer to the same or similar parts. Although the drawings show areas with clearly defined lines and boundaries, some or all of these lines and / or boundaries may be idealized. In reality, the boundaries and / or lines may be unobservable, mixed, and / or irregular.

[0018] Figure 1 This is an example of power delivery in a system containing a multiphase buck regulator circuit. Figure 1 It includes a power supply 102, an AC power supply unit 104, a DC power supply unit 106, a multiphase step-down regulator circuit system 108, and a load 110.

[0019] Power supply 102 provides AC power. Power supply 102 can be implemented by any device that provides AC electrical energy. For example, in Figure 1 In the example, power supply 102 is implemented by a 120 VAC socket.

[0020] AC power supply unit 104 converts 120 VAC into different AC signals, which can be operated by DC power supply unit 106. In particular, AC power supply unit 104 can change one or more of the following, such as voltage, frequency, signal shape, number of phases, etc., depending on the type of power supply 102 and the requirements of DC power supply unit 106.

[0021] DC power supply unit 106 converts the AC signal received from AC power supply unit 104 into a DC signal. DC power supply unit 106 includes a rectifier circuit system and a filter circuit system for converting the AC signal into a DC signal. DC power supply unit 106 is configured to provide a DC signal at a voltage operable by multiphase buck regulator circuit system 108. In some examples, DC power supply unit 106 is referred to as a voltage source.

[0022] As described below, the example multiphase buck regulator circuit system 108 is a voltage regulator circuit that, according to the teachings of this disclosure, converts a first DC voltage provided by the example DC power supply unit 106 into a second DC voltage usable by the load 110. The example multiphase buck regulator circuit system 108 is combined with... Figure 2 Further discussion.

[0023] exist Figure 1 In this example, load 110 is a processor circuit system that performs operations using power from a second DC voltage. In other examples, the load receiving the second DC voltage is another form of circuit system, including, but not limited to, transceivers, volatile memory, etc. The example processor circuit system of load 110 can be implemented by any type of programmable circuit system. Examples of programmable circuit systems include, but are not limited to, programmable microprocessors, field-programmable gate arrays (FPGAs) that can instantiate instructions, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), XPUs, or microcontrollers and integrated circuits, such as application-specific integrated circuits (ASICs).

[0024] Figure 2 yes Figure 1 Example block diagram of a voltage regulator circuit system. Figure 1The example multiphase buck regulator circuit system 108 includes an example controller circuit system 202, which includes an example bus 205 and example local controller circuit systems 206A, 206, 206C, and 206D (collectively referred to as local controller circuit 206). The example multiphase buck regulator circuit system 108 also includes example power stage circuit systems 204A, 204B, 204C, and 204D (collectively referred to as power stage circuit 204), example pulse width modulation (PWM) signals 226A, 226B, 226C, and 226D (collectively referred to as PWM signal 226), example PWM signals 228A, 228B, 228C, and 228D (collectively referred to as PWM signal 228), example flying voltage (V_FLY) signals 212A, 212B, 212C, and 212D (collectively referred to as V_FLY signal 212), and an example output capacitor 214. The flying voltage refers to the voltage across the flying capacitor, as will be discussed further below.

[0025] Power stage circuit 204 delivers power to load 110 based on pulses from local controller circuit 206. Given that power stage circuit 204A receives a constant input voltage from example DC power supply unit 106 and two PWM signals 226A and 228A from the corresponding local controller circuit 206A, both PWM signals 226A and 228A are used to change the current and / or voltage of the output voltage (VOUT) signal supplied to load 110.

[0026] To perform voltage and current transformation, the example power stage circuit 204 may include an inductor and one or more switches rated for high power. In the example described herein, the given power stage circuit 204A is a three-level buck converter circuit with a flying capacitor. The flying capacitor is explained below. More generally, the power stage circuit 204 can be implemented as any type of multilevel buck converter with a flying capacitor. In other examples, the power stage circuit 204 may be implemented with another buck converter architecture that does not include a flying capacitor.

[0027] The flying capacitor within power stage circuit 204 stores varying amounts of energy throughout the operating cycle and helps provide the desired voltage to load 110. Specifically, power stage circuit 204A provides the voltage across the flying capacitor in the V_FLY signal 212A. Local controller circuitry system 206A adjusts the timing of pulses within PWM signals 226A and / or 228A, based in part on the V_FLY signal 212A and in accordance with the teachings described herein. In some examples, the power stage circuitry may be referred to as a phase converter circuit.

[0028] Although for the sake of simplicity, Figure 2Four power stage circuits 204 are shown, but in practice, the multiphase buck regulator circuit system 108 can contain any number of power stage circuits. In some examples, the power stage circuits 204 are referred to as phase circuits. The power stage circuits 204 are combined with... Figure 4 Further discussion.

[0029] The controller circuitry 202 coordinates the operation of the power stage circuitry 204, as described herein. The controller circuitry 202 can be implemented by any type of programmable circuitry. In some examples, the controller circuitry 202 includes additional components besides the bus 205 and the local controller circuitry 206.

[0030] Within the example controller circuit system 202, bus 205 refers to one or more physical connections (e.g., interconnects, copper traces, etc.) that enable communication between local controller circuits 206. Bus 205 can be implemented using one or more communication systems that meet predetermined threshold power and delay requirements.

[0031] Within the example controller circuitry 202, local control circuitry 206 transmits PWM signals 226A and 228A to the corresponding power stage circuitry 204. For example, local controller circuitry 206A transmits PWM signals 226A and 228A to power stage circuitry 204A, local controller circuitry 206B transmits PWM signals 226B and 228B to power stage circuitry 204B, and so on. The two sets of PWM signals 226 and 228 contain pulses that, when received by one of the power stage circuits 204, temporarily increase the current in that power stage circuit and provide power to load 110 via the VOUT signal.

[0032] In some examples, one or more of the local controller circuits 206 can adjust the voltage and / or current of the VOUT signal based on the type of load 110. For example, suppose... Figure 1 One or more components of the local controller circuit 206 are implemented within the laptop computer. Compared to when the laptop computer is in sleep mode (e.g., the lid is closed and several applications are closed or idle), the one or more components of the local controller circuit 206 can enable the corresponding power stage circuit 204 to provide more power in the VOUT signal when the laptop computer is in an active state (e.g., the lid is open and several applications are running). The local controller circuit 206 can be implemented by any type of programmable circuit system.

[0033] Power stage circuits 204 can exhibit errors independently of each other in the sense that, at any given time, the amount of error in the output of power stage circuit system 204A can be different from and uncorrelated with the amount of error in the output of power stage circuit system 204B. However, in many examples, specific performance metrics of load 110 require power stage circuits 204 to provide coordinated outputs so that the VOUT signal is sufficiently timely and accurate.

[0034] Advantageously, the local controller circuits 206 communicate with each other to send PWM pulses according to the teachings described herein, such that a given local controller circuit system 206A transmits: a) a PWM signal globally synchronized with other local controllers, and b) a PWM signal not globally synchronized. In the example described herein where the power stage circuit 204 is a three-level buck converter, PWM signals 226A and 228B are globally synchronized with each other to meet the performance requirements of load 110, while PWM signals 226B and 228A enable the correction of errors in the individual flying capacitors within the power stage circuits 204A and 204B. More generally, the teachings described herein enable each local controller 206 to transmit the non-globally synchronized PWM signal in an architecture specific to the corresponding power stage circuit. This capability allows the multiphase buck regulator circuit system 108 to be implemented with a more efficient and cost-effective PCB design than previous solutions.

[0035] Figure 3 yes Figure 2 An example block diagram of the local controller circuit system 206A is provided. The local controller circuit system 206A includes an example ramp generator circuit system 302A, an example clock manager circuit system 304A, an example PWM generator circuit system 320A, example ramp signals 306A and 308A, and example clock signals 316A and 318A. Figure 3 The local controller circuit system 206A can be instantiated (e.g., created, made to exist for any length of time, materialized, implemented, etc.) by a programmable circuit system such as a central processing unit (CPU) that executes the first instruction. Alternatively, Figure 3 The local controller circuit system 206A can be instantiated (e.g., instantiated, materialized, implemented, etc.) by constructing and / or configuring an (i) application-specific integrated circuit (ASIC) or (ii) field-programmable gate array (FPGA) to perform operations corresponding to the first instruction in response to the execution of the second instruction. It should be understood that... Figure 3 Some or all of the circuit system can therefore be instantiated at the same or different times. Figure 3Some or all of the circuitry can be instantiated, for example, in one or more threads that execute concurrently on hardware and / or serially on hardware. Furthermore, in some examples, Figure 3 Some or all of the circuitry in the system can be implemented by a microprocessor circuitry that executes instructions and / or an FPGA circuitry that performs operations to implement one or more virtual machines and / or containers.

[0036] Figure 3 It also includes local controller circuits 206B, 206C, and 206D, each containing a local instance of the aforementioned components. Specifically, local controller circuit system 206B includes example ramp generator circuit system 302B, example clock manager circuit system 304B, example ramp signals 306B and 308B, example clock signals 316B and 318B, etc. Furthermore, the components within local controller circuits 206B, 206C, and 206D can be operated according to the description herein and the teachings discussed below with reference to local controller circuit system 206A.

[0037] Example ramp generator circuit system 302A generates ramp signals 306A and 308A for clock manager circuit system 304A to generate clock signals 316A and 318A. Ramp generator circuit system 302A generates ramp signals 306A and 308A, where the slope of the ramp signals is modulated based on V_FLY signal 212A. Therefore, the voltage within the ramp signals is based on an error present within power stage circuit system 204A. Ramp generator circuit system 302A combines... Figure 5 and 6 Further discussion. In some examples, the ramp generator circuit system 302A is configured to execute ramp generator instructions and / or perform, for example, by... Figure 10 and 11 The flowchart represents the operation of a programmable circuit system to be instantiated.

[0038] Clock manager circuitry 304A generates pulses (e.g., high-voltage cycles) within clock signals 316A and 318A based on ramp signals 306A and 308A, respectively. Clock manager circuitry 304A within local controller circuitry 206A is also connected via bus 205 to other local controller circuits 206B, 206C, and 206D. In some examples, clock manager circuitry 304A transmits pulses in clock signals 316A and / or 318A based on instructions from one of the other local controller circuits 206. In other examples, clock manager circuitry 304A may send instructions to one or more of the other local controller circuits 206 (e.g., local controller circuitry 206B) causing the other local controller circuitry 206B to transmit pulses in clock signals 316B and / or 318B. The transmission and / or reception of instructions by clock manager circuitry 304A can generally be referred to as synchronization between local controller circuits 206. By synchronizing with other local controller circuits 206 and monitoring the ramp signal, the clock manager circuit system 304A increases the accuracy of the V_OUT signal while correcting errors within the power stage circuit system 204A. The clock manager circuit system 304A combines... Figure 7-11 Further discussion. In some examples, the clock manager circuitry 304A executes clock manager instructions and / or is configured to perform, for example, by... Figure 10 and 11 The flowchart represents the operation of a programmable circuit system to be instantiated. As used above and here, high voltage can refer to a voltage that is interpreted as logic '1', and low voltage can refer to a voltage that is interpreted as logic '0'.

[0039] The PWM generator circuit system 320A generates pulses in PWM signals 226A and 228A based on pulses in clock signals 316A and 318A, respectively. As used above and here, a pulse refers to a rectangular waveform in which a signal transitions from a low voltage to a high voltage, remains at the high voltage for one time period (which defines the pulse width), and returns to the low voltage. In the example described herein, the pulses in clock signals 316A and 318A have fixed widths. When a pulse in clock signal 316A is generated, it causes the output of the PWM generator circuit system 320A to be compared with the ramp signal 306A to generate the pulse in PWM signal 226A. It is worth noting that the pulse widths in PWM signals 226A and 228A determine the length of operation of power stage circuit system 204A in a given phase, as combined with... Figure 4Further discussion. Therefore, the PWM generator circuit system 320A can modulate (e.g., expand or contract) the width of any pulse in the PWM signals 226A and 228A to achieve desired characteristics within the power stage circuit system 204A. In some examples, the PWM generator circuit system 320A is configured to execute PWM generator instructions and / or perform, for example, actions initiated by... Figure 10 and 11 The flowchart represents the operation of a programmable circuit system to be instantiated.

[0040] Figure 4 yes Figure 2 An example block diagram of the power stage circuit system 204A is provided. The power stage circuit system 204A includes example transistors 402A, 402B, 402C, and 402D (collectively referred to as transistor 402), an example flying capacitor 404 (which may be referred to herein as C_FLY 404), an example switching node 406, and an example inductor 408. Additionally, the voltage supplied by the DC power supply unit 106 may be referred to as V_IN, the voltage at the switching node 406 may be referred to as V_SW, and the voltage across C_FLY 404 may be referred to as the V_FLY signal 212A.

[0041] Transistor 402A includes a first power terminal (e.g., drain) configured to receive V_IN via DC power supply unit 106, a control terminal (e.g., gate) configured to receive PWM signal 226A, and a second power terminal (e.g., source) connected to the positive terminal of C_FLY 404. In the example described herein, transistor 402A is implemented as an n-channel metal-oxide-semiconductor (NMOS) transistor. In other examples, transistor 402A may be implemented as a p-channel MOS (PMOS) transistor, a bipolar junction transistor (BJT), or another transistor architecture.

[0042] Transistor 402B includes a first power terminal (e.g., drain) connected to the positive terminal of C_FLY 404 and the second power terminal of transistor 402A, a control terminal (e.g., gate) also configured to receive the PWM signal 228A, and a second power terminal (e.g., source) connected to the switching node 406. In the example described herein, transistor 402B is implemented as an n-channel metal-oxide-semiconductor (NMOS) transistor. In other examples, transistor 402A may be implemented as a p-channel MOS (PMOS) transistor, a bipolar junction transistor (BJT), or another transistor architecture.

[0043] Transistor 402C includes a first power terminal (e.g., drain) connected to switching node 406, a control terminal (e.g., gate) configured to receive a complementary signal to PWM signal 228A, and a second power terminal (e.g., source) connected to the negative terminal of C_FLY 404. In the example described herein, transistor 402C is implemented as an n-channel metal-oxide-semiconductor (NMOS) transistor. In other examples, transistor 402C may be implemented as a p-channel MOS (PMOS) transistor, a bipolar junction transistor (BJT), or another transistor architecture.

[0044] Transistor 402D includes a first power terminal (e.g., drain) connected to the negative terminal of C_FLY 404 and the second power terminal of transistor 402C, a control terminal (e.g., gate) also configured to receive a complementary signal to the PWM signal 226A, and a second power terminal (e.g., source) grounded. In the example described herein, transistor 402D is implemented as an n-channel metal-oxide-semiconductor (NMOS) transistor. In other examples, transistor 402A may be implemented as a p-channel MOS (PMOS) transistor, a bipolar junction transistor (BJT), or another transistor architecture.

[0045] Some buck converter architectures operate at two voltage levels by either: a) enabling the high-side power transistor so that V_SW is approximately equal to V_IN, or b) enabling the low-side power transistor so that V_SW is approximately equal to ground. Therefore, the switching nodes of such buck converter architectures alternate between V_IN and ground.

[0046] Example power stage circuit system 204A supports this voltage level by using transistor 402B as the high-side power transistor and transistor 402C as the low-side power transistor. Example power stage circuit system 204A also supports a third voltage level, where V_SW is approximately equal to (V_IN / 2). Therefore, in some examples, power stage circuit system 204A is referred to as a three-level buck converter.

[0047] In some examples, when the duty cycle of power stage circuitry 204A is greater than 50%, power stage circuitry 204A alternates between V_IN and (V_IN / 2). In other examples, when the duty cycle is less than 50%, power stage circuitry 204A alternates between (V_IN / 2) and ground. This configurability of V_SW allows power stage circuitry 204A to support a wider range of power requirements from load 110 with lower output current ripple and higher power density than buck converters that only support two voltage levels at V_SW.

[0048] To support the operation phase where V_SW≈(V_IN / 2), power stage circuitry 204A includes transistors 402B, 402D, and C_FLY 404. For example, suppose power stage circuitry 204A operates in an environment where V_SW will alternate between (V_IN / 2) and ground. To achieve this characteristic in power stage circuitry 204A, local controller circuitry 206A disables transistors 402A and 402C and enables transistors 402B and 402D during the first phase. Additionally, C_FLY 404 is connected to switching node 406 during the first phase. Therefore, C_FLY 404 discharges into switching node 406 (thus establishing V_SW = V_FLY≈(V_IN / 2)). The voltage at switching node 406 also energizes inductor 408 and increases the current supplied to load 110.

[0049] As used above and here, one of the enabling transistors 402 may refer to providing a high voltage in the appropriate PWM signal 226A or 228A, thereby providing a high voltage to the control terminal and allowing current to flow through the transistor. Because the PWM signals 226A and 228A are transmitted as pulses, the pulse width determines the length of time the transistor is enabled (and thus the length of time the power stage circuit system 204A operates in a given phase).

[0050] Once the current flowing through inductor 408 reaches the first threshold ampere, the local controller circuitry 206A transitions to the second stage by disabling transistor 402B and enabling transistor 402C. Therefore, during the second stage, transistors 402A and 402B are disabled, and transistors 402C and 402D are enabled. Additionally, during the second stage, switching node 406 is grounded (e.g., V_SW ≈ 0 V), C_FLY 404 is disconnected, inductor 408 is de-energized, and the current supplied to load 110 decreases.

[0051] After the current flowing through inductor 408 decreases to the second threshold ampere, the local controller circuitry 206A enables transistors 402A and 402C and disables transistors 402B and 402D in the third stage. In this third stage, the current from V_IN charges C_FLY 404, energizes inductor 408, and is supplied to load 110. In the first stage, the voltage at V_SW = V_IN - V_FLY ≈ (V_IN / 2).

[0052] After the current flowing through inductor 408 reaches the first threshold ampere again, the local controller circuit system 206A transitions to the fourth stage. The fourth stage is functionally equivalent to the second stage as described above. That is, transistors 402A and 402B are disabled, transistors 402C and 402D are enabled, switching node 406 is grounded (e.g., V_SW ≈ 0 V), and C_FLY 404 is disconnected. Therefore, inductor 408 is de-energized in preparation for another cycle.

[0053] As used above and here, a cycle can refer to a continuous time period during which the local controller circuitry 206A enables and disables transistor 402 to alternate the value of V_SW between two of the three supported voltage levels (e.g., V_IN, (V_IN / 2) and ground). In the example above, the cycle in which V_SW alternates between (V_IN / 2) and ground is implemented by the local controller circuitry 206A by discharging C_FLY 404 in a first phase, disconnecting C_FLY in a second phase, charging C_FLY 404 in a third phase, and then disconnecting C_FLY again in a fourth phase. In other examples, the local controller circuitry 206A enables and disables transistor 402 in a different order, and / or implements a cycle in which V_SW alternates between two different voltages (e.g., V_IN and (V_IN / 2)). In some examples, the phase that forms a cycle of the power stage circuitry 204A may be referred to as a period. In such examples, the first phase can be referred to as a discharge cycle, the second phase as a first disconnection cycle, the third phase as a charging cycle, and the fourth phase as a second disconnection cycle.

[0054] Ideally, the local controller circuitry 206A implements the example loop described above, such that any charge removed from C_FLY 404 during the first phase is subsequently added back to C_FLY 404 during the third phase. If there is a net difference in the amount of charge stored in C_FLY 404 after one cycle, the value of V_FLY will change over multiple cycles, and the accuracy of the output provided by the power stage circuitry 204A will decrease.

[0055] In some examples, the power stage circuitry 204A exhibits an error that results in a net difference in charge after one cycle. This type of error may be referred to herein as the V_FLY error, since the error causes V_FLY ≠ (V_IN / 2). Errors within the power stage circuitry 204A can occur for any reason, including but not limited to minor timing differences in the charging and discharging operating modes of the three-level converter.

[0056] U.S. Patent Application No. 15 / 858,626 describes a technique for controlling a power stage circuit system 204A such that the value of V_FLY remains equal to V_IN / 2 across multiple cycles, thereby correcting errors exhibited in the power stage circuit system 204A. U.S. Patent Application No. 15 / 858,626 is incorporated herein by reference in its entirety. In some examples, the technique described in No. 15 / 858,626 may be referred to as harmonic modulation. Harmonic modulation combined with... Figure 5 Further discussion.

[0057] Figure 5 It is by Figure 2 Example timing diagrams of the signals generated by the local controller circuit system 206A and the power stage circuit system 204A. Specifically, Figure 5 This demonstrates how the local controller circuit system 206A can use harmonic modulation techniques to correct the V_FLY error within the power stage circuit system 204A. Figure 5 Includes clock signals 316A, 318A and Figure 2 The pulse of the V_FLY signal 212A. Figure 5 It also includes an example reference voltage 501 (which may be referred to herein as V_REF 501) and example ramp signals 502, 504, 506 and 508.

[0058] Suppose an error occurs in power stage circuitry 204A such that V_FLY > (V_IN / 2) at the end of the cycle. In such an example, power stage circuitry 204A can attempt to implement the next cycle, where the charge on C_FLY404 is reduced net. The net charge reduction in subsequent cycles will offset the V_FLY error, thereby restoring V_FLY = (V_IN / 2) and increasing the accuracy of the output provided to the load.

[0059] Figure 5 The operation in the subsequent loop of the example above is shown (e.g., the net reduction of charge on C_FLY 404). That is, Figure 5 The timing diagram is divided into first, second, third, and fourth stages of the power stage circuit system 204A with pre-existing errors, such that V_FLY > (V_IN / 2). Therefore, the labels for the first, second, third, and fourth stages correspond to ramp signals 504 and 508 (which respectively show ramp signals 306A and 308A when the power stage circuit system 204A has a V_FLY error). During these stages, the power stage circuit system 204A is configured as described above. Figure 4The operation is described above. It is worth noting that the local controller circuit system 206A changes the state of transistor 402 so that the first stage (where C_FLY 404 discharges) is longer than the third stage (where C_FLY 404 charges) to achieve a net reduction in charge.

[0060] exist Figure 5 In this context, the change in the stage length, performed by the local controller circuit system 206A to correct the V_FLY error, is called δT. Therefore, the length of the first stage is (T3 - T1) = D. 180 (T_SW / 2 + δT), and the length of the third stage is (T6 - T5) = D0(T_SW / 2 - δT). As used above and here, D(T_SW / 2) refers to the length of the first stage, and the third stage does not have V_FLY error.

[0061] One cycle of the power stage circuit system 204A can be subdivided into two half-cycles, where the first and second stages constitute the first half-cycle, and the third and fourth stages constitute the second half-cycle. The local controller circuit system 206A strives to maintain the duty cycle of the first half-cycle (e.g., the length of the first stage divided by the length of the first half-cycle) equal to the duty cycle of the second half-cycle (e.g., the length of the third stage divided by the length of the second half-cycle).

[0062] To maintain equal duty cycles between the first and second half-cycles, the power stage circuitry 204A should operate such that the ratio between the lengths of the first and second stages is equal to the ratio between the lengths of the third and fourth stages. If the power stage circuitry 204A operates such that the duty cycle of the first half-cycle is not equal to that of the second half-cycle, then the inductor current in this half-cycle changes, and the efficiency of the power stage circuitry 204A decreases.

[0063] When implementing harmonic modulation techniques, the local controller circuitry 206A expands or contracts the two stages within a half-cycle to maintain the desired duty cycle. For example, in Figure 5In the first and second half-cycles, the duty cycle is 50% in the previous cycle without V_FLY error (as shown by ramp signals 502 and 506). In response to the occurrence of an error causing V_FLY > (V_IN / 2), the local controller circuitry 206A: a) increases the length of the first stage to extend the discharge cycle of C_FLY 404, and b) also increases the length of the second stage by δT(1-D) / D relative to the cycle without V_FLY error, such that the length of the first stage divided by the length of the first half-cycle remains at 50%. Similarly, in response to the decrease in the length of the third stage, the local controller circuitry 206A also decreases the length of the fourth stage by δT(1-D) / D relative to the cycle without V_FLY error. Although the length variations of the second and fourth stages do not affect the value of V_FLY (because C_FLY 404 is disconnected from switch node 406 during such cycles), the variations do maintain the duty cycle of the two half-cycles while allowing the half-cycles to have different lengths (thus correcting for the previously exhibited V_FLY error). In the example where the power requirements described by load 110 necessitate different duty cycles, the local controller circuitry 206A can vary the length of each stage by different amounts.

[0064] Generally, the ramp generator circuit system 302A uses the V_FLY signal 212A and a threshold (in...) Figure 5 The slope of ramp signals 306A and 308A is changed by V_REF 501 to implement harmonic modulation. In some examples, the value of V_REF 501 is set by current sources, resistors, and capacitors within or connected to the clock manager circuitry 304A.

[0065] Ramp signal 504 indicates that when ramp signal 306A reaches V_REF 501 at T5, clock manager circuitry 304A generates a pulse in clock signal 318A, thereby enabling and / or disabling one or more transistors 402, causing power stage circuitry 204A to operate in the third phase. Ramp signal 306A reaching a threshold also resets ramp signal 306A to a low voltage. Ramp signal 306A reaching the V_REF 501 threshold at T5 also causes clock manager circuitry 304A to begin monitoring ramp signal 308A, allowing a pulse to be generated later in clock signal 316A. Therefore, when ramp signal 508 (e.g., ramp signal 308A with error) reaches V_REF 501 at T7, clock manager circuitry 304A generates a pulse in clock signal 316A, thereby enabling and / or disabling one or more transistors 402, causing power stage circuitry 204A to operate in the first phase of subsequent cycles. When ramp signal 308A reaches V_REF 501, it also causes: a) ramp signal 306A to reset to a low voltage, and b) clock manager circuitry 304A to resume monitoring of ramp signal 306A.

[0066] exist Figure 5 In the example, ramp signals 502 and 506 represent how ramp signals 306A and 308A are generated without any V_FLY error, while ramp signals 504 and 508 represent how ramp signals 306A and 308A are generated in response to V_FLY > (V_IN / 2). Ramp signal 502 shows that without V_FLY error, at T4, ramp signal 306A will reach V_REF 501, generating a pulse in clock signal 318A, and the second half-cycle will begin. When V_FLY > (V_IN / 2), ramp signal 504 shows that ramp signal 306A is generated by ramp generator circuitry 302A, which has a shallower slope than its original slope (e.g., ramp signal 504 has a shallower slope than ramp signal 502). Therefore, the duration of the first half-cycle is longer than its duration without the V_FLY error, and the discharge of C_FLY 404 exceeds its discharge without the V_FLY error. Similarly, the ramp signal 508 is steeper than the ramp signal 506, causing the duration of the second half-cycle to be shorter than its duration without the V_FLY error, and the charging of C_FLY 404 to be less than its charging without the V_FLY error. Therefore, compared to when the error correction cycle begins at T1, when the error correction cycle ends... Figure 5The V_FLY signal 212A in the circuit is closer to (V_IN / 2) at T7. In some examples, the local controller circuitry 206A can implement multiple consecutive error correction cycles to proportionally decrease or increase the value of V_FLY over time.

[0067] Harmonic modulation enables the correction of V_FLY errors while maintaining a balanced duty cycle within the power controller circuitry 206A, as discussed above. However, the aforementioned techniques increase the total cycle length whenever a V_FLY error occurs. For example, for simplicity, using arbitrary values, assume that ramps 502 and 506 both have a slope of 1 volt per microsecond (V / μs), and V_REF501 = 1 V. Therefore, two half-cycles would take 1 microsecond to complete without V_FLY errors, and T8 – T2 (the total length of the error-free cycle) would equal 2.0 μs. Further assuming that to correct V_FLY > (V_IN / 2), the ramp generator circuitry 302A reduces the slope of ramp signal 504 to 0.5 V / μs and increases the slope of ramp signal 508 to 2 V / μs. In such an example, ramp signal 504 requires 2.0 µs to reach the threshold voltage of 1 V (therefore the first half-cycle lasts 2.0 µs), ramp signal 506 requires 0.5 µs to reach the threshold voltage (therefore the second half-cycle lasts 0.5 µs), and the total cycle length (e.g., the length of T7–T1) is 2.5 µs. More generally, V_FLY error correction using harmonic modulation alone can increase the total cycle length (compared to the length of the corresponding period in a cycle without the error), regardless of whether the error correction cycle net increases or decreases the charge application of C_FLY 404. Furthermore, because the amount of V_FLY error is specific to each power stage circuit 204A and can change between clock cycles, harmonic modulation techniques alone can cause any cycle to extend by any amount of time. Therefore, other buck converter circuits that enable harmonic modulation techniques cannot synchronize the outputs of multiple buck converters because the cycle length is unpredictable.

[0068] The example methods, apparatus, and systems described herein implement a local controller circuit that can both correct local V_FLY errors using harmonic modulation and synchronize with the outputs of multiple power stage circuits at a global level. That is, although the V_FLY error exhibited by any one of the power stage circuits 204A may differ in magnitude and be independent of the V_FLY errors of the other power stage circuits 204B, 204C, and 204D, the example local controller circuit system 206A can communicate with the other local controller circuits 206 such that the outputs of the power stage circuit system 204A all correct the V_FLY error and are synchronized with the outputs of the power stage circuits 204. To achieve this, the clock manager circuit system 304A in the local controller circuit system 206A communicates with instances of the other clock manager circuit systems 304A such that pulses in one of the clock signals (e.g., a synchronization pulse) occur globally at approximately the same time, while pulses in other clock signals (e.g., harmonic modulation pulses) are positioned based on the synchronization pulse to correct the local V_FLY error.

[0069] Figure 6 It contains by Figure 3 An example of a timing diagram of the signals generated by the ramp generator circuit system and the clock manager circuit system. Figure 6 Include Figure 3 The ramp signals are 306A, 308A, 306B, and 308B. Figure 3 Clock signals 316A, 318A, 316B, 318B and Figure 5 V_REF 501. Figure 6 It also includes example synchronization window signals 604A and 604B and independent of Figure 5 The timestamp of the timestamp (for example, it can refer to the timestamp of ... Figure 5 (Different timestamps).

[0070] Ramp signals 306A and 308A are generated by ramp generator circuit system 302A and describe the lengths of the first and second half-cycles of power stage circuit system 204A, respectively. Similarly, ramp signals 306B and 308B are generated by ramp generator circuit system 302B and describe the lengths of the first and second half-cycles of power stage circuit system 204B, respectively. Figure 6 The example describes a power stage circuit system 204A that does not have a V_FLY error, while the power stage circuit system 204B has a positive V_FLY error such that V_FLY > (V_IN / 2) time period.

[0071] If the local controller circuit systems 206A and 206B operate independently of each other, then when a suitable ramp signal reaches a threshold, the two controllers will cause their respective power stage circuits 204A and 204B to switch between half-cycles, the threshold being... Figure 6 This is referred to as V_REF 501. In the example described herein, V_REF 501 refers to the voltage approximately at the midpoint between the maximum and minimum voltages exhibited on ramp signals 306 and 308 (e.g., ...). Figure 6 (As shown). In some examples, the value of V_REF 501 is proportional to the value of V_IN provided by the DC power supply unit 106. Figure 6 In the example, local controller circuit systems 206A and 206B communicate with each other according to the teachings described herein. Therefore, one or more clock pulses can be triggered before the corresponding ramp signal passes through V_REF 501, as further discussed below.

[0072] When C_FLY 404 voltage does not have a power stage circuit system 204A in Figure 6 When the error present in the example occurs, the slopes of ramp signals 306A and 308A are equal. Furthermore, when ramp signal 308A reaches V_REF 501 at T2, ramp signal 306A is at or near its peak voltage because ramp signals 306A and 308A are at or near 180 degrees out of phase (where a change in phase shift amplitude occurs due to harmonic modulation). Therefore, clock manager circuitry 304A triggers a pulse in clock signal 316A, causing the first half-cycle to end at T2. Similarly, ramp signal 306A reaching V_REF 501 causes clock manager circuitry 304A to trigger a pulse in clock signal 318A, causing the second half-cycle to end at T6.

[0073] exist Figure 5 In the power stage circuit system 204B, CFLY 404 has a voltage higher than the ideal voltage. To correct this error, a device using only harmonic modulation will reduce the slope of ramp signal 308B (relative to ramp signal 306A) to increase the discharge time, and will increase the slope of ramp signal 306B (relative to ramp signal 308A) to reduce the charging time. Using this technique, the first half-cycle of the power stage circuit system 204B will end at T3, and the second half-cycle will end at T5. Therefore, if the power stage circuit systems 204A and 204B are controlled by a device using only harmonic modulation, the clock pulses in clock signals 316A, 318A, 318B, and 318B will not occur simultaneously, and global synchronization will not be achieved.

[0074] exist Figure 6In the example, ramp generator circuit systems 302A and 302B independently and simultaneously initiate ramp signals 308A and 306B, but with different slopes due to the difference in V_FLY error. Then, according to the teachings described herein, ramp signal 308A crosses V_REF 501 at T2, causing clock manager circuit system 304A to send a message to clock manager circuit system 304B. This message causes clock manager circuit system 304B to trigger a pulse in clock signal 318B at T2 earlier than it would normally (e.g., before a threshold time has elapsed), instead of at T3. The triggering of the pulse in clock signal 318B causes the first half-cycles of both power stage circuits 204A and 204B to end at approximately the same time (e.g., T2), achieving global synchronization.

[0075] Because the clock manager circuitry 304B is forced to trigger the pulse in clock signal 318B at T2 instead of T3, the desired increase in discharge time intended to correct for V_FLY > (V_IN / 2) is not fully achieved. Therefore, the clock manager circuitry 304 triggers the pulse in clock signal 316B at T4, earlier than in the case where harmonic modulation is only used for V_FLY errors (e.g., at T5) or where there are no V_FLY errors (e.g., at T6). The earlier triggering of the pulse at T4 reduces the length of the third cycle in which C_FLY 404 is charging. The clock manager circuitry 304B determines the precise timing of the pulse in clock signal 316B based on the reduced length of the first cycle in which C_FLY 404 is discharging. Therefore, the power stage circuitry 304B still exhibits a longer discharge cycle (e.g., between T1 and T2) than the charging cycle (e.g., between T2 and T4), thus allowing for the correction of V_FLY > (V_IN / 2).

[0076] exist Figure 6 In the example, clock manager circuitry 304A sends a message to clock manager circuitry 304B at T2 because power stage circuitry 204A has no V_FLY error, while power stage circuitry 304B has V_FLY error, causing ramp signal 308A to reach V_REF 501 before ramp signal 306B. More generally, for any n power stages synchronized together according to the teachings described herein, the power stage circuitry with the smallest error will have its local controller send messages to the other local controllers. It is worth noting that because the amount of V_FLY error can change in any cycle, the local controller sending messages to other controllers can also change in any cycle. Therefore, local controller circuitry 206 does not contain a primary or secondary role. In practice, local controller circuitry 206 sends and receives messages cycle-by-cycle for mutual synchronization.

[0077] Synchronization window signal 604A refers to a rectangular waveform describing when the local controller circuitry 206A is ready for synchronization. When synchronization window signal 604A is high, local controller circuitry 206A is ready to send or receive messages from other local controller circuitry 206, causing pulses in clock signals 316A and 318B to be fired globally simultaneously. Clock signals 316A and 318B are synchronized with each other in this example, such that the power stages are out of phase during synchronization. By being out of phase during synchronization, power stage circuitry 204A can reduce the power connected to the output terminal of load 110, while power stage circuitry 204B can increase the power connected to the output terminal of load 110 (and vice versa). This configuration allows controller circuitry 202 as a whole to reduce the amplitude of the ripple appearing in the V_OUT voltage supplied to load 110, thereby improving the performance of multiphase buck regulator circuitry 108.

[0078] When the synchronization window signal 604A is at a low voltage, the local controller circuit system 206A waits to trigger a pulse in the clock signal 318A at a specific time to achieve harmonic modulation and correct any potential V_FLY error in the power stage circuit system 204A. Therefore, the synchronization window signal 604A transitions to a low voltage at T2 and transitions back to a high voltage at T6.

[0079] Synchronization window signal 604B refers to when the local controller circuitry 206B is ready to synchronize and operate as described above. It is worth noting that the power stage circuitry 204B may have a different V_FLY error amount than the power stage circuitry 204A; therefore, synchronization window signal 604B may transition between high and low voltages at different times than synchronization window signal 604A. For example, the error correction cycle ends, and synchronization window signal 604B transitions to high voltage at T4, while synchronization window signal 604A does not transition to high voltage until T6. Therefore, when synchronizing n different power stage circuits, the local controller circuitry 206 collectively waits until each of these n different synchronization window signals 604 is at a high voltage before sending or receiving messages from each other. As used herein, a synchronization window can refer to the period within synchronization window signal 604 during which each of the n different local controller circuits 204 participating in the synchronization is at a high voltage.

[0080] exist Figure 6 In the example, local controller circuit systems 206A and 206B implement the above technique, such that the next set of global synchronization pulses in clock signals 316A and 318B does not occur until after T6. Based on the amount of V_FLY error present in power stage circuit systems 204A and 204B, the excitation of the next set of global synchronization pulses in clock signals 316A and 318B occurs at T7.

[0081] Figure 7 yes Figure 3 A first example block diagram of the clock manager circuit system 304A. The clock manager circuit system 304A includes... Figure 3 The ramp signals 306A and 308A, V_REF 501 and Figure 6 The synchronization window signal 604A. The clock manager circuit system 304A also includes an example engagement synchronization signal 701A (which may be referred to herein as the EN_SYNC signal 701A), an example comparator circuit system 706A, an example OR gate 708A, an example clock generator circuit system 710A, an example AND gate 712A, an example multiplexer 714A, and an example SYNC_SELECT signal 716A.

[0082] Figure 7 It also includes clock manager circuits 304B, 304C, and 304D, each containing a local instance of the above components. Specifically, clock manager circuit system 304B includes an example EN_SYNC signal 701B, an example comparator circuit system 706B, an example OR gate 708B, an example clock generator circuit system 710B, an example AND gate 712B, an example multiplexer 714B, an example SYNC_SELECT signal 716B, etc. Furthermore, the components within clock manager circuit systems 304B, 304C, and 304D can be operated according to the teachings described herein and referred to below in the discussion of clock manager circuit system 304A.

[0083] The EN_SYNC signal 701A is a binary signal (e.g., set to high or low voltage) used to describe whether the local controller circuitry 206A is currently participating in synchronization. Figure 6 In the example, EN_SYNC signals 701A and 701B are at high voltage, while EN_SYNC signals 701C and 701D are at low voltage. Therefore, local controller circuits 206A and 206B synchronize the clock signals with each other, and local controller circuits 206C and 206D do not participate in synchronization. More generally, although the example described herein involves synchronization between two local controller circuits 206A and 206B, the teachings described herein can be applied to any number of controller circuits.

[0084] The values ​​of the EN_SYNC signals 701A-701D are determined by... Figure 2The programmable circuitry is located within the controller circuitry 202 but outside the local controller circuitry 206. The programmable circuitry provides EN_SYNC signals 701A-701D to the corresponding local controller circuitry via bus 205. The programmable circuitry can selectively enable or disable synchronization using the EN_SYNC signals 701A-701D. In some examples, the EN_SYNC signal 701C is at a low voltage because the corresponding power stage circuitry 204C is de-energized. Operating the multiphase buck regulator circuitry 108 while some, but not all, power stage circuitry 204 is energized can be referred to as phase shedding.

[0085] During the first half-cycle, comparator circuitry 706A compares ramp signal 306A with V_REF 501. If the value of ramp signal 306A meets (e.g., reaches) or exceeds the value V_REF 501 during the first half-cycle, comparator circuitry 706A outputs a pulse (e.g., a high voltage lasting for a certain time period). During the remainder of the first half-cycle, comparator circuitry 706A outputs a low voltage. Similarly, during the second half-cycle, comparator circuitry 706A compares ramp signal 308A with V_REF 501. If the value of ramp signal 308A meets, reaches, or exceeds the value V_REF 501 during the second half-cycle, comparator circuitry 706A outputs a pulse. During the remainder of the second half-cycle, comparator circuitry 706A outputs a low voltage.

[0086] OR gate 708A receives a first input from comparator circuitry 706A and a second input from AND gate 712A. Subsequently, AND gate 712A receives a synchronization window signal 604A as its first input, an EN_SYNC signal 701A as its second input, and the output of multiplexer 714A as its third input. As used herein, "first component receiving signal" can refer to the first component being connected to (e.g., coupled to) a second component carrying the signal (e.g., a copper trace, wire, pin, terminal, etc.).

[0087] Multiplexer 714A provides messages from local controller circuitry 206B. The message value is based on the SYNC_SELECT signal 716A. In the example described herein, clock signals 316A and 318B are globally synchronized. Therefore, SYNC_SELECT = 0, and the message received at AND gate 712A is a pulse from clock signal 318B. More generally, any arbitrary index of the clock signals can be synchronized and shared via bus 205, provided that each of the local controller circuitry 206s participating in the synchronization uses one clock signal for global synchronization (e.g., a timing excitation pulse based on another controller) and one clock signal for harmonic modulation (e.g., an excitation pulse independent of another controller). The values ​​of the SYNC_SELECT signals 716A-716D, which can be set by a programmable circuitry system external to local controller circuitry 206, select which clock signals will be used for synchronization. In some examples, clock signal 316B may be referred to as an external clock signal because it is generated externally to local controller circuitry 206A.

[0088] As discussed above, when the local controller circuitry 206A is ready to synchronize the pulses in clock signal 316A (e.g., without waiting for the pulses in clock signal 318A to be excited using harmonic modulation techniques), the synchronization window signal 604A is at a high value. Similarly, when the synchronization window signal 604B is at a high voltage and the ramp signal 306B crosses V_REF 501, the local controller circuitry 206B only sends the pulses in clock signal 318B. Therefore, when the ramp signal 306B crosses V_REF 501 and both local controller circuits 206A and 206B are ready to synchronize, the output of AND gate 712A (which may be referred to herein as the SYNC_CLK_EDGE signal) simply transitions to a high voltage.

[0089] During the first half-cycle, the synchronization window signal 604A is at a high voltage, as discussed above. Therefore, the OR gate 708A can receive a high voltage from one or both input terminals during the first half-cycle. During the synchronization window, if the V_FLY error of the power stage circuit system 204A is less than that of the power stage circuit system 204B, then the output of the comparator circuit system 706A transitions to a high voltage before the SYNC_CLK_EDGE signal, because the difference in V_FLY error causes the ramp signal 308A to reach V_REF 501 (e.g., before the ramp signal 306B). Figure 6(As shown at T2 in the diagram). In this type of example, the output of the OR gate transitions to a high voltage, causing the clock generator circuitry 710A to generate a pulse in the clock signal 316A. The pulse is: a) received by the PWM generator circuitry 320A, thereby generating the pulse in the PWM signal 226A, and b) received via the bus by the local controller circuitry 206B, thereby generating the pulse in the clock signal 318B.

[0090] Alternatively, if the V_FLY error of power stage circuitry 204A is greater than that of power stage circuitry 204B during the synchronization window, then the SYNC_CLK_EDGE signal transitions to high voltage before the output of comparator circuitry 706A, because the difference in V_FLY error causes ramp signal 306B to reach V_REF 501 before ramp signal 308A. In this example, the output of the OR gate transitions high, causing clock generator circuitry 710A to generate a pulse in clock signal 316A. The pulse is: a) received by PWM generator circuitry 320A, thereby generating the pulse in PWM signal 226A, and b) received by local controller circuitry 206B via bus 205. However, in this example, local controller circuitry 206B does not generate a pulse in clock signal 316B in response to a pulse in clock signal 316A, because a smaller V_FLY error in power stage circuitry 204B means that a pulse in clock signal 316B has already been transmitted. Therefore, the local controller circuit system 206B is already in the second half-cycle and no longer requires synchronization. Furthermore, when the pulse from clock signal 316A is received at AND gate 712B and the pulse from clock signal 316A is ignored, the synchronization window signal 604B is at a low voltage.

[0091] During the second half-cycle, the synchronization window is closed, and the SYNC_CLK_EDGE signal in both clock manager circuits 304A and 304B remains at a low voltage. Therefore, once the ramp signal 306A reaches V_REF 501, the OR gate 708A only transitions to a high voltage during the second half-cycle. It is worth noting that the ramp generator circuit system 302A receives the V_FLY signal 212A and thus observes the change in charge of C_FLY 404 during the first half-cycle. Then, taking into account any current V_FLY error (which could be greater than expected if the local controller circuit system 206B causes the clock generator circuit system 710A to generate a pulse in the clock signal 316A before the ramp signal 308A reaches V_REF 501), the ramp generator circuit system 302A adjusts the slope of the ramp signal 306A as needed. Subsequently, due to the adjusted slope of the ramp signal 306A, the ramp generator circuit system 710A excites pulses in the clock signal 318A at different times. Therefore, the local controller circuit system 206A is synchronized with the local controller circuit system 206B, and still implements harmonic modulation by timing the excitation of pulses in the clock signal 318A based on the pulses in the clock signal 316A.

[0092] Clock generator circuit system 710A generates pulses in clock signals 316A and 318A based on a logic '1' received from OR gate 708A. Clock generator circuit system 710A can be implemented by any form of programmable circuit system. An example implementation of clock generator circuit system 710A is combined with... Figure 8 Further discussion.

[0093] Figure 8 yes Figure 3 The second example block diagram of the clock manager circuit system. Figure 8 Example clock manager circuit system 304A includes the above combined Figure 7 The same components, signals, and connections are described. Figure 8 The clock generator circuit system 710A is also shown, including example RS flip-flop circuit systems 802A and 806A, example time delay circuit system 803A, example D flip-flop circuit system 804A, example inverter 808A, example AND gates 810A, 812A, 814A, 816A, and example multiplexer 818A. The clock generator circuit system 710A further includes example excitation signals 826A and 828A, example monitoring signals 836A and 838A, and a SYNC_SELECT signal 716A.

[0094] RS flip-flop circuit system 802A has an S-terminal connected to the output of OR gate 708A. When OR gate 708A transitions to a high voltage state (e.g., when a pulse in one of clock signals 316A or 318A should be fired for synchronization or harmonic modulation), the Q-terminal of RS flip-flop circuit system 802A outputs the same high state until time delay circuit system 803A resets RS flip-flop circuit system 802A. The time delay circuit system provides a high voltage to the R-terminal of RS flip-flop circuit system 802A, thereby resetting the circuit after a predetermined amount of time (e.g., a few nanoseconds). Therefore, the period before time delay circuit system 803A resets RS flip-flop circuit system 802A defines the pulse width of clock signals 316A and 318A.

[0095] Monitoring signals 836A and 838A are both digital signals, respectively indicating whether ramp signals 306A and 308A have crossed V_REF 501 at any given time. In some examples, the clock manager circuit system 304A includes a first comparator circuit for comparing ramp signal 306A with V_REF 501 and a second comparator circuit for comparing ramp signal 308A with V_REF 501 (instead of...). Figure 6 , 7 The single comparator circuit system 706A described herein performs both comparisons simultaneously. In such an example with two comparators, the clock generator circuit system 710A can be implemented without monitoring signals 836A and 838A, since the outputs of the comparator circuits will provide the same voltage.

[0096] The Q and Q-not terminals of the D flip-flop circuit system 804A generate excitation signals 828A and 826A, respectively. Excitation signals 826A and 828A indicate when pulses in clock signals 318A and 316A should be excited (e.g., when clock generator circuit system 710 should generate rectangular pulses within clock signals 318A and 316A). AND gate 810A receives excitation signal 828A at its first terminal and the output of RS flip-flop circuit system 802A at its second terminal. Similarly, AND gate 812A receives excitation signal 826A at its first terminal and the output of RS flip-flop circuit system 802A at its second terminal. Therefore, whenever the ramp signal reaches V_REF 501, one input of either AND gate 810A or 812A reaches a high voltage. However, because the Q and Q-not terminals are inverted, only one of the excitation signals 828A and 826A is high at any given time. Therefore, when the ramp signal reaches V_REF 501, only one of the clock signals 316A and 318A will have a pulse triggered. The D flip-flop circuit system 804A tracks which ramp signal last reaches V_REF 501 and sets the voltages of the Q and Q-NOT terminals so that a pulse is triggered in the corresponding clock signal when the ramp signal next reaches V_REF 501.

[0097] The clock generator circuitry 710A is also connected to bus 205, such that if, during the synchronization window, ramp signal 308A reaches V_REF 501 before ramp signal 306B, then clock generator circuitry 710A can provide one of clock signals 318A or 316A to local controller circuitry 206B based on the value of SYNC_SELECT signal 716A. Figure 7 In the example, SYNC_SELECT=0, and the clock generator circuitry 710A sends clock signal 316A once it is triggered. In some examples, clock signal 316A may contain pulse commands, messages, etc.

[0098] RS flip-flop circuit system 806A and inverter 808A jointly generate monitoring signals 836A and 838A. At any given time, the Q terminal of RS flip-flop circuit system 806A outputs monitoring signal 836A. The output of the Q terminal is simultaneously provided to: a) the appropriate AND gate 816A, and b) the inverter 808A to generate monitoring signal 838A. As described with ramp signals 306A and 308A, monitoring signals 836A and 838A can be considered to be inverses of each other because they have opposite values. For example, if ramp signal 306A reaches V_REF 501, then ramp signal 308A has not yet reached V_REF 501, therefore monitoring signal 838A is at a high voltage to allow ramp signal 308A to be used by the comparator. Therefore, at any given time, monitoring signals 836A and 838A are present to be used by comparator 706A and AND gates 816A and 814A, respectively.

[0099] Example multiplexer 818A generates a synchronization window signal 604A based on inputs from the SYNC_SELECT signal 716A and AND gates 814A and 816A. AND gate 814A receives an excitation signal 828A at a first input terminal and a monitoring signal 838A at a second input terminal. Similarly, AND gate 816A receives an excitation signal 826A at a first input terminal and a monitoring signal 836A at a second input terminal.

[0100] like Figure 6 As shown, the SYNC_WINDOW signal 604A indicates when the power stage circuitry 204A has completed the second half-cycle (and the local controller circuitry 206A is therefore ready to synchronize in subsequent cycles). In the example described herein, SYNC_SELECT = 0, and the local controller circuitry 206 synchronizes the clock signals 316A and 318B based on ramp signals 308A and 306B. Therefore, the output of the AND gate 816A is high after the end of the second half-cycle. When the excitation signal 826A is high, it indicates that the clock signal 316A will next excite a pulse, and when the monitoring signal 838A is high, it indicates that the ramp signal 308A will next cross V_REF 501, and the clock generator circuitry 710A determines that the second half-cycle has ended.

[0101] Figure 9 It is by Figure 7 and 8 Example timing diagram of signals generated by the clock manager circuit system. Figure 9 Include Figure 3 Clock signals 316A, 318A, 316B, 318B and Figure 7 The EN_SYNC signal 701A. Figure 9It also includes example enable signals 902 and 904, and timestamps that are independent of the timestamps discussed above (e.g., they may refer to a different point in time than the timestamps discussed above).

[0102] Example enable signals 902 and 904 are binary signals that describe the functions of local controller circuit systems 206A and 206B, respectively. For example, when enable signal 902 is high, local controller circuit system 206A is generating pulses in clock signals 316A and 318A, sending pulses in PWM signals 226A and 228A, and causing power stage circuit system 204A to supply voltage to load 110. When enable signal 902 is low, local controller circuit system 206A is not generating pulses, and power stage circuit system 204A is not contributing to load 110. Similarly, a high voltage indication enable signal 904 indicates that local controller circuit system 206B is generating pulses, and a low voltage indication indicates that local controller circuit system 206B is not generating pulses. Programmable circuitry within controller circuit system 202 and outside the local controller circuitry can set the values ​​of enable signals 902 and 904 based on the requirements of load 110 and power shedding capabilities.

[0103] exist Figure 9 In the example, enable signal 902 transitions from low to high voltage at T0, and enable signal 904 transitions from low to high voltage at T3. Therefore, the local controller circuitry 206A generates pulses in clock signals 316A and 318A between T0 and T3 without needing to synchronize with other local controllers (as shown, where the EN_SYNC signal 701A is set to low voltage from T0 until after T2).

[0104] It is worth noting that the programmable circuitry waits until T3, at which point it transitions the enable signal 904 to a high voltage on the rising edge of the pulse in clock signal 318A. Therefore, both local controller circuitry 206A and local controller circuitry 206B begin the first half-cycle after T3. Furthermore, because the programmable circuitry transitions the EN_SYNC signal 701 to a high voltage before T3 (e.g., before turning on local controller circuitry 206B), the start of the first half-cycle after T3 also marks the beginning of the synchronization window.

[0105] exist Figure 9In the example, local controller circuitry 206B has a smaller V_FLY error than local controller circuitry 206A in the first synchronization window. Therefore, ramp signal 306B reaches V_REF 501 before ramp signal 308A, and local controller circuitry 206B sends a copy of the corresponding pulse in clock signal 318B to local controller circuitry 206A at T4. Receiving the copy of the pulse in clock signal 318B at multiplexer 714A causes local controller circuitry 206A to also excite the pulse in clock signal 316A at approximately T4.

[0106] exist Figure 9 In the example, the first synchronization window ends after T4. Therefore, local controller circuitry systems 206A and 206B independently excite pulses in clock signals 318A and 316B at different times to perform harmonic modulation. For example, local controller circuitry system 206B excites a pulse in clock signal 316B that ends at T5 because the pulse in clock signal 318B is excited at the expected time (e.g., at T4 when ramp signal 306B reaches V_REF 501). In contrast, a pulse in clock signal 316A excited before ramp signal 308A can reach V_REF 501, so local controller circuitry system 206A excites a pulse in clock signal 318A before T5 to reduce the amount of time C_FLY 404 is charged.

[0107] Although the second half-cycle in local controller circuit system 206A ends before the second half-cycle in local controller circuit system 206B, Figure 9 The second synchronization window doesn't start until T5 because the two controllers aren't ready to resynchronize until T5. Figure 9 In the example, local controller circuitry 206A has a smaller V_FLY error than local controller circuitry 206B in the second synchronization window. Therefore, ramp signal 308A reaches V_REF 501 before ramp signal 306B, and local controller circuitry 206A sends a copy of the corresponding pulse in clock signal 316A to local controller circuitry 206B at T6.

[0108] exist Figure 9In the example, the second synchronization window ends after T6. Therefore, local controller circuitry systems 206A and 206B independently trigger pulses in clock signals 318A and 316B at different times to perform harmonic modulation. For example, local controller circuitry system 206A triggers a pulse in clock signal 318A that ends at T7 because the pulse in clock signal 316A is triggered at the expected time (e.g., at T6 when ramp signal 308A reaches V_REF 501). In contrast, the pulse in clock signal 318B is triggered before ramp signal 306B can reach V_REF 501, so local controller circuitry system 206B triggers the pulse in clock signal 316B before T7 to reduce the amount of time C_FLY 404 is charged.

[0109] exist Figure 9 In the example, the third synchronization window begins at T7, at which point the two controllers are ready to resynchronize. Figure 9 In the example, local controller circuitry 206A has a smaller V_FLY error in the third synchronization window than local controller circuitry 206B. Therefore, ramp signal 308A reaches V_REF 501 before ramp signal 306B, and local controller circuitry 206A transmits a copy of the pulse in clock signal 316A at T8. After T8, local controller circuitry 206A and 206B independently excite the pulses in clock signals 318A and 316B at different times to perform harmonic modulation, as discussed above.

[0110] Although Figure 3 The implementation is shown in the figure. Figure 2 The example mode of the local controller circuit system 206A and / or more generally the controller circuit system 202, but Figure 3 One or more of the elements, processes, and / or devices shown may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other way. Furthermore, examples include ramp generator circuit system 302A, clock manager circuit system 304A, PWM generator circuit system 320A, and / or more generally... Figure 2 Example local controller circuitry 206A and / or more generally controller circuitry 202 can be implemented by hardware alone or by a combination of hardware and software and / or firmware. Thus, for example, example ramp generator circuitry 302A, clock manager circuitry 304A, PWM generator circuitry 320A and / or more generally… Figure 2Any of the example local controller circuitry 206A and / or more generally the controller circuitry 202 can be implemented by a programmable circuitry system in combination with machine-readable instructions (e.g., firmware or software), a processor circuitry system, analog circuitry, digital circuitry, logic circuitry, a programmable processor, a programmable microcontroller, a graphics processing unit (GPU), a digital signal processor (DSP), an ASIC, a programmable logic device (PLD), and / or a field-programmable logic device (FPLD) such as an FPGA. Furthermore, Figure 2 Example local controller circuit system 206A and / or more generally controller circuit system 202 may include one or more elements, processes and / or devices as Figure 2 The supplements or substitutions shown may include more than one of any or all of the elements, processes and apparatus shown.

[0111] Figure 10 and 11 The flowchart shown herein represents an implementation and / or instantiation that can be executed by a programmable circuit system. Figure 2 Example machine-readable instructions and / or representations of the local controller circuit system 206A and / or more generally the controller circuit system 202 can be executed by a programmable circuit system to implement and / or instantiate. Figure 2 Example operation of the local controller circuitry 206A and / or more generally, the controller circuitry 202. Machine-readable instructions may be one or more executable programs or portions thereof for execution by a programmable circuitry system, as described below. Figure 12 The programmable circuit system 1212 shown in the example programmable circuit system platform 1200 described herein can be one or more functions or functional portions that will be performed by the example programmable circuit system. In some examples, machine-readable instructions cause operations, tasks, etc., to be performed and / or executed automatically in the real world. As used herein, “automatic” means without human intervention.

[0112] The program may be embodied in instructions (e.g., software and / or firmware) stored on one or more non-transitory computer-readable and / or machine-readable storage media, such as cache memory, magnetic storage devices or disks (e.g., floppy disks, hard disk drives (HDDs), etc.), optical storage devices or optical discs (e.g., Blu-ray discs, optical discs (CDs), digital versatile optical discs (DVDs), etc.), redundant arrays of independent disks (RAID), registers, ROM, solid-state drives (SSDs), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., any type of random access memory (RAM), etc.), and / or any other storage device or storage disk. The instructions on the non-transitory computer-readable and / or machine-readable media may be programmed and / or executed by a programmable circuit system located in one or more hardware devices, but the entire program and / or portions thereof may alternatively be executed and / or instantiated and / or embodied in dedicated hardware by one or more hardware devices other than the programmable circuit system. Machine-readable instructions may be distributed across multiple hardware devices and / or executed by two or more hardware devices (e.g., server and client hardware devices). For example, client hardware devices may be implemented by end-user client hardware devices (e.g., hardware devices associated with human and / or machine users) or by an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that facilitates communication between the server and the end-user client hardware devices. Similarly, non-transitory computer-readable storage media may contain one or more media. Furthermore, although the example program is for reference only... Figure 10 and 11The flowchart illustrates, but may be used alternatively with many other implementation examples of the local controller circuitry system 206A and / or more generally, the controller circuitry system 202. For example, the execution order of the flowchart blocks may be changed, and / or some of the described blocks may be altered, eliminated, or combined. Additionally or alternatively, any or all of the flowchart blocks may be implemented by one or more hardware circuits (e.g., processor circuitry systems, discrete and / or integrated analog and / or digital circuitry systems, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuitry, etc.) configured to perform the corresponding operations without executing software or firmware. The programmable circuitry system may be distributed across different network locations and / or local to one or more hardware devices (e.g., single-core processors (e.g., single-core CPUs), multi-core processors (e.g., multi-core CPUs, XPUs, etc.)). For example, a programmable circuit system may be a CPU and / or FPGA located in the same package (e.g., in the same integrated circuit (IC) package, or in two or more separate housings), one or more processors in a single machine, multiple processors distributed on multiple servers in a server rack, multiple processors distributed on one or more server racks, and / or any combination of one or more thereof.

[0113] The machine-readable instructions described herein can be stored in one or more of the following formats: compressed format, encrypted format, segmented format, compiled format, executable format, and encapsulated format. The machine-readable instructions described herein can be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), bit streams (e.g., computer-readable bit streams, machine-readable bit streams, etc.)) or data structures (e.g., portions of instructions, code, representations of code, etc.), which can be used to create, manufacture, and / or generate machine-executable instructions. For example, machine-readable instructions can be segmented and stored on one or more storage devices, disks, and / or computing devices (e.g., servers) located in the same or different locations (e.g., in the cloud, at an edge device, etc.) within a network or network set. Machine-readable instructions may require one or more of the following processes: installation, modification, adaptation, updating, combination, supplementation, configuration, decryption, decompression, decapsulation, allocation, reassignment, compilation, etc., so that they can be directly read, interpreted, and / or executed by computing devices and / or other machines. For example, machine-readable instructions may be stored in multiple parts, which are individually compressed, encrypted, and / or stored on separate computing devices, wherein the parts, when decrypted, decompressed, and / or combined, form a set of computer-executable and / or machine-executable instructions, the implementation of which together form one or more functions and / or operations of the program described herein.

[0114] In another example, machine-readable instructions may be stored in a state readable by a programmable circuit system, but require the addition of libraries (e.g., dynamic link libraries (DLLs)), software development kits (SDKs), application programming interfaces (APIs), etc., to execute the machine-readable instructions on a specific computing device or another device. In another example, it may be necessary to configure the machine-readable instructions (e.g., store settings, input data, record network addresses, etc.) before they can be fully or partially executed. Therefore, machine-readable, computer-readable, and / or machine-readable media as used herein may contain instructions and / or programs, regardless of the specific format or state of the machine-readable instructions and / or programs.

[0115] The machine-readable instructions described in this article can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, machine-readable instructions can be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0116] As mentioned above, Figure 10 and 11Example operations can be implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transitory computer-readable and / or machine-readable media. As used herein, the terms non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and / or non-transitory machine-readable storage media are explicitly defined as including any type of computer-readable storage device and / or storage disk, excluding propagation signals and transmission media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and / or non-transitory machine-readable storage media include optical storage devices, magnetic storage devices, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, caches, any type of RAM, registers, and / or any other storage devices or storage disks in which information is stored for any duration (e.g., extended time period, permanent, transient, for temporary buffering, and / or for caching information). As used herein, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined as comprising any physical (mechanical, magnetic, and / or electrical) hardware designed to retain information for a period of time, excluding the propagation of signals and the transmission medium. Examples of non-transitory computer-readable storage devices and / or non-transitory machine-readable storage devices include any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disk, magnetic disk, disk drive, and / or redundant array of independent disks (RAID) system. As used herein, the term "device" refers to a physical structure, such as mechanical and / or electrical equipment, hardware, and / or circuitry, which may or may not be configured by computer-readable instructions, machine-readable instructions, etc., and / or may or may not be manufactured to execute computer-readable instructions, machine-readable instructions, etc.

[0117] "Comprising" and "including" (and all their forms and tenses) are used herein as open-ended terms. Therefore, whenever a claim uses any form of "comprising" or "including" (e.g., includes, encompassing, including, having, etc.) as a preamble or in any type of claim statement, it should be understood that additional elements, terms, etc., may be present without exceeding the scope of the corresponding claim or statement. As used herein, the phrase "at least" is open-ended when used as a transitional term, for example, in a preamble of a claim, in the same way as the terms "comprising" and "including". For example, the term "and / or" when used in the form of, for example, A, B, and / or C, refers to any combination or subset of A, B, C, such as (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing structures, components, projects, objects, and / or things, the phrase “at least one of A and B” is intended to refer to an implementation comprising any of the following: (1) at least one A; (2) at least one B; or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, projects, objects, and / or things, the phrase “at least one of A or B” is intended to refer to an implementation comprising any of the following: (1) at least one A; (2) at least one B; or (3) at least one A and at least one B. As used herein in the context of describing the execution or performance of processes, instructions, actions, activities, and / or steps, the phrase “at least one of A and B” is intended to refer to an implementation comprising any of the following: (1) at least one A; (2) at least one B; or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the execution or performance of processes, instructions, actions, activities and / or steps, the phrase “at least one of A or B” is intended to refer to an implementation comprising any of the following: (1) at least one A; (2) at least one B; or (3) at least one A and at least one B.

[0118] As used herein, singular references (e.g., "a(a / an)", "first", "second", etc.) do not exclude plurals. As used herein, the term "a(a)" or "an" refers to one or more of the said objects. The terms "a(a)" (or "an"), "one or more", and "at least one" are used interchangeably herein. Furthermore, although listed separately, multiple components, elements, or actions may be implemented by, for example, the same entity or object. Additionally, although individual features may be included in different examples or technical solutions, these features may be combined, and inclusion in different examples or technical solutions does not imply that the combination of features is unfeasible and / or disadvantageous.

[0119] Figure 10 It means that it can be used. Figure 2 Flowcharts illustrating example machine-readable instructions and / or example operations performed, instantiated, and / or executed by example programmable circuit system implementations of local controller circuits 206A and 206B. Figure 10 The example flowchart is divided into two columns, labeled '206A' and '206B'. Therefore, the boxes in column '206A' represent operations performed by local controller circuitry 206A, and the boxes in column '206B' represent operations performed by local controller circuitry 206B. Figure 10 In the example, the EN_SYNC 701 signal is set to high, so both local controller circuits 206A and 206B are configured to synchronize with each other. Furthermore, Figure 10 The example flowchart begins at the start of a new loop for both local controller circuits 206A and 206B.

[0120] Example machine-readable instructions and / or operations 1000 begin with local controller circuitry 206A discharging C_FLY 404 in power stage circuitry 204A based on local errors (Box 1002A). During the same period, local controller circuitry 206B charges C_FLY 404 in power stage circuitry 204B based on local errors (Box 1002B). Power stage circuitry 204A and 204B perform different operations during the synchronization window to reduce ripple in the V_OUT signal supplied to load 110, as discussed above.

[0121] Power stage circuit systems 204A and 204B are two separate circuits with two separate instances of C_FLY 404. Therefore, the magnitude of the local error (e.g., V_FLY error) at block 1002A differs from the magnitude of the local error at block 1002B. In the example described herein, local controller circuit system 206A enables and disables transistor 402 such that C_FLY 404 discharges during the first half-cycle and charges during the second half-cycle. Conversely, local controller circuit system 206B enables and disables transistor 402 such that C_FLY 404 charges during the first half-cycle and discharges during the second half-cycle. Therefore, C_FLY 404 in power stage circuit system 204A discharges at block 1002A, and C_FLY 404 in power stage circuit system 204B charges at block 1002B. In other examples, local controller circuit 206 may enable and disable transistor 402 in a different order.

[0122] Local controller circuitry 206A determines whether discharging in block 1002A is complete (block 1004A). To determine block 1004A, comparator circuitry 706A compares ramp signal 308A with V_REF 501. Similarly, local controller circuitry 206B determines whether charging in block 1002B is complete (block 1004B).

[0123] If ramp signal 308A has not yet reached V_REF 501 (box 1004A: No), then control returns to box 1002A, where C_FLY 404 in power stage circuitry 204A continues to discharge. Similarly, if ramp signal 306B has not yet reached V_REF 501 (box 1004B: No), then control returns to box 1002B, where C_FLY 404 in power stage circuitry 204B continues to charge.

[0124] exist Figure 10 In the example, power stage circuitry 204A has a smaller V_FLY error than power stage circuitry 204B. Therefore, ramp signal 308A reaches V_REF 501 (box 1004A: Yes), while ramp signal 306B does not reach V_REF 501 (box 1004B: No). After the ramp signal reaches V_REF 501, clock generator circuitry 710A fires a pulse in a first local clock signal (e.g., clock signal 316A) (box 1006A). Clock generator circuitry 710A also sends a copy of the pulse to local controller circuitry 206B (box 1008A). In some examples, the copy of the pulse at box 1008A may be referred to as a message or instruction.

[0125] In response to receiving a copy of the pulse at block 1008A, power stage circuitry 204B excites a pulse in a first local clock signal (e.g., clock signal 318B) (block 1006B). The pulses in blocks 1006A and 1006B are synchronized because they occur at approximately the same time.

[0126] Local controller circuitry 206A excites pulses in a second local clock signal (e.g., clock signal 318A) based on a first local clock signal (box 1010A). Specifically, the pulses in clock signal 318A are excited at times allowing a specific C_FLY charge amount to achieve harmonic modulation in power stage circuitry 204A. Similarly, local controller circuitry 206B excites pulses in a second local clock signal (e.g., clock signal 316B) based on a first local clock signal (box 1010B). The pulses in clock signal 316B also achieve harmonic modulation in power stage circuitry 204B. Boxes 1010A and 1010B are implemented at different times because power stage circuitry 204A... Figure 10 The example has a smaller V_FLY error than the power stage circuit system 204B.

[0127] After the pulse in clock signal 318A is triggered, the second half-cycle ends, and local controller circuitry 206A determines whether to generate additional clock and PWM pulses in another cycle (box 1012A). Local controller circuitry 206A can enter another cycle as long as controller circuitry 202 permits it via enable signal 902. Programmable circuitry within controller circuitry 202 can disable or enable another cycle of local controller circuitry 206A for any reason. Similarly, local controller circuitry 206B determines whether to generate additional clock and PWM pulses in another cycle (box 1012B). In Figure 10 In the example, the decision boxes for 1012A and 1012B occur at different times because the length of the loop in power stage circuit system 204A is not equal to the length of the loop in power stage circuit system 204B.

[0128] If the local controller circuitry 206A enters another loop (box 1012A: Yes), then control returns to box 1002A, where, as part of the first stage of the power stage circuitry 204A, the local controller circuitry 206A discharges C_FLY 404. If the local controller circuitry 206A does not enter another loop (box 1012A: No), then the machine-readable instructions and / or operation 1000 of the local controller circuitry 206A terminate.

[0129] Similarly, if the local controller circuitry 206B enters another loop (box 1012B: Yes), then control returns to box 1002B, where, as part of the first stage of the power stage circuitry 204B, the local controller circuitry 206B charges C_FLY 404. If the local controller circuitry 206B does not enter another loop (box 1012B: No), then the machine-readable instructions and / or operation 1000 of the local controller circuitry 206B terminate.

[0130] Figure 11 It means that it can be used. Figure 3 This is a flowchart illustrating the example machine-readable instructions and / or operations performed, instantiated, and / or executed by an example programmable circuit system implementation of the clock manager circuit system 304A. Example machine-readable instructions and / or operations 1100 begin with the clock manager circuit system 304A determining whether to participate in synchronization with other local controllers (Box 1102). The clock manager circuit system 304A makes this determination based on the value of the EN_SYNC signal 701, as described above in conjunction with... Figure 7 As discussed. If the clock manager circuitry 304A determines that it will not participate in synchronization with other local controllers (box 1102: No), then the example machine-readable instructions and / or operations 1100 end.

[0131] If the clock manager circuitry 304A determines that it is participating in synchronization with other local controllers (box 1102: Yes), then the comparator circuitry 706A monitors the voltages of the synchronized and unsynchronized local ramp signals, where the slope of the ramp signals indicates the C_FLY charge and discharge rates (box 1104). In the example described herein, ramp signals 308A and 306B are synchronized local ramp signals, and ramp signals 306A and 308B are unsynchronized local ramp signals. Additionally, in the example described herein, ramp signals 308A and 308B indicate the C_FLY discharge rate, while ramp signals 306A and 306B indicate the C_FLY charge rate. In other examples, ramp signals with other indices are synchronized / unsynchronized and / or indicate the C_FLY charge / discharge rate.

[0132] Comparator circuitry 706A determines whether the synchronized local ramp signal has exceeded a reference voltage (box 1106). In the example described herein, the reference voltage is referred to as V_REF 501 and is proportional to V_IN provided by DC power supply unit 106. In other examples, the reference voltage is a different value. If the synchronized local ramp signal has not yet exceeded the reference voltage (box 1106: No), then comparator circuitry 706A waits for a period of time (box 1108) before control returns to box 1106.

[0133] In comparator circuitry 706A implementation blocks 1106 and 1108, multiplexer 714A also monitors bus 205 for instructions (e.g., copies of clock pulses) from local controller circuitry 206B. In some examples, the V_FLY error in local controller circuitry 206A has a smaller magnitude than the V_FLY error in local controller circuitry 206B, so ramp signal 308A exceeds V_REF 501 before the instruction is received from local controller circuitry 206B. In other examples, the V_FLY error in local controller circuitry 206A has a larger magnitude than the V_FLY error in local controller circuitry 206B, so the instruction is received before ramp signal 308A crosses V_REF 501.

[0134] If the V_FLY error in power stage circuitry 204A has a smaller magnitude than the V_FLY error in power stage circuitry 204B, then the synchronized local ramp signal eventually exceeds the reference voltage (box 1106: Yes). Meeting or exceeding the reference voltage at box 1106 causes clock generator circuitry 710A to generate pulses in the synchronized clock signal (e.g., clock signal 316A) (box 1110). Meeting or exceeding the reference voltage at box 1106 also causes clock manager circuitry 304A to send an instruction to cause an external controller (e.g., local controller circuitry 206B) to generate pulses in the synchronized clock signal (e.g., clock signal 316B) (box 1112). In such examples, local controller circuitry 206A does not implement boxes 1114 or 1116 in the current loop.

[0135] Alternatively, if the V_FLY error in power stage circuitry 204A has a larger magnitude than the V_FLY error in power stage circuitry 204B, then multiplexer 714A receives instructions from an external controller (e.g., local controller circuitry 206B) (Box 1114). In the example described herein, the instructions are copies of pulses in clock signal 318B. In other examples, the instructions are formatted differently (e.g., interrupts, bit flags, etc.).

[0136] Clock manager circuitry 304A generates pulses in the synchronized local clock signal based on instructions (Box 1116). In such examples where the V_FLY error in local controller circuitry 206A has a larger magnitude than the V_FLY error in local controller circuitry 206B, local controller circuitry 206A does not implement Boxes 1106-1112 in the current loop.

[0137] When the voltage of the unsynchronized ramp (e.g., ramp signal 306A) enables regulation of C_FLY 404 via harmonic modulation, the clock manager circuitry 304A excites a pulse in the unsynchronized local clock signal (e.g., clock signal 318A) (box 1118). For example, if the harmonic modulation of the current cycle requires a net increase in charge at C_FLY 404, the local controller circuitry 206A can excite a pulse in clock signal 318A later (thus allowing C_FLY 404 more time to charge). The local controller circuitry 206A implements box 1118 regardless of whether the pulse in the synchronized clock signal is excited at box 1110 or 1116. Therefore, the pulse in box 1118 can be excited at a time that takes into account the fact that the pulse in the synchronized clock signal is excited earlier than expected (e.g., at box 1116).

[0138] Clock manager circuitry 304A determines whether ramp signals 306A and 308A are still active (box 1120). If control circuitry 202 disables local controller circuitry 206A during power cut-off operation, ramp signals 306A and 308A can become inactive. If ramp signals 306A and 308A are still active (box 1120: Yes), control returns to box 1104, where comparator circuitry 706A monitors the voltages of these two ramp signals. Alternatively, if ramp signals 306A and 308A are inactive (box 1120: No), then machine-readable instructions and / or operation 1100 terminates.

[0139] Figure 12 It is constructed to execute and / or instantiate Figure 10 and 11 Example machine-readable instructions and / or example operations for implementation Figure 2 A block diagram of an example programmable circuit system platform 1200, including a local controller circuit system 206A and / or more generally a controller circuit system 202. The programmable circuit system platform 1200 may be, for example, a server, personal computer, workstation, self-learning machine (e.g., neural network), mobile device (e.g., mobile phone, smartphone, such as iPad). TM Tablet computers, personal digital assistants (PDAs), internet devices, DVD players, CD players, digital video recorders, Blu-ray players, game consoles, personal video recorders, set-top boxes, head-mounted devices (e.g., augmented reality (AR) head-mounted devices, virtual reality (VR) head-mounted devices, etc.) or other wearable devices, or any other type of computing and / or electronic device.

[0140] The programmable circuit system platform 1200 shown in the example includes a programmable circuit system 1212. The programmable circuit system 1212 shown in the example is hardware. For example, the programmable circuit system 1212 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired family or manufacturer. The programmable circuit system 1212 can be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit system 1212 implements a ramp generator circuit system 302A, a clock manager circuit system 304A, a PWM generator circuit system 320A, and / or more generally, a local controller circuit system 206 and / or more generally, a controller circuit system 202.

[0141] The programmable circuit system 1212 of the example shown includes local memory 1213 (e.g., cache, registers, etc.). The programmable circuit system 1212 of the example shown communicates via bus 1218 with main memories 1214, 1216, including volatile memory 1214 and non-volatile memory 1216. Volatile memory 1214 may be implemented by synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS® dynamic random access memory (RDRAM®), and / or any other type of RAM device. Non-volatile memory 1216 may be implemented by flash memory and / or any other desired type of memory device. Access to the main memories 1214, 1216 of the example shown is controlled by a memory controller 1217. In some examples, the memory controller 1217 may be implemented by one or more integrated circuits, logic circuits, microcontrollers, or any other type of circuit system from any desired family or manufacturer to manage data flow to and from the main memories 1214, 1216.

[0142] The programmable circuit system platform 1200 shown in the example also includes an interface circuit system 1220. The interface circuit system 1220 can be implemented in hardware according to any type of interface standard, such as an Ethernet interface, a Universal Serial Bus (USB) interface, a Bluetooth® interface, a Near Field Communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, and / or a Peripheral Component Interconnect High Speed ​​(PCIe) interface.

[0143] In the illustrated example, one or more input devices 1222 are connected to the interface circuitry 1220. The input devices 1222 allow users (e.g., human users, machine users, etc.) to input data and / or commands into the programmable circuitry 1212. The input devices 1222 may be implemented using, for example, audio sensors, microphones, cameras (still or video), keyboards, buttons, mice, touchscreens, trackpads, trackballs, isotope devices, and / or voice recognition systems.

[0144] One or more output devices 1224 are also connected to the interface circuitry 1220 of the illustrated example. The one or more output devices 1224 may be implemented, for example, by a display device (e.g., a light-emitting diode (LED), an organic light-emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, a home-switching (IPS) display, a touchscreen, etc.), a haptic output device, a printer, and / or a speaker. Therefore, the interface circuitry 1220 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or a graphics processor circuitry system such as a GPU.

[0145] The interface circuit system 1220 of the example shown also includes communication devices, such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces, to facilitate the exchange of data with external machines (e.g., any kind of computing device) via network 1226. Communication can be carried out via, for example, Ethernet connections, digital subscriber line (DSL) connections, telephone line connections, coaxial cable systems, satellite systems, out-of-line-of-sight wireless systems, line-of-sight wireless systems, cellular telephone systems, optical connections, etc.

[0146] The programmable circuit system platform 1200 illustrated also includes one or more mass storage disks or devices 1228 for storing firmware, software, and / or data. Examples of such mass storage disks or devices 1228 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray discs, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or devices, such as flash memory devices and / or SSDs.

[0147] It can be by Figure 10 and 11 The machine-readable instructions 1232 implemented by the machine-readable instructions may be stored in a mass storage device 1228, a volatile memory 1214, a non-volatile memory 1216 and / or on at least one non-transitory computer-readable storage medium such as a removable CD or DVD.

[0148] In this specification, the term "and / or" (when used in the form of, for example, A, B, and / or C) means any combination or subset of A, B, and C, such as (a) only A; (b) only B; (c) only C; (d) A and B; (e) A and C; (f) B and C; and (g) A, B, and C. Furthermore, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") means an embodiment comprising any of the following: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

[0149] In this description, the term "coupled" may encompass a connection, communication, or signaling path that enables the functional relationship to be consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B via a direct connection; or (b) in a second example, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0150] Numerical identifiers such as "first," "second," and "third" are used only to distinguish elements that are substantially the same type in terms of structure and / or function. These identifiers used in the specific embodiments may not necessarily be identical to those used in the claims.

[0151] A device “configured” to perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function during manufacturing by the manufacturer, and / or may be configured (or reconfigurable) by the user after manufacturing to perform the function and / or other additional or alternative functions. Configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of the device’s hardware components and interconnects, or through a combination thereof.

[0152] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless otherwise specified, these terms are generally used to refer to interconnects or terminals between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0153] The circuits or devices described herein as containing certain components can conversely be adapted to be coupled to components used to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may substantially contain only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure during or after manufacturing, for example, by an end user and / or a third party.

[0154] The circuits described herein are reconfigurable to include alternative components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent one or more elements coupled in series and / or in parallel to provide a certain amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component can actually be multiple resistors or capacitors respectively coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component can instead be multiple resistors or capacitors respectively coupled in series between the same two nodes as a single resistor or capacitor. While some components in the described examples are included in the integrated circuit and others are outside the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all features shown as being outside the integrated circuit may be included in the integrated circuit, and / or some features shown as being inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0155] The use of the phrase “grounding” in the foregoing description includes chassis grounding, earth grounding, floating grounding, virtual grounding, digital grounding, common grounding and / or any other form of grounding connection applicable to or suitable for the teachings of this specification.

[0156] As used herein, recognizing the variations that may occur in real-world applications, the terms "approximately" and "about" are used to modify objects / values. For example, "approximately" and "about" may modify dimensions that may be imprecise due to manufacturing tolerances, signal propagation delays, and / or other real-world imperfections, as will be understood by one of ordinary skill in the art. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means that the value differs from the stated value by no more than + / - 10%, or, if the value is zero, that it is within a reasonable range of values ​​near zero.

[0157] Within the scope of the claims, the described embodiments may be modified, and other embodiments are possible.

[0158] Based on the foregoing, it should be understood that example systems, apparatuses, articles, and methods have been described that synchronize the outputs of power stage circuits while also using harmonic modulation to correct V_FLY errors that can vary independently between power stage circuits. The described systems, apparatuses, articles, and methods improve the efficiency of using computing devices by using a first clock signal of two globally synchronized clock signals, wherein a local controller circuit connected to the power stage circuit with the smallest amplitude V_FLY error first excites its synchronization clock pulse, and causes all other synchronization controllers to excite pulses in the synchronization clock signal. Synchronization is then performed independently by exciting pulses in the second clock signal at specific times based on when pulses in the first clock signal are excited (thus achieving a net increase or decrease in charge on the flying capacitor required to correct and / or mitigate V_FLY errors). Therefore, the described systems, apparatuses, articles, and methods also relate to one or more improvements in the operation of machines such as computers or other electronic and / or mechanical devices.

[0159] The appended claims are hereby incorporated by reference in this detailed description. While certain example systems, devices, articles of manufacture, and methods have been described herein, the scope of this patent is not limited thereto. Rather, this patent covers all systems, devices, articles of manufacture, and methods that fall within the scope of the claims of this patent.

Claims

1. A device for controlling a power stage circuit, the device comprising a programmable circuit system configured to: In response to a command from an external controller, a pulse in a first local clock signal is generated when the flying capacitor in the power stage circuit has discharged for a discharge cycle less than a threshold time; and A pulse in a second local clock signal is generated after the flying capacitor has been charged for one charging cycle, wherein the length of the charging cycle is based on the length of the discharging cycle.

2. The device according to claim 1, wherein: The power stage circuit is the first power stage circuit; The external controller corresponds to a second power stage circuit with a second error; The first power stage circuit has a first error, which is proportional to the difference between the length of the charging cycle and the length of the discharging cycle; and The programmable circuit system is configured to receive the instruction from the external controller before the threshold time amount, because the second error is less than the first error.

3. The device according to claim 2, wherein: The programmable circuit system is used to generate one or more pulses in the first local clock signal and the second local clock signal, such that the duty cycle of the discharge cycle and the first disconnection cycle in the first power stage circuit is equal to the duty cycle of the charging cycle and the second disconnection cycle in the first power stage circuit; and The total length of the discharge cycle, the first disconnection cycle, the charging cycle, and the second disconnection cycle of the first power stage circuit is longer than the total length of the corresponding cycle in the second power stage circuit because the second error is smaller than the first error.

4. The device according to claim 1, wherein: The power stage circuit is the first power stage circuit; The external controller corresponds to the second power stage circuit; The first power stage circuit delivers power to the load based on pulses in the first local clock signal and the second local clock signal; The second power stage circuit delivers power to the load based on pulses from the first and second external clock signals; and The programmable circuit system is used to synchronize the generation of pulses in the first local clock signal with the generation of pulses in the first external clock signal based on the instructions.

5. The device according to claim 1, wherein: The pulse in the first local clock signal is the first synchronization pulse; The pulse in the second local clock signal is a first harmonic modulation pulse; and The programmable circuit system is used to excite the first harmonic modulation pulse before exciting the second synchronization pulse.

6. The device according to claim 5, wherein: The first synchronization pulse and the first harmonic modulation pulse correspond to the first cycle; The second synchronization pulse and the second harmonic modulation pulse correspond to the second cycle; The error in the power stage circuit during the second cycle is less than the error in the power stage circuit during the first cycle; and The length of the first loop is greater than the length of the second loop.

7. An apparatus comprising: The comparator circuit system is configured as follows: Receive a ramp signal having a slope modulated proportionally to the discharge period of the flying capacitor in the power stage circuit; and In response to determining that the ramp signal exceeds the reference voltage, an output voltage is generated; as well as A clock generator circuit system is used for: In response to determining that the comparator circuitry generates the output voltage before the external controller generates a pulse in the external clock signal, a pulse in the first local clock signal is generated; In response to generating the pulse in the first local clock signal, the external controller generates the pulse in the external clock signal; as well as A pulse in a second local clock signal is generated after the flying capacitor has been charged for one charging cycle, wherein the length of the charging cycle is based on the length of the discharging cycle.

8. The device according to claim 7, wherein: The power stage circuit is a first power stage circuit and the flying capacitor is a first flying capacitor. The first power stage circuit has a first error, which is proportional to the difference between the length of the charging cycle and the length of the discharging cycle. The external controller is a second power stage circuit with a second error based on a second flying capacitor; and The clock generator circuit system is also used to generate the output voltage based on the comparator circuit system before the pulse in the external clock signal generated by the external controller, and to determine that the first error is less than the second error.

9. The device according to claim 8, wherein: The clock generator circuit system is used to generate one or more pulses in the first local clock signal and the second local clock signal, such that the duty cycle of the discharge cycle and the first disconnection cycle in the first power stage circuit is equal to the duty cycle of the charging cycle and the second disconnection cycle in the first power stage circuit; and The total length of the discharge cycle, the first disconnection cycle, the charging cycle, and the second disconnection cycle of the first power stage circuit is shorter than the total length of the corresponding cycle in the second power stage circuit because the first error is smaller than the second error.

10. The device according to claim 8, wherein: The first power stage circuit delivers power to the load based on pulses in the first local clock signal and the second local clock signal; The external clock signal is the first external clock signal; and The second power stage circuit delivers power to the load based on pulses in the first and second external clock signals.

11. The device of claim 7, further comprising a ramp generator circuit system for changing the slope of the ramp signal based on an error in the flying capacitor.

12. The device according to claim 7, wherein: The pulse in the first local clock signal is the first synchronization pulse; The pulse in the second local clock signal is a first harmonic modulation pulse; and The comparator circuit system is used to excite the first harmonic modulation pulse before exciting the second synchronization pulse.

13. The device according to claim 12, wherein: The first synchronization pulse and the first harmonic modulation pulse correspond to the first cycle; The second synchronization pulse and the second harmonic modulation pulse correspond to the second cycle; The error in the flying capacitor during the second cycle is less than the error in the flying capacitor during the first cycle; and The length of the first loop is greater than the length of the second loop.

14. A method comprising: Receive a ramp signal having a slope modulated proportionally to the discharge period of the flying capacitor in the power stage circuit; In response to determining that the ramp signal exceeds the reference voltage, an output voltage is generated; In response to generating the output voltage before the external controller generates a pulse in the external clock signal, a pulse in the first local clock signal is generated; In response to generating the pulse in the first local clock signal, the external controller generates the pulse in the external clock signal; as well as A pulse in a second local clock signal is generated after the flying capacitor has been charged for one charging cycle, wherein the length of the charging cycle is based on the length of the discharging cycle.

15. The method of claim 14, wherein: The power stage circuit is a first power stage circuit and the flying capacitor is a first flying capacitor. The first power stage circuit has a first error, which is proportional to the difference between the length of the charging cycle and the length of the discharging cycle. The external controller is a second power stage circuit with a second error based on a second flying capacitor; and The method further includes generating the output voltage based on the external controller generating the pulse in the external clock signal before the external controller generates the output voltage, and determining that the first error is less than the second error.

16. The method of claim 15, wherein: The method further includes generating one or more pulses in the first local clock signal and the second local clock signal, such that the duty cycle of the discharge cycle and the first disconnection cycle in the first power stage circuit is equal to the duty cycle of the charging cycle and the second disconnection cycle in the first power stage circuit; and The total length of the discharge cycle, the first disconnection cycle, the charging cycle, and the second disconnection cycle of the first power stage circuit is shorter than the total length of the corresponding cycle in the second power stage circuit because the first error is smaller than the second error.

17. The method of claim 15, wherein: The external clock signal is the first external clock signal; and The method further includes: Based on the pulses in the first local clock signal and the second local clock signal, power is delivered to the load using the first power stage circuit. as well as Power is delivered to the load using the second power stage circuit based on pulses in the first and second external clock signals.

18. The method of claim 14, further comprising changing the slope of the ramp signal based on an error in the flying capacitor.

19. The method of claim 14, wherein: The pulse in the first local clock signal is the first synchronization pulse; The pulse in the second local clock signal is a first harmonic modulation pulse; and The method further includes exciting the first harmonic modulation pulse before exciting the second synchronization pulse.

20. The method of claim 19, wherein: The first synchronization pulse and the first harmonic modulation pulse correspond to the first cycle; The second synchronization pulse and the second harmonic modulation pulse correspond to the second cycle; The error in the flying capacitor during the second cycle is less than the error in the flying capacitor during the first cycle; and The length of the first loop is greater than the length of the second loop.

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