Programmable drive circuit for a tunable probabilistic bit array

Abstract

This application relates to a programmable drive circuit for tunable probability bits. A programmable drive circuit (54) and related method (600) for simultaneously controlling multiple tunable probability bit generators are disclosed. The drive circuit includes multiple programmable voltage generators (52; 30), a programming unit (35), and non-volatile memory cells (34a-b). The inputs of the multiple programmable voltage generators can be connected to a single voltage supply source. The programming unit is configured to generate programming pulse sequences for different voltage generators. Each voltage generator includes a single-stage or multi-stage voltage divider circuit (31) formed by a series of resistive elements (32-1; 32-2; 33). The non-volatile memory cells (34a-b) include at least a resistive element located at a first position in the series of resistive elements as a programmable resistor, and a programming control transistor (34-1) connected in series between the programmable resistor and a fixed reference voltage. The control gate of the programming control transistor is operatively coupled to the programming unit to receive a programming pulse sequence for the programmable voltage generator when operating in programming mode.

Description

Technical Field

[0001] This invention generally relates to the field of random bit generation, and more specifically, to a programmable electronic drive circuit that assists in generating multiple tunable probability bits in hardware. Background Technology

[0002] In the article "p-bits for probabilistic spin logic" by Kerem Y. Camsari, Brian M. Sutton, and Supriyo Datta, Appl. Phys. Rev. 2019 Mar 1;6 (1): 011305, the authors describe p-bit-based circuits that require a programmable input voltage for each p-bit.

[0003] Programmable analog voltage sources are needed to generate all the different analog voltage signals simultaneously. A drawback of using traditional programmable analog voltage sources is the requirement for a high fan-out, which increases quadratically with the number of p-bits in the circuit. Furthermore, the design and layout of the routing network becomes complex due to the large amount of wiring required, and the number of wires also increases quadratically with the number of p-bits that require averaging. Summary of the Invention

[0004] One object of this invention is to provide a simpler electronic drive circuit for simultaneously controlling multiple tunable probability bit generators, which does not require a voltage source with a high fan-out. Another object of this invention is to provide a simpler electronic drive circuit for simultaneously controlling multiple tunable probability bit generators, which requires fewer wire connections for voltage signal distribution to the probability bit generators.

[0005] The above objectives are achieved by the device and method according to the present invention.

[0006] In one aspect, the present invention relates to a programmable drive circuit for simultaneously controlling multiple tunable probability bit generators. Each probability bit generator has an input for individually controlling the statistical expectation of the probability bits generated by the probability bit generator. The drive circuit includes multiple programmable voltage generators and a programming unit configured to generate a programming pulse sequence based on a target level of the output signal to be generated by each voltage generator. Each voltage generator has an input and an output and is configured to generate a corresponding output signal of the drive circuit when the voltage generator operates in drive mode. The inputs of the multiple programmable voltage generators can be commonly connected to a single voltage supply source, and the output of each voltage generator can be directly connected to the input of a corresponding one of the multiple tunable probability bit generators for driving the output signal generated by the voltage generator to that tunable probability bit generator. Furthermore, each voltage generator includes a single-stage or multi-stage voltage divider circuit formed by a series of resistive elements. A resistive element located at a first position in this series of resistive elements is operatively connected to the input for receiving a supply voltage from a single voltage supply source. The last resistor in the series is operatively connected to a fixed reference voltage. The output of the voltage generator is operatively coupled to an electrical connection between two consecutive resistors in the series, whereby, when the voltage generator operates in drive mode, the voltage signal at the electrical connection between these two consecutive resistors determines the output signal. Each voltage generator also includes a non-volatile memory cell comprising at least one resistor in the first position of the series as a programmable resistor, and a programming control transistor connected in series between the programmable resistor and the fixed reference voltage. The control gate of the programming control transistor is operatively coupled to a programming unit to receive a sequence of programming pulses for the programmable voltage generator when operating in programming mode.

[0007] In another aspect, the present invention relates to an apparatus for generating a plurality of tunable probability bits (or p-bits), the apparatus comprising a plurality of tunable probability bit generators, a single voltage supply source, and a programmable drive circuit according to an embodiment of the foregoing aspect. Each probability bit generator has an input for individually controlling the statistical expectation of the probability bits generated by the probability bit generator. The inputs of the plurality of programmable voltage generators of the programmable drive circuit are commonly connected to the single voltage supply source. The output of each voltage generator of the programmable drive circuit is directly connected to the input of a corresponding one of the plurality of tunable probability bit generators for driving the output signal generated by the voltage generator to that tunable probability bit generator.

[0008] In another aspect, the present invention relates to a method of operating a drive circuit according to an embodiment of the foregoing aspects. The method includes the following steps: A single voltage supply signal is supplied to the input terminals of the plurality of programmable voltage generators; Connect the resistor element located at the first position in the series of resistor elements of each voltage generator to the input terminal of the voltage generator; Connect the last resistor in the series of resistors in each voltage generator to a fixed reference voltage; and Disconnect the control gate of each programmable control transistor in each voltage generator from the programming unit.

[0009] Operating the drive circuit can be a method of controlling the mean associated with each of the multiple probability bit generators, the method including the following further steps: Multiple tunable probability bit generators are provided, each probability bit generator having an input for individually controlling the statistical expectation of the probability bits generated by the probability bit generator; The output signal generated by each voltage generator is driven to the input of a corresponding one of the plurality of tunable probability bit generators.

[0010] One method of operating the drive circuit is to program the mean associated with each of the multiple probability bit generators, the method including the following further steps: Select one voltage generator from a plurality of programmable voltage generators to program a target level for the output signal to be generated by that voltage generator when operating in drive mode; Generate a programming pulse sequence based on the target level of the output signal of the voltage generator selected in the previous step; Disconnect the resistor element located at the last position in the series of resistor elements in the selected voltage generator from the fixed reference voltage; The programming units are sequentially coupled to the control gates of different programming control transistors in the selected voltage generator, and each control gate is driven by the programming pulse sequence or a portion of the programming pulse sequence generated in the previous step, thereby turning on and off the programming current flowing through the programmable resistor addressed by the programming control transistor.

[0011] The method of programming the mean associated with each of the multiple probability bit generators can be executed before the method steps related to controlling and the mean associated with each of the multiple probability bit generators.

[0012] Specific and preferred aspects of the invention are set forth in the appended independent and dependent claims. Features from the dependent claims may be suitably combined with features of the independent claims and other dependent claims, not merely as expressly set forth in the claims.

[0013] For the purpose of summarizing the invention and its advantages over the prior art, certain objects and advantages of the invention have been described above. It should be understood, of course, that not all such objects or advantages may be achieved according to any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention can be embodied or practiced in a manner that achieves or optimizes one or more advantages as taught herein, without necessarily achieving other objects or advantages as may be taught or suggested herein.

[0014] The above and other aspects of the invention will be apparent from the embodiments described below and will be illustrated with reference to the embodiments. Attached Figure Description

[0015] The invention will now be further described by way of example with reference to the accompanying drawings, in which: Figure 1 A prior art driving circuit is shown that is suitable for simultaneously controlling multiple tunable probability bit generators.

[0016] Figures 2 to 4 These are circuit diagrams of different programmable voltage generators that can be used in the drive circuits according to embodiments of the present invention.

[0017] Figure 5 A driving circuit for simultaneously controlling multiple tunable probability bit generators is shown according to an embodiment of the present invention.

[0018] Figure 6 The steps of a method for simultaneously controlling multiple tunable probability bit generators are shown.

[0019] These accompanying drawings are merely illustrative and not restrictive. In the drawings, some elements may be enlarged and not drawn to scale for illustrative purposes. Scale and relative scale do not necessarily correspond to an actual simplification of the practice of this invention.

[0020] Any reference numerals in the claims should not be construed as limiting the scope.

[0021] In different accompanying drawings, the same reference numerals refer to the same or similar elements. Detailed Implementation

[0022] The invention will be described with reference to specific embodiments and certain accompanying drawings, but the invention is not limited thereto, but is limited only by the claims.

[0023] The directional terms such as top, bottom, front, back, beginning, end, lower, and upper in the specification and claims are used for illustrative purposes with reference to the orientation of the described drawings and are not necessarily used to describe relative positions. Since the components of the embodiments of the invention can be positioned in many different orientations, the directional terms are for illustrative purposes only and do not constitute a limitation of the invention unless otherwise stated. Therefore, it is to be understood that the terms thus used are interchangeable where appropriate, and the embodiments of the invention described herein can operate in orientations different from those described or illustrated herein.

[0024] It should be noted that the term "comprising" as used in the claims should not be construed as limiting itself to the means listed thereafter; it does not exclude other elements or steps. Therefore, the term should be interpreted as specifying the presence of the features, integers, steps, or components stated as mentioned, but does not exclude the presence or addition of one or more other features, integers, steps, or components, or groups thereof. Thus, the scope of a description of an apparatus comprising "A and B" should not be limited to an apparatus consisting solely of components A and B. This means that for the present invention, the only relevant components of the apparatus are A and B.

[0025] Throughout this specification, the reference to "an embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. Therefore, the appearance of the phrase "an embodiment" or "in one embodiment" in various places throughout this specification does not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, as will be apparent to those skilled in the art from this disclosure, particular features, structures, or characteristics may be combined in any suitable manner.

[0026] Similarly, it should be understood that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, drawing, or description for the purpose of simplification and to aid in understanding one or more of the various inventive aspects. However, this approach of the disclosure should not be construed as reflecting an intention to claim more features than are expressly recited in each claim. Rather, as reflected in the appended claims, inventive aspects lie in fewer features than all the features of a single foregoing disclosed embodiment. Therefore, the appended claims are thus explicitly incorporated into this detailed description, wherein each claim itself represents a separate embodiment of the invention.

[0027] Furthermore, although some embodiments described herein include some features included in other embodiments but not all other features included in those other embodiments, as will be understood by those skilled in the art, combinations of features from different embodiments are intended to fall within the scope of the invention and form different embodiments.

[0028] Numerous specific details are set forth in the description provided herein. However, it should be understood that embodiments of the invention can be practiced without these specific details. In other instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0029] Electronic circuits known in the art for simultaneously controlling multiple tunable probability bits rely on programmable analog voltage sources to simultaneously generate different analog signals that control the mean (statistical expectation) of each probability bit generator. Figure 1 An example of such a prior art drive circuit 10 is shown, wherein an analog voltage source 11 provides up to 'p' voltage signals V1, V2, ..., Vp of different amplitudes as output signals. A wiring network 12 and a selection stage 13 are connected between the analog voltage source 11 and the probability generator array 14, and are used to distribute the p output signals to each of the probability bit generators 14-1 to 14-n. More specifically, the wiring 15 of the 'p' different output signals is routed to a corresponding multiplexing circuit of the selection stage 13 located before each probability bit generator in the array, so as to select the output signal from the wiring of the output signal required to drive that probability bit generator by an appropriate selection signal. In this prior art embodiment, selection signals SEL1, ..., SELn are provided to select the corresponding voltage signals VD1, VD2, ..., VDn from the wiring of the corresponding voltage source output signals, which are driven to the respective probability bit generators 14-1 to 14-n of the array 14. One drawback of this type of drive circuit is that it requires an analog voltage source with a high fan-out, which increases quadratically with the number of probability generators in the array. Furthermore, the design and layout of the routing network becomes complex due to the need for extensive wiring, and the number of wires also increases quadratically with the number of probability bit generators in the array.

[0030] Therefore, the inventors are committed to overcoming the above-mentioned shortcomings and providing a simpler electronic drive circuit for simultaneously controlling multiple tunable probability bit generators. This circuit does not require a single voltage source to generate output signals with different voltage amplitudes and requires fewer wire connections to distribute the voltage signals to the probability bit generators.

[0031] In embodiments of the invention, this is achieved by providing a separate programmable (single) voltage generator for each tunable probability bit generator to be controlled. Each programmable voltage generator, for example, is supplied with an output signal (e.g., output voltage or output current) suitable for controlling the statistical expectation of the probability bit sequence generated by the individual tunable probability bit generator, via a control input terminal of the probability bit generator. That is, when operating in drive mode, the output signal voltage / current supplied by the programmable voltage generator is used as a control signal that causes tuning of the statistical expectation of the probability bit sequence generated by the tunable probability bit generator receiving the output voltage from the programmable voltage generator. A plurality of programmable voltage generators, which can be powered by a common supply voltage, are then provided to drive a corresponding tunable probability bit generator in a plurality of tunable probability bit generators (e.g., an array of tunable probability bit generators). Each programmable voltage generator includes a voltage divider circuit consisting of a series of resistive elements arranged in one or more voltage divider stages. A voltage divider stage of the voltage divider circuit is defined as a single resistive element or group of resistive elements from which a voltage signal can be extracted. In other words, each voltage divider stage is associated with a signal tap that supplies a voltage signal, which is a (divided) portion of the input voltage signal applied across the entire voltage divider circuit. The resistor element of the first voltage divider stage, located at a first position in a series of resistor elements in the voltage divider circuit, is operatively connected to the input of a programmable voltage generator for receiving a common supply voltage, which is, for example, a voltage generated by a single voltage source shared by all programmable voltage generators in the drive circuit. Therefore, the inputs of multiple programmable voltage generators can be commonly connected to a single voltage supply source. The resistor element at the last position in the series of resistor elements in the voltage divider circuit is operatively connected to a fixed reference voltage, for example, the ground level of the drive circuit. The output of the programmable voltage generator can be directly connected to the input of a corresponding one of multiple tunable probability bit generators, which supplies the output signal to be driven to the corresponding tunable probability bit generator when the programmable voltage generator is operating in drive mode. The output terminal is operatively coupled to an electrical connection between two consecutive resistive elements in a series of resistive elements in a voltage divider circuit. Thus, when the voltage generator is operated in drive mode, the voltage signal at the electrical connection between these two consecutive resistive elements determines the output signal at the output terminal. Typically, the output terminal is operatively coupled to an electrical connection between the resistive element of the last programmable voltage divider stage and a reference resistor (e.g., a fixed resistor) that serves as the last resistive element in the series of resistive elements in the voltage divider circuit. Alternatively, the output terminal is operatively coupled to an electrical connection between the resistive element of the last programmable voltage divider stage and the resistive element of the first non-programmable voltage divider stage.

[0032] At least the first voltage divider stage of the voltage divider circuit is programmable; that is, the resistive element of the first stage is a programmable resistor. The programmable voltage divider stage of the voltage divider circuit is associated with a non-volatile memory cell of a non-volatile memory unit. More specifically, each memory cell of the memory unit includes a programmable resistor of the programmable voltage divider stage and a programming control transistor connected in series between the programmable resistor and a fixed reference voltage (e.g., ground level of the drive circuit). When the programmable voltage generator operates in programming mode, the control gate of the programming control transistor is operatively coupled to the programming unit. This allows programming of the programmable resistor of the memory cell. That is, the resistance value of the programmable resistor of the memory cell can be set to a desired resistance value determined by a sequence of programming pulses received at the control gate of the programming control transistor of the programmable voltage generator when operating in programming mode. Furthermore, the programming unit of the drive circuit is configured to generate a sequence of programming pulses based on a target output level of the output signal to be generated by each voltage generator. The programming unit can generate one or more programming pulse sequences for each programmable voltage generator, depending on the number of programmable voltage divider stages of the voltage divider circuit and the currently programmed resistance values ​​associated with those voltage divider stages. If the programming unit generates different programming pulse sequences for one of the programmable voltage generators with multiple programmable voltage divider stages, one or more components of the selection circuit of the drive circuit (under the control of the programming unit or a separate control unit) can be used to individually address different control gates of the programming control transistor of the programmable voltage generator and apply different programming pulse sequences sequentially to the corresponding control gates of the programming control transistor.

[0033] A programmable voltage generator according to embodiments of the present invention solves the problem of the quadratic increase in the number of wiring wires in the prior art. The programmable voltage generators of the driving circuit can be commonly connected to a single voltage supply source, and the number of wires increases only linearly with the number of programmable voltage generators, and therefore also linearly with the number of probability bit generators that need to be controlled. Furthermore, a specially designed and / or programmable voltage supply source shared by the programmable voltage generators is not required. A simpler voltage supply source that only delivers a single (e.g., fixed) supply voltage level can be used instead. Moreover, complex selection circuitry is not required to select among multiple different output voltages, because each programmable voltage generator of the driving circuit is directly supplied with one of the different output voltages required for the statistical expectation of the probability bit sequence generated by the control probability bit generator. The present invention also provides a method for decoupling the tuning stage and sampling stage for probability bits into different functional circuits.

[0034] The programmable voltage generator according to embodiments of the invention can be advantageously used as a basic building block. A replica of this building block can then be used to assemble a complete drive circuit, allowing for simplified design. Furthermore, faulty voltage generators in the drive circuit can be detected and discarded during use, for example, disabled or deactivated when the drive circuit is operating in drive mode, without completely impairing the desired control functionality of the drive circuit with respect to the tunable probability bit generator.

[0035] The programmable voltage generator according to the embodiment can be programmed on demand, and the programmed resistance value is then persistently stored in the voltage divider circuit. If the drive circuit and its programmable voltage generator are temporarily disabled, reprogramming is not required. This saves energy and allows the drive circuit to operate quickly in drive mode after a static phase. Furthermore, the programmable resistors of the memory cells associated with the programmable voltage divider stages of the voltage divider circuit can be programmed very precisely.

[0036] In embodiments of the invention, the control unit of the drive circuit can be configured to switch the operating mode of the drive circuit between a drive mode and a programming mode. The control unit can be configured to generate a set of control signals for each operating mode and apply these control signals to the programmable voltage generator and the programming unit. In some embodiments of the invention, the control unit can also act as the programming unit of the drive circuit. The drive circuit according to embodiments of the invention may include more than one programming unit, for example, multiple programming units, wherein each programming unit is operatively coupled to a subset of multiple programmable voltage generators. This allows for faster, parallel programming of a subset of the programmable voltage generators, for example, parallel programming of all programmable voltage generators.

[0037] According to some embodiments of the invention, at least one programmable voltage generator in the drive circuit, for example, each programmable voltage generator, may include a voltage follower circuit, a current follower circuit, or a transconductance amplifier circuit inserted between the output terminal of the programmable voltage generator and an electrical connection, the electrical connection being between two consecutive resistive elements of a series of resistive elements in the programmable voltage generator. This has the beneficial effect of isolating the output signal from the voltage signal at the electrical connection between two consecutive resistive elements of the series of resistive elements in the programmable voltage generator. The current flowing through the series of resistive elements of the voltage divider circuit becomes virtually independent of the load current flowing into the corresponding probability bit generator. Therefore, the magnitude of the current flowing through the series of resistive elements of the voltage divider circuit can be made very small by designing the voltage divider circuit, thereby reducing the power consumption of the drive circuit when operating in drive mode. Similarly, if the output signal is isolated from the voltage signal at the electrical connection between two consecutive resistive elements of the series of resistive elements in the programmable voltage generator, the output signal variation caused by the variation of the load impedance (e.g., the input impedance of the probability bit generator) which varies as a function of the mean of the tuning parameters is greatly reduced or completely suppressed.

[0038] According to some embodiments of the invention, each programmable voltage generator of the drive circuit may further include a pair of access transistors: a first access transistor for operatively connecting a resistor element located at a first position in the series of resistor elements to a single voltage supply source; and a second access transistor for operatively connecting a resistor element located at the last position in the series of resistor elements to a fixed reference voltage. This allows for the controllable enabling and disabling of the output signal at the output terminal of each programmable voltage generator in the drive circuit, as well as any current flowing through the voltage divider circuit of each programmable voltage generator in the drive circuit. If the drive circuit operates in drive mode, the pair of access transistors is enabled (i.e., turned on, in conduction mode). A power-saving static mode of the drive circuit may correspond to the case where the access transistors are disabled (i.e., turned off, in non-conducting mode).

[0039] In embodiments of the invention, the common supply voltage can be adjusted to adapt the drive circuit to different input ranges possible at the control inputs of the probability bit generator, depending on the target application and / or hardware used to implement the probability bit generator requiring tuning. Alternatively, additional resistive elements (e.g., resistors) can be inserted into a series of resistive elements in the voltage divider circuit, which also provides the effect of adapting the output range of the output signals generated at the outputs of the multiple programmable voltage generators of the drive circuit. For example, the programmable resistor of the first voltage divider stage of the voltage divider circuit can be a composite resistor comprising a programmable resistive element and a resistor in series; or, an additional resistor can be added to a reference resistor that is the last resistive element in a series of resistive elements operably connected to a fixed reference voltage. In this case, the reference resistor is a composite resistor comprising the last resistive element in the series of resistive elements and one or more additional resistive elements (e.g., resistors).

[0040] In embodiments of the invention, the programmable resistor of the non-volatile memory cell associated with the programmable voltage divider stage of the voltage divider circuit in each programmable voltage generator of the drive circuit can be one of the following elements: a memristor based on phase-change memory, a memristor based on resistive RAM, or a memristor based on bridge RAM. These types of programmable resistor elements allow their resistance values ​​to be precisely programmed to any analog value contained within a continuous range of permissible resistance values ​​(e.g., a permissible range of analog programmable resistance values ​​between a minimum resistance value and a maximum resistance value).

[0041] In embodiments of the invention, the programmable resistor of the non-volatile memory cell associated with the programmable voltage divider stage of the voltage divider circuit in each programmable voltage generator of the drive circuit can be a switchable magnetoresistive element, such as the magnetoresistive element of a magnetic tunnel junction (MTJ). In this case, the resistance value of the programmable resistor element can be digitally programmed to one or more intermediate resistance values ​​within a permissible range of resistance values ​​(i.e., a discrete set of resistance values ​​between the minimum and maximum resistance values).

[0042] Now for reference Figure 2A programmable voltage generator is described, which can be used in a drive circuit according to an embodiment of the present invention. The programmable voltage generator 20 includes a single-stage voltage divider circuit 21, which consists of two series-connected resistive elements 22 and 23. The first resistive element 22 of the voltage divider circuit 21 is associated with a first and only voltage divider stage 21-1 of the single-stage voltage divider circuit 21. This first voltage divider stage is programmable, i.e., its resistance can be changed by programming. A first terminal of the first resistive element 22 is connected to an input terminal 29-1 of the programmable voltage generator 20, which is connected to a supply voltage 'VDD'. A second terminal of the first resistive element 22 is electrically connected to a first terminal of a second resistive element 23. This second resistive element 23 may be a fixed reference resistor, for example, a fixed reference resistor. An access transistor 27 operatively connects the second terminal of the second resistive element 23 to a fixed reference voltage of the drive circuit, for example, ground level 'GND' in this embodiment. When driven to the control gate of access transistor 27, the enable signal 'EN' turns on the access transistor, thereby coupling the second resistive element 23 to the fixed reference voltage 'GND'. Access transistor 27 can be of any size. The purpose of access transistor 27 is to limit leakage current and provide individual programmability of the programmable voltage divider stage of the voltage divider circuit when the drive circuit operates in programmable mode. The output terminal 29-2 of programmable voltage generator 20 supplies the output signal 'OUT' when the drive circuit operates in drive mode. Output terminal 29-2 is directly connected to the electrical connection between the first resistive element 22 and the second resistive element 23. Therefore, the voltage signal 'V0' at this electrical connection directly determines the output voltage signal 'OUT' of the programmable voltage generator. The programmable voltage generator also includes a non-volatile memory cell, which in this embodiment consists of a single non-volatile memory cell 24. Non-volatile memory cell 24 includes a programmable first resistive element 22 and a programmable control transistor 24-1 connected between the second terminal of the first resistive element 22 and the fixed reference voltage 'GND'. When the drive circuit operates in programming mode, the programming signal 'VPRG' acts on the control gate of the programming control transistor 24-1, thereby controlling the programming current flowing from input 29-1 through the programmable resistor element 22 and the channel of the programming control transistor 24-1 to the fixed reference potential 'GND'. When the drive circuit operates in programming mode, the programming signal 'VPRG'—a series of programming voltage pulses—is provided by the programming unit 25. The programming unit 25, or a separate control unit of the drive circuit, determines the set of control signals required to switch operating modes (e.g., switching between drive mode and programming mode of the drive circuit). The programming unit 25 may be part of the programmable voltage generator 20, or it may be a global or semi-global programming unit of the drive circuit, meaning it is shared by all or a subset of programmable voltage generators in the drive circuit.

[0043] Figure 3Another programmable voltage generator is shown that can be used in a drive circuit according to an embodiment of the present invention. The programmable voltage generator 30 includes a two-stage voltage divider circuit 31, which consists of three series-connected resistive elements 32-1, 32-2, and 33. The first resistive element 32-1 and the second resistive element 32-2 of the voltage divider circuit 31 are respectively associated with the first voltage divider stage 31-1 and the second voltage divider stage 31-2 of the two-stage voltage divider circuit 31. Both the first voltage divider stage 31-1 and the second voltage divider stage 31-2 are programmable, i.e., their respective resistances can be changed by programming. A first terminal of the first resistive element 32-1 is operatively connected to the input terminal 29-1 of the programmable voltage generator 30 via a first access transistor 37-1, which is connectable to a supply voltage 'VDD'. A second terminal of the first resistive element 32-1 is connected to the first terminal of the second resistive element 32-2. The second terminal of the second resistive element 32-2 is electrically connected to the first terminal of the third resistive element 33. The third resistor element 33 can be a fixed (i.e., non-programmable) reference resistor, such as a fixed reference resistor. The second access transistor 37-2 operatively connects the second terminal of the third resistor element 33 to a reference voltage of the drive circuit, such as ground level 'GND' in this embodiment. When driven to the respective control gates of the first and second access transistors 37-1 and 37-2, the enable signal 'EN' turns on these two access transistors 37-1 and 37-2, thereby coupling the first resistor element 32-1 to the supply voltage 'VDD' and the third resistor element 33 to the fixed reference voltage 'GND', respectively. The output terminal 29-2 of the programmable voltage generator 30 supplies the output signal 'OUT' when the drive circuit operates in drive mode. The output terminal 29-2 is directly connected to the electrical connection between the second resistor element 32-2 and the third resistor element 33. Therefore, the voltage signal 'V0' at this electrical connection directly determines the output voltage signal 'OUT' of the programmable voltage generator. The programmable voltage generator also includes a non-volatile memory cell, which in this embodiment comprises two non-volatile memory cells 34a and 34b. Non-volatile memory cell 34a is associated with a first programmable voltage divider stage 31-1 and includes a programmable first resistor element 32-1 and a programmable control transistor 34-1 connected between the second terminal of the first resistor element 32-1 and a fixed reference voltage 'GND'. Similarly, non-volatile memory cell 34b is associated with a second programmable voltage divider stage 31-2 and includes a programmable second resistor element 32-2 and another programmable control transistor 34-2 connected between the second terminal of the second resistor element 32-2 and the fixed reference voltage 'GND'. When the drive circuit operates in programming mode, the programming signal 'VPRG' acts individually on the control gate of either the programmable control transistors 34-1 and 34-2, but not simultaneously on both.A second programming signal is applied to the control gate of the second programming control transistor 34-2, allowing control of a second programming current flowing from input 29-1 through the first and second programmable resistor elements 32-1, 32-2, and further through the channel of the second programming control transistor 34-2 to the fixed reference potential 'GND'. A first programming signal is applied to the control gate of the first programming control transistor 34-1, allowing control of a first programming current flowing from input 29-1 through the first programmable resistor element 32-1 and the channel of the first programming control transistor 34-1 to the fixed reference potential 'GND'. These two separately applicable programming signals 'VPRG' are programming voltage pulse sequences and are provided by the programming unit 35 when the drive circuit operates in programming mode. The programming control transistors of unprogrammed voltage divider stages are turned off, for example, by disconnecting their control gates from the programming unit or by configuring the programming unit to provide a voltage below a threshold to their control gates. This leaves the resistor elements of the unprogrammed voltage divider stages, as well as the resistor elements following the programmed voltage divider stages, in a floating state. Therefore, no programming current flows into those resistive elements. During the programming phase of the programmable voltage divider stage of the voltage divider circuit, the voltage applied to the control gate of the first access transistor 37-1 can be maintained above the threshold voltage or synchronized with the corresponding programming signal 'VPRG'. A separate control unit of programming unit 35 or drive circuit 30 determines the set of control signals required to switch operating modes (e.g., switching between drive mode and programming mode of the drive circuit). Programming unit 35 can be part of programmable voltage generator 30 or can be a global or semi-global programming unit of drive circuit, meaning it is shared by all or a subset of programmable voltage generators in drive circuit. In this embodiment, appropriate selection logic circuitry 36, such as a multiplexer or multiplexer tree structure, can be used to direct or route programming signals to the intended memory cell. Programming unit 35 can combine different programming signals 'VPRG' to generate selection signals 'SEL' for selection logic circuitry 36.

[0044] Figure 4 Another variation of the programmable voltage generator 40, which can be used in the drive circuit described in the embodiments of this application, is shown. Figure 2The voltage generator differs in that an additional access transistor 37-1 is provided between the first resistive element 22 and the input terminal 29-1, which allows the output signal 'OUT' to be disabled whenever the access transistor 37-1 is turned off. Furthermore, the programmable voltage generator 40 includes an isolation unit 48 that isolates the output signal 'OUT' from the voltage 'V0' and stabilizes the output signal relative to changes in the input impedance associated with the probability bit generator. The isolation unit 48 can be one of the following: a voltage follower circuit, a voltage buffer, or a transimpedance amplifier.

[0045] Embodiments of the present invention are not limited to the single-stage or two-stage voltage divider circuits of the foregoing embodiments, but may include additional programmable and / or non-programmable voltage divider stages. As an example, each programmable voltage generator of a drive circuit according to another embodiment of the present invention may include N programmable voltage divider stages, followed by N-1 non-programmable voltage divider stages and a reference resistor as the last resistive element in a series of resistive elements. The resistors of these N programmable stages may be switchable magnetoresistors, such as MTJs, whose resistance values ​​can be individually set to one of a high-resistance state (R-HRS) and a low-resistance state (R-LRS). The resistors of these N-1 non-programmable voltage divider stages and the reference resistor may be selected to be equal to the value of the high-resistance state (R-HRS). The output signal 'VOUT' may be a voltage signal at the electrical connection between the Nth programmable voltage divider stage and the first non-programmable voltage divider stage. In such an embodiment, the output voltage may be a low output voltage VOUT(LOW) = VDD. (R-LRS) / (R-LRS + R-HRS) = VDD / TRM and high output voltage VOUT(HIGH) = VDD / 2 = VDD The value varies gradually between (R-HRS) / (R-HRS + R-HRS). Here, 'VDD' is the common supply voltage for each programmable voltage generator, and 'TMR' represents the tunnel magnetoresistance ratio TMR = [(R-HMS) – (R-LRS)] / (R-RLS). Therefore, the lower output voltage depends on the specified TMR parameter of the MTJ used as the programmable resistor. Although an example using N identical MTJs as programmable resistors has been discussed, this choice is not limiting. Other embodiments of the invention may include N different MTJs as programmable resistors, for example, they may have different TMR coefficients and / or different resistance values ​​in one or both of the high-resistance and low-resistance states. Similarly, the number of non-programmable voltage divider stages may be different from N-1; for example, fewer or more non-programmable voltage divider stages may be feasible. Furthermore, non-programmable voltage divider stages may also include MTJs, but these are not programmable, for example, they are not connected in series with the programmable control transistor, and therefore are not part of the memory cell as understood in the context of this invention.

[0046] In the programmable voltage generator of the foregoing embodiments, only one resistive element is shown for each voltage divider stage. Nevertheless, multiple consecutive resistive elements of the voltage divider circuit can be grouped together to form a voltage divider stage of the voltage divider circuit, for example, forming a distributed resistor with respect to the voltage divider stage of the voltage divider circuit.

[0047] In embodiments of the invention where programmable resistors can be programmed in an analog manner (i.e., a continuous sequence of resistance values ​​can be programmed), a single-stage voltage divider circuit may be sufficient. Memristors based on phase-change memory, resistive RAM, or bridge RAM can be used as programmable resistive elements for memory cells associated with a single programmable voltage divider stage. Therefore, the output signal can vary continuously within a permissible output signal range.

[0048] In embodiments of the invention that use discrete programmable resistive elements (e.g., switchable two- or multi-stage magnetoresistive elements) in the memory cells associated with the programmable voltage divider stages of the voltage divider circuit, the resulting output signal can only be changed incrementally. Therefore, it is advantageous to increase the number of achievable output signal levels and output signal resolution by selecting a multi-stage voltage divider circuit instead of a single-stage voltage divider circuit.

[0049] Figure 5A driving circuit according to an embodiment of the present invention is shown. The driving circuit 54 includes a voltage source 51 and a plurality of programmable voltage generators 52-1 to 52-4, which can be implemented as described above. The voltage source 51 supplies a single supply voltage 'VDD', which is common to all programmable voltage generators 52-1 to 52-4. The inputs of the plurality of programmable voltage generators 52-1 to 52-4 are commonly connected to the output of the voltage source 51. The output of each programmable voltage generator 52-1 to 52-4 is connected to a control input connector of a corresponding one of the plurality of probability bit generators 53-1 to 53-4. Therefore, when the driving circuit 54 operates in driving mode, the output signals of the programmable voltage generators are driven to the corresponding control input connectors of the probability bit generators. When the driving circuit 54 operates in programming mode or static mode (i.e., power-saving mode), the output signals are disabled. The driving circuit 54 also includes a global programming unit 55 and a control unit 56. Programming unit 55 is configured to generate a programming pulse sequence based on the target output level of the output signal to be generated by each voltage generator 52-1 to 54-1. When a programmable voltage generator to be programmed is selected, programming unit 55 can sequentially address different memory cells of the selected voltage generator and apply the programming pulse sequence to the control gate of the programming control transistor of the addressed memory cell. Control unit 56 is configured to generate a set of control signals according to the operating mode of the drive circuit, including a drive mode and a programming mode. In embodiments of the invention, control unit 56 can directly or indirectly control the access transistors of programmable voltage generators 52-1 to 52-4 via programming unit 55.

[0050] The present invention also relates to an apparatus for generating a plurality of tunable probability bits, the apparatus comprising a driving circuit according to an embodiment of the invention, a single voltage supply source, and a plurality of tunable probability bit generators. The input of each probability bit generator allows individual control over the statistical expectation of the probability bits generated by that probability bit generator. Figure 5 A device 50 for generating multiple tunable probability bits is described. Tunable probability bit generators based on stacks of magnetic tunnel junctions formed above SOT orbitals (spin-orbit moments) have been described in, for example, in P. Debashis et al.'s "Gaussian Random Number Generator With Reconfigurable Mean and Variance Using Stochastic Magnetic Tunnel Junctions" (…). Gaussian random number generation with reconfigurable mean and variance using random magnetic tunnel junctions. instrumentThe effect of SOT current on the random switching behavior of the magnetoresistive field in the MJT stack is described in IEEE Magnetics Letters, vol. 13, pp. 1-5, 2022.

[0051] The present invention also relates to a method for simultaneously controlling the statistical expectation of a probability bit stream generated by multiple probability bit generators, the method using a driving circuit according to an embodiment of the foregoing aspects of the present invention. Reference Figure 6 The steps of the exemplary method 600 are briefly described.

[0052] Assuming the output signals of the programmable voltage generators have been correctly set to their target levels, in step 602, the control gate of the programming control transistor in the memory cell of each voltage generator is turned off. This may include disconnecting the control gate from the programming cell and / or applying a voltage below a threshold to the control gate. If one or more output signals of the programmable voltage generator are incorrect, programming step 601 is performed first. Then, in step 603, a common supply voltage is provided to the inputs of the plurality of programmable voltage generators in the drive circuit. Next, in step 604, a resistor element located at the first position in the series of resistor elements of each voltage generator is connected to the input of that voltage generator, and a resistor element located at the last position in the series of resistor elements of each voltage generator is connected to a fixed reference voltage. This may include, for example, turning on the access transistor of each voltage generator by applying an enable signal to the control gate of the access transistor of each voltage generator. If the drive circuit is no longer used to control the plurality of probability bits, the enable signal may be temporarily removed from the control gate of the access transistor of each voltage generator. This will disable the output signals of the voltage generator.

[0053] Programming step 601 includes the following sub-steps: In step 611, a voltage generator with an incorrect output signal is selected from a plurality of programmable voltage generators.

[0054] In step 612, a programming pulse sequence is generated according to the target level of the output signal to be supplied by the selected voltage generator.

[0055] In step 613, the last resistor in the series of resistors in the selected voltage generator is disconnected from the fixed reference voltage. This may include, for example, turning off the access transistor of the selected voltage generator by removing the enable signal from the control gate of the access transistor.

[0056] In step 614, the control gates of different programming control transistors in the memory cells of the selected voltage generator are sequentially driven using a programming pulse sequence or a partial programming pulse sequence, thereby turning on and off the programming current flowing through the programmable resistors addressed by the programming control transistors. During step 614, only the control gate of one programming control transistor is driven at a time by the programming pulse sequence or a partial programming pulse sequence, while the remaining programming control transistors of the selected voltage generator are turned off. Furthermore, throughout step 614, the resistor element located at the first position in the series of resistor elements of the selected voltage generator is operatively connected to the input terminal of the selected voltage generator. If an access transistor exists between the input terminal and the resistor element located at the first position in the series of resistor elements of the selected voltage generator, a constant voltage or programming pulse sequence above a threshold can be applied to the control gate of the access transistor.

[0057] For any other voltage generator whose output signal has not yet been set correctly, substeps 612 to 614 can be repeated.

[0058] In embodiments of the present invention, various programming schemes based on pulse sequences can be used, for example, in Figure 6 In step 614 of method 600. As an example, a suitable programming scheme for a discrete MTJ as a programmable resistor includes using a single write pulse with a predetermined pulse width in each programming pulse sequence / subsequence. On the other hand, a programmable resistor based on ReRAM or phase-change memory can use one of the following pulse programming schemes: pulse amplitude encoding, pulse width encoding, incremental write / verify pulse programming, or a combination thereof.

[0059] In an embodiment of the invention, the input of the selected voltage generator may receive a voltage different from the voltage applied to the input in drive mode.

[0060] The driving circuit according to embodiments of the present invention may further include a readout unit for detecting the magnitude of the output signal generated by different programmable voltage generators. This has the advantage that drift or offset in the output signal can be detected, and the programmable voltage divider stage can be reprogrammed for compensation based on an error signal indicating the amount of detected offset or drift. The readout unit is also useful in embodiments of the invention that use incremental write / verify pulse programming techniques.

[0061] This invention can be implemented in various ways and is not limited to the disclosed embodiments. By studying the drawings, this disclosure, and the appended claims, those skilled in the art can understand and implement other variations of the disclosed embodiments when practicing the claimed invention. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite articles "a" or "an" do not exclude a plural. The mere fact that certain measures are stated in mutually different dependent claims does not imply that combinations of these measures cannot be advantageously used. Any reference numerals in the claims should not be construed as limiting the scope.

Claims

1. A programmable drive circuit (54) for simultaneously controlling multiple tunable probability bit generators (53), each probability bit generator having an input for individually controlling the statistical expectation of probability bits generated by the probability bit generator, the drive circuit comprising: A plurality of programmable voltage generators (52; 30), each voltage generator having an input (29-1) and an output (29-2), are configured to generate a corresponding output signal of the drive circuit when operating in drive mode. The inputs of the plurality of programmable voltage generators can be connected to a single voltage supply source, and the output of each voltage generator can be directly connected to the input of a corresponding one of the plurality of tunable probability bit generators for driving the output signal generated by the voltage generator to the tunable probability bit generator. Programming unit (35), the programming unit being configured to generate a programming pulse sequence according to the target level of the output signal to be generated by each voltage generator; Each voltage generator includes: A single-stage or multi-stage voltage divider circuit (31) is formed by a series of resistive elements (32-1; 32-2; 33), wherein the resistive element at the first position in the series is operatively connected to the input terminal for receiving a supply voltage from the single voltage supply source, and the resistive element at the last position in the series is operatively connected to a fixed reference voltage, and the output terminal of the voltage generator is operatively coupled to an electrical connection between two consecutive resistive elements in the series, thereby, when the voltage generator operates in the drive mode, the voltage signal at the electrical connection between the two consecutive resistive elements determines the output signal at the output terminal; A non-volatile memory cell (34a-b) includes at least one of the resistive elements located at a first position in the series of resistive elements as a programmable resistor, and a programming control transistor (34-1) connected in series between the programmable resistor and the fixed reference voltage. The control gate of the programming control transistor is operatively coupled to the programming cell so as to receive the programming pulse sequence for the programmable voltage generator when operating in programming mode.

2. The circuit according to claim 1, characterized in that, At least one of the plurality of voltage generators further includes a voltage follower circuit inserted between the output terminal of the voltage generator and the electrical connection, the electrical connection being between two consecutive resistive elements in the series of resistive elements of the voltage generator.

3. The circuit according to claim 1, characterized in that, At least one of the plurality of voltage generators further includes a transconductance amplifier circuit inserted between the output terminal of the voltage generator and the electrical connection, the electrical connection being between two consecutive resistive elements in the series of resistive elements of the voltage generator.

4. The circuit according to any one of the preceding claims, characterized in that, Each voltage generator further includes a first access transistor and a second access transistor, the first access transistor being configured to operatively connect the resistive element located at a first position in the series of resistive elements to the single voltage supply source, and the second access transistor being configured to operatively connect the resistive element located at the last position in the series of resistive elements to the fixed reference voltage.

5. The circuit according to any one of claims 1 to 4, characterized in that, The resistance value of the programmable resistor in the non-volatile memory cell of each voltage generator can be programmed by the programming pulse sequence to any analog value within the range between the lower limit resistance value and the upper limit resistance value.

6. The circuit according to claim 5, characterized in that, The programmable resistor of the non-volatile memory cell is one of the following: a memristor based on phase-change memory, a memristor based on resistive RAM, or a memristor based on conductive bridge RAM.

7. The circuit according to any one of claims 1 to 4, characterized in that, The resistance value of the programmable resistor in the non-volatile memory cell of each voltage generator can be programmed into a set of digital values ​​by the programming pulse sequence. This set of digital values ​​includes at least a lower limit resistance value and an upper limit resistance value, and optionally includes one or more intermediate resistance values ​​within the range between the lower limit resistance value and the upper limit resistance value.

8. The circuit according to claim 7, characterized in that, The programmable resistor of the non-volatile memory cell is a switchable magnetoresistive resistor.

9. The circuit according to any one of the preceding claims, wherein the voltage divider circuit is multi-stage, characterized in that, The non-volatile memory cell of each voltage generator includes a plurality of non-volatile memory cells, wherein the first memory cell of the plurality of non-volatile memory cells includes the resistive element located at a first position in the series of resistive elements as a programmable resistor, and a first programmable control transistor connected in series between the programmable resistor and the fixed reference voltage. Furthermore, each of the remaining memory cells in the plurality of nonvolatile memory cells includes a corresponding intermediate resistor element in the series of resistor elements as a programmable resistor, and a separate programming control transistor connected in series between the programmable resistor and the fixed reference voltage. The control gate of each programming control transistor of the nonvolatile memory cell is selectively connected to the programming cell so as to receive the programming pulse sequence for the programmable voltage generator when operating in programming mode.

10. The circuit according to claim 9, characterized in that, The programmable resistor of each cell of the non-volatile memory cell is a switchable magnetoresistor, wherein the low-resistance state of the switchable magnetoresistor is different between different cells of the non-volatile memory cell.

11. An apparatus for generating a plurality of tunable probability bits, comprising: Multiple tunable probability bit generators, each probability bit generator having an input for individually controlling the statistical expectation of the probability bits generated by the probability bit generator; Single voltage supply source; According to any one of the preceding claims, in the programmable drive circuit, the input terminals of the plurality of programmable voltage generators of the programmable drive circuit are commonly connected to the single voltage supply source, and the output terminal of each voltage generator of the programmable drive circuit is directly connected to the input terminal of a corresponding one of the plurality of tunable probability bit generators, for driving the output signal generated by the voltage generator to the tunable probability bit generator.

12. A method of operating a drive circuit according to any one of claims 1 to 10, comprising the following steps: A single voltage supply signal is supplied to the input terminals of the plurality of programmable voltage generators; Connect the resistor element located at the first position of the series of resistor elements in each voltage generator to the input terminal of the voltage generator; The last resistor in the series of resistors in each voltage generator is connected to a fixed reference voltage; The control gate of each programmable control transistor in each voltage generator is disconnected from the programming unit.

13. The method according to claim 12, characterized in that, Further steps include: Multiple tunable probability bit generators are provided, each probability bit generator having an input for individually controlling the statistical expectation of the probability bits generated by the probability bit generator; The output signal generated by each voltage generator is driven to the input of a corresponding one of the plurality of tunable probability bit generators.

14. The method according to claim 12 or 13, characterized in that, The output signal of the programmable drive circuit generated by the plurality of programmable voltage generators is a voltage signal or a current signal.

15. The method according to claim 12, characterized in that, Further steps include: Select one of the plurality of programmable voltage generators to program a target level for the output signal to be generated by that voltage generator when operating in drive mode; Generate a programming pulse sequence based on the target level of the output signal of the voltage generator selected in the previous step; Disconnect the last resistor in the series of resistors in the selected voltage generator from the fixed reference voltage; The programming units are sequentially coupled to the control gates of different programming control transistors in the selected voltage generator, and each control gate is driven by the programming pulse sequence or part of the programming pulse sequence generated in the previous step, thereby turning on and off the programming current flowing through the programmable resistor addressed by the programming control transistor.

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