Semiconductor devices and systems including stacked logic dies

Abstract

A semiconductor device includes a first logic die including: a clock source configured to generate a clock signal; and a first clock mesh for receiving the clock signal from the clock source. The device includes a second logic die stacked above the first logic die, the second logic die including: a second clock mesh for receiving the clock signal from the clock source. The device includes a plurality of conductive connections between the first clock mesh and the second clock mesh to send the clock signal from the first clock mesh to the second clock mesh. Various other methods and systems are also disclosed.

Description

Background Technology

[0001] A computer processor is an integrated circuit that executes instructions and performs computational tasks. To save space, reduce power consumption, and / or increase processing speed, some processors include two stacked logic dies that are assembled to communicate with each other. The stacked logic dies perform computational tasks together or individually.

[0002] At a basic level, the operation of a computer processor involves sending, storing, and retrieving data bit by bit. Some modern processors can perform billions of these operations per second, or at a speed of one gigahertz or more. Clock signals are electrical pulses that processors often use to indicate when components of the processor are performing operations. Attached Figure Description

[0003] The accompanying drawings illustrate several exemplary implementations and are part of the specification. Together with the following description, these drawings demonstrate and explain the various principles of this disclosure.

[0004] Figure 1 This is a diagram of a system comprising a computing device having stacked logic dies, specifically implemented according to at least one example of this disclosure.

[0005] Figure 2 A diagram of a semiconductor device specifically implemented according to at least one example of this disclosure.

[0006] Figure 3 The diagram illustrates an example embodiment of a state storage element integrated into or integrated with a computing device, according to at least one example of this disclosure.

[0007] Figure 4 This is a flowchart illustrating a method for manufacturing a semiconductor device according to one or more specific embodiments of the present disclosure.

[0008] Throughout the accompanying drawings, the same reference characters and descriptions indicate similar but not necessarily identical elements. While the examples described herein are susceptible to various modifications and alternatives, specific embodiments have been shown by way of example in the drawings and will be described in detail herein. However, the specific embodiments of the examples described herein are not intended to be limited to the specific forms disclosed. Rather, this disclosure covers all modifications, equivalents, and alternatives falling within the scope of the appended claims. Detailed Implementation

[0009] This disclosure generally relates to semiconductor devices, computer systems, and methods employing two logic dies (e.g., processor dies) stacked on top of each other. Each logic die includes a clock grid, and a plurality of conductive connections are used to short the two clock grids to each other for transmitting clock signals between the clock grids.

[0010] Clock skew occurs when a clock signal from a clock source arrives at different active components (e.g., state storage elements) at different times, causing these components to be activated at different times. Clock skew can also occur when a clock signal arrives at one component after passing through a few stages and at another after passing through a large number of stages, resulting in longer paths with potentially additional resistance and / or impedance. Clock skew can make the setup and hold operation of semiconductor devices challenging, which can cause performance problems (e.g., delayed or slowed operation) or require mitigation techniques (e.g., buffer installation, etc.) to address.

[0011] Multiple conductive connections between clock grids in a stacked logic die can suppress (e.g., reduce, minimize, or eliminate) clock skew between two dies. In other words, a clock signal can cross the interface between two logic dies via a clock grid and multiple conductive connections. The clock signal is then passed (e.g., directly passed, shorted) to another clock grid for use by the other die via the conductive connections. This passage of the clock signal occurs with little or no divergence. Therefore, the clock signal can reach the active components of both logic dies with little or no clock skew.

[0012] The following will refer to Figures 1 to 3 Detailed descriptions of example semiconductor devices, computer systems including semiconductor devices, and components thereof, according to various examples of this disclosure, are provided. (The descriptions will also be combined with...) Figure 4 Provides a detailed description of methods for manufacturing semiconductor devices.

[0013] In some aspects, the technology described herein relates to a semiconductor device including a first logic die and a second logic die stacked on top of the first logic die. The first logic die includes a clock source configured to generate a clock signal and a first clock grid for receiving the clock signal from the clock source. The second logic die includes a second clock grid for receiving the clock signal from the clock source. The semiconductor device also includes a plurality of conductive connections between the first and second clock grids to transmit the clock signal from the first clock grid to the second clock grid.

[0014] In some respects, the technology described herein relates to a semiconductor device in which a plurality of conductive interconnects include conductive vias electrically connecting a first clock grid to a second clock grid.

[0015] In some respects, the techniques described herein relate to a semiconductor device in which a conductive via is located in and passes through at least a portion of a first logic die.

[0016] In some respects, the techniques described herein relate to a semiconductor device in which conductive vias are electrically connected to corresponding conductive bonding pads.

[0017] In some respects, the techniques described herein relate to a semiconductor device in which a first logic die includes conductive vias and a second logic die includes conductive bonding pads.

[0018] In some respects, the technology described herein relates to a semiconductor device in which the clock source includes a phase-locked loop clock source.

[0019] In some respects, the technology described herein relates to a semiconductor device in which a second logic die further includes a local clock source configured to generate a test clock signal for testing a second logic die that is separate from a first logic die.

[0020] In some respects, the technology described herein relates to a semiconductor device in which a second logic die further includes a tri-state driver between a local clock source and a second clock grid.

[0021] In some respects, the technology described herein relates to a semiconductor device in which a plurality of conductive connections are included among at least one hundred conductive connections between a first clock grid and a second clock grid.

[0022] In some respects, the technology described herein relates to a semiconductor device in which a plurality of conductive connections are included between a first clock grid and a second clock grid, comprising at least one thousand conductive connections.

[0023] In some aspects, the technology described herein relates to a semiconductor device in which: a first logic die further includes: a first plurality of state storage elements configured to receive a clock signal from a first clock grid; and at least one first-level gate between the first clock grid and the first plurality of state storage elements; and a second logic die further includes: a second plurality of state storage elements configured to receive a clock signal from the first clock grid; and at least one second-level gate between the second clock grid and the second plurality of state storage elements.

[0024] In some respects, the technology described herein relates to a semiconductor device in which: a first plurality of state storage elements include a first plurality of flip-flop elements; and a second plurality of state storage elements include a second plurality of flip-flop elements.

[0025] In some aspects, the technology described herein relates to a semiconductor device in which a first logic die further includes a tri-state driver between a clock source and a first clock grid, wherein the tri-state driver is deactivated during testing of the first logic die separated from the second logic die, and activated during operation of the first logic die and a second logic die stacked above the first logic die to boost a generated clock signal for use by both the first logic die and the second logic die.

[0026] In some aspects, the technology described herein relates to a computer system including a memory device configured to store computer-executable instructions and a semiconductor device communicating with the memory device and configured to execute the computer-executable instructions. The semiconductor device includes a first logic die and a second logic die stacked on the first logic die. The first logic die includes: a clock source configured to generate a clock signal; a first plurality of state storage elements; and a first clock grid for distributing the generated clock signal from the clock source to the first plurality of state storage elements. The second logic die includes: a second plurality of state storage elements; and a second clock grid for distributing the clock signal from the clock source to the second plurality of state storage elements. The semiconductor device also includes a plurality of conductive connections between the first clock grid and the second clock grid to transmit a clock signal from the first clock grid to the second clock grid.

[0027] In some respects, the technology described herein relates to a system in which a plurality of conductive connectors include conductive vias passing through at least a portion of a first logic die and conductive bonding pads of a second logic die.

[0028] In some respects, the technology described herein relates to a system in which a first plurality of state storage elements include a first plurality of trigger elements, and a second plurality of state storage elements include a second plurality of trigger elements.

[0029] In some respects, the technology described herein relates to a system in which a plurality of conductive connectors comprise an array of at least one hundred conductive connectors.

[0030] In some aspects, the technology described herein relates to a method of manufacturing a logic device, the method comprising: stacking and bonding a first logic die including a clock source and a first clock grid with a second logic die including a second clock grid; and electrically coupling the first clock grid to the second clock grid using a plurality of conductive connections to transmit clock signals from the clock source and the first clock grid to the second clock grid.

[0031] In some respects, the techniques described herein relate to a method in which electrically coupling a first clock grid to a second clock grid using a plurality of conductive connectors includes electrically shorting the first clock grid to the second clock grid using an array of conductive connectors.

[0032] In some respects, the techniques described herein relate to a method in which an array of conductive connectors electrically shorts a first clock grid to a second clock grid, comprising an array of at least one hundred conductive vias passing through at least a portion of a first logic die.

[0033] Figure 1 An example system 100 relating to computing device 102 is illustrated. Examples of computing device 102 include, but are not limited to, memory devices, processing devices, central processing units (CPUs), graphics processing units (GPUs), microprocessors, microcontrollers, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), system-on-a-chip (SoCs), static random access memory (SRAM) devices, random access memory (RAM) devices, read-only memory (ROM) devices, flash memory devices, hard disk drives (HDDs), solid-state drives (SSDs), optical disk drives, caches, routers, switches, hubs, modems, bridges, repeaters, gateways (such as Broadband Network Gateways (BNGs)), network devices, client devices, laptop computers, tablet computers, desktop computers, servers, cellular phones, personal digital assistants (PDAs), multimedia players, embedded systems, wearable devices, game consoles, portions of one or more of the foregoing, variations or combinations of one or more of the foregoing, and / or any other suitable device.

[0034] like Figure 1 As illustrated, computing device 102 includes and / or represents a physical processor 110 communicating with memory device 120. In some specific implementations, physical processor 110 includes a stack of a first logic die 112 and a second logic die 114 located above (e.g., bonded to) the first logic die 112.

[0035] See below for reference. Figure 2 To further explain, the first logic die 112 includes a clock source and a first clock grid for distributing clock signals from the clock source to active components of the first logic die 112 (e.g., to a first plurality of state storage elements, such as flip-flops). The second logic die 114 includes a second clock grid for distributing clock signals to active components of the second logic die 114 (e.g., to a second plurality of state storage elements, such as flip-flops).

[0036] In some examples, the first and second clock grids are electrically coupled to each other (e.g., shorted, directly electrically coupled) using multiple conductive connectors (such as multiple conductive vias 116, conductive pads 118, combinations thereof, etc.). For example, the first and second clock grids are electrically coupled to each other using arrays of more than one hundred conductive connectors, more than five hundred conductive connectors, more than one thousand conductive connectors, or thousands of conductive connectors. The specific number of conductive connectors in a given implementation depends on the size and capacity of the physical processor 110, space constraints, manufacturing capabilities, and / or other possible considerations.

[0037] For example, a via 116 may pass through at least a portion of a first logic die 112, and conductive pads 118 coupled to the via 116 may be located in or on a second logic die 114. In another example, the via 116 may pass through at least a portion of a second logic die 114, and the conductive pads 118 may be in or on the first logic die 112. Alternatively, both the first logic die 112 and the second logic die 114 may include conductive vias 116 electrically coupled to each other. In a further embodiment, both the first logic die 112 and the second logic die 114 may include conductive pads 118 electrically coupled to each other.

[0038] Conductive vias 116 and / or conductive pads 118 are electrically coupled (e.g., directly coupled) to a first clock grid and a second clock grid to electrically short the first clock grid and the second clock grid to each other at many (e.g., more than one hundred, more than five hundred, more than one thousand, thousands, etc.) locations. This arrangement of numerous conductive connections suppresses (e.g., reduces, minimizes, or eliminates) clock skew between the first logic die 112 and the second logic die 114, such as by redundantly passing clock signals derived from a clock source from the first clock grid to the second clock grid to send clock signals to the active components of the first logic die 112 and the second logic die 114.

[0039] Examples of physical processor 110 include, but are not limited to, CPUs, GPUs, microprocessors, microcontrollers, FPGAs, ASICs, SoCs, combinations or variations of one or more of the foregoing, and / or any other suitable processing device of any type. In some examples, physical processor 110 may include and / or represent any type or form of hardware-implemented processor capable of executing computer-readable instructions stored in memory device 120.

[0040] In some examples, memory device 120 may include and / or represent any type or form of volatile or non-volatile storage device or computer-readable medium capable of storing data and / or computer-readable instructions. In one example, memory device 120 includes and / or represents an SRAM device. In some examples, memory device 120 maintains and / or stores data, including executable instructions for execution by physical processor 110.

[0041] As used herein, the term "computer-readable medium" generally refers to any form of device, carrier, or medium capable of storing or carrying computer-readable instructions. Examples of computer-readable media include, but are not limited to, transmissive media such as carrier waves, and non-transitory media such as magnetic storage media (e.g., hard disk drives, magnetic tape drives, and floppy disks), optical storage media (e.g., optical discs (CDs), digital video discs (DVDs), and Blu-ray discs), electronic storage media (e.g., solid-state drives and flash memory media), and other distribution systems.

[0042] Many other devices or subsystems can be connected to Figure 1 System 100 in the middle. Conversely, Figure 1 Not all components and devices illustrated herein need to exist to implement the specific implementations described and / or illustrated herein. The devices and subsystems mentioned above may also be used with... Figure 1 The different interconnections shown are further illustrated. System 100 may also employ any number of software, firmware, and / or hardware configurations. For example, one or more embodiments of the exemplary embodiments disclosed herein may be encoded as a computer program on a computer-readable medium (also referred to as computer software, software application, computer-readable instructions, and / or computer control logic).

[0043] Figure 2 This is a diagram of a semiconductor device 200 (e.g., a processor device) including a first logic die 202 (e.g., a first processor die) and a second logic die 204 (e.g., a second processor die) stacked on top of and bonded to the first logic die 202. In some specific embodiments, the first logic die 202 includes a clock source 206 configured to generate clock signals for the operation of both the first logic die 202 and the second logic die 204. The first logic die 202 also includes a first clock grid 208 that receives clock signals from the clock source 206 and distributes the clock signals to other components of the first logic die 202, such as a first plurality of state storage elements 210.

[0044] In some embodiments, the second logic die 204 includes a second clock grid 212 that receives clock signals from a clock source 206 via a first clock grid 208 and distributes the clock signals to other components of the second logic die 204, such as a second plurality of state storage elements 214. In some embodiments, the first clock grid 208 and the second clock grid 212 each comprise a grid or mesh of metal or other conductive material.

[0045] In some examples, the first clock grid 208 and the second clock grid 212 are electrically coupled (e.g., shorted) to each other using multiple conductive connectors 216. For example, each of the conductive connectors 216 may include a conductive via 218 electrically coupled to a corresponding conductive bonding pad 220 (e.g., a so-called "through-silicon via" or "TSV"). Figure 2 In the example shown, the first logic die 202 includes an array of conductive vias 218, and the second logic die 204 includes an array of conductive bonding pads 220 corresponding to and electrically coupled to the conductive vias 218. The conductive vias 218 pass through at least a portion of the first logic die 202, such as the portion including the first clock grid 208 and the surface of the first logic die 202 adjacent to the second logic die 204.

[0046] For simplicity, Figure 2 Two conductive connectors 216 are illustrated. However, the number of conductive connectors 216 depends on the size of the overlap between the first clock grid 208 and the second clock grid 212. In some examples, the semiconductor device 200 includes dozens, at least one hundred, at least five hundred, at least one thousand, or several thousand conductive connectors 216 between the first clock grid 208 and the second clock grid 212.

[0047] Clock source 206 is a device or element that generates a clock signal for use by other components of semiconductor device 200 (e.g., for synchronizing the operation of components of semiconductor device 200). As a non-limiting example, clock source 206 may be implemented as a phase-locked loop (PLL) circuit, a frequency-locked loop (FLL) circuit, a delay-locked loop (DLL) circuit, etc. In some specific implementations, clock source 206 generates a clock signal and transmits the clock signal to a first plurality of state storage elements 210 via a first clock grid 208. The clock signal is also transmitted to a second plurality of state storage elements 214 via the first clock grid 208, a plurality of conductive connections 216, and a second clock grid 212. In some examples, at least some of the first state storage elements 210 of the first logic die 202 may transmit data to and / or from at least some of the second state storage elements 214 of the second logic die 204. Data transmission between the first state storage elements 210 and the second state storage elements 214 may include substantially synchronous set and hold operations.

[0048] In some instances, the term "substantially" regarding a given parameter, property, or condition refers to the degree to which a given parameter, property, or condition is satisfied with small variations (e.g., within acceptable manufacturing tolerances) as would be understood by a person skilled in the art. For example, a parameter that is substantially satisfied could be satisfied with at least about 90%, at least about 95%, at least about 99%, or fully satisfied.

[0049] In some implementations, the second logic die 204 may optionally include a local clock source 222. The local clock source 222 generates a test clock signal for testing the second logic die 204, which is separate from the first logic die 202, such as before the second logic die 204 is bonded to the first logic die 202. For example, the operability of the second logic die 204 can be tested at the wafer level using the local clock source 222 before the wafer is diced and / or stacked on top of the first logic die 202. Wafer-level testing reduces manufacturing costs by discarding only the individual second logic die 204 if it fails to meet a given specification, rather than discarding the entire semiconductor device 200 containing both the first and second logic dies 202 if only the second logic die 204 fails.

[0050] like Figure 2As illustrated in the example, a local clock source 222 (if present) is connected to a second clock grid 212 via a tri-state driver 224. When activated, the tri-state driver 224 allows the local clock signal to be delivered to the second clock grid 212 and ultimately to a second plurality of state storage elements 214 for testing, but prevents the use of the local clock source 222 during normal operation of the second logic die 204 (e.g., during operation of the second logic die 204 together with the first logic die 202 in the semiconductor device 200). Preventing the use of the local clock source 222 during normal operation of the second logic die 204 saves power and suppresses (e.g., reduces, minimizes, or eliminates) clock skew between the first logic die 202 and the second logic die 204, where clock skew might exist if both the local clock source 222 and clock source 206 were used simultaneously.

[0051] In some examples, the first logic die 202 may optionally include at least one first-level gate 226 between the first clock grid 208 and the first plurality of state storage elements 210. Similarly, the second logic die 204 may include at least one second-level gate 228 between the second clock grid 212 and the second plurality of state storage elements 214. The first-level gate 226 and the second-level gate 228 are used to shut down circuitry (e.g., portions of the first plurality of state storage elements 210 and the second plurality of state storage elements 214, buses, bridges, controllers, etc.), such as to reduce the power consumption of the first logic die 202 and / or the second logic die 204.

[0052] exist Figure 2 In the illustrated example, the first logic die 202 includes one or more gain stages 230 between a clock source 206 and a first clock grid 208, which amplify and / or sharpen the clock signal generated by the clock source 206 before it reaches the first clock grid 208. The one or more gain stages 230 in... Figure 2 The symbol in the middle represents an inverter. Figure 2 An inverter represents one or more inverters or other signal driving elements, which may exist in the form of a tree of multiple inverters or other signal driving elements and / or multiple inverters or other signal driving elements connected in series and / or in parallel.

[0053] Optionally, the first logic die 202 may also include a programmable driver 232 in combination with (e.g., in parallel) one or more gain stages 230. For example, Figure 2The clock source 206, together with one or more gain stages 230 and programmable driver 232, is sized and powered to drive the operation of both the first logic die 202 and the second logic die 204 when they are stacked and operated together. When the first logic die 202 is to be operated alone without operating the second logic die 204 (e.g., in another specific embodiment excluding the second logic die 204, during testing of the first logic die 202, etc.), the combination of one or more gain stages 230 and programmable driver 232 would therefore be too large. In this case, the programmable driver 232 is disabled, thereby reducing the power consumption of the circuit to the power required to drive the operation of only the first plurality of state storage elements 210. On the other hand, if the clock source 206 is to send a clock signal to both the first plurality of state storage elements 210 and the second plurality of state storage elements 214 (e.g., as...), Figure 2 (As illustrated), the programmable driver 232 is then enabled, thereby increasing the power consumption of the circuit to a level sufficient to drive the operation of both the first plurality of state storage elements 210 and the second plurality of state storage elements 214.

[0054] In some implementations, when present, the programmable driver 232 may be or include a tri-state driver. The programmable driver 232 may be a fuse-programmable driver 232 enabled when the second logic die 204 is coupled to and will be driven by the first logic die 202. When the first logic die 202 is to operate independently (e.g., without the second logic die 204), the fuse-programmable driver 232 is disabled to reduce power consumption, reduce heat generation, etc.

[0055] In some implementations, at least some of the state storage elements 210 of the first plurality of state storage elements 212 communicate with at least some of the state storage elements 214 of the second plurality of state storage elements 214. Reducing clock skew can help improve or maintain processing performance, such as during set-up or hold operations, when these components transfer data (e.g., bits) to each other. Therefore, some aspects of this disclosure reduce clock skew between the first plurality of state storage elements 210 and the second plurality of state storage elements 214 to improve or maintain performance.

[0056] Figure 3An example state storage element 300 is illustrated in the form of a flip-flop having multiple external inputs and / or outputs. State storage element 300 can be used as any of the first plurality of state storage elements 210 or the second plurality of state storage elements 214 described above. In some examples, state storage element 300 represents or includes a one-bit memory device whose output state can be changed by various input signals applied to its inputs, such as D-type flip-flops, T-type flip-flops, JK-type flip-flops, latches, portions of one or more of the above, variations or combinations of one or more of the above, and / or any other suitable device. In some examples, state storage element 300 represents or includes a master-slave flip-flop (e.g., constructed from two back-to-back sequential elements such as latches). In some examples, state storage element 300 represents or includes an edge-triggered memory device whose output state changes on a clock edge. In at least one example, state storage element 300 represents or includes a positive-edge-triggered, static or quasi-static D-type flip-flop. Figure 3 In the illustrated example, state storage element 300 includes an external data input 301, an external data output 303, and an external clock input 305 (e.g., for receiving clock signals from clock source 206 and / or from local clock source 222). In some examples, state storage element 300 is configured to sample the state of the signal at external data input 301, output the sampled state at external data output 303, and / or store the sampled state until it is replaced by another state.

[0057] In some examples, combined Figures 1 to 3 The various circuits, components, and / or devices described may include and / or represent, but are not necessarily illustrated and / or marked in Figures 1 to 3 One or more additional or functionally equivalent circuits, components, devices, and / or features may be included. For example, such circuits, components, and / or devices may also include and / or represent additional or functionally equivalent analog and / or digital circuits, onboard logic components, transistors, resistors, capacitors, diodes, inductors, switches, registers, flip-flops, connectors, traces, buses, semiconductor (e.g., silicon) devices and / or structures, memory devices, circuit boards, housings, combinations or variations of one or more of the foregoing, and / or any other suitable components. One or more of these additional or functionally equivalent circuits, components, and / or devices may be inserted and / or applied in accordance with the purposes and / or objectives provided herein. Figures 1 to 3 Between any existing circuits, components, and / or devices illustrated herein. Therefore, refer to Figures 1 to 3 The described electrical and / or communication coupling can be a direct connection without intermediate components, devices and / or nodes, or an indirect connection with one or more intermediate components, devices and / or nodes.

[0058] Figure 4 This is a flowchart illustrating a method 400 for manufacturing a semiconductor device according to one or more examples of the present disclosure. In operation 402, a first logic die and a second logic die are stacked and bonded. The first logic die includes a clock source and a first clock grid, and the second logic die includes a second clock grid. Operation 402 can be performed in a variety of ways. For example, the first logic die may be a base die mounted to an underlying support structure (e.g., a printed circuit board, an interposer, a heat sink, etc.), and the second logic die may be mounted above and bonded to the top surface of the first logic die. The first and second logic dies may have the same geometry (e.g., in length and width), or the second logic die may have a different size (e.g., a smaller size) than the first logic die. In an additional specific embodiment, the second logic die may be a base die, and the first logic die may be mounted above and bonded to the top surface of the second logic die. In some examples, the first and second logic dies may have the same or similar technology level and / or type (e.g., technology generation and / or version). In additional examples, the first and second logic dies may have different technology levels and / or types.

[0059] In operation 404, a first clock grid is electrically coupled (e.g., shorted) to a second clock grid using multiple conductive connections to transmit a clock signal from a clock source and the first clock grid to the second clock grid. Operation 404 can be performed in a variety of ways. For example, the multiple conductive connections may include multiple conductive vias (e.g., TSVs) in the first logic die and multiple conductive bonding pads in the second logic die, each coupled to a conductive via. In an additional example, the conductive bonding pads may be in the first logic die, and the conductive vias may be in the second logic die. Alternatively, both the first and second logic dies may include conductive vias, or both the first and second logic dies may include conductive bonding pads.

[0060] In some implementations, multiple conductive connections extend across the interface (e.g., bonding interface) between the first logic die and the second logic die. The multiple conductive connections may include an array of conductive connections. This array may include at least one hundred, at least five hundred, at least one thousand, or several thousand conductive connections between the first clock grid and the second clock grid to suppress (e.g., reduce, minimize, or eliminate) potential clock skew between the first clock grid and the second clock grid.

[0061] Therefore, this disclosure includes computer systems, semiconductor devices, and methods employing stacked logic dies, the stacked dies comprising respective clock grids shorted to each other using multiple (e.g., more than one hundred, more than five hundred, more than one thousand, or thousands) conductive interconnects. This arrangement can suppress clock skew between two logic dies, which can reduce the complexity of packages including two logic dies and / or improve their performance.

[0062] While the foregoing disclosures use specific block diagrams, flowcharts, and examples to illustrate various concrete implementations, each block diagram component, flowchart step, operation, and / or component described and / or illustrated herein can be implemented individually and / or collectively using various hardware, software, or firmware (or any combination thereof) configurations. Furthermore, any disclosures of components contained within other components should be considered exemplary in nature, as many other architectures can be implemented to achieve the same functionality.

[0063] In some examples, Figure 1 All or part of the example system 100 or example semiconductor device 200 may represent portions of a cloud computing environment or a network-based environment. A cloud computing environment can provide various services and applications via the Internet. These cloud-based services (e.g., Software as a Service, Platform as a Service, Infrastructure as a Service, etc.) can be accessed via a web browser or other remote interface. The various functionalities described herein can be provided via a remote desktop environment or any other cloud-based computing environment.

[0064] In various specific implementations, Figure 1 Example system 100 or Figure 2 All or part of the example semiconductor device 200 described herein can be used to facilitate multi-tenancy within a cloud-based computing environment. In other words, the systems and devices described herein can be used to configure computing systems (e.g., servers) to facilitate multi-tenancy for one or more of the functions described herein. For example, one or more of the systems and devices described herein can be used to program a server so that two or more clients (e.g., customers) can share applications running on the server. A server programmed in this way can share applications, operating systems, processing systems, and / or storage systems among multiple customers (i.e., tenants). One or more of the systems and devices described herein can also be used to partition the data and / or configuration information of a multi-tenant application for each customer, such that one customer cannot access the data and / or configuration information of another customer.

[0065] Depending on the specific implementation, Figure 1 Example system 100 or Figure 2All or part of the example semiconductor device 200 described herein can be implemented within a virtual environment. For example, the data described herein can reside in and / or be executed within a virtual machine. As used herein, the term "virtual machine" generally refers to any operating system environment abstracted from computing hardware by a virtual machine manager (e.g., a hypervisor).

[0066] In some examples, Figure 1 Example system 100 or Figure 2 All or part of the example semiconductor device 200 may represent various parts of a mobile computing environment. A mobile computing environment may be implemented by a variety of mobile computing devices, including mobile phones, tablet computers, e-book readers, personal digital assistants, wearable computing devices (e.g., computing devices with head-mounted displays, smartwatches, etc.), variations or combinations of one or more of the above, or any other suitable mobile computing device. In some examples, a mobile computing environment may have one or more different characteristics, including, for example, dependence on battery power, presenting only one foreground application at any given time, remote management features, touchscreen features, location and motion data (e.g., provided by a GPS, gyroscope, accelerometer, etc.), a restricted platform that limits modification of system-level configuration and / or limits the ability of third-party software to inspect the behavior of other applications, controls that limit application installation (e.g., only from approved app stores), etc. The various functionalities described herein may be provided to and / or interact with a mobile computing environment.

[0067] The process parameters and sequence of steps described and / or illustrated herein are given by way of example only and can be changed as needed. For example, while the steps illustrated and / or described herein may be shown or discussed in a particular order, these steps do not necessarily need to be performed in the illustrated or discussed order. The various example methods described and / or illustrated herein may also omit one or more steps described or illustrated herein, or include additional steps in addition to those disclosed.

[0068] Although various embodiments have been described and / or illustrated in the context of a full-featured computing system, one or more of these example embodiments can be distributed as a program product in various forms, regardless of the specific type of computer-readable medium on which the distribution is actually performed. The embodiments disclosed herein can also be implemented using modules that perform specific tasks. These modules can include scripts, batch files, or other executable files that can be stored on computer-readable storage media or stored in a computing system. In some embodiments, these modules can configure the computing system to execute one or more of the example embodiments disclosed herein.

[0069] The foregoing description has been provided to enable others skilled in the art to best utilize the various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or limited to any precise form disclosed. Many modifications and variations are possible without departing from the spirit and scope of this disclosure. The specific embodiments disclosed herein should be considered illustrative rather than restrictive in all respects. In determining the scope of this disclosure, reference should be made to the appended claims and their equivalents.

[0070] Unless otherwise stated, the terms “connected to” and “coupled to” (and their derivatives) as used in the specification and claims will be considered to allow both direct and indirect connections (i.e., via other elements or components). Additionally, the terms “a” or “an” as used in the specification and claims will be considered to mean “at least one”. Finally, for ease of use, the terms “comprising” and “having” (and their derivatives) as used in the specification and claims are interchangeable with the word “including” and have the same meaning.

Claims

1. A semiconductor device, the semiconductor device comprising: The first logic die includes: A clock source, configured to generate a clock signal; and A first clock grid, the first clock grid being used to receive the clock signal from the clock source; A second logic die, stacked on top of the first logic die, includes: A second clock grid, the second clock grid being used to receive the clock signal from the clock source; and Multiple conductive connectors are located between the first clock grid and the second clock grid to transmit the clock signal from the first clock grid to the second clock grid.

2. The semiconductor device of claim 1, wherein the plurality of conductive connectors includes conductive vias electrically connecting the first clock grid to the second clock grid.

3. The semiconductor device of claim 2, wherein the conductive via is located in at least a portion of the first logic die and passes through the at least a portion of the first logic die.

4. The semiconductor device of claim 2, wherein the conductive via is electrically connected to a corresponding conductive bonding pad.

5. The semiconductor device of claim 4, wherein the first logic die includes the conductive via, and the second logic die includes the conductive bonding pad.

6. The semiconductor device according to claim 1, wherein the clock source comprises a phase-locked loop clock source.

7. The semiconductor device of claim 1, wherein the second logic die further comprises a local clock source configured to generate a test clock signal for testing the second logic die, which is separate from the first logic die.

8. The semiconductor device of claim 7, wherein the second logic die further comprises a tri-state driver between the local clock source and the second clock grid.

9. The semiconductor device of claim 1, wherein the plurality of conductive connectors comprises at least one hundred conductive connectors between the first clock grid and the second clock grid.

10. The semiconductor device of claim 1, wherein the plurality of conductive connectors comprises at least one thousand conductive connectors between the first clock grid and the second clock grid.

11. The semiconductor device according to claim 1, wherein: The first logic die also includes: A first plurality of state storage elements, the first plurality of state storage elements being configured to receive the clock signal from the first clock grid; and At least one first-level gating, the at least one first-level gating being located between the first clock grid and the first plurality of state storage elements; and The second logic die also includes: A second plurality of state storage elements, configured to receive the clock signal from the second clock grid; and At least one second-level gating, the at least one second-level gating being between the second clock grid and the second plurality of state storage elements.

12. The semiconductor device according to claim 11, wherein: The first plurality of state storage elements include a first plurality of trigger elements; and The second plurality of state storage elements includes a second plurality of trigger elements.

13. The semiconductor device of claim 1, wherein the first logic die further comprises a tri-state driver between the clock source and the first clock grid, wherein the tri-state driver is deactivated during testing of the first logic die separated from the second logic die, and is activated during operation of the first logic die and a second logic die stacked above the first logic die to boost the clock signal for use by both the first logic die and the second logic die.

14. A computer system, the computer system comprising: A memory device configured to store computer-executable instructions; and A semiconductor device, which communicates with the memory device and is configured to execute the computer-executable instructions, the semiconductor device comprising: The first logic die includes: A clock source, configured to generate a clock signal; The first multiple state storage elements; and A first clock grid, the first clock grid being used to distribute the clock signal from the clock source to the first plurality of state storage elements; A second logic die, stacked on top of the first logic die, includes: The second set of multiple state storage elements; and A second clock grid, the second clock grid being used to distribute the clock signal from the clock source to the second plurality of state storage elements; and Multiple conductive connectors are located between the first clock grid and the second clock grid to transmit the clock signal from the first clock grid to the second clock grid.

15. The computer system of claim 14, wherein the plurality of conductive connectors include conductive vias passing through at least a portion of the first logic die and conductive bonding pads of the second logic die.

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