Photoelectric detection device and electronic device

Abstract

Provided is a photoelectric detection device in which performance degradation is suppressed. The photoelectric detection device includes: a semiconductor layer having one face that is a light incident face and another face that is a device formation face, the semiconductor layer having a plurality of unit regions isolated from each other by a partition wall extending from the light incident face to the device formation face; a device isolation structure made of an insulating material, provided on the device formation face side of the corresponding unit region, and dividing the device formation face side of the unit region into a plurality of active regions in a plan view; a through-hole penetrating the device isolation structure along a thickness direction; and a conductor provided inside the through-hole, a first end portion of the conductor that is an end portion on the light incident face side being in contact with a semiconductor portion in the unit region. The unit region includes a photoelectric conversion region, and a reference potential is supplied to the unit region through the conductor.

Description

Technical Field

[0001] This technology (based on the technology disclosed herein) relates to photoelectric detection devices and electronic devices. Background Technology

[0002] Patent document 1 discloses a structure in which a conductor serving as a reference potential contact for an image sensor is embedded in a portion of a trench for inter-pixel isolation, such that the conductor has a side that is connected to the silicon substrate.

[0003] Patent document 2 discloses that p+ impurity regions are formed not only on the surface of the pixel, but also on the bottom and sidewalls of the STI region to suppress the generation of dark current. List of cited references Patent documents

[0004] Patent Document 1: Japanese Patent Application Publication No. 2016-39315 Patent Document 2: Japanese Patent Application Publication No. 2013-153174 Patent Document 3: Japanese Patent Application Publication No. 2023-179619 Patent Document 4: Japanese Patent Application Publication No. 2022-135130 Summary of the Invention The problem the invention aims to solve

[0005] Sometimes the full potential of an image sensor cannot be realized.

[0006] The purpose of this technology is to provide photoelectric detection devices and electronic equipment that prevent performance degradation. Solution to the problem

[0007] A photoelectric detection device according to one aspect of the present technology includes: a semiconductor layer having one side as a light incident surface and another side as a device forming surface, the semiconductor layer including a plurality of unit regions isolated from each other by isolation walls extending from the light incident surface to the device forming surface; a device isolation structure made of an insulating material disposed on the device forming surface side of each of the unit regions, the device isolation structure dividing the device forming surface side of the unit regions into a plurality of active regions in a plan view; a through-hole penetrating the device isolation structure in the thickness direction; and a conductor disposed within the through-hole, the conductor having a first end, the first end being an end on the light incident surface side and in contact with a semiconductor portion in the unit region, wherein each unit region includes a photoelectric conversion region, and a reference potential is supplied to the unit region through the conductor.

[0008] According to another aspect of the present technology, a photoelectric detection device includes: a semiconductor layer having one side as a light incident surface and another side as a device forming surface, the semiconductor layer including a plurality of matrix-shaped unit regions, each unit region including a photoelectric conversion region of a first conductivity type; and a device isolation structure made of an insulating material, the device isolation structure being disposed on the device forming surface side of each of the unit regions, the device isolation structure dividing the device forming surface side of the unit regions into a plurality of active regions in a plan view, wherein each unit region includes a first impurity region, the first impurity region being a semiconductor region of a second conductivity type located at a depth position between the photoelectric conversion region and the active region, the first impurity region containing impurities that make the semiconductor of the second conductivity type, and the concentration of the impurities in the first impurity region having a gradient that gradually increases from a depth position at the bottom surface of the device isolation structure to a deeper side.

[0009] An electronic device according to one aspect of the present technology includes: any of the above-described photoelectric detection devices; and an optical system configured to image image light from a subject onto the respective photoelectric detection device. Attached Figure Description

[0010] Figure 1 This is a chip layout diagram illustrating an exemplary construction of a photoelectric detection device according to a first embodiment of the present technology. Figure 2 This is a block diagram illustrating an exemplary construction of a photoelectric detection device according to a first embodiment of the present technology. Figure 3 This is an equivalent circuit diagram of a pixel in a photoelectric detection device according to a first embodiment of the present technology. Figure 4A This is a longitudinal sectional view showing the cross-sectional structure of the pixels included in the photoelectric detection device according to Comparative Example 1. Figure 4B This is a longitudinal sectional view showing the cross-sectional structure of the pixels included in the photoelectric detection device according to Comparative Example 2. Figure 4C This is an enlarged longitudinal cross-sectional view of the main part of the pixels included in the photoelectric detection device according to Comparative Example 2. Figure 4D This is an explanatory diagram showing the side where the element forming surface of the unit region included in the photoelectric detection device according to Comparative Example 2 is located. Figure 5A This is an explanatory diagram showing the positional relationship between the element isolation structure and the conductor on the side where the element forming surface of the unit region is located in the photoelectric detection device according to a first embodiment of the present technology. Figure 5B It is illustrated along Figure 5AAn enlarged longitudinal sectional view of the cross-sectional structure when the plane intercepted by line AA is viewed in section. Figure 5C It is illustrated along Figure 5B A sectional view of the cross-section structure when the plane intercepted by line BB is viewed in section. Figure 6A This is a cross-sectional view showing the steps of a method for manufacturing a photoelectric detection device according to a first embodiment of the present technology. Figure 6B yes Figure 6A The following steps are shown in the sectional view. Figure 6C yes Figure 6B The following steps are shown in the sectional view. Figure 6D yes Figure 6C The following steps are shown in the sectional view. Figure 6E yes Figure 6D The following steps are shown in the sectional view. Figure 7 This is an enlarged longitudinal sectional view showing a portion of the cross-sectional structure of a pixel included in a photoelectric detection device according to a first embodiment of the present technology, modified 1. Figure 8 This is an enlarged longitudinal sectional view showing a portion of the cross-sectional structure of a pixel included in a photoelectric detection device according to a first embodiment of the present technology, variant 2. Figure 9 This is an enlarged longitudinal sectional view showing a portion of the cross-sectional structure of a pixel included in a photoelectric detection device according to a first embodiment of the present technology, variant 3. Figure 10 This is an explanatory diagram showing the positional relationship between the element isolation structure and the active region on the side where the element forming surface of the unit region is located in the photoelectric detection device according to a second embodiment of the present technology. Figure 11 It is illustrated along Figure 10 An enlarged longitudinal sectional view of a portion of the cross-sectional structure when viewed in section by the plane intercepted by line A-A'. Figure 12 It shows along Figure 11 The diagram shows the impurity distribution along line B-B'. Figure 13 It shows along Figure 11 A diagram showing the potential distribution along line B-B' in the diagram. Figure 14 This is an equivalent circuit diagram used to illustrate the pixels of a switching transistor. Figure 15A This is a cross-sectional view showing the steps of a method for manufacturing a photoelectric detection device according to a second embodiment of the present technology. Figure 15B yes Figure 15A The following steps are shown in the sectional view. Figure 15C yes Figure 15B The following steps are shown in the sectional view. Figure 16 This is an explanatory diagram showing the positional relationship between the element isolation structure and the active region on the side where the element forming surface of the unit region is located in the photoelectric detection device according to the second embodiment of the present technology, a variation of Example 1. Figure 17 This is an explanatory diagram showing the positional relationship between the element isolation structure and the active region on the side where the element forming surface of the unit region is located in the photoelectric detection device according to the second embodiment of the present technology, Modified Example 2. Figure 18 The illustration shows the photoelectric detection device according to the second embodiment of the present invention, variant 3, including the unit region along... Figure 10 An enlarged longitudinal sectional view of a portion of the cross-sectional structure when viewed in section by the plane intercepted by line A-A'. Figure 19 It shows along Figure 18 A graph showing the impurity distribution along line B-B'. Figure 20 This is a longitudinal sectional view showing the cross-sectional structure of the pixel transistor included in the photoelectric detection device according to the second embodiment of the present technology, Modified 4. Figure 21 This is a block diagram illustrating an exemplary schematic structure of an electronic device. Figure 22 This is an explanatory diagram showing the positional relationship between the conductor and the shielding wall on the side where the element forming surface of the unit region is located in the photoelectric detection device according to the fourth embodiment of the present technology. Figure 23 It is illustrated along Figure 22 The longitudinal sectional view of the cross-section structure when the plane intercepted by line AA is viewed in section. Figure 24 It is illustrated along Figure 22 The longitudinal sectional view of the cross-section structure when the plane intercepted by line BB is viewed in section. Figure 25 It is illustrated along Figure 22 A process cross-sectional view of the manufacturing method of the photoelectric detection device according to the fourth embodiment of this technology when the plane is cut by the line CC for cross-sectional observation. Figure 26 yes Figure 25 The following steps are shown in the sectional view. Figure 27 yes Figure 26The following steps are shown in the sectional view. Figure 28 yes Figure 27 The following steps are shown in the sectional view. Figure 29 This is an explanatory diagram showing the positional relationship between the conductor and the shielding wall on the side of the element forming surface of the unit region included in the photoelectric detection device according to the fourth embodiment of the present technology, a variation of Example 1. Figure 30 It is illustrated along Figure 29 A longitudinal sectional view of the cross-section structure when the plane intercepted by line DD is viewed in section. Figure 31 This is an explanatory diagram showing the positional relationship between the conductor and the shielding wall on the side of the element forming surface of the unit region included in the photoelectric detection device according to the fourth embodiment of the present technology, a variation of Example 2. Figure 32 This is an explanatory diagram showing the positional relationship between the conductor and the shielding wall on the side of the element forming surface of the unit region included in the photoelectric detection device according to the fourth embodiment of the present technology, a variation 3. Figure 33 This is a longitudinal sectional view showing the cross-sectional structure of the conductor included in the photoelectric detection device according to the fourth embodiment of the present technology, a variation 4. Figure 34 This is a longitudinal sectional view showing the cross-sectional structure of the shielding wall included in the photoelectric detection device according to the fourth embodiment of the present technology, variation 5. Figure 35 This is an explanatory diagram showing the positional relationship between the conductor, shielding wall, and through-hole on the side of the element forming surface of the unit region included in the photoelectric detection device according to the fourth embodiment of the present technology, a variation of 6. Figure 36 It is illustrated along Figure 35 The longitudinal sectional view of the cross-section structure when the plane intercepted by line BB is viewed in section. Figure 37 This is an explanatory diagram showing the positional relationship between the conductor, shielding wall, and through-hole on the side of the element forming surface of the unit region included in the photoelectric detection device according to the fourth embodiment of the present technology, a variation 7. Figure 38 This is an explanatory diagram showing the positional relationship between the conductor and the shielding wall on the side of the element forming surface of the unit region included in the photoelectric detection device according to the fourth embodiment of the present technology, a variation 8. Figure 39 This is an explanatory diagram showing the positional relationship between the conductor and the shielding wall on the side of the element forming surface of the unit region included in the photoelectric detection device according to the fourth embodiment of the present technology, a variation 8. Figure 40 This is an explanatory diagram showing the positional relationship between the conductor and the shielding wall on the side of the element forming surface of the unit region included in the photoelectric detection device according to the fourth embodiment of the present technology, a variation 8. Figure 41 This is an explanatory diagram showing the positional relationship between the conductor and the shielding wall on the side of the element forming surface of the unit region included in the photoelectric detection device according to the fourth embodiment of the present technology, a variation 8. Detailed Implementation

[0011] Preferred embodiments for implementing this technology will now be described with reference to the accompanying drawings. Note that the embodiments described below are exemplary representative embodiments of this technology and should not be construed as limiting the scope of this technology.

[0012] In the following figures, identical or similar parts are indicated by identical or similar reference numerals. It should be noted that the figures are schematic, and therefore the relationship between thickness and planar dimensions, the thickness ratio between layers, etc., may differ from reality. Therefore, the following description should be considered to determine specific thicknesses and dimensions. Furthermore, it goes without saying that parts differing in dimensional relationships or ratios in the various figures are included. Moreover, the figures used are suitable for illustrating this technique, and therefore, differences in construction may exist between the figures.

[0013] Furthermore, the following embodiments are intended to illustrate devices / apparatus and methods for embodying the technical concept of this technology; therefore, the technical concept of this technology does not limit the materials, shapes, structures, and arrangements of the constituent components to those described below. Various modifications can be made to the technical concept of this technology without departing from the scope defined by the claims.

[0014] Furthermore, the definitions of directions (such as up and down) in the following description are merely for illustrative purposes and do not limit the technical concept of this disclosure. Needless to say, for example, if the target is rotated 90° for observation, the up and down direction will become the left and right direction, and if the target is rotated 180° for observation, its up and down direction will be reversed.

[0015] The explanation will proceed in the following order. 1. First Implementation Plan 2. Second Implementation Plan 3. Third Implementation Plan Application examples of electronic devices 4. Fourth Implementation Plan

[0016] [First Implementation Plan] In this embodiment, an example of applying this technology to a photoelectric detection device as a back-illuminated complementary metal-oxide-semiconductor (CMOS) image sensor will be described.

[0017] <<Overall Structure of the Photoelectric Detection Device>> First, the overall structure of the photoelectric detection device 1 will be explained. For example... Figure 1 As shown, the photoelectric detection device 1 according to the first embodiment of this technology is mainly formed of a semiconductor chip 2, and the two-dimensional planar shape of the semiconductor chip 2 is rectangular in the planar view. That is, the photoelectric detection device 1 is mounted on the semiconductor chip 2. Figure 21 As shown, the photoelectric detection device 1 captures image light (incident light 106) from the subject through an optical system (optical lens) 102, and converts the amount of light of the incident light 106 that is formed into an image on the imaging surface into an electrical signal in units of pixels, so as to output the electrical signal as a pixel signal.

[0018] like Figure 1 As shown, the semiconductor chip 2 on which the photoelectric detection device 1 is mounted includes, in a two-dimensional plane along the intersecting X and Y directions, a pixel region 2A, which is rectangular in shape and located in the center; and a peripheral region 2B, which is located outside the pixel region 2A and surrounds the pixel region 2A.

[0019] For example, pixel region 2A is the receiver of... Figure 21 The optical system 102 shown has a light-receiving surface that converges light. Furthermore, in pixel region 2A, a plurality of pixels 3 are arranged in a matrix in a two-dimensional plane along the X and Y directions. In other words, the pixels 3 are arranged in a repeating manner in both the X and Y directions, which intersect each other, in the two-dimensional plane. Note that, in this embodiment, as an example, the X and Y directions are orthogonal to each other. Furthermore, the direction orthogonal to both the X and Y directions is the Z direction (thickness direction, stacking direction, or depth direction). Furthermore, the direction perpendicular to the Z direction is the horizontal direction.

[0020] like Figure 1 As shown, a plurality of bonding pads 14 are arranged in the peripheral region 2B. Each of the plurality of bonding pads 14 is arranged, for example, along one of the four sides in the two-dimensional plane of the semiconductor chip 2. Each of the plurality of bonding pads 14 is an input / output terminal for electrically connecting the semiconductor chip 2 to an external device.

[0021] <Logic Circuits> like Figure 2 As shown, semiconductor chip 2 includes logic circuit 13. Logic circuit 13 includes vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, output circuit 7, control circuit 8, etc. For example, logic circuit 13 includes complementary MOS (CMOS) circuit, which includes an n-channel conductive metal-oxide-semiconductor field-effect transistor (MOSFET) and a p-channel conductive MOSFET as field-effect transistors.

[0022] For example, the vertical driving circuit 4 includes a shift register. The vertical driving circuit 4 sequentially selects the desired pixel driving lines 10 and supplies pulses to the selected pixel driving lines 10 for driving the pixels 3, thereby driving each pixel 3 row by row. That is, the vertical driving circuit 4 selectively scans each pixel 3 in the pixel region 2A row by row in the vertical direction, and supplies the pixel signal from each pixel 3, based on the signal charge generated by the photoelectric conversion element of the pixel 3 according to the amount of received light, to the column signal processing circuit 5 through the vertical signal line 11.

[0023] For example, the column signal processing circuit 5 is arranged in a one-to-one correspondence with the columns of pixels 3, and performs signal processing such as noise removal on the signal output from a row of pixels 3, column by column. For example, the column signal processing circuit 5 performs signal processing such as correlated double sampling (CDS) and analog-to-digital (AD) conversion for removing pixel-specific fixed-pattern noise. Each column signal processing circuit 5 has an output stage, which is provided with a horizontal selection switch (not shown) connected to the horizontal signal line 12.

[0024] For example, the horizontal drive circuit 6 includes a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scan signals to the column signal processing circuit 5 to select each column signal processing circuit 5 in sequence, and causes each column signal processor 5 to output the processed pixel signal to the horizontal signal line 12.

[0025] The output circuit 7 performs signal processing on each pixel signal sequentially supplied from the column signal processing circuit 5 via the horizontal signal line 12, and then outputs the pixel signal. For example, buffering, black level adjustment, column offset correction, and various types of digital signal processing can be used for signal processing.

[0026] Based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal, control circuit 8 generates clock and control signals that serve as references for the operation of vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6. Then, control circuit 8 outputs the generated clock and control signals to vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6.

[0027] <pixel> Pixel 3, for example, represents the phase difference detection pixel. Figure 3As shown, such a pixel 3 includes a photoelectric conversion unit 16. The photoelectric conversion unit 16 includes: photoelectric conversion elements PD1 and PD2, charge accumulation regions (floating diffusion sections) FD1 and FD2 that accumulate (hold) the signal charge photoelectrically converted by the photoelectric conversion elements PD1 and PD2, and transfer transistors TR1 and TR2 that transfer the signal charge photoelectrically converted by the photoelectric conversion units PD1 and PD2 to the charge accumulation regions FD1 and FD2. Furthermore, each of the plurality of pixels 3 includes a readout circuit 15 electrically connected to the photoelectric conversion unit 16, and more specifically, electrically connected to the charge accumulation regions FD1 and FD2.

[0028] Two photoelectric conversion elements, PD1 and PD2, each generate a signal charge corresponding to the amount of light they receive. PD1 and PD2 also temporarily accumulate (hold) the generated signal charge. The cathode side of photoelectric conversion element PD1 is electrically connected to the source region of transmission transistor TR1, and its anode side is electrically connected to a reference potential line (e.g., ground). The cathode side of photoelectric conversion element PD2 is electrically connected to the source region of transmission transistor TR2, and its anode side is electrically connected to a reference potential line (e.g., ground). For example, photodiodes can be used as photoelectric conversion elements PD1 and PD2.

[0029] Of the two transfer transistors TR1 and TR2, the drain region of transfer transistor TR1 is electrically connected to the charge accumulation region FD1. The gate electrode of transfer transistor TR1 is electrically connected to the transfer transistor drive line in pixel drive line 10 (see reference). Figure 2 The drain region of the transfer transistor TR2 is electrically connected to the charge accumulation region FD2. The gate electrode of the transfer transistor TR2 is electrically connected to the transfer transistor drive line in the pixel drive line 10.

[0030] In the two charge accumulation regions FD1 and FD2, charge accumulation region FD1 temporarily accumulates and retains the signal charge transmitted from photoelectric conversion element PD1 through transmission transistor TR1. Charge accumulation region FD2 temporarily accumulates and retains the signal charge transmitted from photoelectric conversion element PD2 through transmission transistor TR2.

[0031] The readout circuit 15 reads the signal charge accumulated in the charge accumulation regions FD1 and FD2 and outputs a pixel signal based on the signal charge. For example, the readout circuit 15 includes, but is not limited to, an amplifying transistor AMP, a selecting transistor SEL, and a reset transistor RST, which serve as pixel transistors. The transistors (AMP, SEL, and RST) are each formed by a MOSFET, which includes a gate insulating film formed of a silicon oxide film (SiO2 film), a gate electrode, and a pair of main electrode regions serving as source and drain regions. Alternatively, the transistors can be metal-insulating semiconductor FETs (MISFETs), whose gate insulating film is formed of a silicon nitride film (Si3N4 film) or a multilayer film including silicon nitride, silicon oxide, etc.

[0032] The source region of the amplifying transistor AMP is electrically connected to the drain region of the select transistor SEL, and its drain region is electrically connected to the power supply line Vdd and the drain region of the reset transistor. Furthermore, the gate electrode of the amplifying transistor AMP is electrically connected to the charge accumulation regions FD1 and FD2 and the source region of the reset transistor RST.

[0033] The source region of the select transistor SEL is electrically connected to the vertical signal line 11 (VSL), and its drain is electrically connected to the source region of the amplifying transistor AMP. Furthermore, the gate electrode of the select transistor SEL is electrically connected to the select transistor drive line in the pixel drive line 10 (see reference). Figure 2 ).

[0034] The source region of the reset transistor RST is electrically connected to the charge accumulation regions FD1 and FD2 and the gate electrode of the amplification transistor AMP, and its drain region is electrically connected to the power supply line Vdd and the drain region of the amplification transistor AMP. The gate electrode of the reset transistor RST is electrically connected to the reset transistor drive line in pixel drive line 10 (see reference). Figure 2 ).

[0035] An electronic device including a photodetector 1 performs autofocus based on the phase difference between corresponding signal charges accumulated in two photoelectric conversion elements PD1 and PD2. In the event of incorrect focus, a phase difference exists between the amount of signal charge Q1 accumulated in photoelectric conversion element PD1 and the amount of signal charge Q2 accumulated in photoelectric conversion element PD2. The electronic device operates to reduce this phase difference, for example, by manipulating the objective lens to correct the focus.

[0036] Then, after focus adjustment, the electronic device generates an image based on the obtained signal charge Q3 (Q3 = Q1 + Q2), where signal charge Q3 is the sum of the amount of signal charge Q1 accumulated in photoelectric conversion element PD1 and the amount of signal charge Q2 accumulated in photoelectric conversion element PD2. That is, the obtained signal charge Q3 corresponds to the pixel signal.

[0037] <<Overview>> First, the following will utilize Figure 4A Comparative Example 1 and 2 shown Figures 4B to 4D Comparative Example 2 shown will be used to illustrate the overview of this technology. First, it will be explained... Figure 4A Comparative Example 1 is shown.

[0038] <Comparative Example 1> A portion corresponding to pixel region 2A of semiconductor layer 20 is provided with island-shaped unit regions 20a, which are separated by isolation regions 20b and correspond one-to-one with pixels 3. Unit regions 20a are provided with well regions 21A, which are p-type semiconductor regions. Well regions 21A include contact regions 21A1, and a reference potential is supplied to well regions 21A through contact regions 21A1. Isolation regions 20b are provided with inter-pixel isolation structures 40A that primarily separate each pixel 3. Inter-pixel isolation structures 40A do not reach the first surface S1, therefore the pixels are not completely isolated. Therefore, well regions 21A can extend over multiple pixels 3, and contact regions 21A1 used to supply reference potential to well regions 21A can be shared among multiple pixels 3. Contact regions 21A1 are formed because the area on the side where the first surface S1 of unit regions 20a is located is separated by isolation structures 50A.

[0039] <Comparative Example 2> Next, I will explain Figures 4B to 4D Comparative Example 2 is shown. For example... Figure 4B As shown, the photoelectric detection device 1B includes an inter-pixel isolation structure 40 extending from the second surface S2 of the semiconductor layer 20 to the first surface S1. In recent years, to improve the optical and electrical characteristics of photoelectric detection devices, the inter-pixel isolation structure 40, which is a full trench isolation (FTI) structure for complete isolation between each unit region 20a, has been used. With this inter-pixel isolation structure 40, complete isolation is achieved between each pixel 3. Therefore, due to the inter-pixel isolation structure 40, the well region 21 cannot extend over multiple pixels 3 and cannot be separated for each pixel 3. Therefore, a contact region 22 for the well region 21 needs to be provided for each pixel 3.

[0040] Figure 4CAn exemplary configuration of the well region 21 and contact region 22 is shown. Contact region 22 is a portion of the semiconductor layer 20 and, in this embodiment, is formed of monocrystalline silicon. An isolation structure 50B is disposed around the contact region 22. The isolation structure 50B has a configuration in which grooves are formed on the semiconductor layer 20 using known photolithography and etching techniques, and insulating material is embedded in the formed grooves. Because the isolation structure 50B is disposed around the contact region 22, a separation is achieved between the contact region 22 and other semiconductor regions. To provide the contact region 22, it is necessary to ensure a dimension d obtained by adding twice the width of the isolation structure 50B to the dimension between the isolation structures 50B (the width of the contact region 22). Furthermore, such a dimension d needs to be ensured for each pixel 3. Therefore, in pixel 3, there is a possibility that the contact region 22 restricts the space for placing other components (such as transistors T). Figure 4D In Comparative Example 2 shown, an isolation structure 50B is provided so that the contact region 22 remains an active region. To ensure dimension d, the space available for placing the transistor T is limited, thus there is a possibility that it is difficult to place a large transistor T.

[0041] <<Detailed Structure of the Photoelectric Detection Device>> Next, the specific structure of the photoelectric detection device 1 according to the first embodiment of this technology will be described. Note that reference will be made to the comparative example 2 described above. Figure 4B The longitudinal cross-sectional structure of the pixels 3 included in the photoelectric detection device 1 is described. Each pixel 3 according to this embodiment is a phase difference detection pixel, while each pixel 2 according to Comparative Example 2 is a normal pixel. Furthermore, the photoelectric detection device 1 according to this embodiment differs from that according to Comparative Example 2 in that it includes a conductor 60 and a non-contact area 22. Despite these differences between this embodiment and Comparative Example 2, similarities also exist. Therefore, reference will be made to... Figure 4B Explain the similarities. Note that, for ease of explanation, [the text will be...]. Figure 4B The photoelectric detection device 1B in the image is considered as photoelectric detection device 1.

[0042] like Figure 4B As shown, the photoelectric detection device 1 includes, for example, a semiconductor layer 20 having one side as a first surface S1 and another side as a second surface S2; and a wiring layer 30 stacked on the second surface S2. Note that the first surface S1 can be referred to as the component forming surface or the main surface, and the second surface S2 can be referred to as the light incident surface or the back surface. Furthermore, the photoelectric detection device 1 may include, for example, a color filter CF, a microlens LN, etc., on the side where the second surface S2 of the semiconductor layer 20 is located.

[0043] Semiconductor layer 20 is formed from a semiconductor substrate. Semiconductor layer 20 is formed, for example, from a single-crystal silicon substrate, but is not limited thereto. Semiconductor layer 20 includes a semiconductor region of a first conductivity type and a semiconductor region of a second conductivity type. In this embodiment, an exemplary case will be given where the first conductivity type is n-type and the second conductivity type is p-type. In the following description, the semiconductor region described as n-type corresponds to the semiconductor region of the first conductivity type, and the semiconductor region described as p-type corresponds to the semiconductor region of the second conductivity type. Note that the technology is not limited to the above; therefore, the first conductivity type can be p-type, and the second conductivity type can be n-type.

[0044] The portion corresponding to the pixel region 2A of the semiconductor layer 20 is provided with a plurality of island-shaped unit regions 20a separated in a matrix by the isolated region 20b. For example, the unit regions 20a are configured to correspond one-to-one with pixels 3. The isolated region 20b is provided with an inter-pixel isolation structure 40 for isolating the unit regions 20a. The inter-pixel isolation structure 40 is an isolation wall that extends from the second surface S2 to the first surface S1 in the thickness direction of the semiconductor layer 20 and penetrates through the semiconductor layer 20 in the thickness direction. The inter-pixel isolation structure 40, for example, has a structure in which an isolation material is embedded in a trench provided in the semiconductor layer 20. Examples of isolation materials include insulating materials such as silicon oxide (SiO2). In addition, examples of isolation materials include conductive materials such as polysilicon and metals. Note that when the isolation material is formed of a conductive material, firstly, the inner wall of the trench is covered with an insulating film, and then the conductive material is embedded.

[0045] Figure 4B An example of an inter-pixel isolation structure 40 comprising multiple parts is shown. The inter-pixel isolation structure 40 mainly includes: a first part 41, which isolates each photoelectric conversion element PD and is located on the second surface S2 side; and a second part 42, which is connected to the first part 41 in the thickness direction and is located on the first surface S1 side. The dimension of the second part 42 in the Z direction is smaller than the dimension of the first part 41 in the Z direction. For example, the second part 42 is characterized by shallow trench isolation (STI), and the first part 41 is characterized by deep trench isolation (DTI). For example, the second part 42 is formed of an insulating material such as silicon oxide. Note that this technology is not limited to... Figure 4B The pixel isolation structure 40 shown may consist of only the first part 41. In this case, the first part 41 extends from the second surface S2 to the first surface S1.

[0046] Wiring layer 30 is a multilayer wiring layer. Wiring layer 30 includes, but is not limited to, an insulating film 31 and wiring such as lateral wiring and longitudinal wiring disposed in the insulating film 31, the insulating film 31 including, for example, a layer formed of a known insulating material. Figure 4BA via 32 is shown as an example of a vertical wiring. For example, the via 32 is formed of a metal such as tungsten (W). Furthermore, the wiring layer 30 is provided with the gate electrode G of a transistor.

[0047] The microlens LN is an on-chip lens that focuses incident light onto the semiconductor layer 20. The color filter CF separates the incident light after it has passed through the microlens LN. For example, the color filter CF and the microlens LN are provided for each pixel 3. For example, the color filter CF and the microlens LN are formed of a resin material.

[0048] Next, we will refer to Figures 5A to 5C Further explanation of the photoelectric detection device 1 according to this embodiment. In this embodiment, as an example, the application of this technology to dual PD phase difference detection pixels will be given. For example... Figure 5C As shown, pixel 3 is a dual-PD pixel, for example, having a pair of photoelectric conversion elements PD1 and PD2 on the left and right sides within a single pixel 3. Furthermore, pixel 3 has a single microlens LN that overlaps with both photoelectric conversion elements PD1 and PD2. Pixel 3 is a pupil-segmented pixel where a beam of light passing through the shared microlens LN (the same single microlens LN) enters photoelectric conversion elements PD1 and PD2 in a segmented manner. Photoelectric conversion element PD1 includes a photoelectric conversion region 23a, which is an n-type semiconductor region, and photoelectric conversion element PD2 includes a photoelectric conversion region 23b, which is also an n-type semiconductor region. Photoelectric conversion regions 23a and 23b perform photoelectric conversion on the incident light. Note that, unless there is a need to distinguish them, photoelectric conversion regions 23a and 23b are simply referred to as photoelectric conversion region 23.

[0049] like Figure 5B As shown, the unit region 20a of pixel 3 is provided with a well region 21, which is a p-type semiconductor region. The well region 21 is a semiconductor region containing known impurities (dopants), which make the semiconductor p-type. Since each pixel 3 is isolated by the inter-pixel isolation structure 40, the well region 21 cannot extend over multiple pixels 3, but is provided for each pixel 3. The conductor 60 is connected to the first surface S1 side of the well region 21, and a reference potential is supplied to the well region 21 through the conductor 60. The conductor 60 is provided in the through hole 51 of the through element isolation structure 50. The element isolation structure 50 and the conductor 60 will be described below.

[0050] <Component Isolation Structure> A component isolation structure 50 is provided on the first surface S1 side of the cell region 20a. The component isolation structure 50 is characterized by shallow trench isolation (STI), in which a trench 52 is formed on the cell region 20a from the first surface S1 side, and an insulating material such as silicon oxide is embedded in the formed trench 52. Note that the second part 42 of the inter-pixel isolation structure 40 is formed similarly to the component isolation structure 50. Then, as... Figure 5A As shown, the component isolation structure 50 and the second part 42 can be integrally formed together in the plan view. Figure 5A and Figure 5B As shown, the element isolation structure 50 divides the first surface S1 side of the unit region 20a into multiple semiconductor regions. The semiconductor regions separated by the element isolation structure 50 are referred to as active regions 24. For example, in each active region 24, elements such as transistors and charge accumulation regions FD, which are n-type semiconductor regions, are formed. Figure 5A As shown, the active region 24 is surrounded by the element isolation structure 50 and the second part 42. The region between each active region 24 can be called the field region. Figure 5B As shown, the element isolation structure 50 has a bottom surface 53 that contacts the well region 21. Furthermore, the well region 21 is closer to the second surface S2 than the active region 24, and closer to the first surface S1 than the photoelectric conversion region 23. That is, the well region 21 is located at a depth between the photoelectric conversion region 23 and the active region 24 in the thickness direction of the semiconductor layer 20.

[0051] For example, in Figure 5A In the example shown, cell region 20a includes four active regions 24 and four transistors T1, T2, T3, and T4. Furthermore, one transistor is formed within each active region 24. Each active region contains a source region, a drain region, and a channel formation region, etc., of the transistor. Transistor T1 is a transfer transistor TR1, and transistor T2 is a transfer transistor TR2. Transistors T3 and T4 are pixel transistors, distinct from the transfer transistors, and are, for example, any one of an amplifying transistor AMP, a selecting transistor SEL, and a reset transistor RST, respectively. Component isolation structure 50 electrically isolates these transistors. The larger the area of ​​the active region 24, the greater the channel length and channel width the transistor can have.

[0052] <Conductor> Conductor 60 serves as a contact portion for supplying a reference potential to semiconductor layer 20. More specifically, conductor 60 serves as a contact portion for supplying a reference potential to a semiconductor portion within unit region 20a. Figure 5BAs shown, the element isolation structure 50 has a portion overlapping the well region 21 in the plan view, and this portion is provided with a through hole 51 extending through the element isolation structure 50 in the thickness direction. The through hole 51 is filled with a conductor 60. A first end 61, which is the end of the conductor 60 on the second surface S2 side, protrudes from the bottom surface 53 of the element isolation structure 50 and connects to the cell region 20a of the semiconductor layer 20, more specifically, to the well region 21. Furthermore, the first end 61 has an end face 62 located at almost the same depth as the bottom surface 53 of the element isolation structure 50 and in contact with the well region 21. The end of the conductor 60 on the wiring layer 30 side is connected to a via 32, and a reference potential as a base voltage is supplied to the conductor 60 through the via 32. Note that the via 32 connected to the end face of the conductor 60 on the first surface S1 side can be referred to as a contact plug. Furthermore, although the case where each transistor is an NMOS transistor has been given in this variant example, even if each transistor is a PMOS transistor, it is only necessary to supply an appropriate reference potential to the conductor 60 through the via 32. Figure 5A and Figure 5B As shown, conductor 60 is isolated from active region 24 by element isolation structure 50. More specifically, conductor 60 has sides surrounded by element isolation structure 50 and isolated from active region 24. The material forming conductor 60 is, for example, polysilicon containing known impurities (dopersants) that make the semiconductor p-type. Note that conductor 60 is not limited in its location and number. Figure 5A .

[0053] <<Manufacturing Method of Photoelectric Detection Device>> The manufacturing method for the photoelectric detection device 1 will be described below. In this embodiment, only the processes related to the element isolation structure 50 and the conductor 60 will be described, and other processes will be described. First, as Figure 6A As shown, using known photolithography and etching techniques, trenches 52 for burying the device isolation structure 50 are formed on the semiconductor layer 20 from its first surface S1 side. Then, for example, an insulating film such as silicon oxide is formed to fill the trenches 52, and any excess is removed. Thus, the device isolation structure 50 is obtained. Next, a well region 21 is formed by ion implantation using a known impurity that makes the semiconductor p-type. Note that the device isolation structure 50 can be formed after ion implantation using impurities.

[0054] Next, as Figure 6BAs shown, a resist pattern R1 with an opening R1a is formed using a known photolithography technique. The opening R1a is located in the device isolation structure 50 at the position where the conductor 60 will be placed. Then, the portion included in the device isolation structure 50 and overlapping the opening R1a in the plan view is etched to form a through-hole 51 penetrating the device isolation structure 50. Thus, a region for burying polysilicon is formed in the device isolation structure 50. Next, as... Figure 6C As shown, a polycrystalline silicon film m1 is formed to fill the through-hole 51 as the material for forming the conductor 60.

[0055] Next, as Figure 6D As shown, any excess portion of the polysilicon film m1 is removed to planarize the exposed surface. Next, as... Figure 6E As shown, a resist pattern R2 with an opening R2a is formed on the exposed surface using a known photolithography technique. The opening R2a is positioned in the planar view at a location overlapping with the polysilicon film embedded in the through-hole 51, and ion implantation of impurities is performed through the opening R2b to make the polysilicon conductive. Thus, a conductor 60 is obtained.

[0056] <<Main Effects of the First Implementation Plan>> The main effects of the first embodiment will now be explained. In the photoelectric detection device 1 according to the first embodiment of the present invention, since the conductor 60 is disposed in the through hole 51 that penetrates the element isolation structure 50 along the thickness direction, the conductor 60 can be disposed in a space-saving manner. Furthermore, in the photoelectric detection device 1 according to the first embodiment of the present invention, the conductor 60 is used as a well contact to supply a reference potential to the semiconductor portion in the cell region 20a. Therefore, the increase in the area required to provide the well contact can be suppressed, thereby enabling the supply of a reference potential to the semiconductor portion in the cell region 20a in a space-saving manner. Therefore, the area occupied by other components such as transistors can be prevented from being limited by the conductor 60, that is, excessive area reduction can be prevented. Therefore, improvements in characteristics such as the roll-off characteristic and random noise of transistors can be expected.

[0057] Furthermore, in the photoelectric detection device 1 according to the first embodiment of the present technology, a through-hole 51 is formed in the element isolation structure 50 and a conductor 60 is embedded in the through-hole 51, instead of forming the element isolation structure 50 to leave a contact area in the well region 21. Therefore, when forming the element isolation structure 50, it is not necessary to leave a semiconductor layer as a contact area. Therefore, the conductor 60 can be formed without considering the minimum size of the trench 52 in which the element isolation structure 50 is provided, thereby enabling the formation of a space-saving conductor 60.

[0058] Note that, according to Patent Document 1, a substrate contact electrode is provided on the upper surface of the FDTI that isolates each pixel, and the substrate contact electrode is shared between adjacent pixels. However, according to Patent Document 1, since the substrate contact electrode and the active region are in contact with each other, there is a possibility that impurities in the substrate contact electrode may diffuse into the active region during heat treatment, thereby interfering with the impurities in the active region. Therefore, it is believed that the proximity between the substrate contact electrode and the active region increases the electric field, which may increase the dark current.

[0059] In contrast, in the photoelectric detection device 1 according to the first embodiment of this technology, since the side of the conductor 60 formed of p-type polysilicon is surrounded by the element isolation structure 50, the conductor 60 is isolated from the active region 24. Therefore, the diffusion of p-type impurities in the conductor 60 into the active region 24 can be suppressed, thereby suppressing the increase of dark current.

[0060] Furthermore, in the photoelectric detection device 1 according to the first embodiment of this technology, the conductor 60 is not formed of a metallic material, but is made of p-type polycrystalline silicon. Metallic materials can potentially cause extensive contamination of the semiconductor layer 20, while the conductor 60 made of polycrystalline silicon is unlikely to cause such contamination, unlike metallic materials.

[0061] <<Variations on the First Implementation Plan>> The following will describe a variation of the first implementation scheme.

[0062] <Variation Example 1> In the photoelectric detection device 1 according to the modified example 1 of the first embodiment, such as Figure 7 As shown, conductor 60 has a first end 61 protruding from the bottom surface 53 of element isolation structure 50, and the first end 61 has an end face 62 and a side face 63 that contact the well region 21.

[0063] Even when using the photoelectric detection device 1 according to the modified example 1 of the first embodiment, it is possible to obtain effects similar to those of the photoelectric detection device 1 according to the first embodiment described above.

[0064] Furthermore, in the photoelectric detection device 1 of the modified example 1 according to the first embodiment, since both the end face 62 and the side face 63 are in contact with the well region 21, the contact area between the conductor 60 and the well region 21 is increased, thereby reducing the contact resistance between the conductor 60 and the well region 21.

[0065] <Variation Example 2> In the photoelectric detection device 1 according to the modified example 2 of the first embodiment, such as Figure 8As shown, conductor 60 and a through-hole (contact plug) 32 connected to conductor 60 are positioned such that this position overlaps with a position located between the sidewalls W disposed on the gate electrode G in the plan view. The sidewalls W are disposed at the edge portions of the gate electrodes G of transistors T3 and T4. The gate electrodes G of transistors T3 and T4 are adjacent to each other, and their adjacent portions are provided with sidewalls W. Then, in the plan view, conductor 60 is disposed at a position overlapping with the position between the adjacent sidewalls W, and the through-hole 32 for supplying a reference potential to conductor 60 is connected to the end face of the first surface S1 side of conductor 60. That is, in the plan view, the through-hole 32, as a contact plug, is also disposed at a position overlapping with the position between the adjacent sidewalls W. In this modified example, the hollow between the sidewalls W is used for self-alignment to form the through-hole 32.

[0066] Even when using the photoelectric detection device 1 according to the modified example 2 of the first embodiment, it is possible to obtain effects similar to those of the photoelectric detection device 1 according to the first embodiment described above.

[0067] Furthermore, in the photoelectric detection device 1 of the modified embodiment 2 according to the first embodiment, since the hollow portion between the sidewalls W of the gate electrode G is used for self-alignment in this modified embodiment, large overlap misalignment between the through hole 32 and the conductor 60 can be suppressed when the through hole 32 is formed. Therefore, the width (diameter) of the conductor 60 can be set to be narrower than in the first embodiment, thereby further saving space. In addition, if the width of the element isolation structure 50, which is the part used to set the conductor 60, is the same as in the first embodiment, then when the conductor 60 is set to be narrower, the width of the element isolation structure 50 is relatively increased, thereby improving the withstand voltage performance.

[0068] <Variation Example 3> In the photoelectric detection device 1 according to the modified example 3 of the first embodiment, such as Figure 9 As shown, a pad 64 is provided between the end face of the conductor 60 on the first surface S1 side and the through hole 32, which serves as a contact plug. Furthermore, in the plan view, the area of ​​the pad 64 is larger than the area of ​​the end face of the conductor 60 on the first surface S1 side. For example, the pad 64 is formed of the same material as the conductor 60.

[0069] Even when using the photoelectric detection device 1 according to the modified example 3 of the first embodiment, similar effects as those of the photoelectric detection device 1 according to the first embodiment are obtained.

[0070] Furthermore, in the photoelectric detection device 1 of the modified example 3 according to the first embodiment, since the pad 64 is provided, by reducing the width of the conductor 60, an overlap margin can be ensured between the through hole 32, which serves as a contact plug, and the conductor 60.

[0071] [Second Implementation Plan] The following will explain Figures 10 to 14 The photoelectric detection device 1 according to the second embodiment of the present technology is shown. First, an overview will be given. <<Overview>> To improve the low-light performance of solid-state imaging devices, research has been conducted to suppress dark currents caused by silicon crystal defects surrounding the element isolation used to isolate the transmission gate or pixel transistor. According to Patent Document 2, p+ impurity regions are formed not only on the surface of the pixel but also on the bottom and sidewalls of the STI region to suppress dark current generation. However, in some cases, slightly generated dark currents flow into the photodiode, affecting its noise characteristics, thus making it difficult to improve the low-light performance of the photodetector.

[0072] <<Detailed Structure of the Photoelectric Detection Device>> Next, the specific structure of the photoelectric detection device 1 according to the second embodiment of the present technology will be described. Note that components similar to those in the photoelectric detection device 1 according to the first embodiment described above are indicated by the same reference numerals, and their descriptions will be omitted.

[0073] Similar to the first embodiment, the portion of the semiconductor layer 20 corresponding to the pixel region 2A is provided with multiple island-shaped unit regions 20a separated by an isolated region 20b in a matrix configuration. For example... Figure 10 As shown, in this embodiment, the isolation region 20b is provided with a first part 41, which serves as an inter-pixel isolation structure that mainly separates each pixel 3.

[0074] The photoelectric detection device 1 includes a plurality of active regions 24 separated by an element isolation structure 50. For mutual distinction, the plurality of active regions 24 are referred to as active regions 24a, 24b, and 24c. When mutual distinction is not required, active regions 24a, 24b, and 24c are simply referred to as active region 24. Active region 24a is provided with transistors T3 and T4, which serve as pixel transistors, and a well contact 25, which serves as a p-type semiconductor region, disposed between transistors T3 and T4. Transistors T3 and T4 each have a pair of main electrode regions that are n+ semiconductor regions. Diffusion regions 26 and 27 disposed in active region 24a are semiconductor regions forming one of the pair of main electrode regions of transistor T3 and one of the pair of main electrode regions of transistor T4, respectively. In a plan view, diffusion regions 26 and 27 are located at a position overlapping with a first impurity region 28. Active region 24b is provided with transistor T1, which serves as a transmission transistor, and charge accumulation region FD, while active region 24c is provided with transistor T2, which also serves as a transmission transistor, and charge accumulation region FD. Furthermore, the photodetector 1 includes a plug 33 electrically connected to the charge accumulation region FD. For example, the plug 33 is made of polysilicon.

[0075] Furthermore, in the planar view, the first impurity region 28, which is a p-type semiconductor region, is set as a unit region 20a covering pixel 3. All transistors T1, T2, T3, and T4 are positioned at locations overlapping the first impurity region 28 in the planar view. (Refer to...) Figures 11 to 13 The first impurity region 28 will be described in more detail. Figure 11 It shows along Figure 10 The first impurity region 28 is a longitudinal sectional view of the cross-section structure in the planar sectional view taken along line A-A'. The first impurity region 28 is a semiconductor region containing a known impurity (dopant) that makes the semiconductor p-type. In this embodiment, the device isolation structure 50 has a bottom surface 53 that contacts the first impurity region 28. Furthermore, the first impurity region 28 is positioned closer to the light incident surface (second surface S2) than the active region 24, and closer to the device formation surface (first surface S1) than the photoelectric conversion region 23. That is, the first impurity region 28 is located at a depth between the photoelectric conversion region 24 and the active region 24 in the thickness direction of the semiconductor layer 20.

[0076] Figure 12 It shows along Figure 11 The impurity distribution (regarding impurities that make the semiconductor p-type) along line B-B'. The vertical axis represents silicon depth, and the horizontal axis represents impurity concentration. Note that the explanation will be based on the assumption that the depth increases from the device formation surface (first surface S1) to the light incident surface. Furthermore, Figure 12The dotted line indicates the depth of the bottom surface 53 of the element isolation structure 50. The impurity concentration has two peaks in the depth direction: peak P1 and peak P2. Peak P1 is due to the formation of the well contact 25, and peak P2 is due to the formation of the first impurity region 28. Peak P2 is located in the region of the first impurity region 28 where the impurity concentration is highest in the depth direction. The impurity concentration gradually decreases from peak P2 towards the shallower side (towards the element forming surface), forming a valley at the depth between the first impurity region 28 and the well contact 25. The valley of impurity concentration is located shallower than the depth of the bottom surface 53, and the impurity concentration has a gradient that gradually increases (rises) from the depth of the valley and the depth of the bottom surface 53 towards the deeper side (more specifically, towards the photoelectric conversion region 23), as shown below. Figure 12 As indicated by the arrow, the depth of peak P2 is shallower than the depth of photoelectric conversion region 23. Furthermore, peak P2 is located deeper than the bottom surface 53 of element isolation structure 50. That is, the impurity concentration in the first impurity region 28 is higher at a depth deeper than the bottom surface 53 than at a depth within the bottom surface 53.

[0077] Note that it is sufficient if the impurity concentration at the peak P2 is more than 8 times, more specifically, more than 10 times, the impurity concentration at the valley. Furthermore, it is sufficient if the impurity concentration at the peak P2 is more than 8 times, more specifically, more than 10 times, the impurity concentration at the depth of the bottom surface 53.

[0078] Figure 13 It shows along Figure 11 The potential distribution along line B-B'. The magnitude of the potential is based on... Figure 12 The concentration of impurities is determined by the concentration of impurities, therefore its behavior is similar to that of impurity concentration. For example... Figure 13 As indicated by the arrows, the magnitude of the potential has a gradient that gradually increases from the depth of the valley and the depth of the bottom surface 53 towards the deeper side (more specifically, towards the photoelectric conversion region 23). Due to this gradient, the charge (electrons) generated as noise hardly exceeds the peak P2, and therefore hardly flows to the side of the semiconductor layer 20 deeper than the peak P2. Since the impurity concentration of the first impurity region 28 increases from the depth of the bottom surface 53 towards the deeper side, a potential barrier is formed between the bottom surface 53 and the photoelectric conversion region 23, thereby preventing dark current generated from the semiconductor around the element isolation structure 50 from easily flowing to the photoelectric conversion region 23. Furthermore, as Figure 11 As shown, the dark current moves along at least one of the bottom surface 53 or the side surface of the element isolation structure 50, and then flows to the diffusion region 26.

[0079] Transistors T3 and T4 are pixel transistors, and are, for example, any of the following: amplifying transistor AMP, selecting transistor SEL, resetting transistor RST, and switching transistor SW. (Refer to the following...) Figure 14 This describes the switching transistor SW. Note that... Figure 14 The equivalent circuit for a normal pixel is shown, not the equivalent circuit for a phase difference pixel. The switching transistor SW is a conversion efficiency switching transistor. The charge accumulation region FD and the reset transistor RST are connected through the switching transistor SW. That is, one of the source / drain terminals of the switching transistor SW is connected to the charge accumulation region FD, and the other is connected to one of the source / drain terminals of the reset transistor RST. The other of the source / drain terminal of the reset transistor RST is connected to the power supply line Vdd.

[0080] Using a pixel with this structure, when the gate of the switching transistor SW is off, the charge accumulation region FD is disconnected from the source / drain of the reset transistor RST, thus having a small capacitance. Because the capacitance of the charge accumulation region FD is small, a small number of electrons can significantly reduce the voltage, resulting in a high-sensitivity output signal. However, when the signal charge is large, the signal charge overflows from the charge accumulation region FD, making it difficult to obtain the original signal corresponding to the incident amount. When the gate of the switching transistor SW is on, the charge accumulation region FD is connected to the source / drain of the reset transistor RST, thus having a large capacitance. Due to the large capacitance, a large number of electrons can be received, but the sensitivity decreases. As described above, by switching the gate of the switching transistor SW, thereby combining the image generated by the charge read in the high-sensitivity operating mode and the image generated by the charge read in the low-sensitivity operating mode, the dynamic range can be increased.

[0081] <<Manufacturing Method of Photoelectric Detection Device>> The manufacturing method of the photoelectric detection device 1 will be described below. In this embodiment, only the processes related to the element isolation structure 50 and the first impurity region 28 will be described, and other processes will be described. First, as Figure 15A As shown, a photoelectric conversion region 23 is formed in a desired region of the semiconductor layer 20 using an ion implantation method. Next, the semiconductor layer 20 is etched from the first surface S1 side using known photolithography and dry etching techniques, and an insulating material is embedded to form a device isolation structure 50. Thus, the active region 24 is separated.

[0082] Next, as Figure 15B As shown, a resist pattern with openings in the desired region is formed using a known photolithography technique. Then, a first impurity region 28 is formed by ion implantation using impurities that make the semiconductor p-type, resulting in an impurity concentration gradient that gradually increases from the bottom surface 53 of the device isolation structure 50 to deeper sides.

[0083] Then, as Figure 15C As shown, a resist pattern is formed using a known photolithography technique, and ion implantation is performed on the desired region using impurities. More specifically, a trap contact 25 is formed by ion implantation using impurities that make the semiconductor p-type, and a diffusion region 26 is formed by ion implantation using impurities that make the semiconductor n-type.

[0084] <<Main Effects of the Second Implementation Plan>> The main effects of the second embodiment will now be explained. In the photoelectric detection device 1 according to the second embodiment of the present invention, the cell region includes a first impurity region 28, which is a p-type semiconductor region, at a depth position between the photoelectric conversion region 23 and the active region 24. The first impurity region 28 contains impurities that make the semiconductor a second conductivity type, and the impurity concentration of the first impurity region 28 has a gradient that gradually increases from the depth position of the bottom surface 53 of the element isolation structure 50 to a deeper side. Therefore, the magnitude of the potential also has a gradient that gradually increases from the depth position of the bottom surface 53 to a deeper side (more specifically, towards the photoelectric conversion region 23). Due to this gradient, the charge (electrons) generated as noise hardly flows to the deeper side. Therefore, dark current hardly flows into the photoelectric conversion region 23, thereby suppressing the degradation of noise characteristics.

[0085] Furthermore, in the photoelectric detection device 1 according to the second embodiment of the present technology, the region with the highest impurity concentration in the depth direction of the first impurity region 28 is located at a depth greater than that of the bottom surface 53. Therefore, a potential barrier is formed between the bottom surface 53 and the photoelectric conversion region 23, thereby preventing dark current generated from the semiconductor around the element isolation structure 50 from easily flowing to the photoelectric conversion region 22.

[0086] <<Variations on the Second Implementation Plan>> The following will describe a variation of the second implementation scheme.

[0087] <Variation Example 1> In the photoelectric detection device 1 according to the second embodiment, such as Figure 16 As shown, diffusion region 26 is the drain region of transistor T3, and diffusion region 27 is the drain region of transistor T4. Diffusion regions 26 and 27 are electrically connected to the power supply line Vdd through via 32. The dark current flowing through diffusion regions 26 and 27 is discharged to the power supply line Vdd. Transistors T3 and T4 are transistors that are any of the following: an amplifying transistor AMP, a selecting transistor SEL, a reset transistor RST, and a switching transistor SW, and their drain regions are connected to the power supply line Vdd. T3 and T4 are, for example, reset transistors.

[0088] Even when using the photoelectric detection device 1 according to the modified example 1 of the second embodiment, it is possible to obtain effects similar to those of the photoelectric detection device 1 according to the second embodiment described above.

[0089] Furthermore, in the photoelectric detection device 1 according to Modification 1 of the second embodiment, when dark current flows into each drain region electrically connected to the power supply line Vdd, the dark current is discharged to the power supply line Vdd. Therefore, it is possible to suppress the influence of the generated dark current on the characteristics of the pixel transistor. Note that although the pixel transistors are NMOS transistors as described in this embodiment, when the pixel transistors are PMOS transistors, it is only necessary to discharge the dark current from the appropriate one of the pair of main electrode regions to the appropriate potential line.

[0090] <Variation Example 2> In the photoelectric detection device 1 according to the second embodiment, variant 2, such as Figure 17 As shown in the plan view, the first impurity region 28 is located outside the channel formation region of transistors T1 and T2, which are transmission transistors.

[0091] Active regions 24b and 24c, among the multiple active regions 24, are respectively provided with a transfer transistor and a charge accumulation region FD. In this modified example, a first impurity region 28 is disposed outside of transistors T1 and T2 and the charge accumulation region FD. Transistors T3 and T4 are disposed at positions overlapping with the first impurity region 28 in the plan view.

[0092] Even when using the photoelectric detection device 1 according to the modified example 2 of the second embodiment, it is possible to obtain effects similar to those of the photoelectric detection device 1 according to the second embodiment described above.

[0093] Furthermore, in the photoelectric detection device 1 according to the modified embodiment of the second embodiment, the first impurity region 28 is removed from the path for transmitting the signal charge generated in the photoelectric conversion region 23 to each charge accumulation region FD, thereby making it easy to ensure the transmission path.

[0094] <Variation Example 3> like Figure 18 As shown, the photoelectric detection device 1 according to the second embodiment, variant 3, includes a second impurity region 29 along the side surface 54 and bottom surface 53 of the element isolation structure 50, which is a semiconductor region of a second conductivity type. Because the second impurity region 29 is provided, dark current generation in the semiconductor region surrounding the element isolation structure 50 can be suppressed.

[0095] Furthermore, the impurity concentration in the second impurity region 29 is set to be lower than the impurity concentration in the first impurity region 28. (Refer to...) Figure 19The dashed line AA represents the impurity distribution in the second embodiment, and the solid line BB represents the impurity distribution in this modified example. As shown, the impurity distribution based on solid line BB, where the second impurity region 29 is provided, has shallower valleys than the impurity distribution based on dashed line AA, and the gradient of impurity concentration is gentle from the depth of the valleys and the depth of the bottom surface 53 toward the photoelectric conversion region 23. Therefore, in order to suppress dark current inflow into the photoelectric conversion region 23, it is desirable to suppress the impurity concentration of the second impurity region 29 to be as low as possible.

[0096] Even when using the photoelectric detection device 1 according to the modified example 3 of the second embodiment, it is possible to obtain effects similar to those of the photoelectric detection device 1 according to the second embodiment described above.

[0097] Furthermore, in the photoelectric detection device 1 of the modified example 3 according to the second embodiment, since the second impurity region 29 is provided, dark current generated from the semiconductor region around the element isolation structure 50 can be suppressed.

[0098] <Variation Example 4> In the photoelectric detection device 1 according to the second embodiment, variant 4, such as Figure 20 As shown, the first impurity region 28 serves as the well region for transistors T3 and T4, which are pixel transistors. The reference numeral CH denotes the channel formation region of each of transistors T3 and T4.

[0099] Even when using the photoelectric detection device 1 according to the modified example 4 of the second embodiment, it is possible to obtain effects similar to those of the photoelectric detection device 1 according to the second embodiment described above.

[0100] Furthermore, in the photoelectric detection device 1 of the modified example 4 according to the second embodiment, since the first impurity region 28 is provided for the well region of the pixel transistor, the manufacturing process can be reduced.

[0101] [Third Implementation Plan] <1. Examples of applications of electronic devices> Next, I will explain Figure 21 The electronic device 100 shown is a third embodiment of the present technology. The electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. The electronic device 100 is, for example, but not limited to, an electronic device such as a camera. Furthermore, the electronic device 100 includes a photoelectric detection device 1, such as that described above, as the solid-state imaging device 101.

[0102] An optical lens (optical system) 102 forms an image of the image light (incident light 106) from the subject on the imaging surface of the solid-state imaging device 101. Therefore, signal charge accumulates in the solid-state imaging device 101 over a certain period of time. A shutter device 103 controls the light illumination period and the light blocking period of the solid-state imaging device 101. A drive circuit 104 supplies drive signals for controlling the transmission operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103. Based on the drive signals (timing signals) supplied from the drive circuit 104, the solid-state imaging device 101 performs signal transmission. A signal processing circuit 105 performs various types of signal processing on the signals (pixel signals) output from the solid-state imaging device 101. The processed video signal is stored in a storage medium such as a memory or output to a monitor.

[0103] By utilizing this structure, performance degradation of the solid-state camera device 101 is suppressed in the electronic device 100, thereby improving the image quality of the video signal.

[0104] Note that electronic device 100 is not limited to a camera, and therefore can be any other electronic device. For example, it could be a camera device (such as a camera module) for mobile devices (such as mobile phones).

[0105] In addition, the electronic device 100 may include any photoelectric detection device 1 according to the first and second embodiments and variations thereof, or a combination of at least two of the first and second embodiments and variations thereof, as a solid-state imaging device 101.

[0106] [Fourth Implementation Plan] The following will explain Figures 22 to 24 The photoelectric detection device 1 according to the fourth embodiment of the present technology is shown. First, an overview will be given.

[0107] <<Overview>> In some cases, pixel transistors and charge accumulation regions are formed side-by-side in the lateral direction within a pixel (e.g., Patent Document 3). In such pixels, for example, STI is used to separate pixel transistors from charge accumulation regions, and between individual pixel transistors. However, when the active region where the pixel transistor is located and the active region where the charge accumulation region is located are adjacent, the STI interface (Si / SiO2 interface) on the charge accumulation region side is depleted due to the potential of the source / drain region (n+ region) of the pixel transistor, becoming a source of dark current and resulting in white spots.

[0108] Patent Document 4 describes a device isolation region with a shallow trench isolation (STI) structure. The device isolation region of Patent Document 4 includes a conductive film disposed in a trench portion via a first insulating film, and a second insulating film superimposed on the conductive film on the first side of the semiconductor layer in a plan view. In the plan view, the conductive film 68 is disposed over the entire device isolation region 65, but is not limited thereto, and a contact portion for applying a reference potential is disposed on the conductive film 68. However, due to miniaturization in recent years, the design rules for wiring are very strict, making it difficult to provide a contact portion for applying a reference potential on the conductive film 68.

[0109] <<Detailed Structure of the Photoelectric Detection Device>> Next, the specific structure of the photoelectric detection device 1 according to the fourth embodiment of this technology will be described. Note that components similar to those in the photoelectric detection device 1 according to the first embodiment described above are indicated by the same reference numerals, and their descriptions will be omitted. Figure 23 As shown, the component isolation structure 50 is disposed on the first surface S1 side of the cell region 20a. The component isolation structure 50 is mainly composed of shallow trench isolation (STI), wherein trenches are formed from the first surface S1 side in the cell region 20a, and an insulating material such as silicon oxide is embedded in the formed trenches. Figure 22 As shown, the semiconductor region separated by at least one of the element isolation structure 50 or the second part 42 of the pixel isolation structure 40 is the active region 24. Furthermore, the element isolation structure 50 and the second part 42 can be integrally formed together. The element isolation structure 50 and the second part 42 are each primarily composed of STI (Surface Mount Technology), and the second part 42 can be used not only to separate individual pixels but also to separate individual active regions 24. The element isolation structure 50 and the second part 42 can be combined together as an element isolation structure (42, 50).

[0110] exist Figure 22 In the example shown, the unit region 20a, which is the semiconductor region of pixel 3, is provided with four active regions 24. Note that the number of active regions is not limited to this. Figure 22The number of active regions is specified. To distinguish them, the four active regions are referred to as active regions 24d, 24e, 24f, and 24g. When no distinction is needed, the four active regions are simply referred to as active region 24. Active region 24d is equipped with transistor T1 and charge accumulation region FD1. Active region 24e is equipped with transistor T2 and charge accumulation region FD2. Active region 24f is equipped with transistor T3. Active region 24g is equipped with transistor T4. Note that when no distinction is needed, charge accumulation regions FD1 and FD2 are simply referred to as charge accumulation region FD. Transistors T3 and T4 are pixel transistors, and active regions 24f and 24g, which are equipped with pixel transistors, correspond to the first active region. Furthermore, active regions 24d and 24e, which are equipped with charge accumulation regions FD1 and FD2 respectively, correspond to the second active region.

[0111] like Figure 22 and Figure 24 As shown, the photoelectric detection device 1 according to this embodiment includes the conductor 60 described in the first embodiment of this technology. As... Figure 24 As shown, the first end 61, which is the end of the conductor 60 on the second surface S2 side, is connected to the well region 21. More specifically, the first end 61 is connected to the contact portion 21B, which is a p+ semiconductor region with a higher impurity concentration than the well region 21. The end of the conductor 60 on the first surface S1 side is exposed from the upper surface of the element isolation structure 50, and a via 32 for supplying a reference potential is directly connected to this end. The via 32 for supplying a reference potential to the conductor 60 can be referred to as via 32a to distinguish it from other vias 32. The reference potential is supplied to the contact portion 21B of the well region 21 through the via 32a and the conductor 60.

[0112] like Figure 22 As shown, the photoelectric detection device 1 according to this embodiment includes a shielding wall 70, which is embedded in the element isolation structure 50 and connected to the conductor 60. For example, the shielding wall 70 is formed of conductive polysilicon and can be integrally formed with the conductor 60 using the same material (p-type polysilicon) as the conductor 60. Similar to the conductor 60, a reference potential is supplied to the shielding wall 70. That is, the shielding wall 70 is a conductor connected to the reference potential. For example, the shielding wall 70 is fixed at the reference potential. Figure 23 As shown, the shielding wall 70 is embedded in the groove 55 provided in the component isolation structure 50, and its upper surface is also covered with the insulating material forming the component isolation structure 50. The upper surface (the surface on the first surface S1 side), the lower surface (the surface on the second surface S2 side), and the side surface of the shielding wall 70 are in contact with the insulating material forming the component isolation structure 50. Without penetrating the component isolation structure 50, the lower surface of the shielding wall 70 is located at a position greater than the lower surface of the conductor 60. Figure 5B The shallow position of end face 62 shown.

[0113] like Figure 22 As shown, a shielding wall 70 is disposed between adjacent active regions 24f and 24d in the Y direction, and shields at least a portion of the electric field generated between active regions 24f and 24d. Similarly, a shielding wall 70 is disposed between active regions 24g and 24e, and shields at least a portion of the electric field generated between active regions 24g and 24e. For example, this electric field is generated by the n-type main electrode region (one of the source and drain regions) of transistors T3 and T4. The shielding wall 70 is provided to suppress the influence of the electric field generated by the n-type main electrode region on other active regions. Figure 23 As shown, the lower surface of the shielding wall 70 is located deeper than the lower surface of the n-type main electrode region (either the source region or the drain region) of transistor T3. Similarly, although not shown, the lower surface of the shielding wall 70 is located deeper than the lower surface of the n-type main electrode region of transistor T4. This configuration of the shielding wall 70 enables more effective electric field shielding. In the plan view, the shielding wall 70 extends in the X direction. The shielding wall 70 extending in the X direction can be referred to as shielding wall 71 to distinguish it from the shielding walls extending in different directions as described later.

[0114] <<Manufacturing Method of Photoelectric Detection Device>> The following will refer to Figures 25 to 28 The manufacturing method of the photoelectric detection device 1 will be described. In this embodiment, only the steps related to the shielding wall 70 and the conductor 60 will be described, and other steps will be described. Figures 25 to 28 It shows along Figure 22 The cross-sectional structure in the planar sectional view intercepted by line CC. For example... Figure 25 As shown, firstly, a shielding wall 70 is embedded in the component isolation structure 50. Then, as... Figure 26 As shown, a resist pattern R3 with an opening R3a is formed using a known photolithography technique. The opening R3a is located in the device isolation structure 50 at the position where the conductor 60 will be placed. Note that a hard mask can be used instead of the resist pattern R3. Then, the portion of the device isolation structure 50 that overlaps with the opening R3a in the planar view is etched to form a through-hole 51 penetrating the device isolation structure 50.

[0115] Next, as Figure 27 As shown, ion implantation using p-type impurities is performed on the well region 21 exposed from the through-hole 51 to form the contact 21B. Next, material for forming the conductor 60 is embedded into the through-hole 51, and any excess is removed to obtain the conductor 60. Then, as... Figure 28As shown, the resist pattern R3 is removed to form wiring layers such as vias 32a.

[0116] <<Main Effects of the Fourth Implementation Plan>> The photoelectric detection device 1 according to the fourth embodiment of the present technology includes a shielding wall 70 embedded in an element isolation structure 50 primarily composed of an STI (Surface Insulation Technology). Therefore, at least a portion of the electric field generated between the active regions 24 is shielded, thereby suppressing the effects of voltage modulation or coupling through the STI. Thus, dark current can be suppressed, thereby suppressing white spots. Furthermore, the shielding wall 70 is embedded in a trench 55, meaning the shielding wall 70 can be formed in a tiny gap.

[0117] Furthermore, in the photoelectric detection device 1 according to the fourth embodiment of this technology, since the shielding wall 70 is disposed between the active regions 24f and 24g, where transistors T3 and T4 are respectively disposed, and the active regions 24d and 24e, where charge accumulation regions FD are respectively disposed, the influence of the electric field generated by the n-type main electrode region on the active regions where charge accumulation regions FD are disposed can be suppressed. Therefore, dark current can be suppressed, thereby suppressing white spots.

[0118] Furthermore, in the photoelectric detection device 1 according to the fourth embodiment of this technology, since the shielding wall 70 is connected to the conductor 60 that supplies a reference potential to the well region, the shielding wall 70 does not require a dedicated contact for applying the reference potential. Therefore, even in pixels with reduced size, the shielding wall 70 can be provided in a space-saving manner, thereby suppressing the limitation on the size of the pixel transistor.

[0119] <<Variations on the Fourth Implementation Plan>> The following will describe a variation of the fourth implementation scheme.

[0120] <Variation Example 1> In the photoelectric detection device 1 according to the fourth embodiment, such as Figure 29 As shown, a shielding wall 70 is provided between transistors T3 and T4 that are adjacent to each other in the X direction. According to this modification, shielding wall 70 extends in the Y direction in the plan view and is referred to as shielding wall 72 to distinguish it from shielding wall 71. When no distinction is needed, shielding walls 71 and 72 are simply referred to as shielding wall 70. Figure 30 As shown, the shielding wall 72 is disposed between the active region 24f and the active region 24g, and shields at least a portion of the electric field generated between the main electrode region of transistor T3 and the main electrode region of transistor T4.

[0121] In the photoelectric detection device 1 of the fourth embodiment of the present invention, since the shielding wall 70 is provided between transistor T3 and transistor T4, the effects of voltage modulation or coupling between the transistors can be suppressed. Therefore, dark current can be suppressed, thereby suppressing white spots.

[0122] <Variation Example 2> The shapes of transistors T3 and T4 are not limited to Figure 22 The rectangle shown is an example of this. Figure 31 As shown, in the photoelectric detection device 1 of Modified Example 2 according to the fourth embodiment, the transistors T3 and T4 are trapezoidal in shape.

[0123] <Variation Example 3> Reference Figure 32 The photoelectric detection device 1 according to the fourth embodiment, variant 3, is described. Figure 32 The diagram shows pixels 3 arranged in two rows and four columns. To distinguish them, pixels 3 in the two rows and two columns on the left side of the diagram are referred to as pixel 3a, and pixels 3 in the two rows and two columns on the right side are referred to as pixel 3b. Pixels 3a and 3b are equipped with color filters of different colors. For example, pixels 3a in the two rows and two columns are equipped with a green filter, and pixels 3b in the two rows and two columns are equipped with a blue filter. As described above, pixels 3a in the two rows and two columns form a pixel unit of the same color Ca, and pixels 3b in the two rows and two columns form a pixel unit of the same color Cb. When there is no need to distinguish them, pixel units Ca and Cb are simply referred to as pixel unit C. Among the multiple charge accumulation regions FD included in pixel unit Ca, to distinguish them from other charge accumulation regions, the charge accumulation region FD located closest to pixel unit Cb is referred to as charge accumulation region FDa. Furthermore, among the multiple charge accumulation regions FD included in the same-color pixel unit Cb, in order to distinguish them from other charge accumulation regions, the charge accumulation region FD located closest to the same-color pixel unit Ca is referred to as charge accumulation region FDb. Charge accumulation regions FDa and FDb are adjacent to each other in the X direction.

[0124] A shielding wall 72 is disposed between adjacent pixel units C of the same color in the X direction. The shielding wall 72 is disposed between each charge accumulation region FDa and corresponding charge accumulation region FDb that are adjacent to each other in the X direction, and shields at least a portion of the electric field generated between each charge accumulation region FDa and corresponding charge accumulation region FDb.

[0125] Note that the shielding wall 72 can be continuously disposed on multiple pixels 3. Furthermore, the photoelectric detection device 1 according to this modification also includes a shielding wall 71 disposed between the charge accumulation regions FD adjacent to each other in the Y direction and the transistors T3 and T4. The shielding wall 71 can be continuously disposed on multiple pixels 3.

[0126] In the photoelectric detection device 1 of Modification 3 according to the fourth embodiment of the present technology, since the charge accumulation regions FDa and FDb are adjacent to each other across the boundary between the same-color pixel unit Ca and the same-color pixel unit Cb, and a shielding wall 72 is provided between each charge accumulation region FDa and its corresponding charge accumulation region FDb, the effects of voltage modulation or coupling between each charge accumulation region FDa and its corresponding charge accumulation region FDb can be suppressed. Therefore, dark current can be suppressed, thereby suppressing white spots. Furthermore, color mixing can be suppressed.

[0127] <Variation Example 4> In the photoelectric detection device 1 according to the fourth embodiment, variation 4, such as Figure 33 As shown, the conductor 60 has a first end 61 that protrudes from the bottom surface of the element isolation structure 50 and reaches the interior of the contact portion 21B.

[0128] <Variation Example 5> In the photoelectric detection device 1 according to the fourth embodiment, variant 5, such as Figure 34 As shown, the lower surface of the shielding wall 70 is disposed at the same depth as the lower surface of the conductor 60. Therefore, the lower end of the shielding wall 70 protrudes from the bottom surface of the element isolation structure 50 and reaches the interior of the trap region 21.

[0129] In the manufacturing method of the photoelectric detection device 1 according to the fourth embodiment, the embedding of the material for forming the shielding wall 70 and the embedding of the material for forming the conductor 60 are performed separately. In contrast, in the photoelectric detection device 1 of the modified example 5 of the fourth embodiment according to the present technology, since the lower surface of the shielding wall 70 is provided at the same depth as the lower surface of the conductor 60, the embedding of the material for forming the shielding wall 70 and the embedding of the material for forming the conductor 60 can be performed simultaneously.

[0130] <Variation Example 6> Although reference Figure 32 Through holes 32a are provided for each conductor 60, but in the photoelectric detection device 1 according to the fourth embodiment, such as Figure 35 As shown, it is not necessary to provide a through-hole 32a for each conductor 60. In this modified example, a reference potential is supplied to multiple conductors 60 through a single through-hole 32a. Furthermore, although the reference... Figure 32The vias 32a used to supply the reference potential are directly connected to the conductors 60, but in the photoelectric detection device 1 according to the fourth embodiment, such as Figure 35 As shown, the via 32a does not need to be directly connected to the conductor 60. In this modified example, the shielding wall 70 is configured to connect the plurality of conductors 60 together, and the via 32a is connected to the shielding wall 70 so that a reference potential is supplied to the plurality of conductors 60 through the shielding wall 70.

[0131] exist Figure 35 In the example shown, a shielding wall 72 is provided for connecting conductors 60 in mutually different unit regions 20a. More specifically, a shielding wall 72 is provided for connecting conductors 60 in two adjacent unit regions 20a. Furthermore, a through-hole 32a is connected to the shielding wall 72 to supply a reference potential to the shielding wall 72. Note that, as... Figure 36 As shown, the upper surface of the shielding wall 72 is covered with insulating material. Therefore, a connecting portion 70A can be provided connected to the shielding wall 72, but whose upper surface is not covered by insulating material, and the through hole 32a can be connected to the upper surface of the connecting portion 70A. The connecting portion 70A is part of the shielding wall 70. Figure 35 In the example shown, although a shield 72 is used to supply a reference potential to multiple conductors 60, a shield 71 can also be used to supply a reference potential to multiple wires 60.

[0132] In the photoelectric detection device 1 of the modified example 6 according to the fourth embodiment, since multiple conductors 60 share a single through hole 32a, the number of through holes 32a can be reduced, and the degree of freedom in wiring design can be increased.

[0133] <Variation Example 7> In the photoelectric detection device 1 according to the fourth embodiment, variation 7, such as Figure 37 As shown, shielding walls 71 and 72 are arranged in a grid pattern on multiple pixels 3, such that the corresponding conductors 60 of each pixel 3 are connected together. Figure 37 In the example shown, because the shielding walls 71 and 72 are arranged in a grid pattern, the four conductors 60 in two rows and two columns included in pixel 3 are electrically connected together. Furthermore, in Figure 37 In the example shown, a through-hole 32a is provided to supply a reference potential to the four conductors 60.

[0134] In the photoelectric detection device 1 of Modification 7 according to the fourth embodiment, since multiple conductors 60 share a single through-hole 32a, the number of through-holes 32a can be reduced, and the flexibility of wiring design can be increased. Furthermore, since the shielding walls 71 and 72 are arranged in a grid pattern, the multiple conductors 60 are connected together, thus further reducing the number of through-holes 32a compared to Modification 6 described above.

[0135] <Variation Example 8> In the photoelectric detection device 1 according to the fourth embodiment, variant 8, such as Figures 38 to 41 As shown, this technology can be applied to square pixels. A square pixel has a structure in which the inter-pixel isolation structure 40 is formed as a square in the X and Y directions, as shown... Figure 38 As shown, a photoelectric conversion region 23 is formed within a pixel. Figure 38 As shown, the photoelectric detection device according to this modification includes multiple transistors T such as pixel transistors, transmission transistors, and transmission gates (TG, vertical gates). The shielding wall 70 is configured such that the active regions 24, each having a charge accumulation region FD, are surrounded in the plan view.

[0136] exist Figure 39 In the square pixel shown, the inter-pixel isolation structure 40 does not isolate the individual charge accumulation regions FD of pixel 3; therefore, the individual charge accumulation regions FD of pixel 3 are integrally formed. Furthermore, the shape of the pixel transistor is not limited to... Figure 38 The shape in, and therefore can be Figure 40 or Figure 41 The shape shown.

[0137] [Other Implementation Plans] As described above, the present technology has been illustrated with first to fourth embodiments; however, it should not be understood that the descriptions and drawings that form part of this disclosure limit the present technology. Various alternative embodiments, examples, and operational techniques will be apparent to those skilled in the art based on this disclosure.

[0138] For example, the various technical ideas described in the first to fourth embodiments can be combined with each other. For instance, various combinations can be made based on the various technical ideas, such as the combination of the first and second embodiments described above. Furthermore, the electronic device 100 described in the third embodiment may include the photoelectric detection device 1 described in the fourth embodiment.

[0139] Furthermore, this technology can be applied not only to the aforementioned solid-state imaging devices as image sensors, but also to any photoelectric detection device, such as a distance measuring sensor also known as a time-of-flight (ToF) sensor. A distance measuring sensor is a sensor that emits illumination light towards an object, detects the reflected light (i.e., illumination light reflected from the object's surface), and calculates the distance to the object based on the time of flight from emitting the illumination light to receiving the reflected light. As the structure of the distance measuring sensor, any of the aforementioned pixel structures can be used.

[0140] Furthermore, for example, the materials mentioned as forming the aforementioned constituent elements may include additives, impurities, etc. Additionally, in the accompanying drawings of embodiments according to this technology, illustrations of some elements such as gate oxide films are omitted.

[0141] As stated above, needless to say, this technology also includes various embodiments not described herein. Therefore, the scope of this technology is limited only by the matters specified in the claims, which are reasonably derived from the foregoing description.

[0142] Furthermore, the effects described in this article are merely examples and are not limiting; therefore, other effects can be achieved.

[0143] Note that this technology can have the following configuration. (1) A photoelectric detection device, comprising: A semiconductor layer having one side as a light incident surface and another side as a device forming surface, the semiconductor layer comprising a plurality of unit regions, the plurality of unit regions being isolated from each other by isolation walls extending from the light incident surface to the device forming surface; A component isolation structure made of insulating material is disposed on the component forming surface side of each of the unit regions, and the component isolation structure divides the component forming surface side of the unit regions into multiple active regions in a plan view; A through hole that penetrates the element isolation structure in the thickness direction; and A conductor disposed within the through-hole has a first end, which is the end on the light incident surface side and contacts the semiconductor portion within the unit region. Each unit region includes a photoelectric conversion region, and A reference potential is supplied to the cell region through the conductor. (2) According to the photoelectric detection device described in (1), wherein The photoelectric conversion region is of the first conductivity type. The unit regions each include a second conductivity type well region located at a depth position between the photoelectric conversion region and the active region, and The first end contacts the trap region. (3) According to the photoelectric detection device described in (2), wherein The component isolation structure is embedded from the component forming surface side in a trench disposed in the unit region, and The bottom surface of the element isolation structure is in contact with the trap region. (4) The photoelectric detection device according to any one of (1) to (3), wherein The first end protrudes from the bottom surface of the element isolation structure, and The end face and side face of the first end portion are in contact with the semiconductor portion within the unit region. (5) The photoelectric detection device according to any one of (1) to (4) further includes: Two transistors are arranged such that their gate electrodes are adjacent to each other; Sidewalls, disposed at each adjacent edge of the gate electrode, are made of an insulating material; and A contact plug for supplying the reference potential to the conductor, the contact plug being connected to an end face of the conductor formed on the element-forming side, wherein... The conductor is positioned such that its position overlaps with the position of each of the sidewalls of the edge portion in a plan view. (6) The photoelectric detection device according to (5) further includes: A pad is disposed between the end face of the conductor on the element forming surface side and the contact plug, wherein In the plan view, the area of ​​the pad is larger than the area of ​​the end face on the element forming side of the conductor. (7) The photoelectric detection device according to any one of (1) to (6), wherein The conductor is made of polycrystalline silicon of the second conductivity type. (8) An electronic device comprising: Photoelectric detection device; And an optical system configured to form an image of the image light from the subject onto the photoelectric detection device, wherein The photoelectric detection device includes: A semiconductor layer having one side as a light incident surface and another side as a device forming surface, the semiconductor layer comprising a plurality of unit regions, the plurality of unit regions being isolated from each other by isolation walls extending from the light incident surface to the device forming surface; A component isolation structure made of insulating material is disposed on the component forming surface side of each of the unit regions, and the component isolation structure divides the component forming surface side of the unit regions into multiple active regions in a plan view; A through hole that penetrates the element isolation structure in the thickness direction; and A conductor disposed within the through-hole has a first end, which is the end on the light incident surface side and contacts the semiconductor portion within the unit region. Each unit region includes a photoelectric conversion region, and A reference potential is supplied to the cell region through the conductor. (9) A photoelectric detection device, comprising: A semiconductor layer having one side as a light incident surface and another side as a component forming surface, the semiconductor layer comprising a matrix of multiple unit regions, each unit region containing a photoelectric conversion region of a first conductivity type; and A component isolation structure made of insulating material is disposed on the component forming surface side of each of the said unit regions. In a plan view, the component isolation structure divides the component forming surface side of the unit regions into multiple active regions, wherein... Each unit region includes a first impurity region, which is a semiconductor region of a second conductivity type located at a depth between the photoelectric conversion region and the active region. The first impurity region contains impurities that enable the semiconductor to become a second conductivity type, and The concentration of the impurities in the first impurity region has a gradient that gradually increases from the depth of the bottom surface of the element isolation structure to the deeper side. (10) According to the photoelectric detection device described in (9), wherein The region in the first impurity region where the concentration of the impurity is highest in the depth direction is located at a depth greater than that of the bottom surface. (11) The photoelectric detection device according to claim 9 further includes: A diffusion region of the first conductivity type is disposed in each of the active regions and overlaps with the first impurity region in a planar view. (12) According to the photoelectric detection device described in (11), wherein The diffusion region is one of a pair of main electrode regions of the pixel transistor located in the active region, and the diffusion region is electrically connected to the power supply line. (13) The photoelectric detection device according to any one of (9) to (12), wherein At least one of the plurality of active regions includes a charge accumulation region as a semiconductor region of a first conductivity type and a transfer transistor capable of transferring signal charge from the photoelectric conversion region to the charge accumulation region, and In the plan view, the first impurity region is located at a position that does not overlap with the channel formation region of the transmission transistor. (14) The photoelectric detection device according to any one of (9) to (13), wherein The active regions each include pixel transistors, and The first impurity region is located at a position overlapping with the pixel transistor in the plan view. (15) The photoelectric detection device according to any one of (9) to (14) further includes The second impurity region is a semiconductor region of a second conductivity type along the side and bottom surfaces of the element isolation structure. (16) According to the photoelectric detection device described in (15), wherein The impurity concentration in the second impurity region is lower than that in the first impurity region. (17) According to the photoelectric detection device of claim 14, wherein The first impurity region serves as the well region of the pixel transistor. (18) According to the photoelectric detection device described in (14), wherein The pixel transistor is an amplification transistor, a selection transistor, a reset transistor, or a conversion efficiency switching transistor. (19) An electronic device comprising: Photoelectric detection device; And an optical system configured to form an image of the image light from the subject onto the photoelectric detection device, wherein The photoelectric detection device includes: A semiconductor layer having one side as a light incident surface and another side as a component forming surface, the semiconductor layer comprising a matrix of multiple unit regions, each unit region containing a photoelectric conversion region of a first conductivity type; and A component isolation structure made of insulating material is disposed on the component forming surface side of each of the said unit regions. In a plan view, the component isolation structure divides the component forming surface side of the unit regions into multiple active regions, wherein... Each unit region includes a first impurity region, which is a semiconductor region of a second conductivity type located at a depth between the photoelectric conversion region and the active region. The first impurity region contains impurities that enable the semiconductor to become a second conductivity type, and The concentration of the impurities in the first impurity region has a gradient that gradually increases from the depth of the bottom surface of the element isolation structure to the deeper side. (20) The photoelectric detection device according to (1) further includes: The shielding wall embedded in the component isolation structure, wherein The shielding wall is connected to the conductor. (twenty one) According to the photoelectric detection device described in (20), wherein The plurality of said active regions include: a first active region, which is an active region containing a pixel transistor; and a second active region, which is an active region containing a charge accumulation region that is a semiconductor region of a first conductivity type. The shielding wall is disposed between the first active region and the second active region. (twenty two) According to the photoelectric detection device described in (20) or (21), wherein The light incident surface of the shielding wall is disposed at the same depth as the light incident surface of the conductor. (twenty three) The photoelectric detection device according to any one of (20) to (22) further includes: A via for supplying the reference potential, wherein The shielding wall is configured to connect the conductor of one unit region of the plurality of unit regions to the conductor of another unit region of the plurality of unit regions, and The through hole is connected to the shielding wall. (twenty four) The photoelectric detection device according to any one of (20) to (23) further includes: Multiple pixel transistors disposed in the active region, wherein The shielding wall is disposed between the pixel transistors. (25) The photoelectric detection device according to any one of (20) to (24), wherein The first end protrudes from the bottom surface of the element isolation structure, and The end face and side face of the first end portion are in contact with the semiconductor portion within the unit region. (26) The photoelectric detection device according to any one of (20) to (25) further includes: Square pixels, which are included in the cell region in two rows and two columns.

[0144] The scope of this technology is not limited to the exemplary embodiments shown and described, and therefore includes all embodiments that produce equivalent effects to those intended by this technology. Furthermore, the scope of this technology is not limited to the combination of features of the invention as defined by the claims, and therefore can be defined by any desired combination of specific features from all disclosed features. List of reference numerals

[0145] 1. Photoelectric detection device 3 pixels 20 Semiconductor Layers 20a Unit Region 20b Isolation Area 21 Tunnel Region 21B Contact Section 23, 23a, 23b Photoelectric conversion regions 24, 24a, 24b, 24c, 24d, 24e, 24f, 24g Active regions 26, 27 Diffusion region (main electrode region) 28 First impurity region 29 Second impurity region 32, 32a Through holes (contact plugs) 40-pixel isolation structure (isolation wall) 50-element isolation structure 51 Through Hole 52. Trench 53 Bottom 54 Side View 60 conductor 61 First end 62 end face 63 Side View 64 pads Shielding walls 70, 71, and 72 70A Connection Part 100 Electronic devices 102 Optical System AMP amplification transistor Charge accumulation regions FD, FD1, and FD2 G gate electrode RST reset transistor SEL selects transistors Transistors T1, T2, T3, T4, and T TR1 and TR2 transfer transistors Vdd power cord W sidewall

Claims

1. A photoelectric detection device, comprising: A semiconductor layer having one side as a light incident surface and another side as a device forming surface, the semiconductor layer comprising a plurality of unit regions, the plurality of unit regions being isolated from each other by isolation walls extending from the light incident surface to the device forming surface; A component isolation structure made of insulating material is disposed on the component forming surface side of each of the unit regions, and the component isolation structure divides the component forming surface side of the unit regions into multiple active regions in a plan view; A through hole that penetrates the component isolation structure in the thickness direction; as well as A conductor disposed within the through-hole has a first end, which is the end on the light incident surface side and contacts the semiconductor portion within the unit region. Each unit region includes a photoelectric conversion region, and A reference potential is supplied to the cell region through the conductor.

2. The photoelectric detection device according to claim 1, wherein... The photoelectric conversion region is of the first conductivity type. The unit regions each include a second conductivity type well region located at a depth position between the photoelectric conversion region and the active region, and The first end contacts the trap region.

3. The photoelectric detection device according to claim 2, wherein... The component isolation structure is embedded from the component forming surface side in a trench disposed in the unit region, and The bottom surface of the element isolation structure is in contact with the trap region.

4. The photoelectric detection device according to claim 1, wherein... The first end protrudes from the bottom surface of the element isolation structure, and The end face and side face of the first end portion are in contact with the semiconductor portion within the unit region.

5. The photoelectric detection device according to claim 1, further comprising: Two transistors are arranged such that their gate electrodes are adjacent to each other; Sidewalls, which are disposed at each adjacent edge of the gate electrode, are made of insulating material; and A contact plug for supplying the reference potential to the conductor, the contact plug being connected to an end face of the conductor formed on the element-forming side, wherein... The conductor is positioned such that its position overlaps with the position of each of the sidewalls of the edge portion in a plan view.

6. The photoelectric detection device according to claim 5 further includes: A pad is disposed between the end face of the conductor on the element forming surface side and the contact plug, wherein In the plan view, the area of ​​the pad is larger than the area of ​​the end face on the element forming side of the conductor.

7. The photoelectric detection device according to claim 1, wherein... The conductor is made of polycrystalline silicon of the second conductivity type.

8. An electronic device comprising: Photoelectric detection device; And an optical system configured to form an image of the image light from the subject onto the photoelectric detection device, wherein The photoelectric detection device includes: A semiconductor layer having one side as a light incident surface and another side as a device forming surface, the semiconductor layer comprising a plurality of unit regions, the plurality of unit regions being isolated from each other by isolation walls extending from the light incident surface to the device forming surface; A component isolation structure made of insulating material is disposed on the component forming surface side of each of the unit regions, and the component isolation structure divides the component forming surface side of the unit regions into multiple active regions in a plan view; A through hole that penetrates the element isolation structure in the thickness direction; and A conductor disposed within the through-hole has a first end, which is the end on the light incident surface side and contacts the semiconductor portion within the unit region. Each unit region includes a photoelectric conversion region, and A reference potential is supplied to the cell region through the conductor.

9. A photoelectric detection device, comprising: A semiconductor layer having one side as a light incident surface and another side as a component forming surface, the semiconductor layer comprising a matrix of multiple unit regions, each unit region containing a photoelectric conversion region of a first conductivity type; and A component isolation structure made of insulating material is disposed on the component forming surface side of each of the said unit regions. In a plan view, the component isolation structure divides the component forming surface side of the unit regions into multiple active regions, wherein... Each unit region includes a first impurity region, which is a semiconductor region of a second conductivity type located at a depth between the photoelectric conversion region and the active region. The first impurity region contains impurities that enable the semiconductor to become a second conductivity type, and The concentration of the impurities in the first impurity region has a gradient that gradually increases from the depth of the bottom surface of the element isolation structure to the deeper side.

10. The photoelectric detection device according to claim 9, wherein... The region in the first impurity region where the concentration of the impurity is highest in the depth direction is located at a depth greater than that of the bottom surface.

11. The photoelectric detection device according to claim 9, further comprising: A diffusion region of the first conductivity type is disposed in each of the active regions and overlaps with the first impurity region in a planar view.

12. The photoelectric detection device according to claim 11, wherein... The diffusion region is one of a pair of main electrode regions of the pixel transistor located in the active region, and the diffusion region is electrically connected to the power supply line.

13. The photoelectric detection device according to claim 9, wherein... At least one of the plurality of active regions includes a charge accumulation region as a semiconductor region of a first conductivity type and a transfer transistor capable of transferring signal charge from the photoelectric conversion region to the charge accumulation region, and In the plan view, the first impurity region is located at a position that does not overlap with the channel formation region of the transmission transistor.

14. The photoelectric detection device according to claim 9, wherein... The active regions each include pixel transistors, and The first impurity region is located at a position overlapping with the pixel transistor in the plan view.

15. The photoelectric detection device according to claim 9, further comprising: The second impurity region is a semiconductor region of a second conductivity type along the side and bottom surfaces of the element isolation structure.

16. The photoelectric detection device according to claim 15, wherein... The impurity concentration in the second impurity region is lower than that in the first impurity region.

17. The photoelectric detection device according to claim 14, wherein... The first impurity region serves as the well region of the pixel transistor.

18. The photoelectric detection device according to claim 14, wherein... The pixel transistor is an amplification transistor, a selection transistor, a reset transistor, or a conversion efficiency switching transistor.

19. An electronic device comprising: Photoelectric detection device; And an optical system configured to form an image of the image light from the subject onto the photoelectric detection device, wherein The photoelectric detection device includes: A semiconductor layer having one side as a light incident surface and another side as a component forming surface, the semiconductor layer comprising a matrix of multiple unit regions, each unit region containing a photoelectric conversion region of a first conductivity type; and A component isolation structure made of insulating material is disposed on the component forming surface side of each of the said unit regions. In a plan view, the component isolation structure divides the component forming surface side of the unit regions into multiple active regions, wherein... Each unit region includes a first impurity region, which is a semiconductor region of a second conductivity type located at a depth between the photoelectric conversion region and the active region. The first impurity region contains impurities that enable the semiconductor to become a second conductivity type, and The concentration of the impurities in the first impurity region has a gradient that gradually increases from the depth of the bottom surface of the element isolation structure to the deeper side.

20. The photoelectric detection device according to claim 1, further comprising: The shielding wall embedded in the component isolation structure, wherein The shielding wall is connected to the conductor.

21. The photoelectric detection device according to claim 20, wherein... The plurality of said active regions include: The first active region is the active region containing the pixel transistor; The second active region is an active region that includes a charge accumulation region that is a semiconductor region of the first conductivity type, and The shielding wall is disposed between the first active region and the second active region.

22. The photoelectric detection device according to claim 20, wherein... The light incident surface of the shielding wall is disposed at the same depth as the light incident surface of the conductor.

23. The photoelectric detection device according to claim 20, further comprising: A via for supplying the reference potential, wherein The shielding wall is configured to connect the conductor of one unit region of the plurality of unit regions to the conductor of another unit region of the plurality of unit regions, and The through hole is connected to the shielding wall.

24. The photoelectric detection device according to claim 20, further comprising: Multiple pixel transistors disposed in the active region, wherein The shielding wall is disposed between the pixel transistors.

25. The photoelectric detection device according to claim 20, wherein... The first end protrudes from the bottom surface of the element isolation structure, and The end face and side face of the first end portion are in contact with the semiconductor portion within the unit region.

26. The photoelectric detection device according to claim 20, further comprising: A square pixel, comprising two rows and two columns of the unit region.

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