Method for manufacturing a semiconductor light-receiving element

Abstract

Multiple semiconductor light-receiving elements (2) are formed on a wafer-shaped semiconductor substrate (1). Wafer testing is performed to check the electrical characteristics of each of the multiple semiconductor light-receiving elements (2). Semiconductor light-receiving elements (2) that fail the wafer testing are coated with ink (22). During the formation of the semiconductor light-receiving elements (2), a semiconductor layer (4) having at least a light-absorbing layer (8) is formed on the semiconductor substrate (1). An annular upper surface electrode (13) opening the light-receiving portion (12) is formed on the semiconductor layer (4), and a first trench (15) and a second trench (16) are formed penetrating the semiconductor layer (4) and reaching the semiconductor substrate (1). When viewed from above, the first trench (15) surrounds the upper surface electrode (13). When viewed from above, the second trench (16) surrounds the first trench (15).

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a semiconductor light-receiving element. Background Technology

[0002] In the manufacture of semiconductor light-receiving devices, wafer testing is typically performed on the wafer to inspect the electrical characteristics of each chip. Chips that fail the wafer test are usually coated with ink to distinguish them from qualified chips. If this ink flows out from the target chip and covers the light-receiving portion or electrodes of an adjacent chip, the adjacent chip will become a defective product during visual inspection, leading to a decrease in yield. On the other hand, to reduce dark current, semiconductor light-receiving devices with annular grooves formed in the light-absorbing layer have been proposed (for example, see Patent Document 1).

[0003] Patent Document 1: Japanese Patent No. 5045436

[0004] However, the grooves in existing semiconductor light-receiving elements are not designed to prevent ink leakage; the shallow grooves extending down to the light-absorbing layer are insufficient to prevent ink leakage. Even assuming the grooves are made deeper, a single groove alone cannot adequately prevent ink leakage. Summary of the Invention

[0005] This disclosure was made to solve the aforementioned problems, and its purpose is to provide a method for manufacturing semiconductor light-receiving elements that can prevent a decrease in yield.

[0006] The method for manufacturing a semiconductor light-receiving element disclosed herein is characterized by comprising the following steps: a step of forming a plurality of semiconductor light-receiving elements on a wafer-shaped semiconductor substrate; a step of performing wafer testing to inspect the electrical characteristics of the plurality of semiconductor light-receiving elements respectively; and a step of coating ink on the semiconductor light-receiving elements that fail the wafer testing. When forming the semiconductor light-receiving element, a semiconductor layer having at least a light-absorbing layer is formed on the semiconductor substrate, an annular upper surface electrode that opens the light-receiving portion is formed on the semiconductor layer, and a first groove and a second groove that penetrate the semiconductor layer and reach the semiconductor substrate are formed. When viewed from above, the first groove surrounds the upper surface electrode, and when viewed from above, the second groove surrounds the first groove.

[0007] In this disclosure, during the formation of the semiconductor photoreceiving element, a first trench and a second trench are formed that penetrate the semiconductor layer and reach the semiconductor substrate. When viewed from above, the first trench surrounds the upper surface electrode, and the second trench surrounds the first trench. This increases the number of times the ink is subjected to surface tension, thus making it easier to trap the ink. Furthermore, ink can flow not only into the first trench but also into the second trench, thereby reducing the amount of ink flowing towards the outer periphery of the upper surface of the semiconductor photoreceiving element. This prevents ink from flowing out into adjacent chips, thereby preventing a decrease in yield. Attached Figure Description

[0008] Figure 1 This is a top view showing a wafer on which the semiconductor light-receiving element of Embodiment 1 is formed.

[0009] Figure 2 This is a cross-sectional view showing the semiconductor light-receiving element of Embodiment 1.

[0010] Figure 3 This is a top view showing the semiconductor light-receiving element of Embodiment 1.

[0011] Figure 4 This is a cross-sectional view showing the case where the semiconductor light-receiving elements of Embodiment 1 are adjacent.

[0012] Figure 5 This is a cross-sectional view showing the wafer testing process.

[0013] Figure 6 This is a cross-sectional view showing the state in which ink has been applied to the semiconductor light-receiving element of Embodiment 1.

[0014] Figure 7 This is a cross-sectional view showing the state in which ink has been applied to the semiconductor light-receiving element of Embodiment 1.

[0015] Figure 8 This is a cross-sectional view showing the semiconductor light-receiving element of Embodiment 2.

[0016] Figure 9 This is a cross-sectional view showing the semiconductor light-receiving element of Embodiment 3.

[0017] Figure 10 This is a top view of the semiconductor light-receiving element according to Embodiment 3. Detailed Implementation

[0018] The manufacturing method of the semiconductor light-receiving element according to the embodiments will be described with reference to the accompanying drawings. The same or corresponding components are labeled with the same reference numerals, and repeated descriptions may be omitted.

[0019] Implementation method 1.

[0020] Figure 1 This is a top view showing a wafer on which the semiconductor light-receiving elements of Embodiment 1 are formed. A plurality of semiconductor light-receiving elements 2 are formed in a matrix on a wafer-shaped semiconductor substrate 1. Cutting lines 3 are formed between adjacent semiconductor light-receiving elements 2.

[0021] Figure 2 This is a cross-sectional view showing the semiconductor light-receiving element of Embodiment 1. Figure 3This is a top view showing the semiconductor light-receiving element according to Embodiment 1. On a semiconductor substrate 1, as a semiconductor layer 4, a multilayer reflective layer 5, a multiplication layer 6, an electric field mitigation layer 7, a light absorption layer 8, a BDR layer 9, a window layer 10, and a contact layer 11 are sequentially formed. The semiconductor substrate 1 is, for example, n-type InP. The multilayer reflective layer 5 is a layer composed of 8 to 20 pairs of low-refractive-index layers such as n-type InP or AlInAs and high-refractive-index layers such as n-type GaInAs, GaInAsP, and AlGaInAs. The multiplication layer 6 is composed of i-type AlInAs, etc. The electric field mitigation layer 7 is composed of p-type InP, AlInAs, etc. The light absorption layer 8 is composed of n-type InGaAs, InGaAsP, InGaAsSb, etc. The BDR layer 9 is composed of n-type InGaAsP, AlGaInAs, etc. The window layer 10 is composed of p-type InP, InGaAsP, AlInAs, AlGaInAs, or combinations thereof. The contact layer 11 is composed of p-type InGaAs, InP, InGaAsP, AlInAs, AlGaInAs, or combinations thereof.

[0022] An annular upper surface electrode 13 is formed on the contact layer 11, opening the light-receiving portion 12. The upper surface electrode 13 is made of Ti, Pt, Au, etc. The opening of the annular upper surface electrode 13 becomes the light-receiving portion 12 of the semiconductor light-receiving element 2. A lower surface electrode 14 is formed on the lower surface of the semiconductor substrate 1. The lower surface electrode 14 is made of Ti, Pt, Ni, Au, etc.

[0023] A first trench 15 and a second trench 16 are formed, penetrating the semiconductor layer 4 and reaching the semiconductor substrate 1. The first trench 15 surrounds the upper surface electrode 13 when viewed from above. The second trench 16 surrounds the first trench 15 when viewed from above. In addition, the second trench 16 is not limited to a single trench; multiple trenches can be formed in a concentric circle to serve as the second trench 16.

[0024] To prevent moisture and physical damage, the upper surface of semiconductor layer 4 and the inner walls of the first trench 15 and the second trench 16 are covered by a protective film 17. However, the first trench 15 and the second trench 16 are not filled by the protective film 17, and there are voids inside. The protective film 17 is composed of SiO2, SiN, SiON, etc.

[0025] An outer peripheral barrier wall 18 is formed on the outer periphery of the upper surface of the semiconductor light-receiving element 2. The outer peripheral barrier wall 18 is made of an insulating film such as SiO2, SiN, or SiON, or a metal such as Ti, Pt, Ni, or Au. Even when the outer peripheral barrier wall 18 is a metal, it is not connected to the electrodes of the element. Furthermore, the outer peripheral barrier wall 18 is not a semiconductor, so it does not need to be covered by a protective film 17.

[0026] Figure 4This is a cross-sectional view showing the case where the semiconductor light-receiving elements of Embodiment 1 are adjacent. A dicing line 3 is formed between the adjacent semiconductor light-receiving elements 2. At the dicing line 3, no contact layer 11, protective film 17, outer peripheral barrier wall 18, electrode, etc. are formed, resulting in a recess. If the recess of the dicing line 3 is made deeper, the wafer is likely to break and difficult to process. Therefore, it is impossible to prevent the ink from flowing out through the shallow recess of the dicing line 3. Additionally, even if the first groove 15 and the second groove 16 are formed in the semiconductor light-receiving element 2, it does not affect the processing.

[0027] Next, the manufacturing method of the semiconductor light-receiving element of the present embodiment will be described. First, on the semiconductor substrate 1, as the semiconductor layer 4, a multilayer reflection layer 5, a multiplication layer 6, an electric field relaxation layer 7, a light absorption layer 8, a BDR layer 9, a window layer 10, and a contact layer 11 are sequentially formed. Next, the first groove 15 and the second groove 16 that penetrate the semiconductor layer 4 and reach the semiconductor substrate 1 are formed by dry etching using a photoresist or the like. Next, a protective film 17, an upper surface electrode 13, an outer peripheral barrier wall 18, a lower surface electrode 14, etc. are formed. The outer peripheral barrier wall 18 is formed at the outer peripheral portion of the upper surface of the semiconductor layer 4. Thus, a plurality of semiconductor light-receiving elements 2 are formed in a matrix on the wafer-shaped semiconductor substrate 1.

[0028] Next, a wafer test is performed. Figure 5 This is a cross-sectional view showing the case of a wafer test. The wafer is placed on the conductive workbench 19. At this time, the lower surface electrode 14 of the semiconductor light-receiving element 2 is brought into contact with the workbench 19 connected to GND. The probe 20 is brought into contact with the upper surface electrode 13, and a voltage is applied between the upper surface electrode 13 and the lower surface electrode 14. Thereby, the current-voltage characteristics of the plurality of semiconductor light-receiving elements 2 are respectively inspected. It is determined whether the desired electrical characteristics are obtained as the inspection result for pass / fail determination. Additionally, the electrical characteristics of the semiconductor light-receiving element 2 can also be measured while irradiating light on the light-receiving portion 12.

[0029] Next, ink 22 is applied to the semiconductor light-receiving elements 2 that failed in the wafer test from the nozzle 21. Figure 6 and Figure 7 This is a cross-sectional view showing the state where ink is applied to the semiconductor light-receiving element of Embodiment 1. The ink 22 is applied to the light-receiving portion 12, the upper surface electrode 13, and the periphery thereof of the semiconductor light-receiving element 2. When the amount of the ink 22 is small, as Figure 6 shown, the ink 22 is restricted to the inner peripheral side on the chip upper surface closer to the first groove 15 due to surface tension. When the amount of the ink 22 is large, as Figure 7As shown, ink 22 enters the first groove 15, but is confined to the inner periphery of the chip surface, closer to the second groove 16, due to surface tension. Even if the amount of ink 22 increases further and flows to the outer side, it is intercepted by the outer periphery barrier 18.

[0030] As explained above, in this embodiment, when forming the semiconductor photoreceiving element 2, a first trench 15 and a second trench 16 are formed that penetrate the semiconductor layer 4 and reach the semiconductor substrate 1. The first trench 15 surrounds the upper surface electrode 13 when viewed from above, and the second trench 16 surrounds the first trench 15. This increases the number of times the ink 22 is subjected to surface tension, making it easier to trap the ink 22. Furthermore, the ink 22 can flow not only into the first trench 15 but also into the second trench 16, thus reducing the amount of ink 22 flowing towards the outer periphery of the upper surface of the semiconductor photoreceiving element 2. This prevents ink 22 from flowing out into adjacent chips and prevents a decrease in yield.

[0031] Furthermore, a peripheral barrier wall 18 is formed on the outer periphery of the upper surface of the semiconductor layer 4. The peripheral barrier wall 18 can intercept ink 22 that cannot be intercepted by the first trench 15 and the second trench 16. The thicker the peripheral barrier wall 18, the easier it is to intercept the ink 22. If the semiconductor layer is formed too thickly, the cost increases; conversely, the peripheral barrier wall 18, made of an insulating film or metal, can be formed thicker. However, if the peripheral barrier wall 18 is made too thick, problems such as wafer warping occur. Therefore, it is necessary not only to form the peripheral barrier wall 18, but also to form the first trench 15 and the second trench 16.

[0032] Implementation method 2.

[0033] Figure 8 This is a cross-sectional view showing the semiconductor light-receiving element of Embodiment 2. In this embodiment, when forming the semiconductor light-receiving element 2, a first barrier wall 23 and a second barrier wall 24 are formed on the upper surface of the semiconductor layer 4. The first barrier wall 23 and the second barrier wall 24 are made of semiconductors such as InP, insulating films such as SiO2, SiN, and SiON, or metals such as Ti, Pt, Ni, and Au. In addition, the first barrier wall 23 and the second barrier wall 24 are covered by a protective film 17, but if the first barrier wall 23 and the second barrier wall 24 are not semiconductors, they do not need to be covered by the protective film 17.

[0034] The first barrier wall 23 surrounds the upper surface electrode 13 when viewed from above, and its height is higher than that of the upper surface electrode 13. The second barrier wall 24 surrounds the first barrier wall 23 when viewed from above, and its height is higher than that of the first barrier wall 23. More specifically, the first barrier wall 23 is formed between the first groove 15 and the second groove 16 when viewed from above. The second barrier wall 24 is formed on the outer periphery side of the second groove 16 when viewed from above. Alternatively, a barrier wall with a height higher than the second barrier wall 24 may be further formed on the outer periphery side of the second barrier wall 24, so that the number of barrier walls is three or more. An outer peripheral barrier wall 18 is formed on the outer periphery of the upper surface of the second barrier wall 24. The structure of the other semiconductor light-receiving elements 2 is the same as in Embodiment 1, and wafer testing and ink 22 coating are performed in the same manner as in Embodiment 1.

[0035] As explained above, in this embodiment, a first barrier wall 23 and a second barrier wall 24 are formed, with a height higher than the upper surface electrode 13 when viewed from above. This allows for the interception of ink 22. Furthermore, the second barrier wall 24 is higher than the first barrier wall 23. This increases the height of the barrier walls towards the outer periphery, thus creating a mortar-like shape on the chip's upper surface. Consequently, ink 22 easily accumulates, suppressing its outward diffusion. Additionally, even when the ink droplet position shifts outward from the chip center, the ink 22 easily moves towards the chip center. As a result, ink 22 is prevented from flowing out onto adjacent chips, thus preventing a decrease in yield.

[0036] Implementation method 3.

[0037] Figure 9 This is a cross-sectional view showing the semiconductor light-receiving element of Embodiment 3. Figure 10 This is a top view showing the semiconductor light-receiving element of Embodiment 3. In this embodiment, when forming the semiconductor light-receiving element 2, instead of forming the first trench 15 and the second trench 16 in Embodiment 1, a stepped barrier wall 25 is formed on the semiconductor layer 4. The stepped barrier wall 25 is made of a semiconductor such as InP, an insulating film such as SiO2, SiN, or SiON, or a metal such as Ti, Pt, Ni, or Au. In addition, the window layer 10 is not conductive, so there is no problem with the stepped barrier wall 25 being in direct contact with the window layer 10.

[0038] The stepped barrier wall 25 surrounds the upper surface electrode 13 when viewed from above, and its height is higher than that of the upper surface electrode 13, increasing in height towards the outer periphery of the upper surface of the semiconductor layer 4. Alternatively, the stepped barrier wall 25 may have three or more steps. An outer peripheral barrier wall 18 is formed on the outer periphery of the upper surface of the stepped barrier wall 25. The structure of the other semiconductor light-receiving elements 2 is the same as in Embodiment 1, and wafer testing and ink 22 coating are performed in the same manner as in Embodiment 1.

[0039] As explained above, in this embodiment, a stepped barrier wall 25, taller than the upper surface electrode 13, is formed to surround the upper surface electrode 13 when viewed from above. This allows for the interception of ink 22. Furthermore, the stepped barrier wall 25 increases in height towards the outer periphery. This increases the height of the barrier wall towards the outer periphery, thus creating a mortar-like shape on the upper surface of the chip. Consequently, ink 22 easily accumulates, suppressing its outward diffusion. Additionally, even when the ink droplet position shifts outward from the chip center, the ink 22 easily moves towards the chip center. As a result, ink 22 is prevented from flowing into adjacent chips, thus preventing a decrease in yield.

[0040] Explanation of reference numerals in the attached figures

[0041] 1… Semiconductor substrate; 2… Semiconductor light-receiving element; 4… Semiconductor layer; 8… Light-absorbing layer; 12… Light-receiving part; 13… Upper surface electrode; 15… First trench; 16… Second trench; 18… Outer peripheral barrier wall; 22… Ink; 23… First barrier wall; 24… Second barrier wall; 25… Stepped barrier wall.

Claims

1. A method for manufacturing a semiconductor light-receiving element, characterized in that, It includes the following processes: The process of forming multiple semiconductor light-receiving elements on a wafer-shaped semiconductor substrate; A wafer testing process that involves individually inspecting the electrical characteristics of the plurality of semiconductor light-receiving elements; as well as The process of coating ink onto semiconductor light-receiving elements that fail the wafer test. When forming the semiconductor light-receiving element, a semiconductor layer having at least a light-absorbing layer is formed on the semiconductor substrate, an annular upper surface electrode that opens the light-receiving portion is formed on the semiconductor layer, and a first trench and a second trench that penetrate the semiconductor layer and reach the semiconductor substrate are formed. When viewed from above, the first groove surrounds the upper surface electrode. When viewed from above, the second groove surrounds the first groove.

2. The method for manufacturing a semiconductor light-receiving element according to claim 1, characterized in that, When forming the semiconductor light-receiving element, an outer peripheral barrier is formed on the outer periphery of the upper surface of the semiconductor layer.

3. The method for manufacturing a semiconductor light-receiving element according to claim 1, characterized in that, During the formation of the semiconductor light-receiving element, a first barrier wall and a second barrier wall are formed on the upper surface of the semiconductor layer. When viewed from above, the first barrier wall surrounds the upper surface electrode and is higher than the upper surface electrode. When viewed from above, the second barrier wall surrounds the first barrier wall and is higher than the first barrier wall.

4. The method for manufacturing a semiconductor light-receiving element according to claim 3, characterized in that, When viewed from above, the first barrier wall is formed between the first groove and the second groove. When viewed from above, the second barrier wall is formed at a position on the outer periphery of the second groove.

5. The method for manufacturing a semiconductor light-receiving element according to claim 3 or 4, characterized in that, When forming the semiconductor light-receiving element, an outer peripheral barrier wall is formed on the outer periphery of the upper surface of the second barrier wall.

6. A method for manufacturing a semiconductor light-receiving element, characterized in that, It includes the following processes: The process of forming multiple semiconductor light-receiving elements on a wafer-shaped semiconductor substrate; A wafer testing process that involves individually inspecting the electrical characteristics of the plurality of semiconductor light-receiving elements; as well as The process of coating ink onto semiconductor light-receiving elements that fail the wafer test. When forming the semiconductor light-receiving element, a semiconductor layer having at least a light-absorbing layer is formed on the semiconductor substrate, an annular upper surface electrode that opens the light-receiving portion is formed on the semiconductor layer, and a stepped barrier wall is formed on the semiconductor layer. When viewed from above, the stepped barrier surrounds the upper surface electrode and is higher than the upper surface electrode, increasing in height towards the outer periphery of the upper surface of the semiconductor layer.

7. The method for manufacturing a semiconductor light-receiving element according to claim 6, characterized in that, When forming the semiconductor light-receiving element, an outer peripheral barrier wall is formed on the outer periphery of the upper surface of the stepped barrier wall.

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