Single complementary metal-oxide-semiconductor backplane supporting multiple light-emitting diode pixel sizes

Abstract

A device (100) comprising a complementary metal-oxide-semiconductor (CMOS) backplane comprising a plurality of light-emitting diode (LED) pixel regions (110). The device comprises pixel drivers (130) within the CMOS backplane. Each of the pixel drivers is coupled to ground (140). The pixel drivers are configured to correspond to groups (150) of the plurality of LED pixel regions.

Description

[0001] Cross-references to related applications This international application claims priority to U.S. Application No. 18 / 524,599, filed November 30, 2023, the entire contents of which are incorporated herein by reference. Background Technology

[0003] Conventional techniques for designing, fabricating, and implementing hybrid pixelated light-emitting diode (LED) arrays using complementary metal-oxide-semiconductor (CMOS) backplanes are typically an order of magnitude more expensive than redefining the segmentation and contact patterning of monolithic microLED (µLED) pixel arrays. Therefore, multiple application-specific integrated circuit (ASIC) CMOS backplanes need to be designed based on the µLED configuration required for specific applications. Conventional techniques currently do not offer a solution. Summary of the Invention

[0005] According to one or more embodiments, a device is provided. The device includes a complementary metal-oxide-semiconductor (CMOS) backplane including a plurality of light-emitting diode (LED) pixel regions. The device includes a plurality of pixel drivers within the CMOS backplane, each of the plurality of pixel drivers being coupled to ground. The one or more pixel drivers are configured to correspond to one or more groups of the plurality of LED pixel regions. Attached Figure Description

[0007] A more detailed understanding can be obtained from the following description, which is given by way of example and in conjunction with the accompanying figures, wherein: Figure 1 A device according to one or more embodiments is described; Figure 3 A schematic diagram of a device according to one or more embodiments; Figure 4 A schematic diagram of a device according to one or more embodiments; Figure 5 A schematic diagram of a device according to one or more embodiments; Figure 6 A schematic diagram of an example vehicle headlight system; and Figure 7 This is a schematic diagram of another example vehicle headlight system. Detailed Implementation

[0009] This article describes a single complementary metal-oxide-semiconductor (CMOS) backplane configured to receive and connect multiple light-emitting diode (LED) pixel sizes. The CMOS backplane can be implemented in a CMOS, which can also be implemented in a device that includes LEDs, each LED corresponding to one or more pixel sizes.

[0010] According to one or more embodiments, a CMOS backplane is configured to receive multiple LED pixel sizes with minimal or no modification to the CMOS chip, and / or only modifications to the software, firmware, or one-time programmable (OTP) memory within the CMOS. The CMOS backplane may include (and can be constructed / manufactured to include) one or more pixel drivers. The one or more pixel drivers may be interconnected in one or more groups (e.g., multiple predefined pixel driver groups) to drive individual pixels.

[0011] According to one or more embodiments, one or more groups can be implemented via the design of a CMOS metal interconnect layer. The technical effects and benefits of the metal interconnect layer design include not redesigning (e.g., keeping it unchanged) the underlying silicon of the CMOS, and therefore requiring little or no intervention at the application level of the CMOS and / or device.

[0012] According to one or more embodiments, one or more groups can be implemented via an n-layer interconnect design of an LED array to provide multiple connection points to individual drivers and combine one or more of the multiple connection points to operate a single pixel. Furthermore, the n-layer interconnect design can be coupled with CMOS application-level software or firmware configuration to operate the CMOS. The technical effects and benefits of the n-layer interconnect design include no additional cost to the downstream processing of the CMOS backplane and CMOS and / or devices. Applications of the CMOS backplane, CMOS, and / or devices described herein include, but are not limited to, µLED pixel arrays and / or Mini-LED pixel arrays (e.g., having very high pixels per inch (PPI) directly mixed on top of the CMOS backplane).

[0013] According to one or more embodiments, one or more groups can be implemented via a hybrid configuration between a CMOS metal interconnect layer design and an n-layer interconnect design of an LED array. The hybrid configuration may include configuring the top metal layer of the CMOS to be different for each different LED array and providing corresponding interconnects. Furthermore, the hybrid configuration may be coupled with pre-programming of the CMOS (e.g., using a fusible OTP memory to one of a plurality of predefined pixel driver groups).

[0014] Examples of different light illumination systems and / or LED implementations will be described more fully below with reference to the accompanying drawings. These examples are not mutually exclusive, and features found in one example may be combined with features found in one or more other examples to achieve further implementations. Therefore, it will be understood that the examples shown in the accompanying drawings are provided for illustrative purposes only and are not intended to limit this disclosure in any way. Similar figures always refer to similar elements. Furthermore, LEDs may have relatively large luminous areas, with their outer walls surrounded on at least one side by very thin reflectors such as dichroic mirrors, as described above. This can support very close spacing between LEDs while still maintaining contrast between adjacent LEDs. In some embodiments, the reflectors may be placed only where the sidewalls are adjacent to the sidewalls of adjacent LEDs. For such LEDs, standard pick-and-place techniques may be difficult for the reasons described above, especially since the spacing is very small, and any movement of the LEDs can cause problems with their functionality.

[0015] Figure 1 Device 100 according to one or more embodiments is illustrated. Device 100 includes a plurality of LED pixel regions (e.g., represented by pixel 110). Device 100 may represent a CMOS backplane. One or more pixel drivers 130 are located inside the CMOS backplane, and each pixel driver 130 may be coupled to ground 140. The one or more pixel drivers 130 may be designed to be included in one or more groups (e.g., represented by group 150). Any of the one or more groups may include one, two, three, four, five, six, seven, eight or more drivers, etc. Groups of one or more pixel drivers 130 may have the same number of pixel drivers 130 (e.g., each group may have two pixel drivers). Groups of one or more pixel drivers 130 may have different numbers of pixel drivers 130 (e.g., a first group may have two pixel drivers, while a second group may have four pixel drivers).

[0016] As shown in pixel 110 (e.g., with respect to each of the plurality of LED pixel regions), pixel 110 includes one or more pixel drivers 130 corresponding to LED 160. Therefore, the plurality of LED pixel regions of device 100 can correspond to and be configured to receive the plurality of LEDs 160. According to one or more embodiments, and as... Figure 1As shown, device 100 may include four (4) pixel drivers 130 interconnected in groups 150 for LED 160 (via configuration 170 described herein). For example, device 100 is shown as having sixteen (16) pixel drivers 130 interconnected in four (4) separate groups 150 to drive corresponding pixels 110 (e.g., multiple predefined pixel drivers grouped to drive individual pixels).

[0017] According to one or more embodiments, configuration 170 can be a hybrid configuration between a CMOS metal interconnect layer design, an n-layer interconnect design for an LED array, and a CMOS metal interconnect layer design and an LED array n-layer interconnect design.

[0018] Figure 2 This is a schematic diagram of device 200 according to one or more embodiments. Device 200 provides a design of metal interconnect layers in a CMOS layer stack. Device 200 includes LED 210, µbumps 221 / 222 (e.g., made of tin (Sn) and copper (Cu) respectively), contact 230, silicon (Si) layer 235, and layer (e.g., phosphosilicate glass) 240. µbumps 221 / 222 are fabricated on top of LED 210. LED 210 is attached to the top of µbumps 221 / 222. LED 210 can be segmented into pixels, with one µbump forming a p-contact for each pixel. n-contacts can be implemented by segmenting the LED to the edge of the die and then back into the CMOS with µbumps. According to one or more embodiments, configuration 170 can keep the underlying silicon of the CMOS (e.g., silicon (Si) layer 235) unchanged (e.g., driver circuitry, their dimensions and locations, and control logic), and increase the pixel size of LED 210 by a factor, such as four (4) times.

[0019] Device 200 includes one or more SiN / SiO2 layers 251, 252, 253, and 254. Device 200 includes one or more metal (e.g., Cu) layers 261, 262, 263, 264, 265, and 266. Device 200 includes layer 270 (e.g., undoped silicate glass) and one or more layers (e.g., fluorosilicate glass) 272, 273, 274, and 275. Device 200 includes one or more contacts 281 and 282. The one or more metal (e.g., Cu) layers 261, 262, 263, 264, 265, and 266 are metal interconnect layers configured according to the embodiments herein.

[0020] The configuration 170 of the CMOS metal interconnect layer design can be achieved by reconfiguring the metal layer stack within device 120. Therefore, for each individual implementation, each metal layer stack can correspond to a unique stock-store unit (SKU). In one embodiment, an all-metal layer stack of the CMOS can be provided to group the pixel drivers 130 into groups 150, avoiding changes to the software, firmware, or OTP memory in the CMOS. In one embodiment, the pixel drivers 130 can be grouped into groups 150 by providing software, firmware, or one-time programmable OTP memory in the CMOS, when only the top layer of device 120 is modified to provide a "short circuit" between the pixel drivers 130.

[0021] According to one or more embodiments, 170 is configured to electrically connect four (4) raw drivers in parallel to drive larger pixels. For example, to achieve parallel connection of four (4) drivers for a single pixel, regarding Figure 3-5 Configuration 170 is shown.

[0022] Figure 3 A schematic diagram of a device 300 (e.g., including a CMOS layer stack) according to one or more embodiments. Device 300 includes an LED 310, a contact 320 (e.g., µbumps), and a driver layer 330. Device 300 includes one or more interconnect layers 361, 362, 363, 364, 365, and 366 (e.g., one or more metal (e.g., Cu) layers 261, 262, 263, 264, 265, and 266) configured by varying the interconnects to fully match the LED 310 on both the driver side (e.g., interconnect layers 365 and 366) and the logic side (e.g., interconnect layers 361, 362, 363, and 364).

[0023] Figure 4 This is a schematic diagram of a device 400 (e.g., including a CMOS layer stack) according to one or more embodiments. Device 400 includes an LED 410, contacts 420 (e.g., µbumps), and a driver layer 430. Device 400 includes one or more interconnect layers 461, 462, 463, 464, 465, and 466 (e.g., one or more metal (e.g., Cu) layers 261, 262, 263, 264, 265, and 266), wherein only the top layers 465 and 466 are configured (e.g., driver power distribution) to connect contacts 420 to driver layer 430, while the logic side (e.g., interconnect layers 461, 462, 463, and 464) includes through connections. Notably, additional CMOS programming can be implemented to drive LED 410.

[0024] Configuration 170, which enables an n-layer interconnect design of the LED array within the die of LED 160, can be achieved by providing multiple n-contacts for pixel 110. Figure 5 This is a schematic diagram of a device 500 (e.g., including a CMOS layer stack) according to one or more embodiments. Device 500 includes an LED 510, one or more contacts 520 (e.g., µbumps), and a driver layer 530. Device 500 includes one or more interconnect layers 561, 562, 563, 564, 565, and 566 (e.g., one or more metal (e.g., Cu) layers 261, 262, 263, 264, 265, and 266). Device 500 provides a solution that utilizes CMOS and µbumps, and performs parallel connection of the drivers of the driver layer 530 on the p-metal side of the LED 510 (e.g., arranging the metallization of the LED 510 to match the CMOS). According to device 500, the CMOS does not need to be changed for any pixel configuration.

[0025] Configuration 170 of the hybrid configuration can be implemented with reference to the examples herein. According to one or more embodiments, the hybrid configuration may include the use of microbumps (e.g., Figure 2 LED pixel arrays are attached to the CMOS backplane using methods such as (µ bumps 221 / 222), gold bumps, direct attachment, or any other attachment method.

[0026] Configuration 170 (e.g., pixel driver grouping) can be provided digitally via software, firmware, or OTP memory in the CMOS. For example, the CMOS firmware digitally combines individual drivers 130 to generate combinations of currents and route them to pixels 110 (e.g., the CMOS firmware digitally configures one or more pixel drivers into one or more groups to generate and route combinations of currents corresponding to the plurality of LED pixel regions). It is worth noting that, although... Figure 1 The device shown is in an anode configuration, but configuration 170 may include an n or p layer, allowing device 100 to work with a cathode configuration. The technical effect and benefit of configuration 170 is that it allows for the combination of currents from any number of independent drivers 130 and routes these current combinations to a single pixel 110 to ensure uniform load on the drivers 130 and uniform distribution of the pixels 110 (e.g., configuration 170 is designed accordingly in a metallization layer on the CMOS or LED 160).

[0027] It is worth noting that conventional chips are typically expensive because they consist of a large number of individual micropixels (e.g., 20,000 individual micropixels) and corresponding drivers and LEDs (e.g., each driver requires a single LED corresponding to each individual micropixel). In contrast, and as a technical effect and benefit, from an electrical perspective, device 100 combines individual drivers 130 into a group 150, where the drivers 130 of group 150 operate together to drive a single large pixel 110 covering a larger surface area of ​​device 100 (e.g., instead of individual micropixels, the device provides 5,000 pixels across 20,000 drivers). Therefore, this device meets the need to design multiple ASIC CMOS backplanes according to the µLED configuration required for a specific application.

[0028] Furthermore, the technical effect and benefit of enabling multiple drivers 130 to operate a single pixel 110 is the increased analog current granularity that can be used to drive the pixel 110, making hybrid dimming of the device 100 much easier than with individual small pixels of a conventional chip (e.g., a scenario of one pixel per driver). According to one or more embodiments, the DC current of any individual pixel driver 130 need not be equivalent with respect to the CMOS backplane, CMOS, and / or device described herein. Furthermore, any pulse width modulation (PWM) of the pixel drivers 130 in group 150 operates synchronously among the pixel drivers 130. Therefore, the pixel grouping 150 of device 100 provides the technical effect and benefit of enabling synchronization of the rising and falling edges of the PWM signal to provide controllable and distributed electromagnetic compatibility (EMC) characteristics for device 100.

[0029] Figure 6 This is a schematic diagram of an example vehicle headlight system 600, which may be combined with one or more of the embodiments and examples described herein. The example vehicle headlight system 600 in... Figure 6 The diagram shows a power line 602, a data bus 604, an input filter and protection module 606, a bus transceiver 608, a sensor module 610, an LED DC-DC (DC / DC) module 612, a logic low dropout (LDO) module 614, a microcontroller 616, and an active headlight 618.

[0030] Power line 602 may have an input for receiving power from the vehicle, and data bus 604 may have inputs / outputs through which data can be exchanged between the vehicle and the vehicle headlight system 600. For example, the vehicle headlight system 600 may receive commands from other locations within the vehicle, such as commands to turn on turn signals or turn on headlights, and may send feedback to other locations within the vehicle if desired. Sensor module 610 may be communicatively coupled to data bus 604 and may provide additional data to the vehicle headlight system 600 or other locations within the vehicle, such additional data relating to environmental conditions (e.g., time of day, rain, fog, or ambient light levels), vehicle status (e.g., parked, moving, speed, or direction of movement), and the presence / location of other objects (e.g., vehicles or pedestrians). A headlight controller, separate from any vehicle controller communicatively coupled to the vehicle data bus, may also be included in the vehicle headlight system 600. Figure 6 In this configuration, the headlight controller can be a microcontroller, such as a microcontroller (μc) 616. The microcontroller 616 can be communicatively coupled to a data bus 604.

[0031] The input filter and protection module 606 can be electrically coupled to the power line 602 and can, for example, support various filters to reduce conducted emissions and provide power immunity. Additionally, the input filter and protection module 606 can provide electrostatic discharge (ESD) protection, load dump protection, alternator field attenuation protection, and / or reverse polarity protection.

[0032] The LED DC / DC module 612 can be coupled between the input filter and protection module 106 and the active headlight 618 to receive filtered power and provide drive current to power the LEDs in the LED array of the active headlight 618. The LED DC / DC module 612 can have an input voltage between 6 volts and 18 volts, with a nominal voltage of approximately 13.2 volts, and an output voltage that can be slightly higher (e.g., 0.3 volts) than the maximum voltage of the LED array (e.g., determined by factors or local calibration and adjustments to operating conditions due to load, temperature, or other factors).

[0033] The logic LDO module 614 can be coupled to the input filter and protection module 606 to receive filtered power. The logic LDO module 614 can also be coupled to the microcontroller 616 and the active headlight 618 to provide power to the electronics (such as CMOS logic) in the microcontroller 616 and / or the active headlight 618.

[0034] The bus transceiver 608 may have, for example, a Universal Asynchronous Receiver / Transmitter (UART) or Serial Peripheral Interface (SPI) interface and may be coupled to the microcontroller 616. The microcontroller 616 may translate vehicle input based on or including data from the sensor module 610. The translated vehicle input may include a video signal that can be transmitted to an image buffer in the active headlight 618. Furthermore, the microcontroller 616 may load a default image frame and test open / short-circuit pixels during startup. In an embodiment, the SPI interface may load an image buffer in CMOS. The image frame may be a full frame, differential, or partial frame. Other features of the microcontroller 616 may include a control interface monitoring of CMOS state, including die temperature and logic LDO outputs. In an embodiment, the LED DC / DC output may be dynamically controlled to minimize headroom. In addition to providing image frame data, other headlight functions may be controlled, such as complementary use with side marker lights or turn signals, and / or activation of daytime running lights.

[0035] Figure 7 This is a schematic diagram of another example vehicle headlight system 700. Figure 7 The example vehicle headlight system 700 shown includes an application platform 702, two LED lighting systems 706 and 708, and secondary optics 710 and 712.

[0036] LED lighting system 708 can emit beam 714 ( Figure 7 (As shown between arrows 714a and 714b). The LED lighting system 706 can emit a beam 716 ( Figure 7 (As shown between arrows 716a and 716b). Figure 7 In the illustrated embodiment, secondary optics 710 are adjacent to LED lighting system 708, and light emitted from LED lighting system 708 passes through secondary optics 710. Similarly, secondary optics 712 are adjacent to LED lighting system 706, and light emitted from LED lighting system 706 passes through secondary optics 712. In an alternative embodiment, secondary optics 710 / 812 are not provided in the vehicle headlight system.

[0037] In the included cases, the secondary optics 710 / 812 may be or include one or more light guides. The one or more light guides may be edge-illuminated or may have internal openings defining the inner edges of the light guides. LED lighting systems 708 and 706 may be inserted into the internal openings of one or more light guides, such that they inject light into the inner edges (internal opening light guides) or outer edges (edge-illuminated light guides) of the one or more light guides. In embodiments, the one or more light guides may shape the light emitted by LED lighting systems 708 and 706 in a desired manner—such as, for example, having a gradient, chamfered distribution, narrow distribution, wide distribution, or angular distribution.

[0038] Application platform 702 can provide power and / or data to LED lighting systems 706 and / or 708 via line 704, which may include Figure 6 One or more of the power lines 602 and the data bus 604, or a portion thereof. One or more sensors (which may be sensors in the vehicle headlight system 700 or other additional sensors) may be inside or outside the housing of the application platform 702. Alternatively or additionally, such as Figure 6 As shown in the example vehicle headlight system 600, each LED lighting system 708 and 706 may include its own sensor module, connectivity and control module, power supply module, and / or LED array.

[0039] In an embodiment, the vehicle headlight system 700 may represent a motor vehicle with a controllable beam of light, wherein LEDs can be selectively activated to provide controllable light. For example, an array of LEDs or emitters may be used to define or project a shape or pattern, or to illuminate only selected portions of a road. In an example embodiment, infrared camera or detector pixels within the LED lighting systems 706 and 708 may be sensors (e.g., similar to) those that identify portions of a scene requiring illumination (e.g., roads or pedestrian crossings). Figure 6 (The sensor in sensor module 610).

[0040] As will be apparent to those skilled in the art, based on the description herein, embodiments of the present invention can be designed in software using a hardware description language (HDL) (such as, for example, Verilog or VHDL). The HDL design can simulate the behavior of an electronic system, which can then be synthesized and ultimately fabricated into a hardware device. Furthermore, the HDL design can be stored in a computer product and loaded into the computer system prior to hardware manufacturing.

[0041] The embodiments have been described in detail, and those skilled in the art will appreciate that, given this description, modifications can be made to the embodiments described herein without departing from the spirit of the inventive concept. Therefore, it is intended that the scope of the invention be limited to the specific embodiments illustrated and described.

[0042] It will be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms may be used to distinguish one element from another. For example, a first element may be referred to as a second element and a second element may be referred to as a first element without departing from the scope of the invention. As used herein, the term "and / or" may include any and all combinations of one or more of the associated listed items.

[0043] It will be understood that when an element such as a layer, region, or substrate is referred to as "on" or "extending" to another element, it may be directly on or directly extended to the other element, or there may be intermediate elements present. In contrast, when an element is referred to as "directly on" or "directly extended" to another element, there may be no intermediate elements present. It will also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element and / or connected or coupled to the other element via one or more intermediate elements. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, there are no intermediate elements present between that element and the other element. It will be understood that, except for any orientation depicted in the figures, these terms are intended to cover different orientations of elements.

[0044] Relative terms such as “below,” “above,” “top,” “lower,” “horizontal,” or “vertical” may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region illustrated in the figures. It will be understood that these terms are intended to cover different orientations of the device in addition to those depicted in the figures.

Claims

1. A device comprising: A complementary metal-oxide-semiconductor (CMOS) backplane, comprising multiple light-emitting diode (LED) pixel regions; Multiple pixel drivers within the CMOS backplane, each pixel driver being coupled to ground. One or more metal interconnect layers of the CMOS backplane configure one or more pixel drivers to correspond to one or more groups of multiple LED pixel regions.

2. The device of claim 1, wherein the one or more metal interconnect layers comprise an all-metal layer stack of a CMOS backplane, configuring one or more pixel drivers into one or more groups.

3. The device of claim 1, wherein the one or more metal interconnect layers include a top layer that provides a short circuit between the plurality of pixel drivers.

4. The device of claim 1, wherein the one or more groups comprise the same number of pixel drivers.

5. The device of claim 1, wherein the one or more groups comprise a different number of pixel drivers.

6. The device of claim 1, wherein one of the groups comprises four (4) pixel drivers of the plurality of pixel drivers.

7. The device according to claim 1, wherein, The device includes a plurality of LEDs, and each region of the plurality of LED pixel regions corresponds to one of the plurality of LEDs.

8. A device comprising: A complementary metal-oxide-semiconductor (CMOS) backplane, comprising multiple light-emitting diode (LED) pixel regions; Multiple pixel drivers are located inside the CMOS backplane, and each pixel driver is coupled to ground. One or more pixel drivers are configured via an n-layer interconnect design to correspond to one or more groups of multiple LED pixel regions.

9. The device of claim 8, wherein the device comprises a plurality of LEDs, and each region of the plurality of LED pixel regions corresponds to one of the plurality of LEDs.

10. The device of claim 9, wherein each of the plurality of LEDs includes an n-layer interconnect design that configures the one or more pixel drivers to correspond to one or more groups of pixel regions of the plurality of LEDs.

11. The device of claim 10, wherein each LED die comprises an n-layer interconnect design and provides a plurality of n contacts for each pixel driver corresponding to one or more pixel drivers in one of one or more groups.

12. The device of claim 8, wherein the one or more groups comprise the same number of pixel drivers.

13. The device of claim 8, wherein the one or more groups comprise a different number of pixel drivers.

14. The device of claim 8, wherein one of the groups comprises four (4) pixel drivers of the plurality of pixel drivers.

15. A device comprising: A complementary metal-oxide-semiconductor (CMOS) backplane, comprising multiple light-emitting diode (LED) pixel regions; Multiple pixel drivers are located inside the CMOS backplane, and each pixel driver is coupled to ground. One or more pixel drivers are configured to correspond to one or more groups of multiple LED pixel regions.

16. The device of claim 15, wherein the hybrid configuration of the device configures the one or more pixel drivers to correspond to one or more groups of the plurality of LED pixel regions.

17. The device of claim 16, wherein the hybrid configuration includes one or more metal interconnect layers of the CMOS backplane.

18. The device of claim 16, wherein the hybrid configuration comprises an n-layer interconnect design.

19. The device of claim 15, wherein the device comprises a plurality of LEDs, and each region of the plurality of LED pixel regions corresponds to one of the plurality of LEDs.

20. The device of claim 15, wherein the firmware of the CMOS digitally configures the one or more pixel drivers into the one or more groups to generate and route combinations of currents corresponding to the plurality of LED pixel regions.

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