Local interconnect in sequential stacks

Abstract

Embodiments of the invention relate to local interconnects in sequential stacks of transistors. A semiconductor structure includes a first transistor stacked below a second transistor. An interconnect layer is located between the first transistor and the second transistor, the interconnect layer including a conductive via and a conductive line.

Description

Technical Field

[0001] The present invention generally relates to methods of manufacturing integrated circuits (ICs) and the resulting structures, and more specifically, to methods of manufacturing transistors having local interconnections in a sequential stack of transistors and the resulting structures. Background Technology

[0002] An IC (also known as a chip or microchip) comprises electronic circuitry on a wafer. The wafer is made of semiconductor material, such as silicon or other materials. An IC is formed from a large number of devices, such as transistors, capacitors, resistors, etc., which are formed in layers of the IC and interconnected with wiring in the back-end process (BEOL) layers of the wafer. A typical IC is formed by first fabricating individual semiconductor devices using a process commonly known as front-end process (FEOL). A metal-oxide-semiconductor field-effect transistor (MOSFET) is a transistor used to amplify or switch electrical signals. A MOSFET has a source, a drain, and a metal-oxide gate electrode. A conventional FET is a planar device, in which the entire channel region of the device is formed parallel to and slightly below the plane of the semiconductor substrate's upper surface. In contrast to planar FETs, there exist so-called three-dimensional (3D) devices, such as FinFET devices, which are three-dimensional structures. A class of devices that shows promise for future advanced integrated circuit products is often referred to as nanosheet transistors. Generally, nanosheet transistors have a fin channel structure, which comprises multiple vertically spaced sheets of semiconductor material. The gate structure for the device is positioned around each of these spaced-apart layers of semiconductor material. Summary of the Invention

[0003] Embodiments of the present invention aim to provide local interconnects in sequentially stacked transistors. A non-limiting method of forming a semiconductor structure includes providing a first transistor. The method includes forming an interconnect layer between a first transistor and a second transistor, the first transistor being located below the second transistor, the interconnect layer including conductive vias and conductive lines.

[0004] According to one or more embodiments, a non-limiting method of forming a semiconductor structure includes providing a first transistor having a first gate. The method also includes providing a second transistor having a second gate, the second transistor being stacked above the first transistor, wherein an interconnect layer is formed between the first transistor and the second transistor, the interconnect layer electrically connecting the first gate and the second gate.

[0005] Other embodiments of the present invention implement the features of the above-described device / structure in the method and / or implement the features of the method in the device / structure.

[0006] Additional technical features and benefits are achieved through the technology of this invention. Embodiments and aspects of the invention are described in detail herein and are considered part of the claimed subject matter. For a better understanding, refer to the detailed description and accompanying drawings. Attached Figure Description

[0007] The specific content of the exclusive rights described herein is specifically pointed out and clearly claimed in the claims at the end of the specification. The foregoing and other features and advantages of the embodiments of the invention will become clear from the following detailed description when read in conjunction with the accompanying drawings, wherein:

[0008] Figure 1A , Figure 1B , Figure 1C and Figure 1D Top and cross-sectional views of a portion of an integrated circuit (IC) in manufacturing, according to one or more embodiments, are shown respectively;

[0009] Figure 2A , Figure 2B , Figure 2C and Figure 2D Top and cross-sectional views of a portion of an IC in the process of manufacturing after a manufacturing operation, according to one or more embodiments, are shown respectively;

[0010] Figure 3A , Figure 3B , Figure 3C and Figure 3D Top and cross-sectional views of a portion of an IC in the process of manufacturing after a manufacturing operation, according to one or more embodiments, are shown respectively;

[0011] Figure 4A , Figure 4B , Figure 4C and Figure 4D Top and cross-sectional views of a portion of an IC in the process of manufacturing after a manufacturing operation, according to one or more embodiments, are shown respectively;

[0012] Figure 5A , Figure 5B , Figure 5C and Figure 5D Top and cross-sectional views of a portion of an IC in the process of manufacturing after a manufacturing operation, according to one or more embodiments, are shown respectively;

[0013] Figure 6A , Figure 6B , Figure 6C and Figure 6D Top and cross-sectional views of a portion of an IC in the process of manufacturing after a manufacturing operation, according to one or more embodiments, are shown respectively;

[0014] Figure 7A , Figure 7B , Figure 7C and Figure 7D Top and cross-sectional views of a portion of an IC in the process of manufacturing after a manufacturing operation, according to one or more embodiments, are shown respectively;

[0015] Figure 8A , Figure 8B , Figure 8C and Figure 8D Top and cross-sectional views of a portion of an IC in the process of manufacturing after a manufacturing operation, according to one or more embodiments, are shown respectively;

[0016] Figure 9A , Figure 9B , Figure 9C , Figure 9D Figures 9 and 9E respectively show a top view and a cross-sectional view of a portion of an IC in the process of manufacturing after a manufacturing operation, according to one or more embodiments;

[0017] Figure 10A , Figure 10B , Figure 10C and Figure 10D Top and cross-sectional views of a portion of an IC in the process of manufacturing after a manufacturing operation, according to one or more embodiments, are shown respectively;

[0018] Figure 11A , Figure 11B , Figure 11C and Figure 11D Top and cross-sectional views of a portion of an IC in the process of manufacturing after a manufacturing operation, according to one or more embodiments, are shown respectively;

[0019] Figure 12A , Figure 12B , Figure 12C and Figure 12D Top and cross-sectional views of a portion of an IC in the process of manufacturing after a manufacturing operation, according to one or more embodiments, are shown respectively;

[0020] Figure 13A , Figure 13B , Figure 13C and Figure 13D Top and cross-sectional views of a portion of an IC in the process of manufacturing after a manufacturing operation, according to one or more embodiments, are shown respectively;

[0021] Figure 14 A flowchart illustrating a method for forming a semiconductor structure according to one or more embodiments is shown; and

[0022] Figure 15 A flowchart illustrating a method for forming a semiconductor structure according to one or more embodiments is shown. Detailed Implementation

[0023] One or more embodiments of the present invention relate to providing local interconnects in a sequential stack of transistors. The semiconductor structure includes a first transistor stacked below a second transistor and an interconnect layer located between the first and second transistors, the interconnect layer including conductive vias and conductive lines.

[0024] This provides improved electrical connectivity for sequentially stacked transistors, especially considering the increased transistor density on the semiconductor structure. Sequential stacking is highly attractive because it avoids the high aspect ratio processes of monolithic stacking. However, it can raise concerns about the impact of the top transistor process on the performance and reliability of the bottom transistors. This offers the unique improvement of inserting additional interconnect layers between the top and bottom transistors for sequential stacking, which is difficult to achieve in monolithic stacking. Conductive vias and conductive lines between the top and bottom transistors are used to form small-size logic cross-coupled structures that significantly contribute to area scaling.

[0025] In addition to one or more of the features described above or below, the additional feature includes: an interconnect layer electrically connecting the first transistor and the second transistor. This advantageously provides cross-coupling for the stacked transistors.

[0026] In addition to one or more of the features described above or below, the additional feature includes: an interconnect layer electrically connecting the first gate of the first transistor and the second gate of the second transistor. This advantageously provides an interconnect layer for the gates of cross-coupled stacked transistors.

[0027] In addition to one or more of the features described above or below, additional features include: conductive vias connecting the first transistor to conductive lines. This advantageously provides cross-coupling for stacked transistors.

[0028] In addition to one or more of the features described above or below, an additional feature includes: another conductive via connecting the second transistor to the conductive line. This advantageously provides cross-coupling for the stacked transistors.

[0029] In addition to one or more features described above or below, additional features include: the space between the first transistor and the second transistor includes a conductive via, a conductive line, and another conductive via. This advantageously provides cross-coupling for the stacked transistors.

[0030] In addition to one or more features described above or below, the additional features include: a first gate of the first transistor connected to a conductive connection, and another conductive via connected to both the conductive connection and the conductive line, the conductive line being connected to the conductive via; and a second gate of the second transistor connected to the conductive via. This advantageously provides an interconnect structure for cross-coupled stacked transistors.

[0031] In addition to one or more features described above or below, the additional feature includes: the gates of the first transistor and the second transistor are connected by an interconnect layer for simultaneous control. This advantageously allows the stacked transistors to be driven simultaneously.

[0032] In addition to one or more features described above or below, additional features include: the first gate of the first transistor is directly below the second gate of the second transistor; or the first gate of the first transistor is obliquely offset below the second gate of the second transistor. This advantageously allows stacked transistors to be driven simultaneously.

[0033] In addition to one or more features described above or below, the additional features include: a top layer comprising a second transistor and a fourth transistor, the fourth transistor being laterally adjacent to the second transistor; a bottom layer comprising a first transistor and a third transistor, the first transistor being directly below the second transistor and the third transistor being directly below the fourth transistor; and gate connections between the first and fourth transistors, and other gate connections between the second and third transistors. This advantageously allows adjacent groups of stacked transistors to be cross-connected.

[0034] According to one or more embodiments, a method for a semiconductor structure is provided. The method includes providing a first transistor and forming an interconnect layer between the first transistor and a second transistor, the first transistor being below the second transistor, the interconnect layer including conductive vias and conductive lines.

[0035] This provides improved electrical connectivity for sequentially stacked transistors, especially considering the increased transistor density on the semiconductor structure. Sequential stacking is very attractive because it avoids the high aspect ratio processes of monolithic stacking, but it can raise concerns about the impact of the top transistor process on the performance and reliability of the bottom transistors. This offers the unique improvement of inserting additional interconnect layers between the top and bottom transistors for sequential stacking, which is difficult to achieve in monolithic stacking. Conductive vias and conductive lines between the top and bottom transistors are used to form small-size logic cross-coupled structures that significantly contribute to area scaling.

[0036] In addition to one or more of the features described above or below, the additional feature includes: an interconnect layer electrically connecting the first transistor to the second transistor. This advantageously provides cross-coupling for the stacked transistors.

[0037] In addition to one or more of the features described above or below, the additional feature includes: an interconnect layer electrically connecting the first gate of the first transistor to the second gate of the second transistor. This advantageously provides an interconnect layer for the gates of stacked transistors.

[0038] In addition to one or more of the features described above or below, additional features include: conductive vias connecting the first transistor to conductive lines. This advantageously provides cross-coupling for stacked transistors.

[0039] In addition to one or more of the features described above or below, an additional feature includes: another conductive via connecting the second transistor to the conductive line. This advantageously provides cross-coupling for the stacked transistors.

[0040] In addition to one or more features described above or below, additional features include: the space between the first transistor and the second transistor includes a conductive via, a conductive line, and another conductive via. This advantageously provides cross-coupling for the stacked transistors.

[0041] In addition to one or more features described above or below, the additional features include: a first gate of the first transistor connected to a conductive connection, and another conductive via connected to both the conductive connection and the conductive line, the conductive line being connected to the conductive via; and a second gate of the second transistor connected to the conductive via. This advantageously provides an interconnect structure for cross-coupled stacked transistors.

[0042] In addition to one or more of the features described above or below, the additional feature includes: the gates of the first transistor and the second transistor are connected via an interconnect layer for simultaneous control. This advantageously allows stacked transistors to be driven simultaneously.

[0043] According to one or more embodiments, a semiconductor structure is provided. The semiconductor structure includes a first transistor having a first gate and a second transistor having a second gate, the second transistor being stacked on top of the first transistor. The semiconductor structure includes an interconnect layer formed between the first transistor and the second transistor, the interconnect layer electrically connecting the first gate and the second gate.

[0044] This provides improved electrical connectivity for sequentially stacked transistors, especially considering the increased transistor density on the semiconductor structure. Sequential stacking is highly attractive because it avoids the high aspect ratio processes of monolithic stacking. However, it can raise concerns about the impact of the top transistor process on the performance and reliability of the bottom transistors. This offers the unique improvement of inserting additional interconnect layers between the top and bottom transistors for sequential stacking, which is difficult to achieve in monolithic stacking. Conductive vias and conductive lines between the top and bottom transistors are used to form small-size logic cross-coupled structures that significantly contribute to area scaling.

[0045] In addition to one or more features described above or below, additional features include: the interconnect layer comprising a first conductive via, a conductive line, and a second conductive via. This advantageously provides an interconnect layer for the gates of cross-coupled stacked transistors.

[0046] In addition to one or more features described above or below, the additional features include: the interconnect layer includes a first conductive via connected to a first gate, a second conductive via connected to a second gate, and conductive lines connected to both the first and second conductive vias. This advantageously provides an interconnect layer for the gates of cross-coupled stacked transistors.

[0047] In addition to one or more features described above or below, the additional features include: a conductive connection connecting the first gate to a first conductive via; and an interconnect layer including a first conductive via connected to the conductive connection, a second conductive via connected to the second gate, and conductive lines connected to both the first and second conductive vias. This advantageously provides cross-coupling for the stacked transistors.

[0048] In addition to one or more features described above or below, the additional feature includes: the first gate and the second gate are connected by an interconnect layer for simultaneous control. This advantageously allows stacked transistors to be driven simultaneously.

[0049] According to one or more embodiments, a method for a semiconductor structure is provided. The method includes providing a first transistor having a first gate and providing a second transistor having a second gate, the second transistor being stacked above the first transistor, wherein an interconnect layer is formed between the first transistor and the second transistor, the interconnect layer electrically connecting the first gate and the second gate.

[0050] This provides improved electrical connectivity for sequentially stacked transistors, especially considering the increased transistor density on the semiconductor structure. Sequential stacking is highly attractive because it avoids the high aspect ratio processes of monolithic stacking. However, it can raise concerns about the impact of the top transistor process on the performance and reliability of the bottom transistors. This offers the unique improvement of inserting additional interconnect layers between the top and bottom transistors for sequential stacking, which is difficult to achieve in monolithic stacking. Conductive vias and conductive lines between the top and bottom transistors are used to form small-size logic cross-coupled structures that significantly contribute to area scaling.

[0051] In addition to one or more features described above or below, additional features include: the interconnect layer comprising a first conductive via, a conductive line, and a second conductive via. This advantageously provides an interconnect layer for the gates of cross-coupled stacked transistors.

[0052] In addition to one or more features described above or below, the additional features include: the interconnect layer includes a first conductive via connected to a first gate, a second conductive via connected to a second gate, and conductive lines connected to both the first and second conductive vias. This advantageously provides an interconnect layer for the gates of cross-coupled stacked transistors.

[0053] In addition to one or more features described above or below, the additional features include: a conductive connection connecting the first gate to a first conductive via; and an interconnect layer including a first conductive via connected to the conductive connection, a second conductive via connected to the second gate, and conductive lines connected to both the first and second conductive vias. This advantageously provides cross-coupling for the stacked transistors.

[0054] For the sake of brevity, this document may or may not describe in detail the conventional techniques associated with the manufacture of semiconductor devices and integrated circuits (ICs). Furthermore, the various tasks and processing steps described herein may be incorporated into a more comprehensive process or technology with additional steps or functions not described in detail here. Specifically, the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well-known; therefore, for the sake of brevity, many conventional steps will only be briefly mentioned here or will be omitted entirely without providing well-known process details.

[0055] A MOSFET is a transistor used to amplify or switch electronic signals. A MOSFET has a source, a drain, and a metal gate electrode. The metal gate is electrically insulated from the main semiconductor n-channel or p-channel by a thin layer of insulating material such as silicon dioxide or glass, which makes the MOSFET's input resistance relatively high. The gate voltage controls whether the current path from the source to the drain is an open circuit ("off") or a resistive path ("on"). N-type field-effect transistors (NFETs) and P-type field-effect transistors (PFETs) are two types of complementary MOSFETs. An NFET consists of an n-doped source and drain junction and uses electrons as charge carriers. A PFET consists of a p-doped source and drain junction and uses holes as charge carriers.

[0056] Now we turn to a more detailed description of aspects of the invention. Figure 1A A top view depicting a simplified diagram of a portion of an integrated circuit (IC) 100. Figure 1B A cross-sectional view taken along the Y axis of IC 100 is depicted. Figure 1C A cross-sectional view taken along X1 of IC 100 is depicted, and Figure 1DA cross-sectional view taken along X2 of IC 100 is depicted. Additional cross-sectional views along X3 may be depicted in subsequent figures. For ease of understanding, some layers may be omitted from the various top views so as not to obscure the figures and to allow the underlying layers to be seen. Therefore, the top views are intended to provide a simplified illustration and general orientation of a portion of the IC. As will be understood by those skilled in the art, the IC can be manufactured using standard semiconductor manufacturing techniques. Any suitable lithography process (including deposition and etching techniques) can be used here.

[0057] Figure 1A , Figure 1B , Figure 1C and Figure 1D The image depicts IC 100 after several manufacturing operations. Top transistor 950 (depicted on...) Figure 9B The bottom transistors 150 and 16 are stacked sequentially on the bottom transistor 150. The bottom transistor 150 is formed on the substrate 102. The substrate 102 (or wafer) may be formed of (pure) silicon. Other suitable materials may be used for the substrate 102. The bottom transistor 150 includes a bottom gate material 114 surrounding a bottom channel region 120. The bottom channel region 120 may be a nanosheet and is separated by a bottom inner spacer 110. Depending on the transistor type, bottom source / drain regions 104 are formed on opposite sides of the bottom channel region 120 and may be doped with a p-type dopant or an n-type dopant. Bottom gate spacers 112 are formed on the bottom gate material 114, and an interlayer dielectric (ILD) layer 116 is formed on the bottom source / drain regions 104. A shallow trench isolation (STI) region 130 is formed in the substrate 102.

[0058] The bottom gate material 114 may include a gate stack formed of a high-k dielectric material formed on the channel region and a work function material formed on the high-k dielectric material. The work function material includes a work function suitable for enhancing the electrical performance of an n-type or p-type semiconductor device, depending on the type of transistor being formed. Exemplary materials for the bottom inner spacer 110 and the bottom gate spacer 112 may include silicon nitride (SiN), porous silicon carbonitride (SiCN), carbon-doped oxide dielectric (including silicon, carbon, oxygen, and hydrogen) (SiCOH), and octamethylcyclotetrasiloxane (OMCTS). Exemplary material for the STI region 130 may include silicon dioxide. The ILD material of the ILD layer 116 may include a low-k dielectric material, an ultra-low-k dielectric material, etc.

[0059] Figure 2A , Figure 2B , Figure 2C and Figure 2DThe IC 100 is depicted in the process of forming an interconnect layer. Additional ILD material 204 is deposited to extend the ILD layer 116, and photolithography is performed to pattern the cavity 202 that exposes the bottom gate material 114 to prepare a metal via.

[0060] Figure 3A , Figure 3B , Figure 3C and Figure 3D The IC 100 after via metallization is depicted. Metal is deposited to form metal vias 302A, 302B, and 302C, as well as other metal vias (not shown). Metal vias 302A, 302B, and 302C may generally be referred to as metal via 302. Additional ILD material 306 is deposited to extend ILD layer 116 to form another interconnect layer, and photolithography is performed to pattern trenches 304 in ILD layer 116 to prepare metal lines / wires.

[0061] Figure 4A , Figure 4B , Figure 4C and Figure 4D The IC 100 is depicted after the metallization of the metal lines / wires, the patterning of the upper vias, and the metallization of the upper vias. Metal is deposited to form metal lines / wires 402A, 402B, and 402C, as well as other metal lines / wires (not shown). Metal lines / wires 402A, 402B, and 402C may generally be referred to as metal lines / wires 402. Some metal lines / wires 402 may extend longitudinally along the y-axis, while others may extend longitudinally along the x-axis.

[0062] Additional ILD material is deposited to extend ILD layer 116, forming another interconnect layer, and photolithography is performed to pattern the cavities in ILD layer 116. Metal is then deposited to form metal vias 404A, 404B, and 404C, as well as other metal vias (not shown). Metal vias 404A, 404B, and 404C may generally be referred to as metal via 404, which is located above metal via 302. Figure 4B As seen in the diagram, the metal via 302B, metal line / line 402B, and metal via 404B form cross-connections or cross-coupled connections between the bottom transistor and the top transistor (e.g., as shown in the diagram). Figure 8B and Figure 9B (As shown in the diagram). Metal via 302B, metal wire / line 402B and metal via 404B are physically and electrically connected.

[0063] It should be noted that metal vias 302A, 302B, and 302C are formed in layer V1, metal lines / wires 402A, 402B, and 402C are formed in layer M1, and metal vias 404A, 404B, and 404C are formed in layer V2. Metal vias 302, metal lines / wires 402, and metal vias 404 may include conductive materials. Exemplary conductive materials may include ruthenium (Ru), tungsten (W), titanium (Ti), molybdenum (Mo), gold (Au), copper (Cu), nickel (Ni), aluminum (Al), etc. In one or more embodiments, a liner, such as a Ti / TiN liner, may be deposited prior to the conductive material.

[0064] Figure 5A , Figure 5B , Figure 5C and Figure 5D The IC 100 is depicted after the deposition of bonding materials and nanosheets. A bonding layer 502 is deposited on top. The bonding layer 502 can be a dielectric material, such as silicon dioxide or other suitable materials. Semiconductor layers 510 and 520 are alternately formed on the bonding layer 502. Semiconductor layer 510 is a sacrificial layer and can be formed of silicon-germanium. Semiconductor layer 520 will become the top channel region. An exemplary material for semiconductor layer 520 may include silicon. Semiconductor layer 520 may be doped to enhance carrier properties.

[0065] Figure 6A , Figure 6B , Figure 6C and Figure 6D The IC 100 is depicted after undergoing several standard manufacturing processes to form the top dummy gate and spacers. For example, a fin cut is performed, resulting in a top channel region 620. The sides of the semiconductor layer 510 are etched, and dielectric material is deposited to form the top inner spacers 610.

[0066] A photolithography process is performed to form a top gate spacer 612, the remaining semiconductor layer 510 is removed, and a sacrificial material is deposited to form a dummy gate 614. The dummy gate 614 may be formed of amorphous silicon. A gate cap 630 is formed on top of the dummy gate 614. The gate cap 630 may be formed of silicon nitride.

[0067] Figure 7A , Figure 7B , Figure 7C and Figure 7D The IC 100 after the recessed bonding material is depicted. Etching is performed to etch a portion of the bonding layer 502. Isotropic etching can be performed.

[0068] Figure 8A , Figure 8B , Figure 8C and Figure 8DThe IC 100 after the directional deposition process is depicted. Now in Figure 8D The image depicts a cross-sectional view of X3. A high-density plasma chemical vapor deposition (HDPCVD) process can be performed to deposit the intermediate spacer material 802. The HPDCVD process is directional and grows only / primarily on horizontal surfaces (and may grow slowly on vertical surfaces). An etch-back process is performed to remove any sidewall material, thereby resulting in the intermediate spacer material 802. The intermediate spacer material 802 can be a nitride-based dielectric material, such as silicon nitride.

[0069] Figure 9A , Figure 9B , Figure 9C and Figure 9D The IC 100 after epitaxial material growth is depicted. A top source / drain region 904 is formed adjacent to a top channel region 602, and an ILD layer 916 is deposited. Etching and / or chemical mechanical planarization / polishing (CMP) can be performed to remove the intermediate spacer material 802 above the dummy gate 614 in preparation for a replacement metal gate process.

[0070] Figure 10A , 10B Figures 10C and 10D depict IC 100 after the metal gate replacement process. Etching is performed to expose the dummy gate 614 by removing the gate cap 630. Etching is then performed to remove the dummy gate 614, forming the top gate material 1014.

[0071] Figure 11A , 11B Figures 11C and 11D depict the IC 100 after gate dicing. Reactive ion etching is performed to etch portions of the top gate material 1014 and the bottom gate material 114, as well as portions of the bonding layer 502 and the ILD layer 116.

[0072] Figure 12A , 12B Figures 12C and 12D depict IC 100 after selectively recessing the bonding material. Etching is performed to partially recess the bonding layer 502, thereby creating gaps 1202 for depositing metal interconnects. Example etchants may include diluted hydrofluoric acid (HF2).

[0073] Figure 13A , 13B Figures 13C and 13D depict IC 100 after the gaps are filled with metal. Metal is deposited to fill gaps 1202, thereby forming a metal connection 1302. Specifically, the metal deposition causes the material to be pinched in the gaps 1202, and an etch-back process is performed to remove any excess metal. Example materials for the metal connection may include titanium nitride (TiN), etc.

[0074] To explain Figure 13B The bottom transistor and top transistor are cross-connected or cross-coupled, with the bottom gate material 114 of one of the bottom transistors 150 electrically connected to the gate material 1014 of one of the top transistors. For example, the bottom gate material 114 of one of the bottom transistors 150 is connected to a metal via 302B, a metal line / wire 402B is connected to both the bottom metal via 302B and the top metal via 404B, and the metal via 404B is connected to the gate material 1014 of one of the top transistors 950. In one or more embodiments, the metal via 404B can be connected to the gate material 1014 of the top transistor 950 via a metal connection 1302. In one or more embodiments, the metal connection 1302 may be absent, and the gate material 1014 may be formed on the metal via 404B for connection. In one or more embodiments, metal vias 302A, 302B and 302C, metal lines / lines 402A, 402B and 402C, and metal vias 404A, 404B and 404C all form an interconnect layer 1350 or interconnect structure between the stacked bottom transistor 150 and the top transistor 950.

[0075] Figure 14 A flowchart depicts a method 1400 for forming a semiconductor structure (such as IC 100) according to one or more embodiments. Reference may be made to any of the figures discussed herein. At block 1402, method 1400 includes providing a first transistor (e.g., bottom transistor 150). At block 1404, method 1400 includes forming an interconnect layer 1350 between the first transistor (e.g., bottom transistor 150) and a second transistor (e.g., top transistor 950), the first transistor being below the second transistor. The interconnect layer includes conductive vias (e.g., metal via 302) and conductive lines (e.g., metal line / wire 402).

[0076] Furthermore, interconnect layer 1350 electrically connects the first transistor to the second transistor. Interconnect layer 1350 electrically connects the first gate of the first transistor (e.g., bottom gate material 114) to the second gate of the second transistor (e.g., top gate material 1014). Conductive vias (e.g., metal vias 302B) connect the first transistor (e.g., bottom transistor 150) to conductive lines (e.g., metal line / wire 402B). Another conductive via (e.g., metal via 404B) connects the second transistor (e.g., top transistor 950) to conductive lines (e.g., metal line / wire 402B). The space between the first transistor and the second transistor includes the conductive via, the conductive line, and another conductive via (e.g., metal via 302B, metal line / wire 402B, and metal via 404B). The first gate of the first transistor (e.g., bottom gate material 114) is connected to the conductive connection, the other conductive via connects to both the conductive connection and the conductive line, and the conductive line connects to the conductive via; the second gate of the second transistor (e.g., top gate material 1014) is connected to the conductive via. The gates of the first transistor and the second transistor (e.g., bottom gate material 114 and top gate material 1014) are connected by an interconnect layer 1350 for simultaneous control.

[0077] The first gate of the first transistor (e.g., one of the top transistors 950) is directly below the second gate of the second transistor (e.g., one of the bottom transistors 150); or the first gate of the first transistor (e.g., one of the top transistors 950) is offset obliquely below the second gate of the second transistor (e.g., one of the bottom transistors 150).

[0078] Additionally, the top layer (e.g., the location of top transistor 950) includes a second transistor (e.g., one of top transistors 950) and a fourth transistor (e.g., another top transistor 950 on the left or right), the fourth transistor being laterally adjacent to the second transistor; the bottom layer (e.g., the location of bottom transistor 150) includes a first transistor (e.g., one of bottom transistors 150) and a third transistor (e.g., another bottom transistor 150), the first transistor being directly below the second transistor, and the third transistor being directly below the fourth transistor; the gates of the first and fourth transistors (e.g., one of the bottom gate materials 114 and one of the top gate materials 1014) are connected, and the other gates of the second and third transistors (e.g., another bottom gate material 114 and another top gate material 1014) are connected. Therefore, this has two separate metal lines / wires (only in...) Figure 13B (As shown in the figure), they extend along the y-axis, like metal wires / lines 402B, to facilitate the cross-connection of the gates of the four transistors mentioned above.

[0079] Figure 15A flowchart illustrating a method 1500 for forming a semiconductor structure (such as IC 100) according to one or more embodiments is provided. Reference may be made to any of the figures discussed herein. At block 1502, method 1500 includes providing a first transistor having a first gate (e.g., a bottom transistor 150 having a bottom gate material 114). At block 1504, method 1500 includes providing a second transistor having a second gate (e.g., a top transistor 950 having a top gate material 1014), the second transistor being stacked above the first transistor, wherein an interconnect layer 1350 is formed between the first and second transistors, the interconnect layer 1350 electrically connecting the first and second gates.

[0080] Furthermore, the interconnect layer 1350 includes a first conductive via, a conductive line, and a second conductive via. The interconnect layer 1350 includes a first conductive via connected to a first gate, a second conductive via connected to a second gate, and a conductive line connected to both the first conductive via and the second conductive via.

[0081] A conductive connection (e.g., metal connection 1302) connects the first gate to the first conductive via; the interconnect layer 1350 includes the first conductive via connected to the conductive connection (e.g., metal connection 1302), the second conductive via connected to the second gate, and conductive lines connected to both the first and second conductive vias.

[0082] Gate materials formed around fins or nanosheets include high-k materials and work function materials commonly referred to as high-k metal gates (HKMGs). Techniques for forming HKMGs in gate openings are known in the art; therefore, details are omitted to allow the reader to focus on the significant aspects of the disclosed method. However, it should be understood that such an HKMG will typically involve forming one or more gate dielectric layers (e.g., interlayer (IL) oxide and a high-k gate dielectric layer) deposited to line the gate openings, and forming one or more metal layers deposited on the gate dielectric layers to fill the gate openings. The materials and thicknesses of the dielectric and metal layers used for the HKMG can be pre-selected according to the conductivity type of the FET to achieve the desired work function. To avoid confusion in the figures and to allow the reader to focus on the significant aspects of the disclosed method, the different layers within the HKMG stack are not shown. For illustrative purposes, the high-k gate dielectric layer can be, for example, a dielectric material having a dielectric constant greater than that of silicon dioxide (i.e., greater than 3.9). Exemplary high-k dielectric materials include, but are not limited to, hafnium (Hf)-based dielectrics (e.g., hafnium oxide, hafnium silicon oxide, hafnium oxynitride, hafnium aluminum oxide, etc.) or other suitable high-k dielectrics (e.g., aluminum oxide, tantalum oxide, zirconium oxide, etc.). Optionally, the metal layer may include a metal with a pre-selected work function that is directly adjacent to the gate dielectric layer and is chosen to achieve the optimal gate conductor work function for the conductivity type of a given nanosheet-FET. For example, the optimal gate conductor work function for a PFET may be, for example, between about 4.9 eV and about 5.2 eV. Exemplary metals (and metal alloys) having a work function in or near this range include, but are not limited to, ruthenium, palladium, platinum, cobalt, and nickel, as well as metal oxides (aluminum carbon oxide, aluminum titanium carbon oxide, etc.) and metal nitrides (e.g., titanium nitride, titanium silicon nitride, tantalum silicon nitride, titanium aluminum nitride, tantalum aluminum nitride, etc.). The optimal gate conductor work function for an NFET may be, for example, between 3.9 eV and about 4.2 eV. Exemplary metals (and metal alloys) having a work function within or near this range include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, and alloys thereof, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. The metal layer may also include a filler metal or filler metal alloy, such as tungsten, tungsten alloys (e.g., tungsten silicide or titanonium tungsten), cobalt, aluminum, or any other suitable filler metal or filler alloy.

[0083] In one or more embodiments, the ILD material may be SiO2, SiN, a low-k dielectric material, or an ultra-low-k dielectric material. Low-k dielectric materials typically include dielectric materials having a k value of about 3.9 or less. Ultra-low-k dielectric materials typically include dielectric materials having a k value of less than 2.5. Unless otherwise stated, all k values ​​mentioned herein are measured relative to vacuum. Exemplary ultra-low-k dielectric materials typically include porous materials such as porous organosilicon glasses, porous polyamide nanofoams, silica dry gels, porous hydrogen silsesquioxanes (HSQ), porous methyl silsesquioxanes (MSQ), porous inorganic materials, porous CVD materials, porous organic materials, or combinations thereof. Ultra-low-k dielectric materials can be prepared using template methods or sol-gel methods commonly known in the art. In template methods, the precursor typically comprises a composite of a thermally unstable material and a stable material. After film deposition, the thermally unstable material can be removed by heating, thereby leaving pores in the dielectric film. In the sol-gel process, porous low-k dielectric films can be formed by the hydrolysis and condensation of alkoxides (such as tetraethoxysilane (TEOS)).

[0084] Various embodiments of the invention are described herein with reference to the accompanying drawings. Alternative embodiments may be devised without departing from the scope of the invention. Although various connections and positional relationships (e.g., above, below, adjacent, etc.) between elements are illustrated in the following description and drawings, those skilled in the art will recognize that many of the positional relationships described herein are orientation-independent even when orientation changes. Unless otherwise stated, these connections and / or positional relationships may be direct or indirect, and this disclosure is not intended to be limiting in this respect. Thus, coupling of entities can refer to direct or indirect coupling, and positional relationships between entities can be direct or indirect positional relationships. As an example of an indirect positional relationship, references in this specification to forming layer "A" on layer "B" include the state of one or more intermediate layers (e.g., layer "C") between layer "A" and layer "B," provided that the relevant characteristics and functions of layer "A" and layer "B" are not significantly altered by intermediate layers.

[0085] The phrase “selected on,” such as, for example, “the first element is selected on the second element,” means that the first element can be etched and the second element can be used as an etch stop.

[0086] As used herein, "p-type" refers to the addition of impurities that dopant in an intrinsic semiconductor to produce insufficient valence electrons. Examples of p-type dopants (i.e., impurities) in silicon-containing substrates include, but are not limited to, boron, aluminum, gallium, and indium.

[0087] As used herein, "n-type" refers to the addition of impurities that contribute free electrons to the intrinsic semiconductor. Examples of n-type dopants (i.e., impurities) in silicon-containing substrates include, but are not limited to, antimony, arsenic, and phosphorus.

[0088] As mentioned earlier, for the sake of brevity, conventional techniques associated with the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail. However, as background, a more general description of semiconductor device manufacturing processes that can be utilized to implement one or more embodiments of the present invention will now be provided. Although specific manufacturing operations used in implementing one or more embodiments of the present invention may be individually known, the combinations of described operations and / or the resulting structures are unique. Thus, the unique combinations of described operations associated with the manufacture of semiconductor devices according to the present invention utilize a variety of individually known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described in the following paragraphs.

[0089] Generally, the various processes used to form microchips that will be packaged into ICs fall into four general categories: film deposition, removal / etching, semiconductor doping, and patterning / photolithography. Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). Removal / etching is any process that removes material from a wafer. Examples include etching processes (wet or dry) and chemical mechanical polishing (CMP). Semiconductor doping modifies electrical properties by doping (e.g., transistor source and drain), typically through diffusion and / or ion implantation. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing serves to activate the implanted dopant. Films of conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selectively doping various regions of a semiconductor substrate allows the conductivity of the substrate to be altered by applying a voltage. By fabricating the structures of these various components, millions of transistors can be built and wired to form the complex circuits of modern microelectronic devices.

[0090] As described above, atomic layer etching (ALT) processes can be used in this invention to remove pathway residues, such as those caused by pathway misalignment. ALT processes provide precise etching of metals using either plasma-based or electrochemical methods. ALT processes are typically defined by two well-defined, sequential, self-limiting reaction steps that can be independently controlled. The process typically includes passivation followed by selective removal of the passivation layer and can be used to remove nanoscale thin metal layers. Exemplary plasma-based methods typically involve a two-step process that typically includes exposing a metal such as copper to a chlorine and hydrogen plasma at low temperatures (below 20°C). This process produces volatile etching products, which minimizes surface contamination. In another example, metals such as copper can be selectively etched by cyclic exposure to an oxidant and hexafluoroacetylacetone (Hhfac) at elevated temperatures (e.g., at 275°C). Exemplary electrochemical methods can also include two steps. The first step involves surface-limited sulfidation of the metal (e.g., copper) to form a metal sulfide (e.g., Cu₂S), followed by selective wet etching of the metal sulfide (e.g., etching Cu₂S in HCl). Atomic layer etching is a relatively new technique, and its optimization for specific metals is entirely within the capabilities of those skilled in the art. The reaction at the surface provides high selectivity and minimal or no attack on the exposed dielectric surface.

[0091] Semiconductor lithography is the process of forming a three-dimensional relief image or pattern on a semiconductor substrate, which is then transferred to the substrate. In semiconductor lithography, the pattern is formed using a photosensitive polymer called a photoresist. To build the complex structure of the many wires that make up the millions of transistors that connect the circuitry, the photolithography and etching pattern transfer steps are repeated multiple times. Each pattern printed on the wafer is aligned with a previously formed pattern, and conductors, insulators, and selectively doped regions are slowly built up to form the final device.

[0092] Photoresist can be formed using conventional deposition techniques such as chemical vapor deposition, plasma vapor deposition, sputtering, dip coating, spin coating, brush coating, spray coating, and other similar deposition techniques. After the photoresist is formed, it is exposed to a desired radiation pattern (such as X-ray radiation, extreme ultraviolet (EUV) radiation, electron beam radiation, or similar radiation). Next, the exposed photoresist is developed using conventional photoresist development processes.

[0093] Following the development step, an etching step may be performed to transfer the pattern from the patterned photoresist to the interlayer dielectric. The etching step for forming at least one opening may include dry etching processes (including, for example, reactive ion etching, ion beam etching, plasma etching, or laser ablation), wet chemical etching processes, or any combination thereof.

[0094] For the sake of brevity, conventional techniques for making and using aspects of the invention may or may not be described in detail herein. In particular, various aspects of computing systems and specific computer programs are well known in order to implement the various technical features described herein. Therefore, for the sake of brevity, many conventional implementation details are only briefly mentioned or omitted entirely, without providing well-known system and / or process details.

[0095] In some embodiments, various functions or actions may occur at a given location and / or in association with the operation of one or more devices or systems. In some embodiments, a portion of a given function or action may be performed at a first device or location, and the remainder of the function or action may be performed at one or more additional devices or locations.

[0096] The terminology used herein is for the purpose of describing particular embodiments and is not restrictive. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that the terms “comprising” and / or “including” as used in this specification indicate the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0097] The corresponding structures, materials, actions, and equivalents of all elements referred to as "means or steps plus function" in the following claims are intended to include any structure, material, or action for performing the claimed function in combination with other claimed elements. This disclosure is presented for purposes of illustration and description, but is not exhaustive or intended to limit the disclosure to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the invention. Embodiments have been chosen and described to best explain the principles and practical application of the invention and to enable others skilled in the art to understand various embodiments of the invention with various modifications suitable for the intended particular purpose.

[0098] The illustrations shown herein are illustrative. Many variations can be made to the illustrations or the steps (or operations) described therein without departing from the scope of the invention. For example, actions may be performed in a different order, or actions may be added, deleted, or modified. Furthermore, the term "coupled" describes a signal path between two elements and does not imply a direct connection between the elements without any intermediate elements / connections. All such variations are considered part of this disclosure.

[0099] The following definitions and abbreviations are used to interpret the claims and specification. As used herein, the terms “comprising,” “including,” “having,” “containing,” or any other variation thereof are intended to cover non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements, but may include other elements not expressly listed or inherently part of such composition, mixture, process, method, article, or apparatus.

[0100] Additionally, the term "exemplary" is used to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily constructed to be superior to other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "multiple" is understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connection" can include both indirect "connection" and direct "connection."

[0101] The terms “about,” “basically,” “approximately,” and their variations are intended to include the degree of measurement error associated with a specific quantity based on the equipment available at the time of application. For example, “about” can include a range of ±8%, 5%, or 2% of a given value.

[0102] The various embodiments of the invention described herein are for illustrative purposes and are not intended to be exhaustive or limiting to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements relative to technology in the market, or to enable others skilled in the art to understand the embodiments described herein.

[0103] In a preferred embodiment of the invention described herein, a semiconductor structure is provided, comprising: a first transistor having a first gate; a second transistor having a second gate, the second transistor being stacked above the first transistor; and an interconnect layer formed between the first transistor and the second transistor, the interconnect layer electrically connecting the first gate and the second gate. The interconnect layer may include a first conductive via, a conductive line, and a second conductive via. The interconnect layer includes a first conductive via connected to the first gate, a second conductive via connected to the second gate, and a conductive line connected to both the first conductive via and the second conductive via. A conductive connection can connect the first gate to the first conductive via; and the interconnect layer may include a first conductive via connected to the conductive connection, a second conductive via connected to the second gate, and a conductive line connected to both the first conductive via and the second conductive via. The first gate and the second gate can be connected via the interconnect layer for simultaneous control.

[0104] In a preferred embodiment of the invention described herein, a method is provided comprising: providing a first transistor having a first gate; and providing a second transistor having a second gate, the second transistor being stacked above the first transistor, wherein an interconnect layer is formed between the first transistor and the second transistor, the interconnect layer electrically connecting the first gate and the second gate. The interconnect layer may include a first conductive via, a conductive line, and a second conductive via.

Claims

1. A semiconductor structure, comprising: The first transistor stacked below the second transistor; as well as An interconnect layer between a first transistor and a second transistor, the interconnect layer including conductive vias and conductive lines.

2. The semiconductor structure according to claim 1, wherein, The interconnect layer electrically connects the first transistor to the second transistor.

3. The semiconductor structure according to claim 1, wherein, The interconnect layer electrically connects the first gate of the first transistor to the second gate of the second transistor.

4. The semiconductor structure according to claim 1, wherein, The conductive via connects the first transistor to the conductive line.

5. The semiconductor structure according to claim 4, wherein, Another conductive via connects the second transistor to the conductive line.

6. The semiconductor structure according to claim 5, wherein, The space between the first transistor and the second transistor includes the conductive via, the conductive line, and the other conductive via.

7. The semiconductor structure according to claim 1, wherein: The first gate of the first transistor is connected to a conductive connection, and another conductive via is connected to both the conductive connection and the conductive line, the conductive line being connected to the conductive via; and The second gate of the second transistor is connected to the conductive via.

8. The semiconductor structure according to claim 1, wherein, The first gate of the first transistor and the second gate of the second transistor are connected through the interconnect layer for simultaneous control.

9. The semiconductor structure according to claim 1, wherein: The first gate of the first transistor is directly below the second gate of the second transistor; or The first gate of the first transistor is obliquely offset below the second gate of the second transistor.

10. The semiconductor structure according to claim 1, wherein: The top layer includes the second transistor and the fourth transistor, wherein the fourth transistor is laterally adjacent to the second transistor; The bottom layer includes the first transistor and the third transistor, with the first transistor located directly below the second transistor and the third transistor located directly below the fourth transistor. as well as The gates of the first transistor and the fourth transistor are connected, and the other gates of the second transistor and the third transistor are connected.

11. A method comprising: Provide the first transistor; as well as An interconnect layer is formed between a first transistor and a second transistor, with the first transistor below the second transistor. The interconnect layer includes conductive vias and conductive lines.

12. The method according to claim 11, wherein, The interconnect layer electrically connects the first transistor to the second transistor.

13. The method according to claim 11, wherein, The interconnect layer electrically connects the first gate of the first transistor to the second gate of the second transistor.

14. The method according to claim 11, wherein, The conductive via connects the first transistor to the conductive line.

15. The method according to claim 14, wherein, Another conductive via connects the second transistor to the conductive line.

16. The method according to claim 15, wherein, The space between the first transistor and the second transistor includes the conductive via, the conductive line, and the other conductive via.

17. The method of claim 11, wherein: The first gate of the first transistor is connected to a conductive connection, and another conductive via is connected to both the conductive connection and the conductive line, the conductive line being connected to the conductive via; and The second gate of the second transistor is connected to the conductive via.

18. The method according to claim 11, wherein, The first gate of the first transistor and the second gate of the second transistor are connected through the interconnect layer for simultaneous control.

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