Semiconductor structure with contacts with sidewall spacers

Abstract

A semiconductor structure includes a transistor at a first side of the semiconductor structure, a contact (148) to the transistor at a second side of the semiconductor structure, and a sidewall spacer (126) around a portion of a sidewall of the contact. The contact has a first width (1201) above the sidewall spacer and a second width (1205) below the sidewall spacer, the second width being different than the first width. The second width can be greater than the first width.

Description

Background Technology

[0001] This application relates to semiconductors, and more specifically, to techniques for forming semiconductor structures. Semiconductor and integrated circuit chips are already ubiquitous in many products, especially as their cost and size continue to decrease. There is a constant desire to reduce the size of structural features and / or to provide a greater number of structural features within a given chip size. Generally speaking, miniaturization enables higher performance with lower power consumption and lower cost. Current technology is at or near the atomic scaling level for certain microdevices, such as logic gates, field-effect transistors (FETs), and capacitors.

[0002] A field-effect transistor (FET) is a three-terminal device with a source, a gate, and a drain. Its operation depends on the flow of charge carriers (electrons or holes) along the channel between the source and drain. The current in the channel between the source and drain can be controlled by a lateral electric field below the gate.

[0003] FETs are widely used in switching, amplification, filtering, and other applications. FETs include metal-oxide-semiconductor (MOS) FETs (MOSFETs). Complementary MOS (CMOS) devices are widely used, with both n-type and p-type transistors (nFETs and pFETs) used in the fabrication of logic and other circuits. The source and drain regions of an FET are typically formed by doping target regions on either side of a channel in a semiconductor substrate, with the gate formed above the channel. The gate consists of a gate dielectric above the channel and a gate conductor above the gate dielectric. The gate dielectric is an insulating material that prevents significant leakage current from flowing into the channel when a voltage is applied to the gate conductor, while allowing the applied gate voltage to generate a lateral electric field in the channel.

[0004] Several techniques can be used to reduce the area of ​​a FET. One technique is to use a finned channel in a FinFET device. Before the advent of FinFET structures, CMOS devices were typically planar along the surface of the semiconductor substrate, except for the FET gate located at the top of the channel. FinFETs utilize a vertical channel structure, increasing the surface area of ​​the channel exposed to the gate. Therefore, in a FinFET structure, the gate can extend to multiple sides or surfaces of the channel, thereby controlling the channel more effectively. In a FinFET structure, the gate surrounds three surfaces of a three-dimensional channel, rather than just being located on the top surface of a traditional planar channel.

[0005] Another technique for reducing FET size is to use stacked nanosheet channels above a semiconductor substrate. The stacked nanosheets can be two-dimensional nanostructures, such as sheets with a thickness of approximately 1 to 100 nanometers (nm). Nanosheets and nanowires are viable options for scaling to process nodes of 7 nm and below. A typical process flow for forming the nanosheet stack involves removing sacrificial layers (which can be formed from silicon (Si)) between the channel material sheets (which can be formed from silicon germanium (SiGe)). Summary of the Invention

[0006] Embodiments of the present invention provide techniques for forming semiconductor structures with contacts having sidewall spacers, wherein the contacts have different widths above and below the sidewall spacers. The sidewall spacers advantageously allow for the retention of placeholders during back-side substrate etching processes.

[0007] In one embodiment, a semiconductor structure includes: a transistor at a first side of the semiconductor structure, a contact to the transistor at a second side of the semiconductor structure, and a sidewall spacer surrounding a portion of the sidewall of the contact. The contact has a first width above the sidewall spacer and a second width below the sidewall spacer, the second width being different from the first width.

[0008] The sidewall spacers of the semiconductor structure are advantageously able to retain the spacers during the back-side substrate etching process, wherein at least one of the spacers is removed and replaced as a contact for a transistor at the second side of the semiconductor structure.

[0009] In another exemplary embodiment, the second width may be greater than the first width, in conjunction with the foregoing paragraph.

[0010] In another exemplary embodiment, in conjunction with the foregoing paragraph, the contact member may have a third width between the upper and lower surfaces of the sidewall spacer, the third width being different from both the first and second widths. The first width may be greater than the third width, and the second width may be greater than the first width.

[0011] In another exemplary embodiment, in conjunction with the foregoing paragraphs, the contact can be connected to the source / drain region of the transistor. The semiconductor structure may further include a berth on a second side of the semiconductor structure, directly below another source / drain region of the transistor, and additional sidewall spacers surrounding a portion of the sidewall of the berth. The berth has a third width above the upper surface of the additional sidewall spacers and a fourth width below the upper surface of the additional sidewall spacers, the third width being different from the fourth width. The fourth width may be greater than the third width. The additional sidewall spacers surrounding a portion of the sidewall of the berth may be perpendicularly aligned with the sidewall spacers surrounding a portion of the sidewall of the contact.

[0012] In another exemplary embodiment, in conjunction with the foregoing paragraph, the semiconductor structure may further include an interlayer dielectric layer disposed between the upper surface of the sidewall spacer and the bottom dielectric insulating layer of the transistor.

[0013] In another embodiment, a semiconductor structure includes: a transistor at a first side of the semiconductor structure, a placeholder self-aligned with the source / drain regions of the transistor at a second side of the semiconductor structure, and a sidewall spacer surrounding a portion of the sidewall of the placeholder. The placeholder has a first width above the upper surface of the sidewall spacer and a second width below the upper surface of the sidewall spacer, the second width being different from the first width.

[0014] The sidewall spacers in the semiconductor structure are advantageous in that they can retain the placeholders during the back-side substrate etching process.

[0015] In another exemplary embodiment, the second width may be greater than the first width, in conjunction with the foregoing paragraph.

[0016] In another exemplary embodiment, in conjunction with the foregoing paragraphs, the semiconductor structure may further include a contact at a second side of the semiconductor structure to another source / drain region of the transistor, and an additional sidewall spacer surrounding a portion of the sidewall of the contact, wherein the contact has a third width above the additional sidewall spacer and a fourth width below the additional sidewall spacer, the third width being different from the fourth width. The fourth width may be greater than the third width.

[0017] In another embodiment, a semiconductor structure includes: a transistor disposed on a first side of the semiconductor structure; a placeholder self-aligned with a first source / drain region of the transistor on a second side of the semiconductor structure; a contact on the second side of the semiconductor structure leading to a second source / drain region of the transistor; and a sidewall spacer surrounding a portion of the sidewall of the contact and the placeholder. A first portion of the placeholder above the upper surface of the sidewall spacer has a different width than a second portion of the placeholder below the upper surface of the sidewall spacer. A first portion of the contact above the upper surface of the sidewall spacer has a different width than a second portion of the contact below the lower surface of the sidewall spacer.

[0018] In another exemplary embodiment, in conjunction with the foregoing paragraph, the width of the first portion of the occupant above the upper surface of the sidewall spacer is smaller than the width of the second portion of the occupant below the upper surface of the sidewall spacer.

[0019] In another exemplary embodiment, in conjunction with the foregoing paragraphs, the width of the first portion of the contact above the upper surface of the sidewall spacer is smaller than the width of the second portion of the contact below the lower surface of the sidewall spacer. The third portion of the contact between the upper and lower surfaces of the sidewall spacer has a different width from both the first portion of the contact above the upper surface of the sidewall spacer and the second portion of the contact below the lower surface of the sidewall spacer.

[0020] In another exemplary embodiment, in conjunction with the foregoing paragraph, the upper surface of the sidewall spacer and the bottom dielectric insulating layer of the transistor may be separated by an interlayer dielectric layer.

[0021] In another embodiment, a transistor structure includes: a first source / drain region, a second source / drain region, a berth self-aligned with the back side of the first source / drain region, a contact connected to the back side of the second source / drain region, and a sidewall spacer surrounding a portion of the sidewall of the contact and the berth. The width of a first portion of the berth above the upper surface of the sidewall spacer differs from the width of a second portion of the berth below the upper surface of the sidewall spacer. The first portion of the contact above the upper surface of the sidewall spacer has a different width than the second portion of the contact below the lower surface of the sidewall spacer.

[0022] The sidewall spacers in the transistor structure advantageously allow for the retention of berths during the back-side substrate etching process, including berths that are self-aligned to the back side of the first source / drain region. At least one other berth can be removed and replaced with a contact to the back side of the second source / drain region.

[0023] In another exemplary embodiment, in conjunction with the foregoing paragraph, the width of the first portion of the occupant above the upper surface of the sidewall spacer is smaller than the width of the second portion of the occupant below the upper surface of the sidewall spacer.

[0024] In another exemplary embodiment, in conjunction with the foregoing paragraph, the width of the first portion of the contact above the upper surface of the sidewall spacer is smaller than the width of the second portion of the contact below the lower surface of the sidewall spacer.

[0025] In another exemplary embodiment, in conjunction with the foregoing paragraph, the upper surface of the sidewall spacer and the bottom dielectric insulating layer of the transistor structure may be separated by an interlayer dielectric layer.

[0026] In another embodiment, an integrated circuit includes a semiconductor structure comprising: a transistor at a first side of the semiconductor structure, a contact to the transistor at a second side of the semiconductor structure, and a sidewall spacer surrounding a portion of a sidewall of the contact. The contact has a first width above the sidewall spacer and a second width below the sidewall spacer, the second width being different from the first width.

[0027] The sidewall spacers of the semiconductor structure are advantageously able to retain the spacers during the back-side substrate etching process, wherein at least one of the spacers is removed and replaced as a contact for a transistor at the second side of the semiconductor structure.

[0028] In another exemplary embodiment, the second width may be greater than the first width, in conjunction with the foregoing paragraph.

[0029] In another exemplary embodiment, in conjunction with the foregoing paragraphs, the contact can be connected to the source / drain region of the transistor. The semiconductor structure may also include a berth on a second side of the semiconductor structure, directly below another source / drain region of the transistor, and an additional sidewall spacer surrounding a portion of the sidewall of the berth, wherein the berth has a third width above the upper surface of the additional sidewall spacer and a fourth width below the upper surface of the additional sidewall spacer, the third width being different from the fourth width. Attached Figure Description

[0030] Figure 1A The illustration shows a first cross-sectional view of a semiconductor structure following an embodiment of the invention, after nanosheet stack patterning, shallow trench isolation region formation, virtual gate structure formation and patterning, gate spacer and bottom dielectric insulator formation, nanosheet recess, nanosheet stack sacrificial layer recess, and internal spacer formation.

[0031] Figure 1B The illustration shows a second cross-sectional view of a semiconductor structure following an embodiment of the invention, after nanosheet stack patterning, shallow trench isolation region formation, virtual gate structure formation and patterning, gate spacer and bottom dielectric insulator formation, nanosheet recess, nanosheet stack sacrificial layer recess, and internal spacer formation.

[0032] Figure 1C A top view is shown according to an embodiment of the present invention, showing... Figure 1A and Figure 1B The cut-off positions of the first and second sectional views.

[0033] Figure 2A This illustrates an embodiment of the invention, after the protective liner and the spacer cavity grooves are formed. Figures 1A to 1C First sectional view of the structure.

[0034] Figure 2B This illustrates an embodiment of the invention, after the protective liner and the spacer cavity grooves are formed. Figures 1A to 1C The second sectional view of the structure.

[0035] Figure 3A This illustrates an embodiment of the invention, following lateral etching of the etch stop layer and formation of the placeholder sidewall spacers. Figure 2A and Figure 2B First sectional view of the structure.

[0036] Figure 3B This illustrates an embodiment of the invention, following lateral etching of the etch stop layer and formation of the placeholder sidewall spacers. Figure 2A and Figure 2B The second sectional view of the structure.

[0037] Figure 4A This illustrates an embodiment of the invention, following the formation of the placeholder, removal of the protective liner, and formation of the source / drain regions. Figure 3A and Figure 3B First sectional view of the structure.

[0038] Figure 4B This illustrates an embodiment of the invention, following the formation of the placeholder, removal of the protective liner, and formation of the source / drain regions. Figure 3A and Figure 3B The second sectional view of the structure.

[0039] Figure 5A This illustrates an embodiment of the invention, following the formation of the gate structure, interlayer dielectric layer, middle contact, and back-end interconnect structure, and bonding to the carrier wafer. Figure 4A and Figure 4B First sectional view of the structure.

[0040] Figure 5B This illustrates an embodiment of the invention, following the formation of the gate structure, interlayer dielectric layer, middle contact, and back-end interconnect structure, and bonding to the carrier wafer. Figure 4A and Figure 4B The second sectional view of the structure.

[0041] Figure 6A This illustrates an embodiment of the invention, following wafer flipping and substrate removal, and stopping at an etch stop layer. Figure 5A and Figure 5B First sectional view of the structure.

[0042] Figure 6B This illustrates an embodiment of the invention, following wafer flipping and substrate removal, and stopping at an etch stop layer. Figure 5A and Figure 5B The second sectional view of the structure.

[0043] Figure 7A This illustrates an embodiment of the invention, following directional etching that removes the etch stop layer and the placeholder portion. Figure 6A and Figure 6B First sectional view of the structure.

[0044] Figure 7B This illustrates an embodiment of the invention, following directional etching that removes the etch stop layer and the placeholder portion. Figure 6A and Figure 6B The second sectional view of the structure.

[0045] Figure 8A An embodiment according to the invention is shown, after the remaining portion of the substrate is removed, Figure 7A and Figure 7B First sectional view of the structure.

[0046] Figure 8B An embodiment according to the invention is shown, after the remaining portion of the substrate is removed, Figure 7A and Figure 7B The second sectional view of the structure.

[0047] Figure 9A This illustrates an embodiment of the invention, after the formation of the back-side interlayer dielectric layer, Figure 8A and Figure 8B First sectional view of the structure.

[0048] Figure 9B This illustrates an embodiment of the invention, after the formation of the back-side interlayer dielectric layer, Figure 8A and Figure 8B The second sectional view of the structure.

[0049] Figure 10A This illustrates an embodiment of the invention, following the formation and patterning of the organic planarization layer and the formation of the back-side contact trenches. Figure 9A and Figure 9B First sectional view of the structure.

[0050] Figure 10B This illustrates an embodiment of the invention, following the formation and patterning of the organic planarization layer and the formation of the back-side contact trenches. Figure 9A and Figure 9B The second sectional view of the structure.

[0051] Figure 11A This illustrates an embodiment of the invention, after removing the occupant exposed in the back contact groove, Figure 10A and Figure 10B First sectional view of the structure.

[0052] Figure 11BThis illustrates an embodiment of the invention, after removing the occupant exposed in the back contact groove, Figure 10A and Figure 10B The second sectional view of the structure.

[0053] Figure 12A This illustrates an embodiment of the invention, after the back-side contacts and the back-side power supply network are formed. Figure 11A and Figure 11B First sectional view of the structure.

[0054] Figure 12B This illustrates an embodiment of the invention, after the back-side contacts and the back-side power supply network are formed. Figure 11A and Figure 11B The second sectional view of the structure.

[0055] Figure 13 An embodiment of the invention is shown, comprising an integrated circuit with one or more semiconductor structures having contacts with sidewall spacers. Detailed Implementation

[0056] Exemplary embodiments of the invention may be described herein within the context of exemplary methods for forming semiconductor structures with contacts having sidewall spacers, and exemplary apparatuses, systems, and devices formed using such methods. However, it should be understood that embodiments of the invention are not limited to the exemplary methods, apparatuses, systems, and devices, but are more broadly applicable to other suitable methods, apparatuses, systems, and devices.

[0057] It should be understood that the various features shown in the accompanying drawings are schematic illustrations and are not necessarily drawn to scale. Furthermore, the same or similar reference numerals used throughout the drawings denote the same or similar features, elements, or structures, and therefore, the same or similar features, elements, or structures will not be described in detail again for each of the drawings. In addition, the terms "exemplary" and "illustrative" as used herein mean "as an example, instance, or illustration." No embodiment or design described herein as "exemplary" or "illustrative" should be construed as being more preferred or advantageous than other embodiments or designs.

[0058] Many semiconductor structures utilize back-side contacts. Back-side contact patterning can utilize placeholders formed in the semiconductor structure substrate, where the back-side process includes patterning a mask on the back side of the structure to selectively remove placeholders located at the position where the back-side contact will be formed to the portion of the device (e.g., a transistor) formed on the front side of the semiconductor structure. However, back-side contact patterning can encounter overlay alignment problems, which cause unwanted placeholders to be exposed and at least partially removed. This problem is exacerbated as the placeholder size becomes smaller after the substrate is removed from the back side, especially in tapered regions. Therefore, undesirable placeholder loss can occur during back-side contact patterning.

[0059] Exemplary embodiments provide techniques for forming sidewall spacers on a placeholder. Such sidewall spacers advantageously allow for better retention of the placeholder during back-side substrate removal. The sidewall spacers also advantageously provide back-side contact etch stops (e.g., reactive ion etching (RIE) etch stops) and alleviate back-side contact patterning alignment problems. Therefore, the techniques described herein mitigate placeholder etch loss problems and enable greater process margins for the formation of self-aligned back-side contacts.

[0060] In some embodiments, the semiconductor structure includes a pair of spacers on the sidewalls of a back-side contact. The semiconductor structure may also include a pair of spacers on the sidewalls of a lower portion of a berth. The back-side contact may be formed to contact the source / drain regions of a transistor device. The berth may also be formed below the source / drain regions of the transistor device. The back-side contact may have a first width above the spacers (e.g., near the source / drain regions of the transistor device) and a second width below the spacers (e.g., near the back-side power supply network (BSPDN)). The first width may be smaller than the second width. The spacers may have a top surface or an upper surface, which may be separated from the bottom dielectric (BDI) layer by a back-side interlayer dielectric (ILD) layer.

[0061] A method for forming a semiconductor structure may include: patterning a nanosheet stack formed over a substrate, wherein an etch stop layer is disposed in the substrate. The nanosheet stack includes a first sacrificial layer, followed by alternating second sacrificial layers and nanosheet channel layers. The first and second sacrificial layers are configured for selective removal relative to each other and the nanosheet channel layers. For example, the first and second sacrificial layers may comprise silicon germanium (SiGe) with different germanium (Ge) percentages, and the nanosheet channel layers may comprise silicon (Si). A dummy gate structure is then formed and patterned over the nanosheet stack, followed by removal of the first sacrificial layer, and the formation of spacer material and gate spacers providing a BDI (e.g., in the space formed by removing the first sacrificial layer) on the sidewalls of the dummy gate structure. The nanosheet stack may then be recessed, subsequently recessing the second sacrificial layer in the nanosheet stack, and forming internal spacers in the recessed etch region. A protective liner (e.g., formed of silicon nitride (SiN) or another suitable material) is then formed over the nanosheet stack above the BDI and the sidewalls of the dummy gate structure. The BDI is then opened, followed by etching the substrate to form a placeholder cavity. The substrate is etched through the etch stop layer and into a portion of the substrate below the etch stop layer. Lateral etching (e.g., recessed etching) of the etch stop layer is then performed, followed by filling the recessed portion of the etch stop layer with internal spacers. A placeholder (e.g., SiGe / Si) is then formed in the placeholder cavity. The protective liner is then stripped, followed by growth of source / drain regions over the placeholder. The gate structure can then be formed using a displacement metal gate (RMG) process, followed by formation of middle-end (MOL) contacts and back-end (BEOL) interconnect structures. The structure is then bonded to a carrier wafer, followed by wafer flipping and substrate removal, stopping at the etch stop layer. Oriented etching (e.g., removing portions of the etch stop layer and placeholder) is then performed. The remaining substrate is then removed, followed by filling the back-side ILD layer and planarizing the back-side ILD layer (e.g., using chemical mechanical planarization (CMP)). Back-side contact patterning is then performed, where internal spacers on the sides of the placeholder provide etch stops for the back-side contact patterning. The placeholder is then removed, followed by back-side contact metallization and formation of BSPDN.

[0062] Figures 1A to 12B The process flow for forming the sidewall spacers of the placeholder is shown, which can better retain the placeholder and control the position of the back contact.

[0063] Figures 1A to 1C Different views of a semiconductor structure are shown. Figure 1A A first cross-sectional view 100 showing the semiconductor structure is shown. Figure 1B A second cross-sectional view 175 shows the semiconductor structure. Figure 1C A top view 185 is shown, which illustrates... Figure 1AFirst sectional view 100 and Figure 1B The cut-off position of the second sectional view 175. Figure 1C Active regions 101-1 and 101-2 (collectively referred to as active region 101) and gate regions 103-1, 103-2 and 103-3 (collectively referred to as gate region 103) are shown. Figure 1C Spacer layer 120 is also shown. Figure 1A First sectional view 100 along Figure 1C The AA line cut is shown in the top view 185 (e.g., along the active region 101-1 and through the gate region 103). Figure 1B Second sectional view 175 along Figure 1C The BB line cut is shown in the top view 185 (e.g., between gate region 103-2 and gate region 103-3 and through active region 101).

[0064] Figures 1A to 1C The semiconductor structure includes a substrate 102, an etch stop layer 104, a substrate 106, a nanosheet stack including an alternating sacrificial layer 108 and a nanosheet channel layer 110, a dielectric layer 112, a shallow trench isolation (STI) region 114, a dummy gate layer 116, a hard mask layer 118, a spacer layer 120, and an internal spacer 122.

[0065] Substrates 102 and 106 can be formed from any suitable semiconductor structure, including various silicon-containing materials, including but not limited to silicon (Si), silicon-germanium (SiGe), silicon-germanium carbide (SiGeC), silicon carbide (SiC), and their multilayer structures. Although silicon is the most commonly used semiconductor material in wafer fabrication, alternative semiconductor materials can be used as additional layers, such as, but not limited to, germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), SiGe, cadmium telluride (CdTe), zinc selenide (ZnSe), etc. The height (Z direction) and width (X / Y direction) of substrates 102 and 106 can be varied as needed according to the type of structure to be formed.

[0066] The etch stop layer 104 may include a buried oxide (BOX) layer or silicon germanium (SiGe), or another suitable material, such as a III-V semiconductor epitaxial layer. The height (Z direction) of the etch stop layer 104 may be in the range of 10 to 30 nm.

[0067] The sacrificial layer 108 can be formed from SiGe. The thickness (Z direction) of each sacrificial layer 108 can be in the range of 5-15 nm.

[0068] The nanosheet channel layer 110 will provide channels for transistors in the transistor structure. The nanosheet channel layer 110 can be formed of Si or another suitable material (e.g., a material similar to that used for the substrate 102). The thickness (Z direction) of each nanosheet channel layer 110 can be in the range of 5-15 nm.

[0069] The dielectric layer 112 can be formed of a suitable dielectric material, such as silicon nitride (SiN). The thickness of the dielectric layer 112 can be in the range of 5-8 nm.

[0070] The STI region 114 can be formed of dielectric materials such as silicon dioxide (SiO2), silicon oxycarbide (SiOC), and silicon oxynitride (SiON). The height (Z direction) of the STI region 114 can be in the range of 10 to 200 nm.

[0071] The virtual gate layer 116 can be formed from amorphous silicon (a-Si), amorphous silicon germanium (a-SiGe) covered with a thin SiO2 or titanium nitride (TiN) layer, or another suitable material.

[0072] The hard mask layer 118 can be formed of a multilayer structure of silicon nitride (SiN), SiN and SiO2, or another suitable material. The height (Z direction) of the hard mask layer 118 can be in the range of 10 nm or greater, and the width (X direction) matches the underlying virtual gate layer 116 (e.g., it can be patterned to a width in the range of 10-100 nm).

[0073] The spacer layer 120 can be formed of silicon boron nitride (SiBCN) or another suitable material, such as SiN, SiOC, silicon oxycarbonitrile (SiOCN), etc. The thickness of the spacer layer 120 can be in the range of 4 to 10 nm. A portion of the spacer layer 120 on the sidewalls of the dummy gate layer 116 and the hard mask layer 118 provides gate spacers, while a portion of the spacer layer 120 between the substrate 106 and the nanosheet stack forms a bottom dielectric insulating (BDI) layer.

[0074] The internal spacer 122 can be formed of SiN, SiBCN, SiOCN, SiC, SiOC, or another suitable material.

[0075] Figures 1A to 1CThe semiconductor structure can be formed as follows: A nanosheet stack (e.g., a sacrificial layer 108 and a nanosheet channel layer 110) is deposited over a substrate 106. The nanosheet stack is then patterned (e.g., using a photolithography process), followed by the deposition of a dielectric layer 112, a material filling the STI region 114, and a material for recessing the STI region 114. A dummy gate layer 116 is then patterned using a hard mask layer 118, followed by etching to remove the sacrificial layer (not shown, but may be formed of SiGe with a different Ge percentage than the sacrificial layer 108) in the region shown by the BDI layer. A spacer layer 120 is then formed to provide gate spacers and the BDI layer. An indentation etching is then performed to recess the sacrificial layer 108. An internal spacer 122 is then formed. The depth (X-direction) of the indentation etching can be in the range of 5-9 nm.

[0076] Figure 2A and Figure 2B The protective liner 124 and the occupier cavity groove 201 are shown separately after their formation. Figures 1A to 1C First sectional view 200 and second sectional view 275 of the structure. Figure 2A First sectional view 200 along Figure 1C The AA line is shown in the top view 185. Figure 2B Second sectional view 275 along Figure 1C The BB line is shown in the top view 185.

[0077] A protective liner 124 can be formed on the sidewalls of the gate spacer, nanosheet channel layer 110, and internal spacer 122 above the BDI layer. The protective liner 124 can be formed of SiN or another suitable material, such as SiCOH, SiNCH, etc. The thickness (X direction) of the protective liner 124 can be in the range of 1-3 nm. After forming the protective liner 124, etching is performed to open the BDI layer and form a placeholder cavity trench 201 through the substrate 106, etch stop layer 104, and a portion of the substrate 102. The placeholder cavity trench 201 can be formed in the substrate 102 to a depth 203 (Z direction), ranging from 50-70 nm. The depth 203 is chosen such that during the directional etching of the etch stop layer 104 (hereinafter referred to as...)... Figure 7A and Figure 7B (Detailed description) Sufficient spacer material is retained in the spacer cavity groove 201.

[0078] Figure 3A and Figure 3B The images show the lateral etching of the etch stop layer 104 and the formation of the placeholder sidewall spacers 126, respectively. Figure 2A and Figure 2B First sectional view 300 and second sectional view 375 of the structure. Figure 3A First sectional view 300 along Figure 1CThe AA line cut shown in the top view 185, and Figure 3B Second sectional view 375 along Figure 1C The BB line is shown in the top view 185.

[0079] Lateral etching is performed in recesses within the etch stop layer 104, with a recess depth (X-direction) ranging from 5 to 7 nm. The recesses are then filled with placeholder sidewall spacers 126. The placeholder sidewall spacers 126 can be formed from nitride-based materials, such as SiN, SiCN, etc. The material used for the placeholder sidewall spacers 126 can be formed using a spacer pinch-off process.

[0080] Figure 4A and Figure 4B The diagrams show the formation of the placeholder 128 in the placeholder cavity trench 201, the removal of the protective liner 124, and the formation of the silicon layer 130 and the source / drain region 132, respectively. Figure 3A and Figure 3B The first sectional view 400 and the second sectional view 475 of the structure. Figure 4A First sectional view 400 along Figure 1C The AA line is shown in the top view 185. Figure 4B Second sectional view 475 along Figure 1C The BB line is shown in the top view 185.

[0081] The placeholder 128 can be formed by depositing a placeholder material (such as SiGe) in the placeholder cavity trench 201. The placeholder material can be planarized (e.g., using chemical mechanical planarization (CMP) or other suitable processes) such that the placeholder 128 has a top surface that is lower than the top surface of the BDI layer and equal to or higher than the top surface of the substrate 106. A silicon layer 130 is then epitaxially grown. The height (Z direction) of the silicon layer 130 can be in the range of 3-5 nm. The protective liner 124 is then removed (e.g., using a suitable etching process), and the source / drain regions 132 are subsequently formed.

[0082] The source / drain region 132 can be formed using an epitaxial growth process. The source / drain region 132 can be appropriately doped, such as using ion implantation, gas-phase doping, plasma doping, plasma immersion ion implantation, cluster doping, infusion doping, liquid-phase doping, solid-phase doping, etc. The n-type dopant can be selected from phosphorus (P), arsenic (As), and antimony (Sb), and the p-type dopant can be selected from boron (B), boron fluoride (BF2), gallium (Ga), indium (In), and thallium (Tl). The source / drain region 132 can be formed using an epitaxial growth process. In some embodiments, the epitaxial process includes in-situ doping (incorporating a dopant into the epitaxial material during epitaxy). The epitaxial material can be grown from a gaseous or liquid precursor. Epitaxial materials can be grown using vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), rapid thermal chemical vapor deposition (RTCVD), metal-organic chemical vapor deposition (MOCVD), ultra-high vacuum chemical vapor deposition (UHVCVD), low-pressure chemical vapor deposition (LPCVD), finite-reaction process CVD (LRPCVD), or other suitable processes. Epitaxial silicon, silicon-germanium (SiGe), germanium (Ge), and / or carbon-doped silicon (Si:C) can be doped during deposition (in-situ doping), adding dopants depending on the type of transistor to be formed, such as n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium). The dopant concentration in the source / drain can range from 1 × 10⁻⁶. 19 cm -3 Up to 3×10 21 cm -3 Or preferably in 2×10 20 cm -3 Up to 3×10 21 cm -3 between.

[0083] Figure 5A and Figure 5B The diagrams illustrate the formation of the gate stack 134, the interlayer dielectric (ILD) layer 136, the middle-end (MOL) contact 138, the back-end (BEOL) interconnect structure 140, and the bonding to the carrier wafer 142, respectively, using the replacement metal gate (RMG) process. Figure 4A and Figure 4B The first sectional view 500 and the second sectional view 575 of the structure. Figure 5A First sectional view 500 along Figure 1C The AA line is shown in the top view 185. Figure 5B Second sectional view 575 along Figure 1C The BB line is shown in the top view 185.

[0084] The RMG process includes removing the hard mask layer 118, the dummy gate layer 116, and the sacrificial layer 108, followed by forming a gate stack 134. The gate stack 134 may include a gate dielectric and a gate conductor. The gate dielectric may be conformally deposited in the structure and may include a high-k material. Examples of high-k materials include, but are not limited to, metal oxides such as hafnium oxide (HfO2), hafnium silicon oxide (Hf-Si-O), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La2O3), lanthanum aluminate (LaAlO3), zirconium oxide (ZrO2), zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanate, barium titanate, strontium titanate, yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium tantalate, and lead zinc niobate. High-k materials may also include dopants such as lanthanum (La), aluminum (Al), and magnesium (Mg). The uniform thickness of the gate dielectric can range from 1 nm to 3 nm. The gate conductor may include a gate work function metal (WFM) layer and a gate metal layer. The gate WFM layer may be formed from WFM, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), titanium aluminum aluminum (TiAl), titanium aluminum carbon (TiAlC), combinations of Ti and Al alloys, including a barrier layer (e.g., TiN, TaN, etc.) followed by a stack of one or more of the above WFM materials, etc. The uniform thickness of the gate WFM layer can range from 1 to 10 nm. The gate metal layer may include a conductive metal (e.g., tungsten (W)).

[0085] The ILD layer 136 can be formed from any suitable insulating material, such as SiO2, SiOC, SiON, etc. The thickness (Z direction) of the ILD layer 136 can be in the range of 150-250 nm.

[0086] MOL contact 138 is formed by patterning a mask layer over ILD layer 136, etching ILD layer 136 to form contact trenches, and filling the contact trenches with contact materials (e.g., silicide liner, such as titanium (Ti), nickel (Ni), nickel-platinum alloy (NiPt), metal adhesion layer, such as titanium nitride (TiN), and low-resistivity metal filler, such as tungsten (W), cobalt (Co) or ruthenium (Ru)).

[0087] Then, a BEOL interconnect structure 140 is formed over the ILD layer 136 and the MOL contact 138. The BEOL interconnect structure 140 may include one or more vias and metallization layers or levels for forming the desired set of interconnect structures within the structure.

[0088] The structure is then bonded to a carrier wafer 142, which may be formed of Si or another material similar to the material used for substrates 102 and 106.

[0089] Figure 6A and Figure 6B The images show the wafer flipping and substrate 102 removal, respectively. Figure 5A and Figure 5B The first sectional view 600 and the second sectional view 675 of the structure. Figure 6A First sectional view 600 along Figure 1C The AA line is shown in the top view 185. Figure 6B Second sectional view 675 along Figure 1C The BB line is shown in the top view 185.

[0090] Using the flip structure of carrier wafer 142, an etching process (e.g., RIE) is subsequently performed to remove substrate 102. The etching process stops at etch stop layer 104. The etching process selectively removes material (e.g., Si) from substrate 102 relative to the material (e.g., SiGe) of etch stop layer 104 and placeholder 128.

[0091] Figure 7A and Figure 7B The images show the process after the removal of the etch stop layer 104. Figure 6A and Figure 6B The first sectional view 700 and the second sectional view 775 of the structure. Figure 7A First sectional view 700 along Figure 1C The AA line is shown in the top view 185. Figure 7B Second sectional view 775 along Figure 1C The BB line is shown in the top view 185.

[0092] The etch stop layer 104 can be removed using a directional etching process (e.g., directional SiGe etching). This etching process will remove the etch stop layer 104, as well as a portion of the material of the placeholder 128 as shown.

[0093] Figure 8A and Figure 8B The following are shown after the substrate 106 is removed: Figure 7A and Figure 7B The first sectional view 800 and the second sectional view 875 of the structure. Figure 8A First sectional view 800 along Figure 1C The AA line is shown in the top view 185. Figure 8B Second sectional view 875 along Figure 1C The BB line is shown in the top view 185.

[0094] The substrate 106 can be removed using an etching process that selectively removes material (e.g., Si) from the substrate 106 relative to the material of the berth 128. However, it should be noted that this etching process may result in damage or removal of some material from the berth 128 (e.g., as shown in the recess 801). Advantageously, the berth sidewall spacers 126 prevent damage to the tip of the berth 128 (e.g., such that the tip of the berth 128 surrounded by the berth sidewall spacers 126 is wider than the portion of the berth 128 between the BDI layer and the berth sidewall spacers 126). The depth (X direction) of the recess 801 in the berth 128 can be in the range of 2-3 nm, mainly due to over-etching.

[0095] Figure 9A and Figure 9B The diagrams show the formation of the dorsal ILD layer 144 after its formation. Figure 8A and Figure 8B First sectional view 900 and second sectional view 975 of the structure. Figure 9A First sectional view 900 along Figure 1C The AA line is shown in the top view 185. Figure 9B Second sectional view 975 along Figure 1C The BB line is shown in the top view 185.

[0096] The back-side ILD layer 144 is filled and planarized (e.g., using CMP). The back-side ILD layer 144 can be filled using a conformal oxide, followed by chemical vapor deposition (CVD) or another suitable deposition process. The back-side ILD layer 144 can be formed from a material similar to that of ILD layer 136, and its height (Z direction) can be in the range of 150-300 nm.

[0097] Figure 10A and Figure 10B The diagrams show the formation and patterning of the organic planarization layer (OPL) 146, and the etching of the back-side ILD layer 144 to form the back-side contact trench 1001. Figure 9A and Figure 9B The first sectional view 1000 and the second sectional view 1075 of the structure. Figure 10A First sectional view 1000 along Figure 1C The AA line is shown in the top view 185. Figure 10B Second sectional view 1075 along Figure 1C The BB line is shown in the top view 185.

[0098] OPL 146 is formed and patterned, leaving openings at locations where the back contact trench 1001 will be formed. The back ILD layer 144 is then etched (e.g., using RIE) to form the back contact trench 1001. Advantageously, the placeholder sidewall spacers 126 can be used as a back contact etch stop layer.

[0099] Figure 11A and Figure 11B The images show the results after the removal of OPL 146 and the exposed occupant 128, respectively. Figure 10A and Figure 10B The first sectional view 1100 and the second sectional view 1175 of the structure. Figure 11A First sectional view 1100 along Figure 1C The AA line is shown in the top view 185. Figure 11B Second sectional view 1175 along Figure 1C The BB line is shown in the top view 185.

[0100] OPL 146 and the exposed placeholder 128 can be removed using any suitable etching process, while retaining the placeholder sidewall spacers 126. The exposed placeholder 128 is removed to expose the silicon layer 130 beneath one of the source / drain regions 132.

[0101] Figure 12A and Figure 12B The diagram shows the process after the optional removal of the exposed silicon layer 130, and the formation of the back-side contact 148 and the back-side power supply network (BSPDN) 150. Figure 11A and Figure 11B The first sectional view 1200 and the second sectional view 1275 of the structure. Figure 12A First sectional view 1200 along Figure 1C The AA line is shown in the top view 185. Figure 12B Second sectional view 1275 along Figure 1C The BB line is shown in the top view 185.

[0102] Optionally, the exposed silicon layer 130 can be removed, but this is not required. Back-side contact metallization is then performed on the back-side contact 148 (e.g., filling the back-side contact trench 1001 with a contact material similar to that used for the MOL contact 138). The BSPDN 150 is then formed. The back-side contact 148 has a first width 1201 "above" the upper surface of the occupant sidewall spacer 126, a second width 1203 between the upper and lower surfaces of the occupant sidewall spacer 126, and a third width 1205 below the lower surface of the occupant sidewall spacer 126. The first width 1201 is greater than the second width 1203 and less than the third width 1205.

[0103] Figure 12A The structure shown in Figure 12D has a first side (e.g., front side) and a second side (e.g., back side) opposite the first side. BEOL interconnect structure 140 is located on the first side or front side of the structure, and BSPDN 150 is located on the second side or back side of the structure. The front or back surface of different layers or other components of the structure mentioned refers to the surface closest to the front or back side of the structure.

[0104] The methods and techniques described above for forming semiconductor devices can be used in various applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing embodiments of the present invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., mobile phones and smartphones), solid-state storage devices, functional circuits, etc. Systems and hardware comprising semiconductor devices are contemplated embodiments of the present invention. Based on the teachings provided herein, those skilled in the art can conceive of other implementations and applications of embodiments of the present invention.

[0105] In some embodiments, the above-described technologies may be used in conjunction with semiconductor devices that may require or otherwise utilize, such as complementary metal-oxide-semiconductor (CMOS) transistors, metal-oxide-semiconductor field-effect transistors (MOSFETs), and / or FinFETs. As a non-limiting example, the semiconductor device may include, but is not limited to, CMOS, MOSFET, and FinFET devices, and / or semiconductor devices using CMOS, MOSFET, and / or FinFET technologies.

[0106] The aforementioned structures can be implemented in integrated circuits. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), bare die form, or in package form. In the latter case, the chip is mounted in a single-chip package (e.g., a plastic carrier with leads attached to a motherboard or other more advanced carrier) or a multi-chip package (e.g., a ceramic carrier with one or both of surface-mount or embedded interconnect structures). In either case, the chip is subsequently integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either: (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be a product with any integrated integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and a central processing unit. Figure 13 An example integrated circuit 1300 is shown, which includes one or more semiconductor structures 1310 having contacts with sidewall spacers.

[0107] In some embodiments, the semiconductor structure includes a transistor on a first side of the semiconductor structure, a contact to the transistor on a second side of the semiconductor structure, and a sidewall spacer surrounding a portion of the sidewall of the contact. The contact has a first width above the sidewall spacer and a second width below the sidewall spacer, the second width being different from the first width.

[0108] The second width can be greater than the first width.

[0109] The contact element may have a third width between the upper and lower surfaces of the sidewall spacer, and this third width is different from both the first and second widths. The first width may be greater than the third width, and the second width may be greater than the first width.

[0110] Contacts can be connected to the source / drain regions of the transistor. The semiconductor structure may also include a placeholder on a second side of the semiconductor structure, directly below another source / drain region of the transistor, and additional sidewall spacers surrounding a portion of the sidewalls of the placeholder. The placeholder may have a third width above the upper surface of the additional sidewall spacer and a fourth width below the upper surface of the additional sidewall spacer, the third width being different from the fourth width. The fourth width may be greater than the third width.

[0111] The semiconductor structure may also include an ILD layer disposed between the upper surface of the sidewall spacer and the transistor BDI layer.

[0112] In some embodiments, the semiconductor structure includes a transistor on a first side of the semiconductor structure, a placeholder self-aligned with the source / drain regions of the transistor on a second side of the semiconductor structure, and a sidewall spacer surrounding a portion of the sidewall of the placeholder. The placeholder has a first width above the upper surface of the sidewall spacer and a second width below the upper surface of the sidewall spacer, the second width being different from the first width.

[0113] The second width can be greater than the first width.

[0114] The semiconductor structure may further include a contact at a second side of the semiconductor structure leading to another source / drain region of the transistor, and an additional sidewall spacer surrounding a portion of the sidewall of the contact, wherein the contact has a third width above the additional sidewall spacer and a fourth width below the additional sidewall spacer, the third width being different from the fourth width. The fourth width may be greater than the third width.

[0115] In some embodiments, the semiconductor structure includes a transistor disposed on a first side of the semiconductor structure, a placeholder self-aligned with a first source / drain region of the transistor on a second side of the semiconductor structure, a contact on the second side of the semiconductor structure leading to a second source / drain region of the transistor, and a sidewall spacer surrounding a portion of the sidewall of the contact and the placeholder. A first portion of the placeholder above the upper surface of the sidewall spacer has a different width than a second portion of the placeholder below the upper surface of the sidewall spacer. A first portion of the contact above the upper surface of the sidewall spacer has a different width than a second portion of the contact below the lower surface of the sidewall spacer.

[0116] The width of the first portion of the occupant above the upper surface of the sidewall spacer is smaller than the width of the second portion of the occupant below the upper surface of the sidewall spacer.

[0117] The width of the first portion of the contact above the upper surface of the sidewall spacer is smaller than the width of the second portion of the contact below the lower surface of the sidewall spacer. The third portion of the contact between the upper and lower surfaces of the sidewall spacer has a different width from the first portion of the contact above the upper surface of the sidewall spacer and the second portion of the contact below the lower surface of the sidewall spacer.

[0118] The upper surface of the sidewall spacer can be separated from the BDI of the transistor by an ILD layer.

[0119] In some embodiments, the transistor structure includes a first source / drain region, a second source / drain region, a placeholder self-aligned to the back side of the first source / drain region, a contact to the back side of the second source / drain region, and a sidewall spacer surrounding a portion of the sidewall of the contact and the placeholder. The width of a first portion of the placeholder above the upper surface of the sidewall spacer differs from the width of a second portion of the placeholder below the upper surface of the sidewall spacer. The first portion of the contact above the upper surface of the sidewall spacer has a different width from the second portion of the contact below the lower surface of the sidewall spacer.

[0120] The width of the first portion of the occupant above the upper surface of the sidewall spacer may be smaller than the width of the second portion of the occupant below the upper surface of the sidewall spacer.

[0121] The width of the first portion of the contact above the upper surface of the sidewall spacer may be smaller than the width of the second portion of the contact below the lower surface of the sidewall spacer.

[0122] The upper surface of the sidewall spacer can be separated from the BDI layer of the transistor structure by an ILD layer.

[0123] In some embodiments, the integrated circuit includes a semiconductor structure including a transistor at a first side of the semiconductor structure, a contact to the transistor at a second side of the semiconductor structure, and a sidewall spacer surrounding a portion of the sidewall of the contact. The contact has a first width above the sidewall spacer and a second width below the sidewall spacer, the second width being different from the first width.

[0124] The second width can be greater than the first width.

[0125] The contacts can be connected to the source / drain regions of the transistor. The semiconductor structure may also include a berth at a second side of the semiconductor structure, directly below another source / drain region of the transistor, and an additional sidewall spacer surrounding a portion of the sidewall of the berth, wherein the berth has a third width above the upper surface of the additional sidewall spacer and a fourth width below the upper surface of the additional sidewall spacer, the third width being different from the fourth width.

[0126] It should be understood that the various layers, structures, and regions shown in the accompanying drawings are schematic illustrations and not drawn to scale. Furthermore, for ease of explanation, one or more types of layers, structures, and regions commonly used to form semiconductor devices or structures may not be explicitly shown in a given drawing. This does not mean that any unshown layers, structures, and regions are omitted from the actual semiconductor structure. Moreover, it should be understood that the embodiments described herein are not limited to the specific materials, features, and process steps shown and described. In particular, regarding semiconductor process steps, it is important to emphasize that the description provided herein is not intended to cover all process steps that may be necessary to form functional semiconductor integrated circuit devices. Instead, for the sake of brevity, certain process steps commonly used in forming semiconductor devices, such as wet cleaning and annealing steps, have been intentionally omitted.

[0127] Furthermore, the same or similar reference numerals are used throughout the accompanying drawings to denote the same or similar features, elements, or structures; therefore, the same or similar features, elements, or structures will not be described in detail for each drawing. It should be understood that the terms "approximately" or "substantially" used herein with respect to thickness, width, percentage, range, temperature, time, and other process parameters mean close to or approximately, but not exactly the same. For example, the terms "approximately" or "substantially" as used herein indicate a small margin of error, such as ±5%, preferably less than 2% or 1% or less than the stated value.

[0128] In the above description, various materials, dimensions, and process parameters for different components are provided. Unless otherwise stated, such materials are given by way of example only, and embodiments are not limited to the specific examples. Similarly, unless otherwise stated, all dimensions and process parameters are given by way of example only, and embodiments are not limited to specific dimensions or ranges.

[0129] This document has presented descriptions of various embodiments of the invention for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is intended to best explain the principles, practical application, or technical improvements to existing technologies in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure, comprising: A transistor, the transistor being located on a first side of the semiconductor structure; Contacts to the transistor, the contacts being located on the second side of the semiconductor structure; as well as Sidewall spacers surrounding a portion of the sidewall of the contact element; The contact member has a first width above the sidewall spacer and a second width below the sidewall spacer, the second width being different from the first width.

2. The semiconductor structure according to claim 1, wherein the second width is greater than the first width.

3. The semiconductor structure of claim 1, wherein the contact has a third width between the upper and lower surfaces of the sidewall spacer, the third width being different from the first width and the second width.

4. The semiconductor structure of claim 3, wherein the first width is greater than the third width, and wherein the second width is greater than the first width.

5. The semiconductor structure of claim 1, wherein the contact is connected to the source / drain region of the transistor.

6. The semiconductor structure according to claim 5, further comprising: The placeholder located on the second side of the semiconductor structure, directly below the other source / drain region of the transistor; as well as Additional sidewall spacers surrounding a portion of the sidewall of the occupant; The placeholder has a third width above the upper surface of the additional sidewall spacer and a fourth width below the upper surface of the additional sidewall spacer, the third width being different from the fourth width.

7. The semiconductor structure according to claim 6, wherein the fourth width is greater than the third width.

8. The semiconductor structure of claim 6, wherein the additional sidewall spacers surrounding a portion of the sidewall of the occupant are perpendicularly aligned with the sidewall spacers surrounding a portion of the sidewall of the contact.

9. A semiconductor structure, comprising: A transistor, the transistor being located on a first side of the semiconductor structure; A placeholder that is self-aligned with the source / drain region of the transistor at a second side of the semiconductor structure; as well as Sidewall spacers surrounding a portion of the sidewall of the occupant; The occupant has a first width above the upper surface of the sidewall spacer and a second width below the upper surface of the sidewall spacer, the second width being different from the first width.

10. The semiconductor structure of claim 9, wherein the second width is greater than the first width.

11. The semiconductor structure according to claim 9, further comprising: A contact at the second side of the semiconductor structure, leading to the other source / drain region of the transistor; as well as Additional sidewall spacers surrounding a portion of the sidewall of the contact element; The contact member has a third width above the additional sidewall spacer and a fourth width below the additional sidewall spacer, the third width being different from the fourth width.

12. The semiconductor structure of claim 11, wherein the fourth width is greater than the third width.

13. A semiconductor structure comprising: A transistor, the transistor being disposed on a first side of the semiconductor structure; A placeholder located on a second side of the semiconductor structure, the placeholder being self-aligned with a first source / drain region of the transistor; A contact at the second side of the semiconductor structure, leading to the second source / drain region of the transistor; as well as Sidewall spacers surrounding a portion of the sidewalls of the contact and the occupant; The first portion of the occupant above the upper surface of the sidewall spacer has a different width than the second portion of the occupant below the upper surface of the sidewall spacer. and The first portion of the contact above the upper surface of the sidewall spacer has a different width than the second portion of the contact below the lower surface of the sidewall spacer.

14. The semiconductor structure of claim 13, wherein the width of the first portion of the occupant above the upper surface of the sidewall spacer is smaller than the width of the second portion of the occupant below the upper surface of the sidewall spacer.

15. The semiconductor structure of claim 13, wherein the width of the first portion of the contact above the upper surface of the sidewall spacer is less than the width of the second portion of the contact below the lower surface of the sidewall spacer.

16. The semiconductor structure of claim 15, wherein the third portion of the contact between the upper and lower surfaces of the sidewall spacer has a different width from the first portion of the contact above the upper surface of the sidewall spacer and the second portion of the contact below the lower surface of the sidewall spacer.

17. The semiconductor structure of claim 13, wherein the upper surface of the sidewall spacer is separated from the bottom dielectric insulating layer of the transistor by an interlayer dielectric layer.

18. A transistor structure, comprising: First source / drain region; Second source / drain region; A placeholder, wherein the placeholder is self-aligned with the back side of the first source / drain region; Contact element, the contact element being connected to the back side of the second source / drain region; as well as Sidewall spacers surrounding a portion of the sidewalls of the contact and the occupant; The width of the first portion of the occupant above the upper surface of the sidewall spacer is different from the width of the second portion of the occupant below the upper surface of the sidewall spacer. and The first portion of the contact above the upper surface of the sidewall spacer has a different width than the second portion of the contact below the lower surface of the sidewall spacer.

19. The transistor structure of claim 18, wherein the width of the first portion of the occupant above the upper surface of the sidewall spacer is smaller than the width of the second portion of the occupant below the upper surface of the sidewall spacer.

20. The transistor structure of claim 18, wherein the width of the first portion of the contact above the upper surface of the sidewall spacer is less than the width of the second portion of the contact below the lower surface of the sidewall spacer.

21. The transistor structure of claim 18, wherein the upper surface of the sidewall spacer is separated from the bottom dielectric insulating layer of the transistor structure by an interlayer dielectric layer.

22. An integrated circuit, comprising: Semiconductor structure, the semiconductor structure comprising: A transistor, the transistor being located on a first side of the semiconductor structure; Contacts to the transistor, the contacts being located on the second side of the semiconductor structure; and Sidewall spacers surrounding a portion of the sidewall of the contact element; The contact member has a first width above the sidewall spacer and a second width below the sidewall spacer, the second width being different from the first width.

23. The integrated circuit of claim 22, wherein the second width is greater than the first width.

24. The integrated circuit of claim 22, wherein the contact is connected to the source / drain region of the transistor.

25. The integrated circuit of claim 24, wherein the semiconductor structure further comprises a placeholder at the second side of the semiconductor structure, directly below another source / drain region of the transistor, and additional sidewall spacers surrounding a portion of the sidewall of the placeholder, and wherein, The occupant has a third width above the upper surface of the additional sidewall spacer and a fourth width below the upper surface of the additional sidewall spacer, the third width being different from the fourth width.

Images