Semiconductor device, semiconductor package, and method of manufacturing semiconductor device

Abstract

A semiconductor device includes a semiconductor substrate. A modified portion is formed inside the semiconductor substrate. The modified portion indicates information about a manufacturing process of the semiconductor device.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, semiconductor packages, and methods for manufacturing semiconductor devices. Background Technology

[0002] For example, Japanese Patent No. 7355970 (Patent Document 1) describes a semiconductor device. The semiconductor device described in Patent Document 1 has a semiconductor substrate. In the semiconductor device described in Patent Document 1, for example, a mark is made on the main surface of the semiconductor substrate. The mark is formed by irradiating the main surface of the semiconductor substrate with a laser.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent No. 7355970. Summary of the Invention

[0006] In the case of marking a semiconductor substrate by irradiating the main surface with a laser, as described in Patent Document 1, the surface roughness of the main surface of the semiconductor substrate increases at the marked location. As a result, this can lead to the generation of particles, for example, during the manufacturing process following the marking.

[0007] The semiconductor device disclosed herein includes a semiconductor substrate. Modification portions are formed within the semiconductor substrate. These modification portions indicate information relating to the manufacturing process of the semiconductor device. Attached Figure Description

[0008] Figure 1 This is a top view of semiconductor device 100.

[0009] Figure 2 This is a top view of the semiconductor device 100 before it is monolithically assembled.

[0010] Figure 3 yes Figure 1 Sectional view at point III-III.

[0011] Figure 4 This is an enlarged top view showing the first example of how the modified part 14 is formed.

[0012] Figure 5 This is an enlarged top view showing a second example of how the modified part 14 is formed.

[0013] Figure 6 This is an enlarged top view showing a third example of how the modified part 14 is formed.

[0014] Figure 7 This is an enlarged top view showing the fourth example of how the modified part 14 is formed.

[0015] Figure 8A This is a cross-sectional view of semiconductor package 200.

[0016] Figure 8B This is a top view of semiconductor package 200.

[0017] Figure 9 This is a manufacturing process diagram of semiconductor device 100.

[0018] Figure 10 This is a cross-sectional view illustrating the component isolation film formation process S2.

[0019] Figure 11 This is a cross-sectional view illustrating the first ion implantation process S3.

[0020] Figure 12 This is a cross-sectional view illustrating the gate insulating film formation process S4.

[0021] Figure 13 This is a cross-sectional view illustrating the gate electrode formation process S5.

[0022] Figure 14 This is a cross-sectional view illustrating the second ion implantation process S6.

[0023] Figure 15 This is a cross-sectional view illustrating the process S7 of forming the sidewall spacer.

[0024] Figure 16 This is a cross-sectional view illustrating the third ion implantation process S8.

[0025] Figure 17 This is a cross-sectional view illustrating the first interlayer insulating film formation process S9.

[0026] Figure 18 This is a cross-sectional view illustrating the contact plug forming process S10.

[0027] Figure 19 This is a cross-sectional view illustrating the first wiring formation process S11.

[0028] Figure 20 This is a cross-sectional view illustrating the second interlayer insulating film formation process S12.

[0029] Figure 21 This is a cross-sectional view illustrating the through-hole plug forming process S13.

[0030] Figure 22 This is a cross-sectional view illustrating the second wiring formation process S14.

[0031] Figure 23 This is a cross-sectional view illustrating the protective film formation process S15.

[0032] Figure 24 This is a cross-sectional view showing the first example of the marking process S17.

[0033] Figure 25 This is a cross-sectional view showing a second example of the marking process S17.

[0034] Figure 26 This is an enlarged top view showing a first example of how the modified portion 14 in the semiconductor device 100A is formed.

[0035] Figure 27 yes Figure 26 A schematic cross-sectional view of sections XXVII-XXVII.

[0036] Figure 28 This is an enlarged top view showing a second example of how the modified portion 14 in the semiconductor device 100A is formed.

[0037] Figure 29 This is an enlarged top view showing a third example of how the modified portion 14 in the semiconductor device 100A is formed.

[0038] Figure 30 yes Figure 29 A schematic top view of section XXX-XXX.

[0039] Figure 31 This is a top view showing a first example of a semiconductor package 200A.

[0040] Figure 32 yes Figure 31 A schematic cross-sectional view of XXXII-XXXII in the diagram.

[0041] Figure 33 This is a top view showing a second example of a semiconductor package 200A.

[0042] Figure 34 yes Figure 33 A schematic cross-sectional view of XXXIV-XXXIV.

[0043] Figure 35 This is a top view showing a third example of a semiconductor package 200A.

[0044] Figure 36 yes Figure 35 A schematic cross-sectional view of XXXVI-XXXVI.

[0045] Figure 37 This is a cross-sectional view of semiconductor device 100B. Detailed Implementation

[0046] The semiconductor device according to the embodiments of this disclosure will be described. In the following drawings, the same or equivalent parts are labeled with the same reference numerals, and the description will not be repeated.

[0047] (First Implementation)

[0048] The semiconductor device of the first embodiment will be described. The semiconductor device of the first embodiment is designated as semiconductor device 100.

[0049] <Structure of Semiconductor Device 100>

[0050] The structure of the semiconductor device 100 will be described below.

[0051] Figure 1 This is a top view of semiconductor device 100. Figure 2 This is a top view of the semiconductor device 100 before it is monolithically assembled. Figure 3 yes Figure 1 The sectional view at point III-III. (See image.) Figures 1 to 3 As shown, the semiconductor device 100 includes a semiconductor substrate 10, a gate insulating film 20, a gate electrode 30, a sidewall spacer 40, an interlayer insulating film 50, wiring 60, a contact plug 61 and a through-hole plug 62, and a protective film 70.

[0052] The semiconductor substrate 10 has a main surface 10a and a main surface 10b. The main surface 10b is the opposite surface of the main surface 10a. The main surfaces 10a and 10b are end faces in the thickness direction of the semiconductor substrate 10. The semiconductor substrate 10 is made of, for example, single-crystal silicon. However, the material of the semiconductor substrate 10 is not limited to this. For example, the material of the semiconductor substrate 10 may be silicon carbide or gallium nitride.

[0053] The term "top view" refers to the view taken along the normal direction of the main surface 10a. The semiconductor substrate 10, when viewed from above, has a device region 11 and a marking region 12. Device region 11 is the region where circuit elements such as transistors are formed. Marking region 12 is the region that holds information about the manufacturing process of the semiconductor device 100. Device region 11 and marking region 12 are located inside the outer periphery of the semiconductor substrate 10 when viewed from above. More specifically, device region 11 and marking region 12 are located inside the scribe line (not shown) of the semiconductor wafer. The semiconductor wafer is monolithically divided into multiple semiconductor devices 100 by being cut along the boundary region of two adjacent semiconductor devices 100; this boundary region is called the scribe line.

[0054] In device region 11, semiconductor substrate 10 has a source region 11a, a drain region 11b, and a well region 11c. The source region 11a is formed on main surface 10a. The drain region 11b is formed on main surface 10a at a distance from the source region 11a. The well region 11c is formed on main surface 10a such that it surrounds the source region 11a and the drain region 11b when viewed in cross-section along the normal direction of main surface 10a.

[0055] The conductivity types of the source region 11a and the drain region 11b are opposite to those of the well region 11c. For example, if the conductivity types of the source region 11a and the drain region 11b are n-type, then the conductivity type of the well region 11c is p-type. Sometimes, the portion of the well region 11c located between the source region 11a and the drain region 11b is referred to as the channel region.

[0056] The source region 11a has a first region 11aa and a second region 11ab. The drain region 11b has a first region 11ba and a second region 11bb. The first region 11aa is closer to the drain region 11b than the second region 11ab, and the first region 11ba is closer to the source region 11a than the second region 11bb. The doping concentration in the first region 11aa is lower than the doping concentration in the second region 11ab, and the doping concentration in the first region 11ba is lower than the doping concentration in the second region 11bb. That is, the source region 11a and the drain region 11b have an LDD (Lightly Doped Diffusion) structure.

[0057] A device isolation film 13 is formed on the main surface 10a. The device isolation film 13 surrounds the well region 11c when viewed from above. The component material of the device isolation film 13 is, for example, silicon oxide. The device isolation film 13 is, for example, embedded in a trench formed on the main surface 10a. That is, the device isolation film 13 is STI (Shallow Trench Isolation). The device isolation film 13 can also be LOCOS (Local Oxidation Of Silicon).

[0058] A gate insulating film 20 is disposed on the main surface 10a in device region 11. More specifically, the gate insulating film 20 is disposed on the channel region. The material constituting the gate insulating film 20 is, for example, silicon oxide. A gate electrode 30 is disposed on the gate insulating film 20. That is, the gate electrode 30 is disposed opposite to the channel region through the gate insulating film 20. The material constituting the gate electrode 30 is, for example, polysilicon containing dopants. The source region 11a, drain region 11b, well region 11c, gate insulating film 20, and gate electrode 30 constitute a transistor, and two adjacent transistors are separated by a device isolation film 13.

[0059] Sidewall spacers 40 are disposed on the main surface 10a in device region 11. More specifically, sidewall spacers 40 are disposed on first region 11aa and first region 11ba in such a way that they contact the side of the gate electrode 30. The sidewall spacers 40 are made of, for example, silicon oxide.

[0060] The bottommost interlayer insulating film 50 is disposed on the main surface 10a in such a way that it covers the element isolation film 13, the gate electrode 30, and the sidewall spacers 40. Wiring 60 is disposed on the interlayer insulating film 50. The bottommost wiring 60 is electrically connected to the source region 11a (first region 11aa) and the drain region 11b (second region 11bb) via contact plugs 61. Additionally, although not shown, the bottommost wiring 60 is also electrically connected to the gate electrode 30 via contact plugs 61. The contact plugs 61 are embedded in contact holes formed in the bottommost interlayer insulating film 50.

[0061] The upper interlayer insulating film 50 is disposed on the lower interlayer insulating film 50 in such a way that it covers the wiring 60 disposed on the lower interlayer insulating film 50. The wiring 60 of adjacent layers are electrically connected through through-hole plugs 62. The through-hole plugs 62 are embedded in through-holes formed in the interlayer insulating film 50 other than the lowermost layer. The protective film 70 is disposed on the uppermost interlayer insulating film 50 in such a way that it covers the wiring 60 of the uppermost layer.

[0062] The interlayer insulating film 50 is made of, for example, silicon oxide. The wiring 60 is made of, for example, aluminum or an aluminum alloy. The contact plug 61 and the through-hole plug 62 are made of, for example, tungsten. The protective film 70 is made of, for example, silicon nitride.

[0063] In the marking area 12, a modification section 14 is formed inside the semiconductor substrate 10. The modification section 14 is a portion of the semiconductor substrate 10 into which defects (dislocations, etc.) are introduced. The modification section 14 indicates information about the manufacturing process of the semiconductor device 100. The information about the manufacturing process of the semiconductor device 100 may include, for example, at least one of the following: the results of inspections during the manufacturing of the semiconductor device 100; the batch number of the semiconductor wafer required to obtain the semiconductor device 100; and the position of the semiconductor device 100 on the semiconductor wafer. However, the information about the manufacturing process of the semiconductor device 100 is not limited to these. The modification section 14 may or may not introduce cracks. The information about the manufacturing process of the semiconductor device 100 may also include, for example, a company code or a product code. To ensure the traceability of each semiconductor device 100, the information about the manufacturing process of the semiconductor device 100 may also differ for each semiconductor device 100. To ensure the traceability of the cause of defects in the manufacturing process, the information about the manufacturing process of the semiconductor device 100 may also include the ID of the manufacturing apparatus used in the manufacturing process of the semiconductor device 100.

[0064] The wiring 60 is arranged in a manner that does not overlap with the marking area 12 when viewed from above. In the portion of the main surface 10a that overlaps with the modified portion 14 when viewed from above, the arithmetic mean roughness (Ra) is 1 nm or less. In other words, the arithmetic mean roughness of the portion of the main surface 10a that overlaps with the modified portion 14 when viewed from above is the same as the arithmetic mean roughness of the portion of the main surface 10a that does not overlap with the modified portion 14 when viewed from above.

[0065] Figure 4 This is an enlarged top view showing the first example of how the modified part 14 is formed. (See attached image.) Figure 4 As shown, the marked region 12 can also be divided into multiple regions 12a arranged in a matrix (in Figure 4 (Represented by dashed lines). Information about the manufacturing process of the semiconductor device 100 is indicated by whether a modified portion 14 is formed in each of the plurality of regions 12a. The marking region 12 may also have multiple columns of regions 12a. Columns in one region 12a and columns in another region 12a represent different information about the manufacturing process of the semiconductor device 100.

[0066] by Figure 4 For example, the column in the leftmost region 12a (the first column) represents the batch number of the semiconductor wafer, the column in the region 12a adjacent to the right of the first column (the second column) represents the position of the semiconductor device 100 on the semiconductor wafer, and the column in the region 12a adjacent to the right of the second column (the third column) represents the inspection results of the semiconductor device 100 during manufacturing.

[0067] Figure 5 This is an enlarged top view showing a second example of how the modified part 14 is formed. (See attached image.) Figure 5 As shown, in the second example, information about the manufacturing process of the semiconductor device 100 is also indicated by whether or not a modified portion 14 is formed in each of the multiple regions 12a, but the two-dimensional arrangement of the modified portions 14 in top view constitutes a QR code (registered trademark).

[0068] Figure 6 This is an enlarged top view showing a third example of how the modified part 14 is formed. In the third example, as... Figure 6 As shown, the modified portions 14 extend along a first direction DR1 when viewed from above, and are arranged along a second direction DR2 when viewed from above. The second direction DR2 is a direction perpendicular to the first direction DR1 when viewed from above. In a third example, information about the manufacturing process of the semiconductor device 100 is represented by the spacing between two adjacent modified portions 14 in the second direction DR2. In other words, the arrangement of the modified portions 14 can also constitute a barcode.

[0069] Figure 7This is an enlarged top view showing a fourth example of how the modified part 14 is formed. (See attached image.) Figure 7 As shown, the modified parts 14 can also be arranged to form text or numbers. In the fourth example, the text or numbers are used to represent information about the manufacturing process of the semiconductor device 100.

[0070] <Composition of Semiconductor Package 200>

[0071] The configuration of the semiconductor package using the semiconductor device 100 will be described below. The semiconductor package using the semiconductor device 100 is designated as semiconductor package 200.

[0072] Figure 8A This is a cross-sectional view of semiconductor package 200. Figure 8B This is a top view of semiconductor package 200. (Example) Figure 8A and Figure 8B As shown, the semiconductor package 200 includes a semiconductor device 100, a substrate 210, and a sealing member 220. The substrate 210 is, for example, a printed circuit board (PCB). The semiconductor device 100 is disposed on and electrically connected to the substrate 210. The sealing member 220 seals the semiconductor device 100 on the substrate 210. More specifically, the sealing member 220 is, for example, a molding resin, disposed on the substrate 210 to cover the semiconductor device 100. The portion of the semiconductor package 200 that overlaps with the marking area 12 when viewed from above, such as the portion of the sealing member 220 that overlaps with the marking area 12 when viewed from above, is formed of a material that does not obstruct X-rays, infrared rays, terahertz waves, visible light, and other electromagnetic waves used for reading the markings formed on the marking area 12.

[0073] <Method for Manufacturing Semiconductor Device 100>

[0074] Figure 9 This is a manufacturing process diagram for semiconductor device 100. (For example...) Figure 9 As shown, the manufacturing method of semiconductor device 100 includes a preparation step S1, an element isolation film formation step S2, a first ion implantation step S3, a gate insulating film formation step S4, a gate electrode formation step S5, a second ion implantation step S6, a sidewall spacer formation step S7, a third ion implantation step S8, a first interlayer insulating film formation step S9, a contact plug formation step S10, a first wiring formation step S11, a second interlayer insulating film formation step S12, a through-hole plug formation step S13, a second wiring formation step S14, a protective film formation step S15, and a monolithization step S16.

[0075] In the preparation process S1, a semiconductor substrate 10 is prepared. Figure 10This is a cross-sectional view illustrating the component isolation film formation process S2. For example... Figure 10 As shown, in the device isolation film formation process S2, a device isolation film 13 is formed. In the device isolation film formation process S2, firstly, a hard mask is formed on the main surface 10a. The hard mask is formed, for example, by laminating a silicon oxide film and a silicon nitride film using a CVD (Chemical Vapor Deposition) method. Secondly, a photoresist pattern is formed on the hard mask. The photoresist pattern is formed by applying a photoresist and then exposing and developing the applied photoresist. Thirdly, the hard mask and the semiconductor substrate 10 are etched using the photoresist pattern as a mask, thereby forming trenches on the main surface 10a.

[0076] Fourth, for example, using CVD, a component isolation film 13 is embedded in the trench. Fifth, using CMP (Chemical Mechanical Polishing), the component isolation film 13 overflowing from the trench is removed. Additionally, after embedding the component isolation film 13 in the trench, the hard mask is removed.

[0077] Figure 11 This is a cross-sectional view illustrating the first ion implantation step S3. (For example...) Figure 11 As shown, in the first ion implantation process, a trap region 11c is formed by ion implantation. Figure 12 This is a cross-sectional view illustrating the gate insulating film formation process S4. (Example) Figure 12 As shown, in the gate insulating film formation process S4, for example, the gate insulating film 20 is formed on the main surface 10a by thermal oxidation.

[0078] Figure 13 This is a cross-sectional view illustrating the gate electrode formation process S5. (Example) Figure 13 As shown, in the gate electrode formation process S5, a gate electrode 30 is formed. In the gate electrode formation process S5, firstly, the gate electrode 30 is formed on the gate insulating film 20, for example, using a CVD method. Secondly, a resist pattern is formed on the gate electrode 30. The resist pattern is formed by applying a photoresist and then exposing and developing the applied photoresist. Thirdly, the gate electrode 30 is patterned by etching using the resist pattern as a mask.

[0079] Figure 14 This is a cross-sectional view illustrating the second ion implantation process S6. (For example...) Figure 14 As shown, in the second ion implantation step S6, ion implantation is performed to form the first region 11aa and the first region 11ba.

[0080] Figure 15 This is a sectional view illustrating process S7 of forming the sidewall spacer. (For example...) Figure 15As shown, in the sidewall spacer formation process S7, a sidewall spacer 40 is formed. In the sidewall spacer formation process S7, firstly, for example, a CVD method is used to form the sidewall spacer 40 on the main surface 10a in a manner that covers the element isolation film 13, the gate insulating film 20, and the gate electrode 30. Secondly, for example, the sidewall spacer 40 is removed except at the position adjacent to the gate electrode 30 by performing an etch-back process.

[0081] Figure 16 This is a cross-sectional view illustrating the third ion implantation process S8. (For example...) Figure 16 As shown, in the third ion implantation step S8, second regions 11ab and second regions 11bb are formed by ion implantation. Figure 17 This is a cross-sectional view illustrating the first interlayer insulating film formation process S9. (For example...) Figure 17 As shown, in the first interlayer insulating film formation step S9, the bottommost interlayer insulating film 50 is formed. In the first interlayer insulating film formation step S9, firstly, the interlayer insulating film 50 is formed on the main surface 10a in a manner that covers the element isolation film 13, the gate electrode 30, and the sidewall spacer 40. Secondly, for example, the upper surface of the interlayer insulating film 50 is planarized using a CMP method.

[0082] Figure 18 This is a cross-sectional view illustrating the contact plug forming process S10. For example... Figure 18 As shown, in the contact plug forming process S10, a contact plug 61 is formed. In the contact plug forming process S10, firstly, a resist pattern is formed on the lowest interlayer insulating film 50. The resist pattern is formed by applying photoresist and exposing and developing the applied photoresist. Secondly, the lowest interlayer insulating film 50 is etched using the resist pattern as a mask, thereby forming a contact hole.

[0083] Third, after forming a metal film on the second region 11ab exposed from the contact hole, the second region 11bb, the upper surface of the gate electrode 30, the inner wall surface of the contact hole, and the lowest interlayer insulating film 50, heat treatment is performed. As a result, the metal film reacts with the second region 11ab, the second region 11bb, and the gate electrode 30, undergoing silicide formation. After silicide formation, any unreacted metal film is removed. Fourth, for example, a contact plug 61 is embedded in the contact hole using CVD. Fifth, for example, the contact plug 61 overflowing from the contact hole is removed using CMP.

[0084] Figure 19 This is a cross-sectional view illustrating the first wiring formation process S11. For example... Figure 19As shown, in the first wiring formation step S11, the bottommost wiring 60 is formed. In the first wiring formation step S11, firstly, the bottommost wiring 60 is formed on the bottommost interlayer insulating film 50, for example, by sputtering. Secondly, a photoresist pattern is formed on the bottommost wiring 60. The photoresist pattern is formed by applying photoresist and exposing and developing the applied photoresist. Thirdly, the bottommost wiring 60 is etched using the photoresist pattern as a mask, thereby patterning the bottommost wiring 60.

[0085] Figure 20 This is a cross-sectional view illustrating the second interlayer insulating film formation process S12. (For example...) Figure 20 As shown, in the second interlayer insulating film forming process S12, another interlayer insulating film 50 is formed on the first interlayer insulating film 50 by means of the same method as in the first interlayer insulating film forming process S9, in a manner that covers the wiring 60 disposed on the first interlayer insulating film 50.

[0086] Figure 21 This is a cross-sectional view illustrating the through-hole plug forming process S13. For example... Figure 21 As shown, in the through-hole plug forming process S13, a through-hole plug 62 is formed. In the through-hole plug forming process S13, firstly, a resist pattern is formed on the interlayer insulating film 50 other than the bottom layer. The resist pattern is formed by applying photoresist and exposing and developing the applied photoresist. Secondly, the interlayer insulating film 50 other than the bottom layer is etched using the resist pattern as a mask, thereby forming a through-hole. Thirdly, the through-hole plug 62 is embedded in the through-hole, for example, by CVD. Fourthly, the through-hole plug 62 overflowing from the through-hole is removed, for example, by CMP.

[0087] Figure 22 This is a cross-sectional view illustrating the second wiring formation process S14. (For example...) Figure 22 As shown, in the second wiring formation step S14, wiring 60 other than the bottom layer is formed on an interlayer insulating film 50 using the same method as in the first wiring formation step S11. The second interlayer insulating film formation step S12, the through-hole plug formation step S13, and the second wiring formation step S14 are repeated until the top layer wiring 60 is formed.

[0088] Figure 23 This is a cross-sectional view illustrating the protective film formation process S15. (For example...) Figure 23As shown, in the protective film formation process S15, a protective film 70 is formed. In the protective film formation process S15, firstly, the protective film 70 is formed on the uppermost interlayer insulating film 50, for example, using a CVD method, to cover the uppermost wiring 60. Secondly, a photoresist pattern is formed on the protective film 70. The photoresist pattern is formed by applying photoresist and exposing and developing the applied photoresist. Thirdly, the protective film 70 is etched using the photoresist pattern as a mask, thereby forming openings (not shown in the figure) in the protective film 70 that expose the pads of the uppermost wiring 60.

[0089] In the monolithization process S16, the semiconductor wafer formed as described above is cut along the boundary region (dicing track) of the adjacent semiconductor device 100, and monolithized into multiple semiconductor devices 100.

[0090] like Figure 9 As shown, the manufacturing method of the semiconductor device 100 also includes a marking step S17. The marking step S17 is performed, for example, after the preparation step S1 and before the element isolation film formation step S2. The marking step S17 may also be performed between the various steps of the manufacturing method of the semiconductor device 100.

[0091] Figure 24 This is a cross-sectional view showing the first example of marking process S17. (Example) Figure 24 As shown, in the marking process S17, the laser L is irradiated in such a way that it is focused and absorbed inside the semiconductor substrate 10. Subsequently, defects are locally introduced into a portion of the semiconductor substrate 10 located near the focus position of the laser L, forming a modified portion 14.

[0092] Figure 25 This is a cross-sectional view showing a second example of the marking process S17. Figure 25 An example is shown where the marking process S17 is performed between the various processes in the manufacturing method of the semiconductor device 100. For example... Figure 25 As shown, in this example, the modified portion 14 is formed inside the semiconductor substrate 10 by irradiating it in a manner that causes the laser L to be focused and absorbed inside the semiconductor substrate 10. However, in this example, the laser L bypasses the wiring 60, passes through the interlayer insulating film 50 (and the protective film 70), and is focused and absorbed inside the semiconductor substrate 10.

[0093] Furthermore, the location of the modified portion 14 formed in the marking process S17 is determined based on MAP data. The MAP data includes, in addition to the batch number of the semiconductor wafer and the location of the semiconductor device 100 on the semiconductor wafer, the results of inspections of the semiconductor device 100 performed during the manufacturing process. Additionally, to ensure that the laser L is focused and absorbed within the semiconductor substrate 10, a wavelength of the laser L with a lower absorptivity relative to the semiconductor substrate 10 and the interlayer insulating film 50 is selected, and the focal point of the laser L is adjusted.

[0094] <Effects of Semiconductor Device 100>

[0095] The effects of the semiconductor device 100 will be explained below.

[0096] When marking a semiconductor substrate 10 by irradiating the main surface 10a with a laser, the surface roughness of the main surface 10a deteriorates near the irradiation location of the laser L. As a result, this may become a cause of particles that adversely affect the manufacturing process in subsequent processes, such as uneven application of photoresist.

[0097] On the other hand, in the semiconductor device 100, the semiconductor substrate 10 is marked by forming a modification portion 14 inside the semiconductor substrate 10. Therefore, in the semiconductor device 100, with the marking, the surface roughness of the main surface 10a is less likely to deteriorate (more specifically, the arithmetic mean roughness of the portion of the main surface 10a that overlaps with the modification portion 14 when viewed from above is less than 1 nm), thereby suppressing the generation of particles that adversely affect the manufacturing process.

[0098] Furthermore, when marking the semiconductor substrate 10 by irradiating the main surface 10a with a laser, the marking of the semiconductor substrate 10 can only be performed when the semiconductor substrate 10 is installed. On the other hand, in the semiconductor device 100, since the marking is performed by forming a modification portion 14 inside the semiconductor substrate 10, it can be performed not only when the semiconductor substrate 10 is installed, but also during the manufacturing process. As a result, in the semiconductor device 100, information such as the results of inspections performed during the manufacturing process of the semiconductor device can also be marked on the semiconductor substrate 10.

[0099] Furthermore, by marking the inspection results during the manufacturing process of the semiconductor device 100, obtaining the batch number of the semiconductor wafer required for the semiconductor device 100, and the position of the semiconductor device 100 on the semiconductor wafer, the traceability of the semiconductor device 100 is ensured. Even when the semiconductor device 100 is in a packaged state (assembled into the semiconductor package 200), for example by irradiation with X-rays, infrared rays, terahertz waves, visible light, or other electromagnetic waves, the markings on the semiconductor substrate 10 (the formation method of the modified portion 14) can be read. Therefore, the semiconductor package 200 can ensure traceability without removing the sealing member 220.

[0100] (Second Implementation)

[0101] The semiconductor device of the second embodiment will be described. The semiconductor device of the second embodiment is referred to as semiconductor device 100A. Here, the differences from semiconductor device 100 will be mainly described, and the descriptions will not be repeated.

[0102] Figure 26 This is an enlarged top view showing a first example of how the modified portion 14 in the semiconductor device 100A is formed. Figure 27 yes Figure 26 A schematic cross-sectional view of sections XXVII-XXVII. (See attached image.) Figure 26 and Figure 27 As shown, in the semiconductor device 100A, the plurality of modified portions 14 can also be arranged in three dimensions. More specifically, the plurality of modified portions 14 includes a plurality of modified portions 14a, a plurality of modified portions 14b, and a plurality of modified portions 14c.

[0103] Multiple modified portions 14a are formed in a first plane, multiple modified portions 14b are formed in a second plane, and multiple modified portions 14c are formed in a third plane. The first, second, and third planes are, for example, planes parallel to the main surface 10a. The first plane is closer to the main surface 10a than the second and third planes. The second plane is closer to the main surface 10a than the third plane.

[0104] Each of the plurality of modified portions 14a is configured not to overlap with any of the plurality of modified portions 14b and 14c when viewed from above. Each of the plurality of modified portions 14b is configured not to overlap with any of the plurality of modified portions 14a and 14c when viewed from above. Each of the plurality of modified portions 14c is configured not to overlap with any of the plurality of modified portions 14a and 14b when viewed from above.

[0105] In the semiconductor device 100A, when reading the marks formed on the semiconductor substrate 10, by changing the depth of the observation focus, each of the modified portions 14a, 14b, and 14c can be read separately. For example, when the observation focus is set to a shallower first position, modified portion 14a can be read, but modified portions 14b and 14c cannot. When the observation focus is set to a deeper third position than the first position, modified portion 14c can be read, but modified portions 14a and 14b cannot. When the observation focus is set to a second position between the first and third positions, modified portion 14b can be read, but modified portions 14a and 14c cannot. In this way, by changing the observation focus when reading the marks, modified portions 14 formed on one surface and modified portions 14 formed on other surfaces can be distinguished, identified, and read.

[0106] Figure 28 This is an enlarged top view showing a second example of how the modified portion 14 in the semiconductor device 100A is formed. (See attached image.) Figure 28 As shown, when viewed from above, modified portion 14a may partially overlap with modified portion 14b or modified portion 14c. Modified portion 14b may also partially overlap with modified portion 14c when viewed from above. In this case, when reading the mark, by detecting the positional offset between modified portion 14a and modified portion 14b (positional offset between modified portion 14a and modified portion 14c, and positional offset between modified portion 14b and modified portion 14c), modified portion 14 formed on one surface and modified portion 14 formed on other surfaces can be distinguished, identified, and read.

[0107] Figure 29 This is an enlarged top view showing a third example of how the modified portion 14 in the semiconductor device 100A is formed. Figure 30 yes Figure 29 A schematic cross-sectional view of section XXX-XXX. For example... Figure 29 and Figure 30 As shown, the modified portion 14a can overlap with the modified portion 14b or the modified portion 14c when viewed from above. Similarly, the modified portion 14b can overlap with the modified portion 14c when viewed from above. In this case, images obtained by rotating the semiconductor device 100A while irradiating it with X-rays or other electromagnetic waves are synthesized to obtain three-dimensional arrangement information of the modified portions 14. Based on this three-dimensional arrangement information of the modified portions 14, information about the manufacturing process of the semiconductor device 100A can be read.

[0108] (Third Implementation)

[0109] The semiconductor package according to the third embodiment will be described. The semiconductor package according to the third embodiment is designated as semiconductor package 200A.

[0110] Figure 31 This is a top view showing a first example of a semiconductor package 200A. Figure 32 yes Figure 31 A schematic cross-sectional view of section XXXII-XXXII. (See attached image.) Figure 31 and Figure 32 As shown, in semiconductor package 200A, semiconductor device 100 is mounted on substrate 210. In semiconductor package 200A, bonding pads 80 formed on the upper surface of semiconductor device 100 are connected to conductor pattern 211 formed on the upper surface of substrate 210 via bonding wires 230.

[0111] The bonding pads 80 are configured so as not to overlap with the marking area 12 when viewed from above. The bonding wires 230 are configured so as not to cross the marking area 12 when viewed from above. The conductor pattern 211 is formed so as not to overlap with the marking area 12 when viewed from above. Thus, in the semiconductor package 200A, the structure formed above or below the semiconductor substrate 10 by a material such as a metal that blocks electromagnetic waves used to read the markings formed in the marking area 12 does not overlap with the marking area 12 when viewed from above. Therefore, according to the semiconductor package 200A, information about the manufacturing process of the semiconductor device 100 can be read more reliably.

[0112] Figure 33 This is a top view showing a second example of a semiconductor package 200A. Figure 34 yes Figure 33 A schematic cross-sectional view of XXXIV-XXXIV. Figure 35 This is a top view showing a third example of a semiconductor package 200A. Figure 36 yes Figure 35 A schematic cross-sectional view of sections XXXVI-XXXVI. (See attached image.) Figures 33 to 36 As shown, in semiconductor package 200A, semiconductor device 100 may not be an LSI (Large Scale Integrated circuit). For example... Figure 33 and Figure 34 As shown, the semiconductor device 100 can also be a discrete semiconductor such as an LED (Light Emitting Diode), for example... Figure 35 and Figure 36As shown, the semiconductor device 100 can also be a power semiconductor element such as a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). The power semiconductor element is not limited to switching elements; it can also be a rectifier element such as an SBD (Schottky Barrier Diode) or an FRD (Fast Recovery Diode). Even in these cases, the structure formed above or below the semiconductor substrate 10 by materials that impede electromagnetic waves used to read the markings formed in the marking region 12 (mainly wiring materials such as lead frames, clips, and bonding wires made of metal materials such as aluminum and copper, or bonding materials such as solder used to join the semiconductor element and the wiring materials) does not overlap with the marking region 12 when viewed from above. For example, a vertically oriented power semiconductor element typically has a substrate with a high impurity concentration and an epitaxial layer with a low impurity concentration formed on the substrate through epitaxial growth, and a device structure such as a MOSFET or SBD is formed in the epitaxial layer. In this case, the modified portion 14 constituting the marking can be formed in the epitaxial layer with a low impurity concentration or in the substrate with a high impurity concentration.

[0113] Furthermore, the wiring material and bonding material described above need only be configured such that they do not overlap with the marking region 12 on at least one side above or below the semiconductor substrate 10. For example, when electromagnetic waves for reading the marking are irradiated from above, it is sufficient that there is no wiring material or bonding material above the marking region 12; the wiring material and bonding material can also overlap below the marking region 12. Figures 33 to 36 The diagram shows an example where gaps 12b are provided in the wiring and bonding materials, meaning that the gaps 12b do not overlap with the wiring and bonding materials above and below the marking area 12. However, gaps 12b may not be provided in the wiring and bonding materials below. Furthermore, the wiring materials mentioned here include electrode materials disposed on the back side of the semiconductor device and lead frames for mounting the semiconductor device (see [reference]). Figure 34 ), substrates for mounting semiconductor components (such as Figure 36 (A substrate with conductive wiring formed on both sides of an insulating substrate). In this case, since the wiring material and bonding material overlap with the marking area 12 below the marking area 12, the marking can be read by reflected light rather than transmitted light. Whether there is wiring material or bonding material overlapping with the marking area 12 can be appropriately selected based on the wavelength of the electromagnetic wave used for reading, the material of the semiconductor element (silicon, silicon carbide, gallium nitride, other materials), and the material, thickness, and shape of the wiring material and bonding material.

[0114] (Fourth Implementation)

[0115] The semiconductor device of the fourth embodiment will be described. The semiconductor device of the fourth embodiment is designated as semiconductor device 100B.

[0116] Figure 37 This is a cross-sectional view of semiconductor device 100B. (Example) Figure 37 As shown, the semiconductor substrate 10 has an impurity diffusion region 11d. The impurity diffusion region 11d is formed, for example, on the main surface 10a of the device region 11. The two ends of the impurity diffusion region 11d form diffusion resistors. The impurity diffusion region 11d is surrounded by a device isolation film 13 when viewed from above. The impurity diffusion region 11d is electrically connected to a wiring 60 via a contact plug 61. However, the wiring 60, except for the two ends of the impurity diffusion region 11d, is arranged in a manner that does not overlap with the impurity diffusion region 11d when viewed from above.

[0117] In semiconductor device 100B, the modified portion 14 does not indicate information about the manufacturing process of semiconductor device 100B and is not formed in the marking region 12. In semiconductor device 100B, the modified portion 14 is formed in a manner that partially overlaps with the impurity diffusion region 11d. In addition, the impurity diffusion region 11d is formed by ion implantation in the first ion implantation process S3, the second ion implantation process S6, or the third ion implantation process S8. The modified portion 14 is formed, for example, after the structure of semiconductor device 100 other than the modified portion 14 is formed, by focusing laser L through the protective film 70 and the interlayer insulating film 50 and having it absorbed by the impurity diffusion region 10d.

[0118] Before forming the modified section 14, the resistance value of the diffusion resistor (impurity diffusion region 10d) is measured. If the resistance value of the diffusion resistor deviates from the desired value, the modified section 14 is formed to adjust the resistance value of the diffusion resistor. After forming the modified section 14, the resistance value of the diffusion resistor is measured again. If it falls within the desired range, the formation of the modified section 14 is terminated. On the other hand, if the resistance value of the diffusion resistor is measured and it does not fall within the desired range, the formation of the modified section 14 continues. In this way, according to the semiconductor device 100B, by forming the modified section 14 while measuring the resistance value of the diffusion resistor, the diffusion resistor can be fine-tuned. In addition, in the semiconductor device 100B, the source region 11a and the drain region 11b can also be adjusted and fine-tuned by forming the modified section 14. In addition, in this embodiment, the impurity diffusion region within the semiconductor substrate 10 is listed as an example of fine-tuning, but the fine-tuning target is not limited to this. For example, the fine-tuning object can be set to polysilicon to adjust the resistance value of polysilicon, or the fine-tuning object can be set to a metal material to adjust the resistance value of the metal material.

[0119] (Postscript)

[0120] The embodiments of this disclosure include the following methods.

[0121] <Postscript 1>

[0122] A semiconductor device comprising a semiconductor substrate,

[0123] A modified portion is formed inside the semiconductor substrate.

[0124] The modified part represents information about the manufacturing process of the semiconductor device.

[0125] <Appendix 2>

[0126] According to the semiconductor device described in Appendix 1, the semiconductor substrate has a marked area when viewed from above.

[0127] The marked area has multiple regions arranged in a matrix when viewed from above.

[0128] The information is represented by whether the modified portion is formed in each of the plurality of regions.

[0129] <Appendix 3>

[0130] According to the semiconductor device described in Appendix 1, the modified portion extends along a first direction when viewed from above.

[0131] The information is represented by the spacing between the two modified portions arranged along a second direction orthogonal to the first direction when viewed from above.

[0132] <Appendix 4>

[0133] According to the semiconductor device described in Appendix 1, the modified portion includes a first modified portion, a second modified portion, and a third modified portion.

[0134] The first modified portion, the second modified portion, and the third modified portion are formed at different positions in the thickness direction of the semiconductor substrate and are arranged in a manner that does not overlap with each other when viewed from above.

[0135] <Appendix 5>

[0136] According to the semiconductor device described in Appendix 1, the modified portion includes a first modified portion, a second modified portion, and a third modified portion.

[0137] The first modified portion, the second modified portion, and the third modified portion are formed at different positions in the thickness direction of the semiconductor substrate and are arranged in a manner that partially overlaps each other when viewed from above.

[0138] <Appendix 6>

[0139] According to the semiconductor device described in Appendix 1, the modified portion includes a first modified portion, a second modified portion, and a third modified portion.

[0140] The first modified portion, the second modified portion, and the third modified portion are formed at different positions in the thickness direction of the semiconductor substrate and are arranged in an overlapping manner when viewed from above.

[0141] <Appendix 7>

[0142] According to the semiconductor device described in Appendix 1, the modified portion is formed to represent text or numbers corresponding to the information when viewed from above.

[0143] <Postscript 8>

[0144] The semiconductor device according to any one of Annexes 1 to 7 further includes wiring arranged on the semiconductor substrate in a manner that does not overlap with the modified portion when viewed from above.

[0145] <Postscript 9>

[0146] The semiconductor device according to any one of Appendices 1 to 8, wherein the semiconductor substrate has a main surface,

[0147] In the portion of the main surface that overlaps with the modified portion when viewed from above, the arithmetic mean roughness is less than 1 nm.

[0148] <Postscript 10>

[0149] According to any one of Annexes 1 to 9, the semiconductor device, wherein the information represents at least one of the following: the result of an inspection during the manufacturing process of the semiconductor device; the batch number of the wafer required to obtain the semiconductor device; the location of the semiconductor device on the wafer; the code of the company that manufactures the semiconductor device; the code of the semiconductor device; and the ID of the manufacturing apparatus used in the manufacturing process.

[0150] <Postscript 11>

[0151] According to the semiconductor device described in Appendix 1, the information varies for each semiconductor device.

[0152] <Postscript 12>

[0153] A semiconductor package, comprising:

[0154] The semiconductor device described in any one of Appendix 1 to Appendix 11; and

[0155] A sealing component for sealing the semiconductor device.

[0156] <Postscript 13>

[0157] According to Appendix 12, the portion of the package located at the position overlapping the modified portion when viewed from above is formed of a material that does not obstruct at least any one of X-rays, infrared light, visible light, and terahertz waves.

[0158] <Postscript 14>

[0159] A method for manufacturing a semiconductor device, comprising:

[0160] The process of preparing a semiconductor substrate; and

[0161] The process of forming a modified portion inside a semiconductor substrate by focusing and absorbing a laser beam inside the substrate.

[0162] The modified part represents information about the manufacturing process of the semiconductor device.

[0163] <Postscript 15>

[0164] The method for manufacturing a semiconductor device according to Appendix 14 further includes:

[0165] The process of forming an insulating film on the semiconductor substrate; and

[0166] The process of forming wiring on the insulating film,

[0167] The laser beam passes through the insulating film in a manner that avoids the wiring and converges and is absorbed inside the semiconductor substrate.

[0168] <Postscript 16>

[0169] A semiconductor device comprising a semiconductor substrate,

[0170] The semiconductor substrate has a main surface, an impurity diffusion region formed on the main surface, and a modified portion formed in a manner that partially overlaps with the impurity diffusion region.

[0171] As described above, embodiments of this disclosure have been illustrated, but various modifications can be made to these embodiments. Furthermore, the scope of this invention is not limited to the described embodiments. The scope of this invention is defined by the claims and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0172] Explanation of reference numerals in the attached figures

[0173] 100 Semiconductor device, 100A Semiconductor device, 100B Semiconductor device, 200 Semiconductor package, 200A Semiconductor package, 10 Semiconductor substrate, 10a Main surface, 10b Main surface, 11 Device region, 11a Source region, 11aa First region, 11ab Second region, 11b Drain region, 11ba First region, 11bb Second region, 11c Well region, 11d Impurity diffusion region, 12 Marking region, 12a Region, 12b Gap, 13 Component isolation film, 14 Modified part, 14a, 14b, 14c Modified part, 20 Gate insulating film, 30 Gate electrode, 40 Sidewall spacer, 50 Interlayer insulating film, 60 Wiring, 61 Contact plug, 62 Through-hole plug, 70 Protective film, 210 Substrate, 220 Sealing component, L Laser, S1 Preparation process, S2 Element isolation film formation process, S3 First ion implantation process, S4 Gate insulating film formation process, S5 Gate electrode formation process, S6 Second ion implantation process, S7 Sidewall spacer formation process, S8 Third ion implantation process, S9 First interlayer insulating film formation process, S10 Contact plug formation process, S11 First wiring formation process, S12 Second interlayer insulating film formation process, S13 Through-hole plug formation process, S14 Second wiring formation process, S15 Protective film formation process, S16 Monolithization process, S17 Marking process, DR1 First direction, DR2 Second direction.

Claims

1. A semiconductor device, characterized in that: Including semiconductor substrates, A modified portion is formed inside the semiconductor substrate. The modified part represents information about the manufacturing process of the semiconductor device.

2. The semiconductor device according to claim 1, characterized in that: The semiconductor substrate has marked areas when viewed from above. The marked area has multiple regions arranged in a matrix when viewed from above. The information is represented by whether the modified portion is formed in each of the plurality of regions.

3. The semiconductor device according to claim 1, characterized in that: The modified portion extends along a first direction when viewed from above. The information is represented by the spacing between the two modified portions arranged along a second direction orthogonal to the first direction when viewed from above.

4. The semiconductor device according to claim 1, characterized in that: The modified part includes a first modified part, a second modified part, and a third modified part. The first modified portion, the second modified portion, and the third modified portion are formed at different positions in the thickness direction of the semiconductor substrate and are arranged in a manner that does not overlap with each other when viewed from above.

5. The semiconductor device according to claim 1, characterized in that: The modified part includes a first modified part, a second modified part, and a third modified part. The first modified portion, the second modified portion, and the third modified portion are formed at different positions in the thickness direction of the semiconductor substrate and are arranged in a manner that partially overlaps each other when viewed from above.

6. The semiconductor device according to claim 1, characterized in that: The modified part includes a first modified part, a second modified part, and a third modified part. The first modified portion, the second modified portion, and the third modified portion are formed at different positions in the thickness direction of the semiconductor substrate and are arranged in an overlapping manner when viewed from above.

7. The semiconductor device according to claim 1, characterized in that: The modified part is formed to represent the text or numbers corresponding to the information when viewed from above.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that: It also includes wiring arranged on the semiconductor substrate in a manner that does not overlap with the modified portion when viewed from above.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that: The semiconductor substrate has a main surface. In the portion of the main surface that overlaps with the modified portion when viewed from above, the arithmetic mean roughness is less than 1 nm.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that: The information represents at least one of the following: the results of an inspection during the manufacturing of the semiconductor device; the batch number of the wafer required to obtain the semiconductor device; the location of the semiconductor device on the wafer; the code of the company that manufactures the semiconductor device; the code of the semiconductor device; and the ID of the manufacturing apparatus used in the manufacturing process.

11. The semiconductor device according to claim 1, characterized in that: The information varies for each of the semiconductor devices.

12. A semiconductor package, characterized in that, include: The semiconductor device according to any one of claims 1 to 11; and A sealing component for sealing the semiconductor device.

13. The semiconductor package according to claim 12, characterized in that: The portion located at the position overlapping the modified portion when viewed from above is formed of a material that does not obstruct at least one of X-rays, infrared light, visible light, and terahertz waves.

14. A method for manufacturing a semiconductor device, characterized in that, include: The process of preparing semiconductor substrates; and The process of forming a modified portion inside a semiconductor substrate by focusing and absorbing a laser beam inside the substrate. The modified part represents information about the manufacturing process of the semiconductor device.

15. The method for manufacturing a semiconductor device according to claim 14, characterized in that, Also includes: The process of forming an insulating film on the semiconductor substrate; and The process of forming wiring on the insulating film, The laser beam passes through the insulating film in a manner that avoids the wiring and converges and is absorbed inside the semiconductor substrate.

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