A method and system for detecting electrical performance of a display driver board

Abstract

The application provides a method and system for detecting the electrical performance of a display driving board, loading a multi-stage stress sequence including a single stress stage, a composite stress stage and a nominal recovery stage to the display driving board, and synchronously collecting electrical response data of each stage; obtaining a single stress sensitive parameter according to the electrical response data of the single stress stage, and predicting the theoretical response data of the display driving board in the composite stress stage by using the single stress sensitive parameter; obtaining an interactive recovery residual, combining a prediction residual sequence between the electrical response data and the theoretical response data of the composite stress stage, and determining an interactive degradation coefficient of the display driving board; identifying a dominant degradation type of the display driving board based on the single stress sensitive parameter and the interactive degradation coefficient, and outputting a health detection result of the electrical performance according to the dominant degradation type. The technical scheme provided by the application can identify the dominant degradation type of the display driving board through multi-stage stress decoupling analysis, so as to realize the health detection of the electrical performance.

Description

Technical Field

[0001] This application relates to the field of display driver board testing technology, and more specifically, to a method and system for testing the electrical performance of display driver boards. Background Technology

[0002] The display driver board is a key functional component in a display terminal. It typically includes a power management chip, timing controller, source driver, and related signal transmission circuits. Its electrical stability directly determines the display quality and lifespan of the entire device. In actual operation, the driver board is subjected to the coupling effects of various stresses such as operating voltage and clock frequency for a long time, which can easily lead to hidden degradation problems such as increased power ripple, enhanced clock jitter, and attenuation of data signal setup time margin and hold time margin.

[0003] However, traditional detection methods typically rely on whether electrical parameters under a single operating condition exceed preset thresholds to determine whether anomalies are primarily caused by voltage stress, clock frequency stress, or a combination of both. Furthermore, existing technologies often directly detect measured electrical responses under combined operating conditions, lacking a mechanism to establish theoretical response benchmarks using response data from a single stress stage, and then quantitatively identify additional interactive degradation effects through the predicted residuals between measured and theoretical responses. Therefore, identifying the dominant degradation type of the display driver board through multi-stage stress decoupling analysis to achieve electrical performance health monitoring remains a challenge for current technologies. Summary of the Invention

[0004] This application provides a method and system for testing the electrical performance of a display driver board, which can identify the dominant degradation type of the display driver board through multi-stage stress decoupling analysis, thereby achieving electrical performance health testing.

[0005] In a first aspect, this application provides a method for testing the electrical performance of a display driver board, comprising the following steps: A multi-stage stress sequence, including a single stress stage, a composite stress stage, and a nominal recovery stage, is applied to the display driver board, and electrical response data of the display driver board at each stage are collected. Based on the electrical response data of the single stress stage, a single stress sensitive parameter is obtained, and the single stress sensitive parameter is used to predict the theoretical response data of the display driver board in the composite stress stage. Interactive recovery residuals are obtained based on electrical response data from the nominal recovery stage. The interactive degradation coefficient of the display driver board is determined based on the predicted residual sequence between the electrical response data from the composite stress stage and the theoretical response data, as well as the interactive recovery residuals. Based on the single stress sensitive parameter and the interactive degradation coefficient, the dominant degradation type of the display driver board is identified, and the health test results of the electrical performance are output according to the dominant degradation type.

[0006] In some embodiments, applying a multi-stage stress sequence comprising a single stress stage, a composite stress stage, and a nominal recovery stage to the display driver board, and collecting electrical response data of the display driver board at each stage specifically includes: The power management chip output test point, timing controller clock test point, and source driver data signal test point of the display driver board are connected through the test fixture. A multi-stage stress sequence consisting of voltage steps and frequency steps is applied to the display driver board. The multi-stage stress sequence includes a voltage-only change stage and a clock-only change stage that belong to a single stress stage, as well as a composite stress stage where voltage and clock frequency change simultaneously, and a nominal recovery stage is inserted between adjacent stages. At each stage, the ripple amplitude value of the power management chip output test point, the clock jitter value of the timing controller clock test point, and the setup time margin and hold time margin of the source driver data signal test point are collected respectively. Channel delay calibration is performed on the collected data to obtain electrical response data after time synchronization at each stage.

[0007] In some embodiments, obtaining single-stress sensitive parameters based on electrical response data from a single stress stage specifically includes: Extract electrical response data corresponding to the voltage-only change stage from the single stress stage, and obtain the electrical response value corresponding to each voltage step within the voltage-only change stage; Based on the reference voltage response value at the nominal operating voltage, determine the voltage response deviation of each voltage step relative to the reference voltage response value; Based on the correlation between voltage stress offset and voltage response deviation corresponding to all voltage steps, the voltage sensitivity parameters are obtained by fitting and solving. Extract electrical response data corresponding to the clock frequency change stage from the single stress stage, and obtain the electrical response value corresponding to each frequency step within the clock frequency change stage. Based on the reference frequency response value at the nominal operating clock frequency, determine the frequency response deviation of the electrical response value of each frequency step relative to the reference frequency response value; Based on the correlation between the frequency stress offset and the frequency response deviation corresponding to all frequency steps, the frequency sensitive parameters are generated by fitting and solving. The voltage-sensitive parameter and the frequency-sensitive parameter are used together as the single stress-sensitive parameter of the display driver board.

[0008] In some embodiments, predicting the theoretical response data of the display driver board in the composite stress stage using the single stress sensitive parameter specifically includes: Obtain the nominal response value of the display driver board at the nominal operating voltage and nominal operating clock frequency; Extract the composite voltage offset of each stress step in the composite stress stage relative to the nominal operating voltage, and the composite frequency offset relative to the nominal operating clock frequency. For each combined stress step, based on the composite voltage offset, the voltage sensitive parameter in the single stress sensitive parameter is scaled to obtain the voltage response increment caused by voltage change under each combined stress step; For each combined stress step, based on the composite frequency offset, the frequency sensitive parameter in the single stress sensitive parameter is scaled to obtain the frequency response increment caused by the clock frequency change under each combined stress step. By combining the nominal response value, the voltage response increment, and the frequency response increment, the step-estimated response value corresponding to each combined stress step is obtained. The theoretical response data of the display driver board in the composite stress stage is constituted by all the step-estimated response values.

[0009] In some embodiments, obtaining interactive recovery residues based on electrical response data from the nominal recovery phase specifically includes: The nominal recovery phase includes: a first nominal recovery phase following the voltage change phase within the single stress phase, a second nominal recovery phase following the clock frequency change phase within the single stress phase, and a third nominal recovery phase following the composite stress phase. Extract the electrical response data corresponding to the first nominal recovery stage, the second nominal recovery stage, and the third nominal recovery stage respectively; The difference between the electrical response data and the nominal response value at each nominal recovery stage is determined, and the first recovery residue, the second recovery residue, and the third recovery residue are obtained sequentially. Based on the first and second recovery residues, a single-stress recovery residue is constructed. The third recovery residue is then weighted and fused with the single-stress recovery residue after performing a differential operation, to obtain the interactive recovery residue of the display driver board.

[0010] In some embodiments, determining the interaction degradation coefficient of the display driver board based on the predicted residual sequence between the electrical response data and the theoretical response data during the composite stress stage, and the interaction recovery residual, specifically includes: The predicted residual sequence between the electrical response data and the theoretical response data in the composite stress stage, as well as the interactive recovery residual, are normalized respectively. Configure composite stress coupling weights, and perform feature aggregation on the predicted residual sequence based on the composite stress coupling weights to generate transient interactive residuals that reflect the degree of deviation of the transient response of the display driver board under multiple stress coupling effects; The transient interaction residual is generated by nonlinear saturation mapping, and the interaction recovery residual is obtained by nonlinear power scaling to obtain the recovery preservation degradation amount. The transient interaction degradation amount and the recovery retention degradation amount are synthesized to obtain the interaction degradation coefficient corresponding to the display driver board.

[0011] In some embodiments, identifying the dominant degradation type of the display driver board based on the single stress sensitive parameter and the interactive degradation coefficient, and outputting the electrical performance health test result according to the dominant degradation type specifically includes: Based on the voltage-sensitive parameter and frequency-sensitive parameter in the single stress-sensitive parameters, the maximum component corresponding to each sensitive parameter is determined as the voltage stress degradation intensity and frequency stress degradation intensity of the display driver board. A degradation intensity determination vector is constructed based on the voltage stress degradation intensity, the frequency stress degradation intensity, and the interaction degradation coefficient; The degradation intensity determination vector is compared with a preset degradation determination threshold to identify the dominant degradation type corresponding to the display driver board. Based on the dominant degradation type and the degradation intensity determination vector, the electrical performance health level and abnormal location information of the display driver board are determined. Generate and output electrical performance health test results, which include the dominant degradation type of the display driver board, electrical performance health level, and anomaly location information.

[0012] Secondly, this application provides an electrical performance testing system for a display driver board, used to perform an electrical performance testing method for the display driver board, including: The data acquisition module is used to load a multi-stage stress sequence, including a single stress stage, a composite stress stage, and a nominal recovery stage, onto the display driver board, and to acquire the electrical response data of the display driver board at each stage. The theoretical prediction module is used to obtain single-stress sensitive parameters based on the electrical response data of the single-stress stage, and to use the single-stress sensitive parameters to predict the theoretical response data of the display driver board in the composite stress stage. The coefficient solving module is used to obtain the interactive recovery residue based on the electrical response data of the nominal recovery stage, and to determine the interactive degradation coefficient of the display driver board based on the predicted residual sequence between the electrical response data of the composite stress stage and the theoretical response data and the interactive recovery residue. The result output module is used to identify the dominant degradation type of the display driver board based on the single stress sensitive parameter and the interactive degradation coefficient, and output the electrical performance health test result according to the dominant degradation type.

[0013] Thirdly, this application provides a computer device, the computer device including a memory and a processor, the memory storing code, the processor being configured to acquire the code and execute the above-described electrical performance testing method for a display driver board.

[0014] Fourthly, this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method for detecting the electrical performance of a display driver board.

[0015] The technical solutions provided by the embodiments disclosed in this application have the following beneficial effects: This application provides a method and system for testing the electrical performance of a display driver board. The method involves loading a multi-stage stress sequence, including a single-stress stage, a composite stress stage, and a nominal recovery stage, onto the display driver board and collecting electrical response data for each stage. A single-stress sensitive parameter is obtained based on the electrical response data of the single-stress stage, and the theoretical response data of the display driver board in the composite stress stage is predicted using the single-stress sensitive parameter. Interactive recovery residuals are obtained based on the electrical response data of the nominal recovery stage. An interactive degradation coefficient of the display driver board is determined based on the predicted residual sequence between the electrical response data of the composite stress stage and the theoretical response data, as well as the interactive recovery residuals. The dominant degradation type of the display driver board is identified based on the single-stress sensitive parameter and the interactive degradation coefficient, and a health test result of the electrical performance is output based on the dominant degradation type.

[0016] Therefore, this application demonstrates several key advantages. First, by correlating and fitting stress offset with response deviation, it effectively suppresses interference from single-step sampling fluctuations, enabling the obtained voltage-sensitive and frequency-sensitive parameters to more stably characterize the response change trend of the display driver board under single stress. Second, by using both voltage-sensitive and frequency-sensitive parameters as single-stress-sensitive parameters, it facilitates the distinction between response changes caused by the linear superposition of single stresses and additional degradation caused by the interaction of composite stresses. Third, by introducing composite voltage offset and composite frequency offset to construct voltage and frequency response increments respectively, it clearly distinguishes the response contributions of different stresses, effectively identifying the interactive degradation effect of voltage and frequency composite stresses, and improving the accuracy and interpretability of composite stress analysis. Fourth, by using electrical response data from each nominal recovery stage to assess unrecoverable or slowly recoverable deviations after stress loading, it effectively distinguishes the residual deviations corresponding to composite stress and single stress, improving the accuracy of interactive degradation identification. Fifth, by weighted fusion of the differential residuals of different electrical parameters, it comprehensively considers the differences in the impact of different electrical parameters on the working stability of the display driver board, thereby obtaining an interactive recovery residual evaluation result that better reflects the actual failure risk. Finally, by constructing a nonlinear saturation mapping function, the saturation characteristics during the degradation process of the display driver board can be simulated, improving the realism of transient degradation modeling; and by using a power-law nonlinear enhancement method, the sensitivity of identifying irreversible residual degradation can be improved, thereby more accurately identifying potential failure risks; by coupling and weighting the fusion of transient degradation terms and reversible degradation terms, a unified quantitative characterization of the overall degradation degree of the display driver board under multi-stress coupling can be achieved, improving the integrity and reliability of electrical performance health test results.

[0017] In summary, the technical solution adopted in this application can identify the dominant degradation type of the display driver board through multi-stage stress decoupling analysis, thereby achieving electrical performance health detection. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only for this embodiment of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is an exemplary flowchart of an electrical performance testing method for a display driver board according to some embodiments of this application; Figure 2 This is a schematic diagram illustrating an application scenario of an electrical performance testing method for a display driver board, according to some embodiments of this application. Figure 3This is an exemplary flowchart illustrating the determination of the interaction degradation coefficient of a display driver board according to some embodiments of this application; Figure 4 This is a schematic diagram of the structure of an electrical performance testing system for a display driver board according to some embodiments of this application; Figure 5 This is a schematic diagram of the structure of a computer device implementing an electrical performance testing method for a display driver board, according to some embodiments of this application. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0021] This application provides a method and system for testing the electrical performance of a display driver board. The core of the method involves loading a multi-stage stress sequence, including a single-stress stage, a composite stress stage, and a nominal recovery stage, onto the display driver board, and collecting electrical response data of the display driver board at each stage. Based on the electrical response data of the single-stress stage, a single-stress sensitive parameter is obtained, and the theoretical response data of the display driver board in the composite stress stage is predicted using the single-stress sensitive parameter. Based on the electrical response data of the nominal recovery stage, an interactive recovery residual is obtained. Based on the predicted residual sequence between the electrical response data of the composite stress stage and the theoretical response data, and the interactive recovery residual, the interactive degradation coefficient of the display driver board is determined. Based on the single-stress sensitive parameter and the interactive degradation coefficient, the dominant degradation type of the display driver board is identified, and the electrical performance health test result is output based on the dominant degradation type. This method can identify the dominant degradation type of the display driver board through multi-stage stress decoupling analysis, thereby achieving electrical performance health testing.

[0022] To better understand the above technical solutions, a detailed description of the technical solutions will be provided below in conjunction with the accompanying drawings and specific embodiments. (Refer to...) Figure 1 This figure is an exemplary flowchart of an electrical performance testing method for a display driver board according to some embodiments of this application. The figure mainly includes the following steps: In step S101, a multi-stage stress sequence including a single stress stage, a composite stress stage, and a nominal recovery stage is applied to the display driver board, and electrical response data of the display driver board at each stage are collected.

[0023] In some embodiments, applying a multi-stage stress sequence comprising a single stress stage, a composite stress stage, and a nominal recovery stage to the display driver board, and collecting electrical response data of the display driver board at each stage, can be specifically done in the following manner: The power management chip output test point, timing controller clock test point, and source driver data signal test point of the display driver board are connected through the test fixture. A multi-stage stress sequence consisting of voltage steps and frequency steps is applied to the display driver board. The multi-stage stress sequence includes a voltage-only change stage and a clock-only change stage that belong to a single stress stage, as well as a composite stress stage where voltage and clock frequency change simultaneously, and a nominal recovery stage is inserted between adjacent stages. At each stage, the ripple amplitude value of the power management chip output test point, the clock jitter value of the timing controller clock test point, and the setup time margin and hold time margin of the source driver data signal test point are collected respectively. Channel delay calibration is performed on the collected data to obtain electrical response data after time synchronization at each stage.

[0024] It should be noted that, Figure 2 This is a schematic diagram illustrating an application scenario of an electrical performance testing method for a display driver board according to some embodiments of this application. As shown in the figure, the test fixture is connected to the power management chip output test point, timing controller clock test point, source driver data signal test point, and frame synchronization signal or line synchronization signal test point of the display driver board, respectively. The output terminal of the programmable power supply is connected to the display driver board to apply stepped voltage stress to the display driver board. The output terminal of the programmable clock source is connected to the display driver board to apply stepped frequency stress to the display driver board. The data acquisition device is connected to the test fixture to acquire electrical data of the display driver board within a preset number of frames for each stress step.

[0025] It should be noted that the ripple amplitude is used to characterize the stability of the output voltage of the power management chip; the clock jitter value is used to characterize the timing reliability of the clock signal output by the timing controller; the setup time margin and the hold time margin are used to characterize the timing safety margin of the source driver data signal relative to the clock sampling edge; the four parameters correspond to the power supply, clock, and data signals respectively, and can cover the core signal link of the display driver board, reflecting the electrical degradation characteristics under voltage-frequency coupling stress.

[0026] In specific implementation, the frame synchronization signal or line synchronization signal of the display driver board is used as the sampling trigger reference. A multi-stage stress sequence consisting of voltage and frequency steps is applied to the display driver board. The multi-stage stress sequence is applied sequentially in the following order: voltage-only change stage, first nominal recovery stage, clock frequency-only change stage, second nominal recovery stage, composite stress stage, and third nominal recovery stage. Specifically, in the voltage-only change stage, the power supply voltage of the display driver board is adjusted step-by-step according to a preset voltage step, while maintaining the clock frequency at the nominal operating clock frequency. In the first nominal recovery stage, the power supply voltage is restored... The clock frequency is adjusted step by step according to a preset frequency step in the nominal state during the clock frequency-only change phase, while maintaining the power supply voltage at the nominal operating voltage. During the second nominal recovery phase, the clock frequency is restored to the nominal state. During the composite stress phase, the voltage step and frequency step are applied synchronously according to a preset combination relationship. During the third nominal recovery phase, the power supply voltage and clock frequency are restored to the nominal state. Furthermore, each stress step maintains a preset number of frames, such as 5 frames, so that the display driver board can complete the data output of at least one display frame window under the corresponding voltage and / or clock frequency conditions.

[0027] It should be noted that the preset voltage step is a plurality of voltage offset levels set around the nominal operating voltage; the preset frequency step is a plurality of clock frequency offset levels set around the nominal operating clock frequency; the preset combination relationship is a voltage-frequency joint loading relationship determined by selecting at least two levels from the plurality of voltage offset levels and the plurality of clock frequency offset levels, used to simulate the combined working state of the display driver board under the combined effect of power supply fluctuations and clock frequency changes.

[0028] In specific implementation, during the voltage-only change stage, in the last display frame window of each voltage step, the peak value is extracted from the original time-domain waveform of the power management chip output test point, the root mean square value is extracted from the original time-domain waveform of the timing controller clock test point, and the minimum value of the setup time margin and the minimum value of the hold time margin are extracted from the original time-domain waveform of the source driver data signal test point, respectively, thereby obtaining the ripple amplitude, clock jitter value, setup time margin, and hold time margin corresponding to the voltage step; during the clock frequency-only change stage, in the last display frame window of each frequency step, the above four electrical parameters corresponding to the frequency step are obtained in the same way; during the combined stress stage, in the last display frame window of each combined stress step, the above four electrical parameters corresponding to the combined stress step are obtained in the same way; during each nominal recovery stage, the above four electrical parameters are extracted in several consecutive display frame windows after stabilization in the same way. Finally, based on the inherent transmission delays of the test fixture, acquisition channel, and probe link, channel delay calibration is performed on the acquired ripple amplitude, clock jitter, setup time margin, and hold time margin. Stress step numbering alignment is performed on the acquired data of the single stress stage and the composite stress stage. Display frame window timing alignment is uniformly performed on the acquired data of all stages, thereby obtaining the electrical response data of the display driver board after timing alignment at each stage. The electrical response data is a multi-parameter timing sequence containing ripple amplitude, clock jitter, setup time margin, and hold time margin.

[0029] It should be noted that before performing multi-stage stress sequence loading, the initial nominal response vector of the display driver board is obtained in advance. Specifically, before applying any stress, under the nominal operating voltage and nominal operating clock frequency conditions, the ripple amplitude, clock jitter value, settling time margin, and hold time margin of multiple display frame windows are continuously collected in the manner described above, and the steady-state average value of each electrical parameter is taken to form the initial nominal response vector. The initial nominal response vector represents the comprehensive electrical reference state of the display driver board under standard nominal operating conditions, providing a unified common reference for subsequent calculations. The reference voltage response value, reference frequency response value, and nominal response value mentioned below all refer to this initial nominal response vector.

[0030] In step S102, a single stress sensitive parameter is obtained based on the electrical response data of the single stress stage, and the single stress sensitive parameter is used to predict the theoretical response data of the display driver board in the composite stress stage.

[0031] In some embodiments, obtaining single-stress sensitive parameters based on electrical response data from a single stress stage can be achieved in the following manner: Extract electrical response data corresponding to the voltage-only change stage from the single stress stage, and obtain the electrical response value corresponding to each voltage step within the voltage-only change stage; Based on the reference voltage response value at the nominal operating voltage, determine the voltage response deviation of each voltage step relative to the reference voltage response value; Based on the correlation between voltage stress offset and voltage response deviation corresponding to all voltage steps, the voltage sensitivity parameters are obtained by fitting and solving. Extract electrical response data corresponding to the clock frequency change stage from the single stress stage, and obtain the electrical response value corresponding to each frequency step within the clock frequency change stage. Based on the reference frequency response value at the nominal operating clock frequency, determine the frequency response deviation of the electrical response value of each frequency step relative to the reference frequency response value; Based on the correlation between the frequency stress offset and the frequency response deviation corresponding to all frequency steps, the frequency sensitive parameters are generated by fitting and solving. The voltage-sensitive parameter and the frequency-sensitive parameter are used together as the single stress-sensitive parameter of the display driver board.

[0032] It should be noted that the voltage stress offset refers to the degree of deviation of the actual applied voltage from the nominal operating voltage; the frequency stress offset refers to the degree of deviation of the actual applied clock frequency from the nominal operating clock frequency; the voltage response deviation and the frequency response deviation are used to characterize the degree of deviation of the electrical response value under each stress step from the initial nominal response vector; the voltage sensitivity parameter and the frequency sensitivity parameter are used to characterize the sensitivity of various electrical parameters of the display driver board to changes in power supply voltage and operating clock frequency, and to provide a single stress reference for theoretical response prediction under composite stress conditions.

[0033] In specific implementation, firstly, electrical response data corresponding only to voltage change stages is extracted from the time-aligned electrical response data of each stage. Based on the stress step number alignment result, the ripple amplitude, clock jitter value, setup time margin, and hold time margin corresponding to each voltage step are obtained from this data. For each voltage step, the above four electrical parameters are combined into a four-dimensional vector in a fixed order as the electrical response value corresponding to that step. At the same time, the voltage difference between the actual applied voltage and the nominal operating voltage of each voltage step is recorded as the voltage stress offset of that step. Secondly, the initial nominal response vector is obtained as the reference voltage response value of the display driver board under the nominal operating voltage. The dimension-wise difference between the electrical response value of each voltage step and the reference voltage response value is calculated to obtain the voltage response deviation corresponding to each voltage step. Then, for the four electrical parameters—ripple amplitude, clock jitter, settling time margin, and hold time margin—the following operations are performed independently: extract the voltage response deviation and corresponding voltage stress offset of the parameter under all voltage steps, and use the voltage stress offset of each step as the abscissa and the voltage response deviation of the parameter as the ordinate to form several data points on a two-dimensional plane; use the least squares method to perform linear fitting on these two-dimensional data points through the origin, and the slope of the fitted line is the voltage sensitivity coefficient of the parameter; combine the voltage sensitivity coefficients obtained from fitting the four electrical parameters into a four-dimensional vector in a fixed order, which serves as the voltage sensitivity parameter of the display driver board.

[0034] In addition, in specific implementation, similarly, for the clock frequency-only variation stage, the same processing procedure as for the voltage-sensitive parameters is adopted. The electrical response values ​​corresponding to each frequency step are extracted, and the frequency difference between the actual loaded frequency of each frequency step and the nominal operating clock frequency is recorded as the frequency stress offset. Based on the reference frequency response value, the frequency response deviation corresponding to each frequency step is determined. Then, for the aforementioned four electrical parameters, a fitting relationship between the frequency stress offset and the frequency response deviation is established. A least-squares method is used for linear fitting through the origin to obtain the frequency sensitivity coefficients corresponding to each electrical parameter. The four frequency sensitivity coefficients are then combined in a fixed order into a four-dimensional vector, which serves as the frequency sensitivity parameter of the display driver board. Finally, the voltage-sensitive parameter and the frequency-sensitive parameter are used together as the single-stress sensitivity parameter of the display driver board for theoretical response prediction in the subsequent composite stress stage.

[0035] It should be noted that by extracting electrical response data from the voltage-only and clock-frequency-only stages separately, and calculating the response deviation based on the baseline response value under nominal operating conditions, the response change of the display driver board under a single stress can be separated from the overall test data. By correlating and fitting the stress offset with the response deviation, the impact of a single step sampling fluctuation on the results can be reduced, allowing the obtained voltage-sensitive and frequency-sensitive parameters to more stably characterize the response change trend of the display driver board under a single stress. By using both the voltage-sensitive and frequency-sensitive parameters as single-stress-sensitive parameters, both supply voltage disturbances and clock frequency disturbances can be covered simultaneously, providing a clear single-stress reference for subsequent composite stress response prediction. This also helps to distinguish between the response change caused by the linear superposition of a single stress and the additional degradation caused by the interaction of composite stresses.

[0036] In some embodiments, the theoretical response data of the display driver board in the composite stress stage can be predicted using the single stress-sensitive parameter in the following manner: Obtain the nominal response value of the display driver board at the nominal operating voltage and nominal operating clock frequency; Extract the composite voltage offset of each stress step in the composite stress stage relative to the nominal operating voltage, and the composite frequency offset relative to the nominal operating clock frequency. For each combined stress step, based on the composite voltage offset, the voltage sensitive parameter in the single stress sensitive parameter is scaled to obtain the voltage response increment caused by voltage change under each combined stress step; For each combined stress step, based on the composite frequency offset, the frequency sensitive parameter in the single stress sensitive parameter is scaled to obtain the frequency response increment caused by the clock frequency change under each combined stress step. By combining the nominal response value, the voltage response increment, and the frequency response increment, the step-estimated response value corresponding to each combined stress step is obtained. The theoretical response data of the display driver board in the composite stress stage is constituted by all the step-estimated response values.

[0037] It should be noted that the composite voltage offset and the composite frequency offset are used to characterize the degree of voltage deviation and frequency deviation of each combined stress step relative to the nominal operating conditions, respectively; the voltage response increment is used to characterize the change in electrical response caused by voltage offset under each combined stress step; the frequency response increment is used to characterize the change in electrical response caused by clock frequency offset under each combined stress step; the step estimated response value is the expected response value obtained by superimposing the voltage response increment and the frequency response increment on the nominal response value, and is used to characterize the theoretical electrical response that the display driver board should exhibit under the corresponding combined stress step under the condition that the interaction coupling effect between voltage stress and clock frequency stress is not considered.

[0038] In specific implementation, firstly, the initial nominal response vector is used as the nominal response value of the display driver board under the nominal operating voltage and nominal operating clock frequency. Secondly, the actual applied voltage and actual applied frequency corresponding to each combined stress step are extracted from the combined stress stage. The difference between the actual applied voltage and the nominal operating voltage of the combined stress step is recorded as the combined voltage offset of the step; simultaneously, the difference between the actual applied frequency and the nominal operating clock frequency of the combined stress step is recorded as the combined frequency offset of the step. Then, for each combined stress step, the combined voltage offset corresponding to the step is multiplied by each dimension component of the voltage-sensitive parameter to generate a four-dimensional vector, which is used as the voltage response increment corresponding to the combined stress step. Following the same calculation method, the combined frequency offset is multiplied by each dimension component of the frequency-sensitive parameter to obtain the frequency response increment corresponding to the combined stress step. Finally, the nominal response value, voltage response increment, and frequency response increment under the same stress step are added together according to their corresponding dimensions to obtain the step-estimated response value corresponding to that step. According to the loading order of each stress step in the composite stress stage, all step-estimated response values ​​are arranged in sequence to form the theoretical response data of the display driver board in the composite stress stage.

[0039] It should be noted that theoretical prediction of the electrical response in the composite stress stage is based on single stress sensitive parameters, avoiding complete reliance on measured composite stress data for modeling, thereby improving prediction efficiency. By introducing composite voltage offset and composite frequency offset to construct voltage response increment and frequency response increment respectively, the contribution of different stress sources to the electrical response can be clearly distinguished, which is beneficial for subsequent identification of the interactive degradation effect under the combined action of voltage stress and frequency stress, and improves the accuracy and interpretability of composite stress analysis.

[0040] In step S103, interactive recovery residuals are obtained based on the electrical response data of the nominal recovery stage. The interactive degradation coefficient of the display driver board is determined according to the predicted residual sequence between the electrical response data of the composite stress stage and the theoretical response data, as well as the interactive recovery residuals.

[0041] In some embodiments, obtaining interactive recovery residues based on electrical response data from the nominal recovery phase can be achieved in the following ways: The nominal recovery phase includes: a first nominal recovery phase following the voltage change phase within the single stress phase, a second nominal recovery phase following the clock frequency change phase within the single stress phase, and a third nominal recovery phase following the composite stress phase. Extract the electrical response data corresponding to the first nominal recovery stage, the second nominal recovery stage, and the third nominal recovery stage respectively; The difference between the electrical response data and the nominal response value at each nominal recovery stage is determined, and the first recovery residue, the second recovery residue, and the third recovery residue are obtained sequentially. Based on the first and second recovery residues, a single-stress recovery residue is constructed. The third recovery residue is then weighted and fused with the single-stress recovery residue after performing a differential operation, to obtain the interactive recovery residue of the display driver board.

[0042] It should be noted that the nominal recovery stage includes a first nominal recovery stage, a second nominal recovery stage, and a third nominal recovery stage. The first nominal recovery stage is set after the voltage-only change stage and is used to characterize the residual response state of the display driver board when it recovers to the nominal operating conditions after experiencing voltage stress loading alone. The second nominal recovery stage is set after the clock frequency-only change stage and is used to characterize the residual response state of the display driver board when it recovers to the nominal operating conditions after experiencing clock frequency stress loading alone. The third nominal recovery stage is set after the composite stress stage and is used to characterize the residual response state of the display driver board when it recovers to the nominal operating conditions after experiencing both voltage stress and clock frequency stress loading together.

[0043] In specific implementation, the electrical response data corresponding to the first nominal recovery stage, the second nominal recovery stage, and the third nominal recovery stage are acquired respectively. For each nominal recovery stage, the ripple amplitude, clock jitter value, setup time margin, and hold time margin corresponding to multiple display frame windows within that stage are averaged dimension by dimension to obtain the first recovery response vector, the second recovery response vector, and the third recovery response vector. Then, each recovery response vector is subjected to a dimension-by-dimensional difference operation with the nominal response value to obtain the first recovery residual, the second recovery residual, and the third recovery residual.

[0044] It should be noted that the first recovery residual is used to characterize the residual offset that the display driver board still retains relative to the initial nominal state after experiencing a voltage-only change phase and returning to the nominal operating conditions; the second recovery residual is used to characterize the residual offset that the display driver board still retains after experiencing a clock frequency-only change phase and returning to the nominal operating conditions; and the third recovery residual is used to characterize the residual offset that the display driver board still retains after experiencing a composite stress phase and returning to the nominal operating conditions.

[0045] In specific implementation, the first recovery residual and the second recovery residual are added dimension by dimension to obtain the single-stress recovery residual. Then, the corresponding dimension components of the single-stress recovery residual are subtracted from each dimension component of the third recovery residual to obtain the ripple amplitude differential residual, clock jitter differential residual, setup time margin differential residual, and hold time margin differential residual in sequence. Finally, based on the degree of influence of ripple amplitude, clock jitter, setup time margin, and hold time margin on the working stability of the display driver board, corresponding fusion weights are configured for each dimension. The differential residuals corresponding to each dimension are multiplied by the fusion weights and then weighted and summed to obtain the interactive recovery residual of the display driver board.

[0046] It should be noted that the single-stress recovery residual characterizes the total degradation amount after linear superposition of the irreversible degradation caused by pure voltage stress and pure frequency stress, which serves as the baseline of irreversible degradation under no coupling effect; the interactive recovery residual characterizes the additional increment of the actual irreversible degradation under the combined stress effect relative to the single-stress recovery residual, that is, the permanent damage caused purely by the coupling effect between voltage and frequency.

[0047] In addition, it should be noted that using electrical response data from each nominal recovery stage to assess the unrecoverable or slow recovery deviation after stress loading, and distinguishing the residual deviation after composite stress from the residual deviation after single stress, helps to improve the accuracy of interactive degradation identification. By weighted fusion of the differential residuals of different electrical parameters, the differences in the impact of different electrical parameters on the working stability of the display driver board can be comprehensively considered, thereby obtaining an interactive recovery residual evaluation result that better reflects the actual failure risk.

[0048] In some embodiments, the determination of the predicted residual sequence based on the electrical response data of the composite stress stage and the theoretical response data can be achieved in the following manner: Based on the electrical response data of the composite stress stage, the electrical response values ​​corresponding to each combined stress step in the composite stress stage are extracted. Obtain the step-estimated response value corresponding to each combined stress step in the theoretical response data; For each stress step combination, the electrical response value corresponding to the stress step combination is differentially calculated with the predicted response value of the step to obtain the predicted residual of the stress step combination. According to the loading sequence of each combined stress step in the composite stress stage, all step prediction residuals are arranged sequentially to form the prediction residual sequence of the display driver board.

[0049] In specific implementation, firstly, from the time-aligned electrical response data of each stage, the electrical response values ​​corresponding to each combined stress step within the composite stress stage are extracted. Each electrical response value is a four-dimensional vector containing ripple amplitude, clock jitter value, setup time margin, and hold time margin. Secondly, the step-based predicted response values ​​corresponding to each combined stress step are retrieved from the theoretical response data obtained in step S102. Then, for each combined stress step, the corresponding electrical response value and the step-based predicted response value are matched according to the step number, and parameter dimension alignment is completed. Subsequently, the two are subjected to a dimension-by-dimensional difference operation to obtain the step prediction residual corresponding to that combined stress step. Finally, according to the loading sequence of each combined stress step within the composite stress stage, all step prediction residuals are arranged sequentially to construct a prediction residual sequence.

[0050] Preferably, in some embodiments, reference is made to Figure 3 As shown, this figure is an exemplary flowchart illustrating the determination of the interaction degradation coefficient of a display driver board according to some embodiments of this application. In this embodiment, the determination of the interaction degradation coefficient of the display driver board based on the predicted residual sequence between the electrical response data of the composite stress stage and the theoretical response data, as well as the interaction recovery residual, can be achieved by the following steps: In step S1031, the predicted residual sequence between the electrical response data and the theoretical response data in the composite stress stage, as well as the interactive recovery residual, are normalized respectively. In step S1032, a composite stress coupling weight is configured, and feature aggregation is performed on the predicted residual sequence based on the composite stress coupling weight to generate a transient interactive residual that reflects the degree of deviation of the transient response of the display driver board under multi-stress coupling. In step S1033, the transient interaction residual is generated by nonlinear saturation mapping to generate transient interaction degradation amount, and the interaction recovery residual is nonlinearly power-scaled to obtain recovery preservation degradation amount; In step S1034, the transient interaction degradation amount and the recovery retention degradation amount are synthesized to obtain the interaction degradation coefficient corresponding to the display driver board.

[0051] It should be noted that the transient interactive residual refers to the comprehensive deviation of the actual electrical response of the display driver board from the predicted response under the combined stress step effect, and is used to characterize the transient abnormal response intensity caused by the coupling effect of voltage stress and clock frequency stress; the transient interactive degradation amount is used to describe the change characteristic of the transient degradation effect of the display driver board under the combined stress effect gradually approaching saturation as the residual increases; the recovery and retention degradation amount is used to reflect the residual degradation degree that the display driver board cannot recover after experiencing combined stress; the interactive degradation coefficient is a comprehensive index of multi-stress coupling degradation obtained by combining the transient interactive degradation amount and the recovery and retention degradation amount, and is used to characterize the overall degradation degree of the power supply-clock signal link of the display driver board under the combined effect of voltage stress and clock frequency stress.

[0052] In specific implementation, firstly, the predicted residual sequence and the interactive recovery residual are obtained respectively; for the predicted residual sequence, the range normalization method is used to map each component of the step prediction residual corresponding to each combined stress step to the [0,1] interval respectively; for the interactive recovery residual, the range normalization method is also used to map it to the [0,1] interval. Secondly, a composite stress coupling weight is configured, which includes two types: step weight and electrical parameter weight. The step weight is dynamically set according to the stress deviation of each combined stress step. The stress deviation of each combined stress step is the weighted sum of the absolute values ​​of the corresponding voltage offset and frequency offset. The voltage weight and frequency weight are fixed empirical weights preset based on the degradation characteristics of the power supply-clock signal link of the display driver board. The electrical parameter weight is preset based on the prior knowledge of the impact of four electrical parameters on the performance of the display driver board. Based on the above two types of weights, feature aggregation is performed on the normalized prediction residual sequence. Specifically, for the step prediction residual corresponding to each combined stress step, the residual of each electrical parameter in the step prediction residual is first multiplied by the corresponding electrical parameter weight, and then multiplied by the step weight of the step to achieve double-layer weighting. The square root of the sum of squares of the weighted residuals corresponding to all combined stress steps and all electrical parameters is taken to obtain the transient interactive residual reflecting the degree of transient response deviation of the display driver board under multi-stress coupling.

[0053] In addition, in the specific implementation, the transient interactive residual is input into a preset nonlinear saturation mapping function. In practice, a sigmoid function or a piecewise linear saturation function can be used to simulate the physical characteristic that the degradation process gradually approaches saturation as the transient residual increases, and the transient interactive degradation amount is output. At the same time, the normalized interactive recovery residual is subjected to nonlinear power scaling, for example, taking the power p=2 and performing a square operation to enhance the sensitivity of the interactive recovery residual to the degradation contribution, and the recovery-maintaining degradation amount is obtained. Finally, combined with the degradation prior characteristics of the power supply-clock signal link of the display driver board, the coupling weights of the transient and recovery terms are preset. The transient interactive degradation amount and the recovery-maintaining degradation amount are weighted and summed using this set of weights to synthesize the interactive degradation coefficient corresponding to the display driver board. The larger the value of this coefficient, the more significant the coupling effect between voltage stress and clock frequency stress, and the more severe the irreversible electrical degradation caused.

[0054] It should be noted that by introducing a composite stress coupling weight composed of stepped weights and electrical parameter weights, the differences in degradation contribution under different combined stress conditions and the differences in the importance of different electrical parameters can be simultaneously reflected, enhancing the adaptability of degradation characterization results to actual physical degradation behavior. Furthermore, by constructing a nonlinear saturation mapping function, the saturation characteristics in the degradation process of the display driver board can be simulated, improving the realism of transient degradation modeling. At the same time, by performing nonlinear power enhancement on the interactive recovery residual, the sensitivity to irrecoverable residual degradation can be improved, thereby more accurately identifying potential failure risks. By coupling and weighting the transient degradation term and the recovery degradation term, a unified quantitative characterization of the overall degradation degree of the display driver board under multi-stress coupling can be achieved, improving the completeness of the interactive degradation assessment results.

[0055] In step S104, the dominant degradation type of the display driver board is identified based on the single stress sensitive parameter and the interactive degradation coefficient, and the health test result of the electrical performance is output according to the dominant degradation type.

[0056] In some embodiments, the dominant degradation type of the display driver board is identified based on the single stress sensitive parameter and the interactive degradation coefficient, and the health test result of electrical performance is output according to the dominant degradation type. Specifically, this can be achieved in the following manner: Based on the voltage-sensitive parameter and frequency-sensitive parameter in the single stress-sensitive parameters, the maximum component corresponding to each sensitive parameter is determined as the voltage stress degradation intensity and frequency stress degradation intensity of the display driver board. A degradation intensity determination vector is constructed based on the voltage stress degradation intensity, the frequency stress degradation intensity, and the interaction degradation coefficient; The degradation intensity determination vector is compared with a preset degradation determination threshold to identify the dominant degradation type corresponding to the display driver board. Based on the dominant degradation type and the degradation intensity determination vector, the electrical performance health level and abnormal location information of the display driver board are determined. Generate and output electrical performance health test results, which include the dominant degradation type of the display driver board, electrical performance health level, and anomaly location information.

[0057] It should be noted that the preset degradation judgment thresholds include voltage degradation threshold, frequency degradation threshold, interaction degradation threshold, and preset difference threshold, all of which are fixed judgment thresholds preset based on the hardware characteristics of the display driver board.

[0058] In specific implementation, firstly, the dimension component with the largest absolute value among the voltage-sensitive parameter and the frequency-sensitive parameter is extracted, corresponding to the voltage stress degradation intensity and frequency stress degradation intensity, respectively. Secondly, the voltage stress degradation intensity, the frequency stress degradation intensity, and the interaction degradation coefficient are combined in sequence to construct a degradation intensity determination vector. Then, the dominant degradation type of the display driver board is identified according to the following rules: when the voltage stress degradation intensity exceeds the voltage degradation threshold and it is the largest component in the degradation intensity determination vector, it is determined to be voltage-dominant degradation; when the frequency stress degradation intensity exceeds the frequency degradation threshold and it is the largest component in the degradation intensity determination vector, it is determined to be frequency-dominant degradation; when the interaction degradation coefficient exceeds the interaction degradation threshold and it is the largest component in the degradation intensity determination vector, it is determined to be composite stress interaction-dominant degradation; when multiple components exceed their corresponding thresholds and the difference between the components is less than a preset threshold... The difference threshold is used to determine mixed degradation; when all components do not exceed the corresponding threshold, it is determined to be in a normal state; at the same time, based on the degree to which each component in the degradation intensity determination vector exceeds the corresponding threshold, the electrical performance health level of the display driver board is divided: when all components are below 50% of the corresponding threshold, it is determined to be in a normal level; when there is a component below the corresponding threshold but greater than or equal to 50% of the corresponding threshold, it is determined to be in a concern level; when there is a component exceeding the threshold but less than 1.5 times the threshold, it is determined to be in a warning level; when there is a component exceeding 1.5 times the threshold, it is determined to be in an abnormal level.

[0059] In addition, in specific implementation, based on the dominant degradation type, the electrical parameter corresponding to the largest component in the corresponding sensitive parameter vector is located to complete the anomaly localization: If it is voltage-dominant degradation, the component with the largest absolute value is located from the voltage sensitive parameters: when the ripple amplitude component is the largest, the anomaly localization information points to an abnormal power supply stability; when the clock jitter component is the largest, it points to clock instability caused by voltage disturbance; when the setup time margin or hold time margin component is the largest, it points to insufficient interface timing margin caused by voltage changes; if it is frequency-dominant degradation, similarly, the component with the largest absolute value is located from the frequency sensitive parameters for anomaly determination: when the clock jitter component is the largest, the anomaly localization is... Bit information indicates clock integrity anomalies; when the ripple amplitude component is at its maximum, it indicates power supply response anomalies caused by frequency disturbances; when the timing margin component is at its maximum, it indicates a decrease in timing reliability due to frequency changes; if it is a composite stress interaction-dominated degradation, the absolute value proportion of each component in the interaction recovery residue is calculated, and the component with the largest proportion is taken as the source of coupling anomalies: if the ripple amplitude component has the largest proportion, it is located as a power supply-clock coupling anomaly; if the clock jitter component has the largest proportion, it is located as a clock-power supply coupling anomaly; if the timing margin component has the largest proportion, it is located as a timing coupling anomaly; if it is a mixed degradation, multiple potential anomaly sources are output by combining the above rules. Finally, an electrical performance health test result containing the dominant degradation type, electrical performance health level, and anomaly location information is generated and output. This result is presented in JSON format to guide the fault repair and good product selection of the display driver board.

[0060] Therefore, this application demonstrates several key advantages. First, by correlating and fitting stress offset with response deviation, it effectively suppresses interference from single-step sampling fluctuations, enabling the obtained voltage-sensitive and frequency-sensitive parameters to more stably characterize the response change trend of the display driver board under single stress. Second, by using both voltage-sensitive and frequency-sensitive parameters as single-stress-sensitive parameters, it facilitates the distinction between response changes caused by the linear superposition of single stresses and additional degradation caused by the interaction of composite stresses. Third, by introducing composite voltage offset and composite frequency offset to construct voltage and frequency response increments respectively, it clearly distinguishes the response contributions of different stresses, effectively identifying the interactive degradation effect of voltage and frequency composite stresses, and improving the accuracy and interpretability of composite stress analysis. Fourth, by using electrical response data from each nominal recovery stage to assess unrecoverable or slowly recoverable deviations after stress loading, it effectively distinguishes the residual deviations corresponding to composite stress and single stress, improving the accuracy of interactive degradation identification. Fifth, by weighted fusion of the differential residuals of different electrical parameters, it comprehensively considers the differences in the impact of different electrical parameters on the working stability of the display driver board, thereby obtaining an interactive recovery residual evaluation result that better reflects the actual failure risk. Finally, by constructing a nonlinear saturation mapping function, the saturation characteristics during the degradation process of the display driver board can be simulated, improving the realism of transient degradation modeling; and by using a power-law nonlinear enhancement method, the sensitivity of identifying irreversible residual degradation can be improved, thereby more accurately identifying potential failure risks; by coupling and weighting the fusion of transient degradation terms and reversible degradation terms, a unified quantitative characterization of the overall degradation degree of the display driver board under multi-stress coupling can be achieved, improving the integrity and reliability of electrical performance health test results.

[0061] In summary, the technical solution adopted in this application can identify the dominant degradation type of the display driver board through multi-stage stress decoupling analysis, thereby achieving electrical performance health detection.

[0062] In another aspect, in some embodiments, this application provides an electrical performance testing system for a display driver board, referring to... Figure 4 The figure is a schematic diagram of an electrical performance testing system for a display driver board according to some embodiments of this application. The electrical performance testing system for the display driver board includes: The data acquisition module 201 is used to load a multi-stage stress sequence, including a single stress stage, a composite stress stage, and a nominal recovery stage, onto the display driver board, and to acquire the electrical response data of the display driver board at each stage. The theoretical prediction module 202 is used to obtain single stress sensitive parameters based on the electrical response data of the single stress stage, and use the single stress sensitive parameters to predict the theoretical response data of the display driver board in the composite stress stage. The coefficient solving module 203 is used to obtain the interactive recovery residue based on the electrical response data of the nominal recovery stage, and to determine the interactive degradation coefficient of the display driver board based on the predicted residual sequence between the electrical response data of the composite stress stage and the theoretical response data and the interactive recovery residue. The result output module 204 is used to identify the dominant degradation type of the display driver board based on the single stress sensitive parameter and the interactive degradation coefficient, and output the health test result of electrical performance according to the dominant degradation type.

[0063] In addition, this application also provides a computer device, the computer device including a memory and a processor, the memory storing code, the processor being configured to acquire the code and execute the above-described electrical performance testing method for a display driver board.

[0064] In some embodiments, reference Figure 5 The figure is a schematic diagram of a computer device implementing an electrical performance testing method for a display driver board according to some embodiments of this application. The electrical performance testing method for a display driver board in the above embodiments can be implemented through... Figure 5 The computer device shown is used to implement this, and the computer device includes at least one processor 301, a communication bus 302, a memory 303, and at least one communication interface 304.

[0065] The processor 301 may be a general-purpose central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more devices for controlling the execution of the electrical performance testing method for the display driver board in this application.

[0066] The communication bus 302 can be used to transmit information between the aforementioned components.

[0067] The memory 303 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disks or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. The memory 303 may exist independently and be connected to the processor 301 via the communication bus 302. The memory 303 may also be integrated with the processor 301.

[0068] The memory 303 stores program code for executing the scheme of this application, and its execution is controlled by the processor 301. The processor 301 executes the program code stored in the memory 303. The program code may include one or more software modules. In the above embodiments, the determination of the electrical performance testing method for the display driver board can be implemented by the processor 301 and one or more software modules in the program code in the memory 303.

[0069] Communication interface 304 uses any transceiver-like device for communicating with other devices or communication networks, such as Ethernet, radio access network (RAN), wireless local area networks (WLAN), etc.

[0070] In a specific implementation, as one example, a computer device may include multiple processors, each of which may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. Here, a processor may refer to one or more devices, circuits, and / or processing cores used to process data (e.g., computer program instructions).

[0071] The aforementioned computer device can be a general-purpose computer device or a special-purpose computer device. In specific implementations, the computer device can be a desktop computer, a portable computer, a network server, a handheld digital assistant (PDA), a mobile phone, a tablet computer, a wireless terminal device, a communication device, or an embedded device. This application does not limit the type of computer device.

[0072] In addition, this application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described electrical performance testing method for a display driver board.

[0073] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0074] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for testing the electrical performance of a display driver board, characterized in that, Includes the following steps: A multi-stage stress sequence, including a single stress stage, a composite stress stage, and a nominal recovery stage, is applied to the display driver board, and electrical response data of the display driver board at each stage are collected. Based on the electrical response data of the single stress stage, a single stress sensitive parameter is obtained, and the single stress sensitive parameter is used to predict the theoretical response data of the display driver board in the composite stress stage. Interactive recovery residuals are obtained based on electrical response data from the nominal recovery stage. The interactive degradation coefficient of the display driver board is determined based on the predicted residual sequence between the electrical response data from the composite stress stage and the theoretical response data, as well as the interactive recovery residuals. Based on the single stress sensitive parameter and the interactive degradation coefficient, the dominant degradation type of the display driver board is identified, and the health test result of the electrical performance is output according to the dominant degradation type; Specifically, obtaining single-stress sensitive parameters based on electrical response data from a single stress stage includes: Extract electrical response data corresponding to the voltage-only change stage from the single stress stage, and obtain the electrical response value corresponding to each voltage step within the voltage-only change stage; Based on the reference voltage response value at the nominal operating voltage, determine the voltage response deviation of each voltage step relative to the reference voltage response value; Based on the correlation between voltage stress offset and voltage response deviation corresponding to all voltage steps, the voltage sensitivity parameters are obtained by fitting and solving. Extract electrical response data corresponding to the clock frequency change stage from the single stress stage, and obtain the electrical response value corresponding to each frequency step within the clock frequency change stage. Based on the reference frequency response value at the nominal operating clock frequency, determine the frequency response deviation of the electrical response value of each frequency step relative to the reference frequency response value; Based on the correlation between the frequency stress offset and the frequency response deviation corresponding to all frequency steps, the frequency sensitive parameters are generated by fitting and solving. The voltage-sensitive parameter and the frequency-sensitive parameter are used together as the single stress-sensitive parameter of the display driver board; Specifically, acquiring interactive recovery residuals based on electrical response data from the nominal recovery phase includes: The nominal recovery phase includes: a first nominal recovery phase following the voltage change phase within the single stress phase, a second nominal recovery phase following the clock frequency change phase within the single stress phase, and a third nominal recovery phase following the composite stress phase. Extract the electrical response data corresponding to the first nominal recovery stage, the second nominal recovery stage, and the third nominal recovery stage respectively; The difference between the electrical response data and the nominal response value at each nominal recovery stage is determined, and the first recovery residue, the second recovery residue, and the third recovery residue are obtained sequentially. Based on the first and second recovery residues, a single-stress recovery residue is constructed. The third recovery residue is then weighted and fused with the single-stress recovery residue after performing a differential operation, to obtain the interactive recovery residue of the display driver board.

2. The method as described in claim 1, characterized in that, A multi-stage stress sequence, including a single stress stage, a composite stress stage, and a nominal recovery stage, is applied to the display driver board, and electrical response data of the display driver board at each stage is collected. Specifically, this includes: The power management chip output test point, timing controller clock test point, and source driver data signal test point of the display driver board are connected through the test fixture. A multi-stage stress sequence consisting of voltage steps and frequency steps is applied to the display driver board. The multi-stage stress sequence includes a voltage-only change stage and a clock-only change stage that belong to a single stress stage, as well as a composite stress stage where voltage and clock frequency change simultaneously, and a nominal recovery stage is inserted between adjacent stages. At each stage, the ripple amplitude value of the power management chip output test point, the clock jitter value of the timing controller clock test point, and the setup time margin and hold time margin of the source driver data signal test point are collected respectively. Channel delay calibration is performed on the collected data to obtain electrical response data after time synchronization at each stage.

3. The method as described in claim 1, characterized in that, The specific methods for predicting the theoretical response data of the display driver board under combined stress using the aforementioned single stress sensitive parameter include: Obtain the nominal response value of the display driver board at the nominal operating voltage and nominal operating clock frequency; Extract the composite voltage offset of each stress step in the composite stress stage relative to the nominal operating voltage, and the composite frequency offset relative to the nominal operating clock frequency. For each combined stress step, based on the composite voltage offset, the voltage sensitive parameter in the single stress sensitive parameter is scaled to obtain the voltage response increment caused by voltage change under each combined stress step; For each combined stress step, based on the composite frequency offset, the frequency sensitive parameter in the single stress sensitive parameter is scaled to obtain the frequency response increment caused by the clock frequency change under each combined stress step. By combining the nominal response value, the voltage response increment, and the frequency response increment, the step-estimated response value corresponding to each combined stress step is obtained. The theoretical response data of the display driver board in the composite stress stage is constituted by all the step-estimated response values.

4. The method as described in claim 1, characterized in that, The interaction degradation coefficient of the display driver board is determined based on the predicted residual sequence between the electrical response data and the theoretical response data during the composite stress stage, as well as the interaction recovery residual. Specifically, this includes: The predicted residual sequence between the electrical response data and the theoretical response data in the composite stress stage, as well as the interactive recovery residual, are normalized respectively. Configure composite stress coupling weights, and perform feature aggregation on the predicted residual sequence based on the composite stress coupling weights to generate transient interactive residuals that reflect the degree of deviation of the transient response of the display driver board under multiple stress coupling effects; The transient interaction residual is generated by nonlinear saturation mapping, and the interaction recovery residual is obtained by nonlinear power scaling to obtain the recovery preservation degradation amount. The transient interaction degradation amount and the recovery retention degradation amount are synthesized to obtain the interaction degradation coefficient corresponding to the display driver board.

5. The method as described in claim 1, characterized in that, Based on the single stress sensitive parameter and the interactive degradation coefficient, the dominant degradation type of the display driver board is identified, and the health test results of electrical performance are output according to the dominant degradation type, specifically including: Based on the voltage-sensitive parameter and frequency-sensitive parameter in the single stress-sensitive parameters, the maximum component corresponding to each sensitive parameter is determined as the voltage stress degradation intensity and frequency stress degradation intensity of the display driver board. A degradation intensity determination vector is constructed based on the voltage stress degradation intensity, the frequency stress degradation intensity, and the interaction degradation coefficient; The degradation intensity determination vector is compared with a preset degradation determination threshold to identify the dominant degradation type corresponding to the display driver board. Based on the dominant degradation type and the degradation intensity determination vector, the electrical performance health level and abnormal location information of the display driver board are determined. Generate and output electrical performance health test results, which include the dominant degradation type of the display driver board, electrical performance health level, and anomaly location information.

6. An electrical performance testing system for a display driver board, used to perform an electrical performance testing method for a display driver board as described in any one of claims 1 to 5, characterized in that, include: The data acquisition module is used to load a multi-stage stress sequence, including a single stress stage, a composite stress stage, and a nominal recovery stage, onto the display driver board, and to acquire the electrical response data of the display driver board at each stage. The theoretical prediction module is used to obtain single-stress sensitive parameters based on the electrical response data of the single-stress stage, and to use the single-stress sensitive parameters to predict the theoretical response data of the display driver board in the composite stress stage. The coefficient solving module is used to obtain the interactive recovery residue based on the electrical response data of the nominal recovery stage, and to determine the interactive degradation coefficient of the display driver board based on the predicted residual sequence between the electrical response data of the composite stress stage and the theoretical response data and the interactive recovery residue. The result output module is used to identify the dominant degradation type of the display driver board based on the single stress sensitive parameter and the interactive degradation coefficient, and output the electrical performance health test result according to the dominant degradation type.

7. A computer device, characterized in that, The computer device includes a memory and a processor, the memory storing code, and the processor being configured to acquire the code and execute the electrical performance testing method for a display driver board as described in any one of claims 1 to 5.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the electrical performance testing method for a display driver board as described in any one of claims 1 to 5.

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