一种全CMOS低失调低温漂的电压基准电路
By combining a full CMOS architecture with local negative feedback, body drive, and source degradation resistors, the inherent offset and temperature drift problems of full CMOS voltage reference sources are solved, achieving low power consumption, low offset, and low temperature drift over a wide temperature range, making it suitable for IoT and wearable devices and other scenarios.
Patent Information
- Application Number
- CN202610866583.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-16
- Publication Date
- 2026-07-17
AI Technical Summary
Existing all-CMOS voltage reference sources suffer from problems such as large inherent offset voltage, high temperature drift over a wide temperature range, parasitic oscillations easily caused by traditional global negative feedback, and insufficient PVT stability, making it difficult to simultaneously achieve low inherent offset, low temperature drift, low voltage and low power consumption, and strong process robustness.
Adopting a full CMOS architecture, it abandons the traditional output global voltage negative feedback topology and integrates body drive threshold control, local chain negative feedback branch and reference voltage local self-calibration mechanism. Combined with local negative feedback, body drive Bulk and source degradation resistor, it achieves nanowatt-level low power consumption, low inherent offset and wide temperature range low temperature drift.
With a pure CMOS structure that eliminates BJTs and on-chip large-value passive resistors, it achieves low intrinsic offset, wide temperature range low temperature drift, and strong process robustness, making it suitable for deep submicron deep N-well processes and adaptable to IoT, wearable devices, and high-precision analog circuit applications.
Smart Images
Figure CN122411698A_ABST