A PCIe asset information processing method and device, electronic equipment and storage medium

Abstract

The present disclosure provides a PCIe asset information processing method and device, electronic equipment and storage medium, and relates to the technical field of computers. The method is applied to a baseboard management controller (BMC), and comprises the following steps: in a target shared memory, acquiring PCIe asset information written by a basic input / output system (BIOS); parsing first position information of each PCIe card from the PCIe asset information; based on hardware topology information in a server, sequentially accessing field replaceable units (FRUs) of risers to acquire second position information of each PCIe card on the risers; in response to the first position information being the same as the second position information, binding corresponding PCIe asset information and topology information of the riser to obtain association data; generating display information of the PCIe card based on the association data and performing rendering display; and the display information comprises a PCIe picture, PCIe asset information and topology information of the corresponding riser. Thus, the correspondence between asset information and actual hardware positions can be intuitively reflected.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a PCIe asset information processing method, apparatus, electronic device, and storage medium. Background Technology

[0002] With the rapid development of artificial intelligence and big data, the application scale of servers has reached ultra-large scale. Among the many characteristics of servers, "manageability" is crucial. The Baseboard Management Controller (BMC), as an important module in server hardware, is known as the server's health monitoring steward. It is responsible for hardware monitoring, remote management, and fault diagnosis. By monitoring information such as temperature, voltage, fan status, and peripheral component interconnect (PCIe) devices, it ensures the safe operation of the server and supports remote maintenance.

[0003] However, existing server BMC management interfaces have significant shortcomings in handling PCIe asset information. Currently, PCIe asset information is typically presented only as text or a list of characters on the BMC's web page, making it difficult for users to gain an intuitive understanding of hardware assets from tedious text. Furthermore, the display of PCIe asset information in existing technologies is usually not linked to the actual hardware location, lacking hardware correlation. Users cannot see the relationships between hardware components from the topology structure, making it difficult to quickly locate the actual hardware location when troubleshooting or understanding the server hardware architecture, thus causing inconvenience for operation and maintenance management. Summary of the Invention

[0004] This disclosure provides a PCIe asset information processing method, apparatus, electronic device, and storage medium to at least solve the above-mentioned technical problems existing in the prior art.

[0005] According to a first aspect of this disclosure, a PCIe asset information processing method is provided, applied to a baseboard management controller (BMC), the method comprising: In the target shared memory, obtain the PCIe asset information written by the Basic Input / Output System BIOS; the target shared memory is the shared memory between the BIOS and the BMC. The first location information of each PCIe card is parsed from the PCIe asset information; Based on the hardware topology information in the server, the field replaceable units (FRUs) of the expansion adapter card Riser are accessed sequentially to obtain the second location information of each PCIe card on the Riser; the second location information is written into the FRU of the Riser by the BIOS; If the first location information and the second location information are the same, the corresponding PCIe asset information is bound to the Riser's topology information to obtain associated data; Based on the associated data, display information for the PCIe card is generated and rendered; the display information includes PCIe images, PCIe asset information, and topology information of the corresponding Riser.

[0006] According to a second aspect of this disclosure, a PCIe asset information processing apparatus is provided, applied to a baseboard management controller (BMC), the apparatus comprising: The first acquisition module is used to acquire PCIe asset information written by the Basic Input / Output System (BIOS) in the target shared memory; the target shared memory is the shared memory between the BIOS and the BMC. The parsing module is used to parse the first location information of each PCIe card from the PCIe asset information; The second acquisition module is used to sequentially access the field replaceable units (FRUs) of the expansion adapter card Riser based on the hardware topology information in the server, and acquire the second location information of each PCIe card on the Riser; the second location information is written into the FRU of the Riser by the BIOS; The binding module is used to bind the corresponding PCIe asset information with the Riser's topology information in response to the first location information and the second location information being the same, so as to obtain associated data; The display module is used to generate and render display information of the PCIe card based on the associated data; the display information includes PCIe images, PCIe asset information and topology information of the corresponding riser.

[0007] According to a third aspect of this disclosure, an electronic device is provided, comprising: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the methods described in this disclosure.

[0008] According to a fourth aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions for causing the computer to perform the methods described in this disclosure.

[0009] This disclosure discloses a PCIe asset information processing method, apparatus, electronic device, and storage medium. It obtains PCIe asset information and parses first location information through the target shared memory between the BIOS and BMC. Based on hardware topology information, it accesses the expansion adapter card FRU to obtain second location information written by the BIOS. It binds the PCIe asset information corresponding to the consistent first and second location information with the expansion adapter card topology information to form associated data. Then, based on the associated data, it generates and renders display information containing PCIe images, asset information, and expansion adapter card topology information. This solves the problem that existing server PCIe asset information is presented only in text or character form, lacking hardware location association and resulting in unintuitive display. It also overcomes the shortcomings of asset information not corresponding to actual hardware locations and difficulty in quickly identifying hardware topology relationships and physical distribution. This ensures that users can intuitively grasp the hardware association between PCIe cards and expansion adapter cards, improving the efficiency of troubleshooting and hardware management.

[0010] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0011] The above and other objects, features, and advantages of this disclosure will become readily apparent from the following detailed description of exemplary embodiments, taken in conjunction with the accompanying drawings. Several embodiments of this disclosure are illustrated in the drawings by way of example and not limitation, in which: In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0012] Figure 1 A flowchart illustrating a PCIe asset information processing method according to an embodiment of this disclosure is shown. Figure 2 A schematic diagram of the structure of a PCIe asset information processing device according to an embodiment of the present disclosure is shown; Figure 3 A schematic diagram of the composition structure of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0013] To make the objectives, features, and advantages of this disclosure more apparent and understandable, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0014] Figure 1 A flowchart illustrating a PCIe asset information processing method according to an embodiment of this disclosure is shown, as follows: Figure 1 As shown, a PCIe asset information processing method, applied to a Baseboard Management Controller (BMC), includes: Step S101: Obtain PCIe asset information written by the Basic Input / Output System BIOS in the target shared memory.

[0015] In this embodiment, the BMC is a hardware management module independent of the server's main processor. It communicates with hardware components such as the server motherboard and expansion cards via a dedicated bus, and has the capabilities for independent operation, hardware monitoring, data processing, and information exchange. In one example, the BMC can implement a PCIe asset information processing method disclosed herein based on OpenBMC, which is an open-source operating system running on the BMC chip.

[0016] In this embodiment, the target shared memory is the shared memory between the BIOS and the BMC, specifically the HostToBMC (H2B) shared memory. This shared memory is a specific area pre-allocated in the server's physical memory, used to implement data communication and information exchange between the BIOS and the BMC. The physical address space of the H2B shared memory is visible to both the BIOS and the BMC. During the server boot process (POST phase), the BIOS accesses this shared memory area through the Memory-Mapped Input / Output (MMIO) mechanism and writes the asset information of all scanned and identified PCIe devices into the designated area of ​​this shared memory.

[0017] In this embodiment, PCIe asset information includes, but is not limited to: PCIe card vendor ID, device ID, subsystem vendor ID, subsystem device ID, serial number, firmware version number, asset tag, class code, and location string. This information is obtained by the BIOS during system initialization by enumerating the PCIe bus topology. Specifically, the BIOS obtains the aforementioned PCIe asset information by reading relevant registers in the PCIe configuration space.

[0018] In this embodiment, the BMC can access the system memory controller through its internal bus interface (such as the LPC bus or eSPI bus) to read the contents of the H2B shared memory. The firmware program running on the BMC side (such as the OpenBMC firmware) contains a dedicated H2B parsing module, which periodically or after receiving a BIOS completion signal reads raw data from the shared memory and parses it.

[0019] In this embodiment, the shared memory mechanism between the BIOS and BMC enables master-slave communication under the out-of-band management architecture, allowing the BMC to obtain detailed asset information of the server hardware even when the operating system has not yet started or the host is powered off, providing a data foundation for subsequent asset management and monitoring.

[0020] Step S102: Parse the first location information of each PCIe card from the PCIe asset information.

[0021] In this embodiment, after the BMC obtains the PCIe asset information in the H2B shared memory, the parsing engine in the BMC firmware performs structured parsing on the asset information, extracts the location-related fields contained therein, and obtains the first location information. The first location information is the LocationStr field, which is a string identifier used to uniquely identify the logical location of each PCIe card in the server's physical structure.

[0022] In this embodiment, the BMC parsing module splits the asset information data into fields according to a predefined data protocol, locates the byte offset of the LocationStr field, and extracts the string content of that field. During the parsing process, the BMC needs to handle character encoding conversion (such as ASCII to UTF-8), string length verification, and special character filtering to ensure that the extracted location information is accurate.

[0023] Step S103: Based on the hardware topology information in the server, sequentially access the field replaceable unit (FRU) of the expansion adapter card Riser to obtain the second location information of each PCIe card on the Riser.

[0024] In this embodiment, the hardware topology information in the server describes the physical connections and communication paths between various hardware components within the server, particularly the I2C (Inter-Integrated Circuit) bus topology, including the I2C bus number, I2C device address, I2C switch chip address, and channel ID. This topology information is predetermined by hardware engineers based on the motherboard design drawings and BOM (Bill of Materials) and configured in the BMC firmware.

[0025] In this embodiment, the Riser expansion adapter card is a hardware module used to expand the number of PCIe slots in a server. It typically connects to the PCIe root port on the motherboard via a high-speed connector. The Riser card integrates multiple PCIe slots for installing various PCIe expansion cards (such as network cards, graphics cards, RAID cards, etc.). Each Riser card is equipped with a Field Replaceable Unit (FRU) memory chip, typically an EEPROM (Electrically Erasable Programmable Read-Only Memory) or a FRU EEPROM, which connects to the BMC via an I2C bus.

[0026] In this embodiment, during the BIOS POST process, when a PCIe card is detected inserted into a specific slot of the Riser card, the BIOS writes the location information (i.e., second location information) of that PCIe card into the FRU memory chip of the corresponding Riser card. In one example, the BIOS writes a data packet containing LocationStr to a specific data area of ​​the Riser FRU via the System Management Bus (SMBus) or Direct Memory Access (DMA). This write operation is completed during the BIOS POST phase, ensuring that the Riser card has stored the location information of all PCIe cards it supports before the operating system starts.

[0027] In this embodiment, after the BIOS POST is completed, the BMC accesses the FRUs of each Riser card sequentially via the I2C bus according to the pre-configured hardware topology information. During the access process, the BMC first selects the corresponding I2C bus (such as I2C Bus 0, I2C Bus 1, etc.), and then addresses the FRU chip of the target Riser card through the I2C address. If there is an I2C switch in the I2C topology, the BMC also needs to configure the switch chip first, select the correct channel, and then access the downstream FRU device. After reading the data from the Riser FRU, the BMC can parse the read data and extract the stored PCIe card location information field, i.e., the second location information. The format of the second location information is consistent with the first location information, which is also a string type, used to identify the specific slot of the PCIe card on the Riser.

[0028] In step S104, in response to the first location information and the second location information being the same, the corresponding PCIe asset information is bound to the Riser's topology information to obtain associated data.

[0029] In this embodiment, after obtaining two sets of location information, the BMC performs a matching and comparison operation. Specifically, the BMC compares the first location information obtained by parsing the H2B shared memory with the second location information read from each Riser FRU. This comparison can employ a string exact matching algorithm, checking if every character of the two strings is identical. When the first and second location information are found to be completely identical, it indicates that the BMC has successfully established the correspondence between the PCIe asset information pushed by the BIOS and the physical Riser card and its slot. At this point, the BMC associates and binds the complete asset information of the PCIe card (including manufacturer ID, device ID, serial number, etc.) with the corresponding Riser topology information, generating associated data.

[0030] In one example, the riser's topology information includes, but is not limited to: the riser card's serial number, its I2C bus serial number, I2C device address, I2C switch channel number, the physical serial number of the PCIe slot on the riser card, and the mapping relationship between the slot and PCIe signals. This topology information describes the connection path and physical location of the PCIe card at the server hardware level.

[0031] Step S105: Generate display information for the PCIe card based on the associated data and render and display it.

[0032] In this embodiment, after generating the associated data, BMC uses it to construct graphical display information. The process of generating display information includes three stages: data preparation, content assembly, and rendering output.

[0033] During the data preparation phase, BMC extracts three core types of content from the associated data: The first type is PCIe images, which are graphical resources representing expansion card devices. These images can be pre-stored generic expansion card icons or schematic diagrams of specific types of devices; the second type is PCIe asset information, including text data such as manufacturer identification, device model, serial number, and firmware version; the third type is the topology information of the corresponding Riser, which is the bus connection path information of the expansion adapter card to which the expansion card is located, including bus number, device address, switch address, and channel number.

[0034] During the content assembly phase, BMC organizes the three types of content mentioned above into a structured display format. This format defines the arrangement and relationships of each element: PCIe images serve as the main visual element, occupying the majority of the display area; PCIe asset information serves as a text description element, which can be arranged around the image (such as above, below, or to the side), displaying various parameters in the form of labels, or it can be hidden and displayed when clicked; the riser's topology information serves as a connection path description, displayed in the form of graphical connections, indicating which bus path the expansion card connects to BMC through.

[0035] During the rendering output phase, the BMC converts the assembled display information into a format that can be parsed and displayed by the browser. This process uses Hypertext Markup Language to describe the page structure, Cascading Style Sheets (CSS) to define visual styles, and scripting languages ​​to implement dynamic interactions. During rendering, PCIe images are embedded in the page as image elements, with their source addresses pointing to the image resource path on the baseboard management controller; PCIe asset information is presented as text elements, with each parameter placed in an independent text container, and font, color, and layout defined through styles; the riser's topology information is presented as a hierarchical list or graphical connections, showing the complete path from the bus root node to the target device. The rendering engine calculates the size, position, and hierarchical relationship of each element and draws the final display interface in the browser window.

[0036] This disclosure establishes a reliable mapping relationship from logical asset information to physical location information through a dual data source design using H2B shared memory and Riser FRU storage mechanisms, solving the problem of lack of hardware correlation in asset information in traditional solutions. Through location information matching algorithms, it achieves automatic association and binding between BIOS-level asset data and BMC-level topology data, establishing accurate hardware asset profiles without manual intervention. Graphical rendering technology transforms abstract textual asset information into intuitive visual displays, enabling administrators to quickly understand the distribution and connection relationships of PCIe devices within the server. This disclosure supports operation in out-of-band management environments; even when the host operating system is not running or the server is powered off, the BMC can still independently complete the collection, association, and display of asset information, improving the reliability and real-time performance of server management.

[0037] In another embodiment, after step S102 "parse the first location information of each PCIe card from the PCIe asset information", the method further includes: A YAML file is created based on the input server hardware information, and the hardware topology information is determined based on the YAML file. The YAML file includes at least one of the following: the type of external hardware in the server, the I2C bus number, the I2C device address, the I2C switch chip address, and the channel number.

[0038] In this embodiment, the server hardware information is structured data compiled by hardware engineers based on technical documents such as server motherboard design drawings, schematics, PCB layout diagrams, and BOM lists. This hardware information describes the connection relationships of all external hardware components within the server that can be accessed via the I2C bus, particularly the physical connection topology of devices such as Riser expansion cards, PCIe devices, I2C switch chips, temperature sensors, and power management chips. YAML (YAML Ain't Markup Language) files are human-readable data serialization formats that use indentation to represent hierarchical structures, making them suitable for describing complex hardware topologies. The BMC receives the input hardware information, converts it into standard YAML format, and persistently stores it in the BMC's file system. The YAML file includes at least one of the following: the type of external hardware in the server, the I2C bus number, the I2C device address, the I2C switch chip address, and the channel number.

[0039] In this embodiment, after the YAML file is created, the BMC's I2C access engine loads the YAML file and uses a YAML parser to parse the file content into in-memory data structures (such as dictionaries, hash tables, or object trees). Based on the parsed data structures, the I2C access engine determines the hardware topology information, including: the I2C bus path of each Riser card, the I2C slave device address of each Riser card, the hierarchical structure and channel configuration of the I2C switch chips, and complete I2C routing information from the BMC to the target device. When the BMC needs to access the FRU of a specific Riser card, the I2C access engine queries the determined hardware topology information to obtain the I2C bus number, device address, and possible I2C switch channel numbers corresponding to that Riser card. Then, it configures the BMC's I2C controller and initiates I2C communication according to the topology path.

[0040] In this disclosure, a YAML file is used as an intermediate configuration layer to convert the design data provided by hardware engineers into a standardized data structure that can be parsed by the BMC. This enables versioned management and flexible updates of hardware topology information. When the server hardware design changes, only the YAML file needs to be updated without modifying the BMC firmware code. This allows the BMC to adapt to the differentiated hardware designs of different server models. By loading different YAML configuration files, multiple hardware platforms can be supported, enhancing the versatility and portability of the BMC firmware.

[0041] In another embodiment, step S105, "generating display information for the PCIe card based on associated data and rendering it," includes: Push the associated data to the BMC's internal communication bus; The web service based on BMC reads associated data from the internal communication bus through the Redfish interface and sends the associated data to the web user interface of BMC. Based on the web-based user interface, the system generates and renders display information about the PCIe card by associating data.

[0042] In this embodiment, after the associated data is generated within the BMC, it is first pushed to the BMC's internal communication bus to achieve data sharing and inter-process communication between different software modules. The internal communication bus adopts the D-Bus (Desktop Bus) system, which is an open-source inter-process communication mechanism widely used in Linux system environments and is particularly suitable for the firmware architecture of embedded devices such as BMCs.

[0043] In this embodiment, associated data can be read from the internal communication bus (D-Bus) via the Redfish interface based on the BMC's web service, and then sent to the BMC's web user interface (WebUI). The BMC web service (BMCweb) is the core component for implementing the out-of-band management web interface. This service provides web server functionality using HTTP and HTTPS protocols, supports RESTful API interfaces and dynamic web content services. The Redfish interface is an open standard API based on a RESTful architecture, specifically designed for out-of-band management of server hardware. Redfish can connect to the system bus through the D-Bus client library to listen for or query previously published associated data. When a frontend request is received or a data update is detected, the Redfish module reads the current value of the associated data from the D-Bus bus and then converts this data into JSON format conforming to the Redfish specification.

[0044] In this embodiment, the BMC web user interface (WebUI) is a front-end application running in the administrator's browser. The BMC web service can return JSON data containing related data to the WebUI front-end. After receiving the response, the WebUI parses the JSON data, extracts the PCIe asset information and Riser topology information, stores them in the front-end data model, and can perform the generation and rendering process of display information based on the PCIe asset information and Riser topology information.

[0045] In this disclosure, the D-Bus internal communication bus is used as a data intermediary layer to achieve decoupled communication between modules within the BMC firmware. The publishers and consumers of associated data can evolve independently, improving the flexibility and maintainability of the system architecture. The Redfish standardized interface is used as an external data service layer, enabling the BMC's PCIe asset data to be exposed in an industry-standard format. This not only supports access via the self-developed WebUI but is also compatible with third-party management tools and automated operation and maintenance platforms, enhancing the system's interoperability. Through a front-end template rendering mechanism, structured associated data is transformed into an intuitive visual interface, allowing administrators to obtain complete PCIe asset and topology information without understanding the underlying technical details, thus reducing management complexity.

[0046] In another embodiment, step S105, "generating display information for the PCIe card based on associated data and rendering it," includes: Based on the vendor information contained in the PCIe asset information in the associated data, the corresponding PCIe image is determined. Based on the topology information of the Riser in the associated data, a topology connection diagram of the Riser is generated. The PCIe image is displayed at the corresponding node in the topology diagram, and the PCIe asset information is bound to the PCIe image to obtain the display information and render it.

[0047] In this embodiment, the PCIe asset information in the associated data includes fields for identifying the device manufacturer, such as manufacturer ID or manufacturer name. PCIe images are pre-designed and stored in the baseboard management controller system or web server, including vector graphics or bitmap formats. Each image corresponds to a specific type of expansion card appearance, such as a full-height, full-length GPU card image, a half-height network card image, a RAID card image, a Fibre Channel card image, etc. The BMC can extract the manufacturer information field from the associated data and determine the matching PCIe image based on the manufacturer information field. If found, it can return the address of the image file for subsequent rendering; if not found, a default generic expansion card device image can be used as a substitute.

[0048] In this embodiment, the Riser topology information in the associated data includes structured data describing the expansion adapter card and its connection relationships, including the unique identifier of the Riser, the I2C bus number connected to the Riser, the I2C device address, the I2C switch chip address, and the channel ID. The process of generating the expansion adapter card topology diagram is executed by the graphics rendering engine of the web user interface front end, which includes node creation, connection drawing, and layout calculation.

[0049] First, node creation begins. The graphics rendering engine parses the riser topology information and creates a graphical node for each hardware component. Node types include: root node (representing the baseboard management controller or bus start point), switch node (representing the bus switch chip), riser node (representing the riser itself), and slot node (representing the high-speed interface slots for peripheral component interconnection on the riser). Each node is assigned a unique graphical element identifier and has visual attributes set, such as shape, size, fill color, and border style. The root node is typically located at the top or leftmost edge of the topology diagram, indicating the start of bus communication; the switch node is downstream of the root node, indicating the bus multiplexing point; the riser node is downstream of the switch node or directly connected to the root node; and the slot node is downstream of the riser node, indicating the specific installation location of the expansion card device.

[0050] Then, the wiring is drawn. The graphics rendering engine draws the connecting lines between the nodes according to the connection relationships in the topology information. The drawing of the connecting lines follows the actual physical connection path of the bus: the first connecting line is drawn from the root node to the switch node, representing the bus backbone; branch connecting lines are drawn from the switch node to its downstream riser node or slot node, with each branch corresponding to one channel of the switch; if there are multiple levels of cascaded switches, the next level of connecting lines is drawn. The connecting lines are in the form of straight lines or curves, and the line width, line color, and endpoint style are set. When multiple devices are connected to different channels of the same switch, the connecting lines fan out from the switch node, clearly showing the multiplexing structure.

[0051] Finally, layout calculations are performed. The graphics rendering engine uses a tree-like or hierarchical layout algorithm to automatically calculate the coordinates of each node on the two-dimensional plane, ensuring the topology diagram is aesthetically pleasing and easy to read. The layout algorithm considers factors such as node hierarchy, spacing between nodes in the same layer, vertical spacing between layers, and avoiding intersecting lines. After calculation, each node obtains its final x and y coordinate values, which are used for positioning in the scalable vector graphics or canvas.

[0052] In this embodiment, after generating the basic framework of the expansion adapter card topology diagram, the web user interface front-end associates the previously determined PCIe image with the corresponding node in the topology diagram and binds the PCIe asset information in text form with the image to form a complete visual display. The corresponding node refers to the slot node representing the PCIe slot in the topology diagram, which has a clear location identifier (such as the slot number) in the Riser topology information. When the associated data indicates that an expansion card device is installed in a slot, the graphics rendering engine creates an image container element at the coordinates of that slot node, loads and displays the previously determined PCIe image resource within the container. The image size is scaled to fit the size of the slot node, maintaining the original image's aspect ratio to avoid distortion. The center point of the image is aligned with the center point of the slot node, or offset and aligned according to design specifications.

[0053] In this embodiment, binding PCIe asset information to PCIe images refers to establishing a relationship between graphic elements and data, and realizing the visual presentation of information. The binding mechanism adopts a data attribute approach, embedding reference identifiers of related data in graphic elements, so that when users interact with the graphics, they can quickly retrieve the corresponding complete asset information. The visualization is presented in the form of information panels or tooltips: in static display mode, simplified asset information text, such as manufacturer name and device model, is displayed below or to the side of each expansion card image; in interactive mode, when the user hovers the mouse pointer over an expansion card image, a tooltip is triggered, displaying more detailed asset information, including serial number, firmware version, asset tags, etc.; when the user clicks on an expansion card image, a complete list of asset information, including all fields extracted from the related data, is displayed in the sidebar or pop-up panel. Thus, a complete, intuitive, and easy-to-use PCIe asset management display interface is obtained.

[0054] In this disclosure, a manufacturer-driven image matching mechanism is used to present different types of expansion card devices with their respective appearance images on the interface. Administrators can quickly identify the device type without reading the text, improving the efficiency of information acquisition. By generating a connection diagram based on bus topology information, the connection path and positional relationship of the expansion adapter card in the server hardware architecture are clearly displayed, making the abstract hardware connection relationship visual and concrete. By associating device images with topology nodes and binding detailed asset information, a complete information chain from physical location to logical information, from appearance recognition to technical parameters, is established, realizing a three-dimensional display of hardware assets.

[0055] In another embodiment, step S105, "generating display information for the PCIe card based on associated data and rendering it," includes: Based on the topological information of the Riser in the associated data, determine the first three-dimensional spatial coordinates of the Riser within the server; Based on the hardware topology information in the server, determine the second three-dimensional spatial coordinates of other hardware within the server; Based on the first and second three-dimensional spatial coordinates, generate and render three-dimensional display information of all hardware in the server.

[0056] In this embodiment, the Riser topology information in the associated data includes not only bus connection relationships but also descriptions of the Riser's physical location within the server chassis. This location description information is determined by hardware engineers during the design and manufacturing phases, recording the spatial position of the expansion adapter card relative to a reference point on the server chassis. The first three-dimensional spatial coordinates refer to the Riser's position coordinates in a three-dimensional coordinate system, typically represented using a Cartesian coordinate system, including three components: x, y, and z. Alternatively, a planar combination of hierarchical methods can be used, such as a Riser located on the third layer having x and y coordinates respectively.

[0057] In this embodiment, the hardware topology information in the server includes not only bus connections but also the physical location information of other key hardware components within the server. These other hardware components include: the central processing unit and its heatsink, memory modules and their slots, power supply modules, system fans, hard drive backplanes, motherboard chipsets, and the BMC itself. The second three-dimensional spatial coordinates of these other hardware components can be obtained based on the physical location identifiers of each component. The coordinates of each hardware component follow a unified coordinate system definition, ensuring the comparability of the coordinates and the accuracy of their relative positional relationships.

[0058] In this embodiment, after obtaining the first three-dimensional spatial coordinates of the Riser and the second three-dimensional spatial coordinates of other hardware, the 3D rendering engine at the front end of the web user interface generates a 3D visualization model of the entire server hardware and renders and displays it in the administrator's browser. The process of generating 3D display information includes four steps: model building, material mapping, lighting settings, and view configuration. In the model building step, the 3D rendering engine creates a solid geometric model based on the 3D coordinates and geometric dimensions of each hardware component. Each hardware component is represented as a 3D solid graphic; for example, the Riser is represented as a thin cuboid, the CPU heatsink as a cuboid with heat dissipation fins, the memory module as a slender cuboid, the power supply module as a large box, and the fan as a cylinder, etc. These solid graphics are placed in corresponding positions in the virtual 3D space according to their 3D coordinates, constructing a complete 3D scene of the server's internal hardware layout.

[0059] In the material mapping step, surface materials and textures are added to each 3D geometric model. For example, the riser uses a green circuit board texture, the CPU cooler uses a metallic silver texture, the memory modules use a black casing texture, the power supply module uses a metallic casing texture, and the fan uses a translucent plastic texture. For the PCIe slots on the riser, special interface identification textures are added to the slot locations for easy identification.

[0060] In the lighting setup step, virtual light sources are configured to illuminate the 3D scene, making the three-dimensionality and spatial relationships of the various hardware components clearer. Typically, a main light source is set up to shine from a slightly upward angle, creating contrast and shadow effects to enhance the realism of the 3D environment.

[0061] In the viewpoint configuration step, the initial viewing angle is set to either isometric or perspective, allowing administrators to view the entire internal structure of the server from a slightly upward angle. Camera control parameters are also configured to allow administrators to rotate the viewpoint, zoom in, and pan the observation point using the mouse, enabling them to view the hardware layout from different angles.

[0062] During rendering, the web user interface creates canvas elements in the browser and uses web graphics libraries or 3D graphics interface technologies for hardware-accelerated rendering. The information displayed to the administrator is an interactive 3D server model: the chassis is semi-transparent or hidden, and the internal hardware components are arranged according to their actual spatial positions. The riser is located in a specific position, and the expansion cards installed on it are presented in a 3D format. When the administrator clicks on a hardware component, that component is highlighted, and its detailed asset and topology information is displayed in the side information panel.

[0063] In this disclosure, the complex hardware layout inside a physical server is presented in the form of a virtual 3D model through precise calculation and mapping of three-dimensional spatial coordinates. This allows administrators to intuitively understand the actual spatial relationships of each hardware component within the chassis. By unifying all hardware components (including expansion cards, CPUs, memory, power supplies, etc.) into a 3D display, a global view of the server hardware architecture is provided, avoiding the limitations of focusing on a single component while ignoring the overall layout. Through interactive 3D rendering technology, administrators can freely adjust the viewing angle and zoom level to view hardware details from macro to micro perspectives. They can see an overview of the entire hardware distribution or focus on the details of a single expansion card, enabling them to quickly locate the physical position of the target device and improving the accuracy and efficiency of on-site operations.

[0064] In another embodiment, a PCIe asset information processing method further includes: In response to an abnormal operating status of the PCIe card, the corresponding PCIe image is highlighted in the display information; Based on the location information of the PCIe card, control the flashing of the positioning indicator light on the outside of the server.

[0065] In this embodiment, the BMC continuously monitors the operating status of each PCIe card within the server through an out-of-band monitoring mechanism. Abnormal operating status refers to deviations from normal operating parameters that occur during PCIe card operation, including but not limited to: excessively high temperature (exceeding a preset temperature threshold), abnormal voltage (deviating from the standard operating voltage range), fan failure (cooling fan stops or operates at too low a speed), communication errors (excessively high bus transmission error rate), performance degradation (operating frequency lower than the nominal value), or device offline (expansion card disappears from the bus), etc.

[0066] In this embodiment, the BMC's sensor monitoring module periodically reads the status registers and sensor data of each PCIe card and compares the read values ​​with preset safety thresholds. When a parameter of a PCIe card is detected to be outside the normal range, the PCIe card is determined to be in an abnormal operating state, triggering an abnormal event notification. The abnormal event notification is broadcast via the internal communication bus, and the web user interface frontend subscribes to and receives the notification.

[0067] In this embodiment, after receiving an abnormal event, the web page user interface performs a highlighting operation. Highlighting refers to changing the visual attributes of the PCIe image to make it stand out significantly in the displayed information, thereby attracting the administrator's attention. Specific implementation methods for highlighting include: changing the image's border color (e.g., changing the normal gray border to a red border), adding background color blocks to the image (e.g., adding a red or yellow semi-transparent background layer around the image), changing the image's brightness or contrast (e.g., increasing brightness or contrast to make the image more eye-catching), or adding dynamic effects (e.g., making the image periodically flash or pulsate).

[0068] In this embodiment, upon detecting an abnormal PCIe card operation status and highlighting it in the display information, the BMC also performs a physical location indication operation. This involves controlling the location indicator light on the outside of the server chassis to flash, helping on-site maintenance personnel quickly locate the faulty physical server. Location information refers to the physical location identifier of the PCIe card within the server, including the riser number and slot number. Based on this location information and a preset indicator light control strategy, the BMC determines which location indicator light needs to be activated.

[0069] In this embodiment, the server chassis is typically equipped with various status indicator lights, including: a power indicator light (indicating the server's power-on status), a hard disk activity indicator light (indicating disk read / write status), a system fault indicator light (indicating the overall system health status), and a positioning indicator light (used to identify the location of a specific server or component). The positioning indicator light can be a general-purpose positioning light on the front panel of the chassis, or a dedicated indicator light for a specific component (such as a slot indicator light for a riser). The BMC sends control signals to the indicator light's driver circuit via a general-purpose input / output interface or a dedicated lighting control interface. The control signal can use pulse width modulation or a simple high / low level switching method to make the indicator light flash at a specific frequency (e.g., flashing twice per second). The flashing pattern can distinguish between different degrees of fault severity; for example, a slow yellow flash indicates a general warning, while a fast red flash indicates a serious fault.

[0070] In this disclosure, by highlighting the image of the faulty expansion card in the display information, remote administrators can instantly identify the faulty device in the graphical interface without manually comparing a large amount of status data, thus improving the efficiency of remote fault diagnosis. By controlling the flashing of the external positioning indicator light on the server, clear physical guidance is provided to on-site maintenance personnel, solving the problem of difficulty in quickly locating the target server and specific faulty components in densely deployed environments. By utilizing the existing out-of-band monitoring capabilities and indicator light control interface of BMC, a low-cost fault visualization alarm function is achieved without the need for additional dedicated hardware deployment.

[0071] In another embodiment, a PCIe asset information processing method further includes: In response to the detection of a hot-plugging operation of a PCIe card, the first location information and the second location information are reacquired, and the associated data is updated. The displayed information is updated based on the updated associated data.

[0072] In this embodiment, hot-swapping refers to the physical operation of inserting or removing a PCIe card without powering off the server. Modern servers typically support hot-swapping in their PCIe slots, allowing administrators to replace expansion cards while the system is running, improving system availability and ease of maintenance. The BMC can detect hot-swapping operations through several mechanisms. The first mechanism is bus status monitoring: the BMC periodically scans the bus topology to detect the appearance of new devices (hot-insertion) or the disappearance of existing devices (hot-removal). The second mechanism is a physical detection signal: the slot on the riser is equipped with an presence detection pin; when an expansion card is inserted, the level of this pin changes, and the BMC captures this change signal through the general-purpose input / output interface. The third mechanism is firmware notification: after detecting a hot-swapping event, the BIOS notifies the BMC via shared memory or an interrupt mechanism.

[0073] In this embodiment, when the BMC detects a hot-plug operation, it triggers a data update process. This process is similar to the initial startup process, but requires incremental updates for the changed parts. The process of re-acquiring the first location information is as follows: the BMC reads the shared memory region to obtain the PCIe asset information updated by the BIOS. Since the hot-plug operation may have changed the device in the slot, the BIOS will rescan the affected slot and update the asset information at that location, including the vendor number, device number, serial number, and location string of the newly inserted device, or clear the asset information of the removed device. The process of re-acquiring the second location information is as follows: the BMC accesses the FRU of the changed riser based on the hardware topology information and reads the updated location information. For a hot-plug operation, the location string of the new PCIe card is written into the FRU; for a hot-plug operation, the BIOS clears the location information field corresponding to the slot, and the BMC receives a null value or an invalid flag when reading.

[0074] In this embodiment, the BMC matches the newly acquired first and second location information. For a newly inserted PCIe card, if the location strings match successfully, the BMC creates a new associated data record containing the asset information of the new PCIe card and the topology information of the riser it resides in. For a removed expansion card, the BMC detects that the first or second location information of the slot has become invalid, and therefore deletes the associated data record corresponding to the PCIe card. For PCIe cards whose location has not changed, their original associated data is retained.

[0075] In this embodiment, after the associated data is updated, the web user interface front-end synchronously updates the displayed information to reflect the latest status of the PCIe card. The update process adopts an incremental update mechanism, refreshing only the changed parts, avoiding re-rendering the entire page, improving update efficiency and user experience. For newly inserted PCIe cards, the web user interface adds a PCIe image display at the corresponding slot node in the topology diagram. First, the front-end determines the corresponding PCIe image type based on the asset information in the new associated data; then, a new image element is created at the coordinate position of the slot node in the topology diagram, loading and displaying the corresponding PCIe image; simultaneously, an interactive event of asset information is bound to the image, allowing the administrator to view the detailed information of the new PCIe card. The display of the new PCIe image can use a fade-in animation effect to prompt the administrator that a new device has been added to this location. For hot-removed PCIe cards, the web user interface removes the PCIe image display from the corresponding slot node in the topology diagram. First, the front-end detects that the associated data for the slot has been deleted; then, it removes the image elements and bound interactive events from the slot node; the slot node is restored to its idle state display style (e.g., displayed as a gray empty slot icon or only showing the slot number). The removal operation can use a fade-out animation effect to notify the administrator that the device at that location has been removed.

[0076] In this embodiment, the updated display information is reflected in the administrator's browser interface in real time. The administrator can see the latest hardware layout after the hot-swap operation without manually refreshing the page. If a hot-swap operation occurs while the administrator is viewing the display information, they can intuitively see the expansion card image appear or disappear in the corresponding position, and promptly grasp the hardware change.

[0077] In this disclosure, the BMC's proactive detection and response to hot-plug events enables the system to promptly detect changes to PCIe cards without requiring server restarts or manual scanning, thus improving the automation of hardware changes. By reacquiring location information and updating associated data, the accuracy and timeliness of asset data are ensured, avoiding data inconsistencies caused by hot-plug operations, such as removed devices still appearing in the asset list or newly inserted devices not being recognized. Through incremental updates of displayed information, administrators can observe the effects of hardware changes in real time without manually refreshing the page or logging back into the system, enhancing the convenience and real-time nature of remote management.

[0078] In another embodiment, a PCIe asset information processing method further includes: In response to input operations on the displayed information, highlight the corresponding PCIe image, PCIe asset information, and Riser topology information; The input operation includes at least one of the following: click operation, selection operation, box selection operation, and drag operation; the highlighting includes at least one of the following: highlighting, magnification, coloring, and pinning to the top.

[0079] In this embodiment, the web user interface allows administrators to interact with the displayed information through various interactive methods. When an administrator performs a specific input operation on the displayed information in the browser, the system recognizes the operation and responds, highlighting the PCIe image pointed to by the operation, the asset information of the PCIe card, and the topology information of the Riser where the PCIe card is located.

[0080] In this embodiment, input operations refer to interactive commands sent by the administrator to the web user interface via input devices such as a mouse, keyboard, or touchscreen. The system captures these operations through an event listening mechanism, including mouse events (such as mouse press, mouse move, mouse release), keyboard events (such as key press), and touch events (such as single-finger touch, multi-finger touch). When a valid input operation is detected, the system determines the target object of the operation (i.e., the PCIe image or topology area being operated on), and then highlights the target object and its associated information elements.

[0081] In this embodiment, the highlighted scope includes three levels: first, the PCIe image itself, i.e., the graphic elements that the administrator can directly manipulate; second, the asset information of the PCIe card, including text information such as manufacturer, model, and serial number, which can be displayed next to the image or in the information panel; and third, the topology information of the Riser where the PCIe card is located, including structural information such as bus connection path, switch level, and slot position.

[0082] In this embodiment, a click operation refers to the administrator's action of briefly pressing and releasing the mouse or finger. Click operations are divided into single-click and double-click: a single click selects a specific expansion card image, making it selected, and the system highlights the expansion card and its related information; a double click opens the expansion card's detailed information page or performs a default operation (such as viewing real-time status monitoring). A selection operation refers to the administrator selecting a specific expansion card image by clicking or using keyboard navigation (such as using the up, down, left, and right arrow keys to move the focus). Selection operations support multi-selection using function keys (such as control keys or the shift key), allowing simultaneous selection of multiple expansion card images for batch viewing or comparative analysis. A bounding box selection operation refers to the administrator holding down the left mouse button or touching the screen to draw a rectangular selection box, selecting multiple expansion card images within the box. Drag and drop refers to the action of an administrator who presses and holds the expansion card image and moves the mouse or finger to drag the image to another location. In the displayed information, drag and drop can be used to rearrange the layout of expansion card images (such as adjusting the display order in a custom view) or drag and drop expansion card images to a specified area to perform specific functions (such as dragging and dropping the device to be maintained to the maintenance area to generate a maintenance work order). During the drag and drop process, the dragged expansion card image remains highlighted to provide visual feedback that the object is being operated on.

[0083] In this embodiment, highlighting refers to making the target element more visually prominent by increasing brightness, contrast, or adding a glowing effect. Highlighting can manifest as a glowing border around an image, a highlighted background color for text, or an overall increase in the brightness of the element. Zooming in refers to proportionally enlarging the display size of the target element, allowing it to occupy more screen space and making details more clearly visible. Zooming in can be a smooth transition (such as animated zooming) or a direct switch (such as jumping to a zoomed-in view). Shading refers to changing the color attributes of the target element, including border color, fill color, or text color. Shading can use specific color codes to convey different meanings, such as blue indicating a normal selected state, red indicating a fault state, green indicating a newly inserted device, and yellow indicating a warning state. Placing the target element on top refers to adjusting the target element to the top of the display hierarchy, covering other potentially overlapping elements, ensuring the target element is fully visible and interactive. Placing the target element on top is suitable for complex topology graphs with dense elements and a risk of overlap.

[0084] In this disclosure, by supporting multiple input operations (click, select, box selection, drag and drop), the interaction needs of different scenarios are met. Administrators can choose the most appropriate operation method according to specific tasks, which improves the flexibility of information query and operation. Through multiple highlighting methods (highlight, zoom, color, pin to top), a rich visual feedback mechanism is established, which enables administrators to quickly identify the object of the current operation and its context information, reducing the risk of getting lost in complex topologies.

[0085] Figure 2 A schematic diagram of the structure of a PCIe asset information processing device according to an embodiment of this disclosure is shown, as follows: Figure 2 As shown, a PCIe asset information processing device, applied to a baseboard management controller (BMC), includes: The first acquisition module 10 is used to acquire PCIe asset information written by the Basic Input / Output System BIOS in the target shared memory; the target shared memory is the shared memory between the BIOS and the BMC. Parsing module 11 is used to parse the first location information of each PCIe card from the PCIe asset information; The second acquisition module 12 is used to sequentially access the field replaceable unit (FRU) of the expansion adapter card Riser based on the hardware topology information in the server, and obtain the second location information of each PCIe card on the Riser; the second location information is written into the FRU of the Riser by the BIOS. Binding module 13 is used to bind the corresponding PCIe asset information with the Riser's topology information in response to the first location information and the second location information being the same, so as to obtain associated data; Display module 14 is used to generate and render display information of PCIe cards based on associated data; the display information includes PCIe images, PCIe asset information and topology information of the corresponding Riser.

[0086] In another embodiment, the second acquisition module 12 is further configured to: A YAML file is created based on the input server hardware information, and the hardware topology information is determined based on the YAML file. The YAML file includes at least one of the following: the type of external hardware in the server, the I2C bus number, the I2C device address, the I2C switch chip address, and the channel number.

[0087] In another embodiment, the display module 14 is further configured to: Push the associated data to the BMC's internal communication bus; The web service based on BMC reads associated data from the internal communication bus through the Redfish interface and sends the associated data to the web user interface of BMC. Based on the web-based user interface, the system generates and renders display information about the PCIe card by associating data.

[0088] In another embodiment, the display module 14 is further configured to: Based on the vendor information contained in the PCIe asset information in the associated data, the corresponding PCIe image is determined. Based on the topology information of the Riser in the associated data, a topology connection diagram of the Riser is generated. The PCIe image is displayed at the corresponding node in the topology diagram, and the PCIe asset information is bound to the PCIe image to obtain the display information and render it.

[0089] In another embodiment, the display module 14 is further configured to: Based on the topological information of the Riser in the associated data, determine the first three-dimensional spatial coordinates of the Riser within the server; Based on the hardware topology information in the server, determine the second three-dimensional spatial coordinates of other hardware within the server; Based on the first and second three-dimensional spatial coordinates, generate and render three-dimensional display information of all hardware in the server.

[0090] In another embodiment, a PCIe asset information processing device further includes an alert module for: In response to an abnormal operating status of the PCIe card, the corresponding PCIe image is highlighted in the display information; Based on the location information of the PCIe card, control the flashing of the positioning indicator light on the outside of the server.

[0091] In another embodiment, a PCIe asset information processing apparatus further includes an update module for: In response to the detection of a hot-plugging operation of a PCIe card, the first location information and the second location information are reacquired, and the associated data is updated. The displayed information is updated based on the updated associated data.

[0092] In another embodiment, a PCIe asset information processing apparatus further includes a response module for: In response to input operations on the displayed information, highlight the corresponding PCIe image, PCIe asset information, and Riser topology information; The input operation includes at least one of the following: click operation, selection operation, box selection operation, and drag operation; the highlighting includes at least one of the following: highlighting, magnification, coloring, and pinning to the top.

[0093] According to embodiments of this disclosure, this disclosure also provides an electronic device and a readable storage medium.

[0094] Figure 3A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0095] like Figure 3 As shown, the electronic device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. The RAM 803 may also store various programs and data required for the operation of the electronic device 800. The computing unit 801, ROM 802, and RAM 803 are interconnected via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0096] Multiple components in electronic device 800 are connected to I / O interface 805, including: input unit 806, such as keyboard, mouse, etc.; output unit 807, such as various types of displays, speakers, etc.; storage unit 808, such as disk, optical disk, etc.; and communication unit 809, such as network card, modem, wireless transceiver, etc. Communication unit 809 allows electronic device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0097] The computing unit 801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as a PCIe asset information processing method. For example, in some embodiments, a PCIe asset information processing method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of a PCIe asset information processing method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform a PCIE asset information processing method by any other suitable means (e.g., by means of firmware).

[0098] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0099] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0100] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0101] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0102] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0103] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0104] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this disclosure can be achieved, and this is not limited herein.

[0105] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0106] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A PCIe asset information processing method, characterized in that, The method, applied to a baseboard management controller (BMC), includes: In the target shared memory, obtain the PCIe asset information written by the Basic Input / Output System BIOS; the target shared memory is the shared memory between the BIOS and the BMC. The first location information of each PCIe card is parsed from the PCIe asset information; Based on the hardware topology information in the server, the field replaceable units (FRUs) of the expansion adapter card Riser are accessed sequentially to obtain the second location information of each PCIe card on the Riser; the second location information is written into the FRU of the Riser by the BIOS; If the first location information and the second location information are the same, the corresponding PCIe asset information is bound to the Riser's topology information to obtain associated data; Based on the associated data, display information for the PCIe card is generated and rendered; the display information includes PCIe images, PCIe asset information, and topology information of the corresponding Riser.

2. The method according to claim 1, characterized in that, After parsing the first location information of each PCIe card from the PCIe asset information, the method further includes: A YAML file is created based on the input server hardware information, and the hardware topology information is determined based on the YAML file; the YAML file includes at least one of the following: the type of external hardware in the server, the I2C bus number, the I2C device address, the I2C switch chip address, and the channel number.

3. The method according to claim 1, characterized in that, The step of generating and rendering the display information of the PCIe card based on the associated data includes: The associated data is pushed to the BMC's internal communication bus; The web service based on the BMC reads the associated data from the internal communication bus through the Redfish interface and sends the associated data to the web user interface of the BMC. Based on the webpage user interface, the display information of the PCIe card is generated and rendered using the associated data.

4. The method according to claim 1, characterized in that, The step of generating and rendering the display information of the PCIe card based on the associated data includes: Based on the vendor information contained in the PCIe asset information in the associated data, the corresponding PCIe image is determined; Based on the topology information of the Riser in the associated data, a topology connection diagram of the Riser is generated. The PCIe image is displayed at the corresponding node in the topology diagram, and the PCIe asset information is bound to the PCIe image to obtain the display information and render it.

5. The method according to claim 1, characterized in that, The step of generating and rendering the display information of the PCIe card based on the associated data includes: Based on the topological information of the Riser in the associated data, the first three-dimensional spatial coordinates of the Riser within the server are determined; Based on the hardware topology information in the server, determine the second three-dimensional spatial coordinates of other hardware within the server; Based on the first and second three-dimensional spatial coordinates, three-dimensional display information of all hardware in the server is generated and rendered.

6. The method according to claim 1, characterized in that, The method further includes: In response to an abnormal operating status of the PCIe card, the corresponding PCIe image is highlighted in the display information; Based on the location information of the PCIe card, the positioning indicator light on the outside of the server is controlled to flash.

7. The method according to claim 1, characterized in that, The method further includes: In response to detecting a hot-plug operation of the PCIe card, the first location information and the second location information are reacquired, and the associated data is updated; The displayed information is updated based on the updated associated data.

8. The method according to claim 1, characterized in that, The method further includes: In response to an input operation on the displayed information, the PCIe image, PCIe asset information, and Riser topology information corresponding to the input operation are highlighted; The input operation includes at least one of click operation, selection operation, box selection operation and drag operation; the highlighting includes at least one of highlighting display, magnification display, color display and top display.

9. A PCIe asset information processing device, characterized in that, The device, applied to a baseboard management controller (BMC), includes: The first acquisition module is used to acquire PCIe asset information written by the Basic Input / Output System (BIOS) in the target shared memory; the target shared memory is the shared memory between the BIOS and the BMC. The parsing module is used to parse the first location information of each PCIe card from the PCIe asset information; The second acquisition module is used to sequentially access the field replaceable units (FRUs) of the expansion adapter card Riser based on the hardware topology information in the server, and acquire the second location information of each PCIe card on the Riser; the second location information is written into the FRU of the Riser by the BIOS; The binding module is used to bind the corresponding PCIe asset information with the Riser's topology information in response to the first location information and the second location information being the same, so as to obtain associated data; The display module is used to generate and render display information of the PCIe card based on the associated data; the display information includes PCIe images, PCIe asset information and topology information of the corresponding riser.

10. The apparatus according to claim 9, characterized in that, The second acquisition module is further configured to: A YAML file is created based on the input server hardware information, and the hardware topology information is determined based on the YAML file; the YAML file includes at least one of the following: the type of external hardware in the server, the I2C bus number, the I2C device address, the I2C switch chip address, and the channel number.

11. The apparatus according to claim 9, characterized in that, The display module is also used for: The associated data is pushed to the BMC's internal communication bus; The web service based on the BMC reads the associated data from the internal communication bus through the Redfish interface and sends the associated data to the web user interface of the BMC. Based on the webpage user interface, the display information of the PCIe card is generated and rendered using the associated data.

12. The apparatus according to claim 9, characterized in that, The display module is also used for: Based on the vendor information contained in the PCIe asset information in the associated data, the corresponding PCIe image is determined; Based on the topology information of the Riser in the associated data, a topology connection diagram of the Riser is generated. The PCIe image is displayed at the corresponding node in the topology diagram, and the PCIe asset information is bound to the PCIe image to obtain the display information and render it.

13. The apparatus according to claim 9, characterized in that, The display module is also used for: Based on the topological information of the Riser in the associated data, the first three-dimensional spatial coordinates of the Riser within the server are determined; Based on the hardware topology information in the server, determine the second three-dimensional spatial coordinates of other hardware within the server; Based on the first and second three-dimensional spatial coordinates, three-dimensional display information of all hardware in the server is generated and rendered.

14. An electronic device, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-8.

15. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-8.

Images