Register enable logic circuit generation method, electronic device, and storage medium

Abstract

The application belongs to the technical field of electronic design automation, and discloses a generation method of a register enable logic circuit, an electronic device and a storage medium. The method comprises the following steps: determining an ODC expression corresponding to a target register output end, and generating an initial logic circuit according to the logical relationship between control signals in the ODC expression; performing signal extension on the control signals in the ODC expression to obtain an extended logic circuit containing boundary signals; performing timing checking on register output signals in the boundary signals, and performing logic verification on the existing enable logic between a first register corresponding to a candidate signal and the target register; and removing useless signals in the extended logic circuit through logic simplification to generate an enable logic circuit used for controlling a clock gating unit corresponding to the target register. The application can generate an enable logic circuit according to an ODC expression to control the clock gating of a register, so as to reduce dynamic power consumption.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation technology, and in particular to a method for generating register-enabled logic circuits, an electronic device, and a storage medium. Background Technology

[0002] With advancements in manufacturing and design technologies, the design methodology for integrated circuits (ICs) has undergone profound changes. From Computer-Aided Design (CAD) and Computer-Aided Engineering (CAE) to Electronic Design Automation (EDA), the degree of automation in design has increased significantly, and the complexity of designs has also grown considerably. Currently, EDA technology has become a powerful tool in modern electronic design. Without the support of EDA technology, it would be unimaginable to design and manufacture very large-scale integrated circuits. IC designers need to utilize EDA tools to develop complex integrated circuits with hundreds of thousands to tens of billions of transistors to reduce design deviations, improve tape-out success rates, and save on tape-out costs.

[0003] In IC design, dynamic power consumption is a crucial factor affecting chip power performance. Clock trees typically have high toggling frequencies and significant loads within chips, thus their power consumption accounts for a large proportion of the chip's dynamic power consumption. To reduce dynamic power consumption, related technologies often employ clock gating integrated cells (CGICs) to control the clock signals of registers or modules, shutting down the corresponding clock signals when the register or module is in an inactive state, thereby reducing unnecessary clock toggling.

[0004] In RTL (Register Transfer Level) design and synthesis flows, clock gating units are typically inserted automatically by EDA tools based on register enable conditions. These enable conditions are generally determined by the designer based on register write conditions, state transition conditions, or related Boolean logic. Therefore, the effectiveness of clock gating depends to some extent on the designer's understanding of circuit functionality, cross-module signal transmission relationships, and low-power scenarios. For larger, more complex designs with deeper hierarchies or more intricate cross-module signal relationships, some enable conditions suitable for gating may not be fully identified, leading to clock flips in registers even when their outputs are not observable for subsequent paths.

[0005] ODC (Observability Don't Care) characterizes the state where changes in the output of a node or register under specific conditions are not observable by subsequent paths. By utilizing ODC, scenarios where register outputs have no impact on subsequent logic can be identified, thus providing a basis for reducing the dynamic power consumption of registers and their related paths. However, the ODC expressions obtained from ODC generation or propagation methods in related technologies are usually not directly usable as enable signals for clock gating units. Therefore, even if it has been identified that the register output is unobservable to subsequent paths in some scenarios, it is still difficult to directly use the ODC result to turn off the gating clock corresponding to the relevant register. This results in the register still potentially clock-flipping even without effective observation requirements, leading to redundant dynamic power consumption and reducing the effectiveness of power optimization. Summary of the Invention

[0006] This invention provides a method for generating register enable logic circuits, an electronic device, and a storage medium, to at least solve the problem in related technologies where ODC cannot be directly used to control the enable logic of gated clocks, resulting in low power consumption optimization efficiency. The technical solution of this invention is as follows: According to a first aspect of the present invention, a method for generating a register enable logic circuit is provided, comprising: determining an ODC expression corresponding to the output terminal of a target register, and generating an initial logic circuit based on the logical relationship between control signals in the ODC expression; extending the control signals in the ODC expression to a boundary signal, and adding the logic devices passed through during the signal extension process to the initial logic circuit to obtain an extended logic circuit containing the boundary signal; performing a timing check on the register output signal in the boundary signal to determine a candidate signal in the register output signal that satisfies the timing consistency condition with the target register, and performing a logic verification on the existing enable logic between the first register corresponding to the candidate signal and the target register; removing useless signals in the extended logic circuit by logic simplification to generate an enable logic circuit for controlling a clock gating unit corresponding to the target register, wherein the useless signals include non-register output signals in the boundary signal and register output signals that fail the timing check and / or the logic verification.

[0007] According to a second aspect of the present invention, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions, wherein, when executed by the processor, the processor causes the processor to execute a method for generating register-enabled logic circuits according to the present invention.

[0008] According to a third aspect of the present invention, a computer-readable storage medium is provided, wherein when instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform a method for generating register-enabled logic circuits according to the present invention.

[0009] The technical solution provided by this invention brings at least the following beneficial effects: This invention can process the ODC expression corresponding to the output of the target register to generate an enable logic circuit that can be used to control the clock gating unit of the target register. This allows the ODC expression, which is originally difficult to use directly to control the gated clock, to be converted into a gated control logic that can be implemented. In this way, unnecessary flipping of the clock signal corresponding to the target register can be reduced when the output of the target register is not observable to the subsequent path, thereby reducing the redundant dynamic power consumption of the circuit and improving the power consumption optimization effect.

[0010] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0011] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention, but do not constitute an undue limitation of the invention.

[0012] Figure 1 This is a flowchart illustrating a method for generating a register-enabled logic circuit according to an exemplary embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the conversion of an ODC expression into a logic circuit according to an exemplary embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the extension of the ODC expression signal according to an exemplary embodiment of the present invention; Figure 4 This is a schematic diagram illustrating fan-in scale control in an extension according to an exemplary embodiment of the present invention; Figure 5 This is a schematic diagram illustrating a timing check according to an exemplary embodiment of the present invention; Figure 6 This is a schematic diagram illustrating a logic verification according to an exemplary embodiment of the present invention; Figure 7 This is a block diagram illustrating an electronic device according to an exemplary embodiment of the present invention. Detailed Implementation

[0013] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0014] It should be noted that the steps in the specification and drawings of this invention are not limited to the specific order or sequence described. It should be understood that the steps used in this way can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in a sequence other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.

[0015] In integrated circuit design, enable logic is the core mechanism for achieving modularity, coordination, and low-power control. It uses a dedicated enable signal to control whether a circuit unit is activated and performs its function.

[0016] As mentioned earlier, in related technologies, the ODC expression generated / propagated through ODC cannot be directly used as the enable signal for clock gating units. This is at least partly because the signals in the ODC expression originate from logic devices containing control signals, such as multiplexers and tri-state gates. These signals may have timing inconsistencies with the relevant registers, such as a one-clock-cycle delay. Directly using them to control the gating clock of the relevant registers could lead to register malfunctions or timing abnormalities.

[0017] For today's increasingly large-scale and complex integrated circuit designs, how to efficiently synthesize ODC to obtain enable logic that meets timing and logic requirements and can be directly used to control gated clocks has become a pressing problem for the industry.

[0018] In view of the above problems, exemplary embodiments of the present invention propose a method for generating register enable logic circuits, an electronic device, and a computer-readable storage medium. By extending each signal in the ODC to the output terminal of a specified type of device, then filtering out the usable signals through timing checks and logic verification, and finally synthesizing multiple usable signals into an enable logic circuit for use as the enable logic of a gated clock, the above problems can be solved or at least alleviated.

[0019] In a first aspect of an exemplary embodiment of the present invention, a method for generating a register-enabled logic circuit is provided, which will be described below with reference to Figures 1 to 6 Provide a detailed description.

[0020] According to an exemplary embodiment of the present invention, the method for generating register enable logic circuits is applicable to electronic design automation (EDA) software. A user terminal can load the EDA software, enabling the user terminal to determine the ODC expression corresponding to the output of the target register and generate an initial logic circuit based on the logical relationships between the control signals in the ODC expression. The control signals in the ODC expression are extended to boundary signals, and the logic devices passed through during the signal extension process are added to the initial logic circuit to obtain an extended logic circuit containing boundary signals. Timing checks are performed on the register output signals in the boundary signals to determine candidate signals that satisfy the timing consistency condition with the target register, and the existing enable logic between the first register corresponding to the candidate signals and the target register is logically verified. Useless signals in the extended logic circuit are removed through logical simplification to generate an enable logic circuit for controlling the clock gating unit corresponding to the target register. The useless signals include non-register output signals in the boundary signals and register output signals that fail the timing check and / or logical verification.

[0021] This method can generate an enable logic circuit that can be used to control the clock gating unit of the target register by processing the ODC expression corresponding to the output of the target register. This allows the ODC expression, which is originally difficult to use directly to control the gated clock, to be converted into a gated control logic that can be implemented. In this way, unnecessary toggling of the clock signal corresponding to the target register can be reduced when the output of the target register is not observable to the subsequent path, thereby reducing the redundant dynamic power consumption of the circuit and improving the power consumption optimization effect.

[0022] The aforementioned user terminal can be such as a tablet computer, laptop computer, digital assistant, wearable device, etc. However, the implementation scenario of the register enable logic circuit generation method described above is only an example scenario. The register enable logic circuit generation method according to the exemplary embodiment of the present invention can also be applied to other application scenarios. For example, it can also be that a user requests access to relevant data from a server via a network on a user terminal (e.g., mobile phone, desktop computer, tablet computer, etc.). The server can access the data by executing the register enable logic circuit generation method according to the exemplary embodiment of the present invention and return the result to the user terminal. Here, the server can be an independent server, a server cluster, a cloud computing platform, or a virtualization center, etc.

[0023] The following will refer to Figure 1 The specific steps of a method for generating a register-enabled logic circuit according to an exemplary embodiment of the present invention are described below. Figure 1 As shown, the method for generating the register enable logic circuit may include the following steps: In step S110, the ODC expression corresponding to the output of the target register can be determined, and the initial logic circuit can be generated according to the logical relationship between each control signal in the ODC expression.

[0024] Here, Chinese invention patent application number CN202510863861.0 discloses a dynamic power consumption optimization method, electronic device, and storage medium, specifically proposing an ODC generation / propagation scheme. The ODC generation / propagation technique in this invention can be used to obtain the ODC expression in the exemplary embodiments of this invention. For the sake of brevity, it will not be elaborated further here. Furthermore, the ODC expression can be stored in a tree structure, such as, but not limited to, a general binary tree.

[0025] According to an exemplary embodiment of the present invention, the ODC expression can be parsed starting from the root node of the tree structure; when a non-leaf node representing a logic device is parsed, a logic gate corresponding to the non-leaf node is generated in the initial logic circuit; when a leaf node is parsed, the control signal corresponding to the leaf node is used as the input signal of the corresponding logic gate for subsequent signal extension.

[0026] In other words, for the ODC expression corresponding to the output of the target register, since its storage structure is a tree structure such as a general binary tree, it can be parsed starting from the root node, generating the corresponding logic circuit according to the type of each node. For example, when a non-leaf node representing a logic device is encountered, the corresponding logic gate is generated; when a leaf node is encountered, it is retained as the input signal of the logic gate, and then extended. After all the nodes in the tree structure have been parsed and transformed, the initial logic circuit can be obtained.

[0027] Through the above analysis, the abstract ODC expression can be converted into a corresponding initial logic circuit according to the logical relationship between each control signal in the ODC expression. This ensures that the generated initial logic circuit can maintain the logical relationship represented by the ODC expression, providing a circuit basis for the subsequent generation of enable logic circuits that can be used to control the gated clock.

[0028] For ease of understanding, please refer to the following: Figure 2 Describe it. Figure 2 This is a schematic diagram illustrating the conversion of an ODC expression into a logic circuit according to an exemplary embodiment of the present invention. Figure 2As shown, for the ODC expression (S1|S2)|(S3|S4), since its storage structure is a general binary tree, it can be parsed starting from the root node. When a non-leaf node OR is encountered, the corresponding OR gate is generated. When leaf nodes S1, S2, S3, and S4 are encountered, they are retained as the input signals of the corresponding OR gates. When all nodes in the binary tree have been parsed and transformed, the initial logic circuit is obtained.

[0029] Return to reference Figure 1 Next, in step S120, the control signals in the ODC expression can be extended to the boundary signals, and the logic devices passed through during the signal extension process can be added to the initial logic circuit to obtain the extended logic circuit containing the boundary signals.

[0030] According to an exemplary embodiment of the present invention, the control signal in the ODC expression can be used as the starting signal, and the fan-in path of the starting signal can be traversed in the reverse direction of signal propagation, i.e., forward traversal. When encountering combinational logic devices during the traversal, the combinational logic devices can be added to the initial logic circuit. Here, when multiple fan-in paths of the starting signals pass through the same logic device, the same logic device can be avoided from being added repeatedly. When encountering a register during the traversal, the output signal of the encountered register can be determined as a boundary signal, and the traversal of the current branch path can be stopped. It should be understood that combinational logic devices are relative to sequential logic devices; their output is determined only by the current input and is independent of past input / output states. There are no memory elements in the circuit, and the signal is transmitted unidirectionally from input to output.

[0031] In other words, since the object of ODC is a register, in order to ensure the timing consistency between the control signals in the ODC expression and the target register, we can first ensure that the type of the control signals is also a register output signal. Therefore, we can extend each signal in the ODC expression to the register output and add the logic devices encountered in the extension process to the logic circuit.

[0032] By performing the aforementioned forward traversal, the control signals in the ODC expression can be extended along their associated logic paths to the boundary signals. The combinational logic relationships related to these control signals during the extension process are incorporated into the initial logic circuit, ensuring that the generated extended logic circuit reflects the logical association between the control signals and boundary signals in the ODC expression. Furthermore, avoiding redundant additions when multiple signals pass through the same logic device helps reduce redundant logic and improves the generation efficiency of the enable logic circuit.

[0033] For ease of understanding, please refer to the following: Figure 3 Describe it. Figure 3This is a schematic diagram illustrating the ODC expression signal extension according to an exemplary embodiment of the present invention. Figure 3 As shown, in the ODC expression (S1|S2)|(S3|S4) described above, S1, S2, S3, and S4 correspond to the control signals of multiplexers Mux1, Mux2, Mux3, and Mux4, respectively. Since the control signals themselves are not register outputs, they can be used as starting points to extend the signals through forward traversal. For example, they can be extended to the output terminals sFF1 / Q, sFF2 / Q, and sFF3 / Q of registers sFF1, sFF2, and sFF3, respectively. Here, the forward traversal stops when it encounters a boundary signal, which can include register output signals such as sFF1 / Q, sFF2 / Q, and sFF3 / Q. During the traversal, when a combinational logic device is encountered, it is added to the initial logic circuit. Multiple control signals are not added repeatedly when traversing to the same logic device. For example, if an OR gate is encountered during the traversal from S2 to sFF1 / Q and sFF2 / Q, the OR gate can be added to the logic circuit.

[0034] According to an exemplary embodiment of the present invention, the boundary signal may further include a non-register output signal. Here, the non-register output signal may include the output signal of a specified logic device or be identified and defined by an algorithm according to actual needs. Specifically, the non-register output signal may include at least some of the output signals of combinational logic devices.

[0035] As an example, when encountering combinational logic devices during traversal, the fan-in size of the combinational logic device can be determined. If the fan-in size meets a preset condition, the combinational logic device is added to the initial logic circuit. If the fan-in size does not meet the preset condition, the output signal of the combinational logic device is determined as a boundary signal, and traversal of the current branch path is stopped. Furthermore, the fan-in size can be determined by the number of input signals of the combinational logic device. Its parameter threshold can be customized according to actual needs, for example, but not limited to, a setting of 3. When the number of input signals of the combinational logic device is greater than this threshold, it can be determined that the fan-in size of the combinational logic device does not meet the preset condition, thus determining the output signal of the combinational logic device as a boundary signal. At this time, the forward traversal will no longer further traverse the branch path, thereby ensuring that the size of the enabling logic is reasonable.

[0036] In other words, during the forward traversal, when the fan-in path of a specific signal is relatively complex, the scale of the logic circuit that needs to be added after the traversal will also increase accordingly. This will increase the power consumption of using the logic circuit as the enabling logic and affect the final optimization effect. Therefore, when the fan-in scale is found to be large during the signal extension process, the scale of the enabling logic can be controlled by using the output signal of the combinational logic as the boundary signal.

[0037] By limiting the fan-in size as described above, the boundary signals of non-register output types can be determined based on the fan-in size of the combinational logic devices during signal extension. Furthermore, the extension of the corresponding branch can be stopped when preset conditions are met, thus avoiding the inclusion of excessively large fan-in paths into the initial logic circuit. This allows control over the circuit size of the extended logic circuit, reducing the additional power consumption and implementation overhead caused by introducing too much combinational logic, and improving the practicality of the generated results from the enabled logic circuit.

[0038] For ease of understanding, please refer to the following: Figure 4 Describe it. Figure 4 This is a schematic diagram illustrating fan-in scale control in an extension according to an exemplary embodiment of the present invention. Figure 4 As shown, when encountering an N:1 multiplexer with multiple input signals during forward traversal, since all its input signals are objects that need to be extended for its output signal, if all combinational logic (such as combinational logic 1, combinational logic 2, and combinational logic 3) in the fan-in path corresponding to each input signal are traversed and added, the final enable logic size will be too large, thereby reducing the optimization effect. Therefore, the fan-in size can be defined to determine whether to add the combinational logic in the fan-in path to the enable logic. For example, if the fan-in size of the N:1 Mux is determined to not meet the preset condition, the output signal OM of the N:1 Mux is determined as the boundary signal to avoid traversing and adding combinational logic 1, combinational logic 2, and combinational logic 3.

[0039] According to an exemplary embodiment of the present invention, after signal extension is completed, an extended logic circuit containing all boundary signals can be obtained, which can then be further optimized to fully meet timing and logic requirements. Here, the boundary signals obtained after signal extension may include register output signals and / or non-register output signals, wherein only the register output signals can be used as enable logic signals. After timing checks and logic verifications of the register output signals, some invalid signals can be filtered out, and these invalid signals can be optimized away together with the non-register output signals.

[0040] Return to reference Figure 1 Next, in step S130, timing checks can be performed on the register output signals in the boundary signals to determine candidate signals that meet the timing consistency conditions with the target register in the register output signals, and logical verification can be performed on the existing enable logic between the first register and the target register corresponding to the candidate signals.

[0041] Here, timing checks can include clock source and clock polarity checks. That is, the register used as the enable logic and the target register can share the same clock signal, and their clock signal polarities can remain consistent. Otherwise, using this signal as the enable logic signal might change the function of the target register. Further, the clock source and clock polarity of the second register corresponding to the register output signal and the target register can be determined separately. If the clock source and clock polarity of the second register and the target register are consistent, the register output signal is determined to have passed the timing check, thus identifying the register output signal as a candidate signal for further logical verification. If the clock source of the second register is inconsistent with the clock source of the target register, or if the clock polarity of the second register is inconsistent with the clock polarity of the target register, the register output signal is determined to have failed the timing check.

[0042] By performing the timing checks described above, the register output signals in the boundary signals can be filtered according to the clock source and clock polarity, avoiding the use of register output signals that are inconsistent with the timing of the target register as enable signals. This reduces the risk of abnormal function of the target register due to inconsistent clock source or clock polarity, and improves the timing reliability of the generated enable logic circuit.

[0043] For ease of understanding, please refer to the following: Figure 5 Describe it. Figure 5 This is a schematic diagram illustrating a timing check according to an exemplary embodiment of the present invention. Figure 5 As shown, assuming the second register is a register providing the enable logic signal, the clock signal clk1 of the second register and the clock signal clk2 of the target register must have completely identical clock sources and polarities. The clock source of clock signal clk1 includes clock source root_clk1 and clock source root_clk2, and its clock path has no inverter, therefore its polarity is 1. The clock source of clock signal clk2 includes clock source root_clk2 and clock source root_clk3, and its clock path has an inverter, therefore its polarity is 0. At this point, the clock sources and clock polarities of the two are inconsistent. Therefore, the register output signal corresponding to the second register fails the timing check and cannot be used as the enable logic signal for the target register.

[0044] According to an exemplary embodiment of the present invention, in addition to timing checks, the register output signal can also be logically verified. The object of the logical verification is the existing enable logic of the register. Here, when a feedback loop exists in the register, it can generate enable logic itself, which ensures that the register can only output under specific enable conditions. Furthermore, before performing logical verification on the existing enable logic between the first register and the target register corresponding to the candidate signal, it can be determined whether each register in the first register and the target register has a feedback loop; if a feedback loop exists in each register, it is determined that each register has existing enable logic; if no feedback loop exists in each register, it is determined that each register does not have existing enable logic.

[0045] By using the above method, the presence of feedback loops in the registers can determine whether the first register and the target register have existing enable logic, thus providing a basis for subsequent logical verification of candidate signals. This avoids directly performing verification without clearly knowing the existence of enable logic in the registers, improving the accuracy and reliability of the candidate signal selection process.

[0046] According to an exemplary embodiment of the present invention, logic verification may involve determining whether the existing enable logic of the first register and the target register satisfies a specific relationship, that is, when the existing enable logic of the first register is true, the existing enable logic of the target register must also be true. The candidate signal corresponding to the first register that satisfies this specific relationship can be used as the enable logic signal of the target register. Here, the verification method may be to merge the two existing enable logics into a single logic circuit and compare it with a constant value of 0. As an example, assuming the existing enable logic of the first register is n1 and the existing enable logic of the target register is n2, it can be determined by verifying whether the two logic circuits satisfy "n1 & !n2 == 0". When this condition is met, the candidate signal corresponding to the first register is determined to pass the logic verification; otherwise, it fails.

[0047] Furthermore, if both the first register and the target register have existing enable logic, the existing enable logic in the first register can be denoted as the first enable logic circuit, and the existing enable logic in the target register can be denoted as the second enable logic circuit. The inverted result of the second enable logic circuit and the first enable logic circuit are combined into the target logic circuit through AND logic, and it is determined whether the output of the target logic circuit is always equal to the constant value 0. If the output of the target logic circuit is always equal to the constant value 0, the candidate signal is determined to have passed the logic verification. If the output of the target logic circuit is not always equal to the constant value 0, the candidate signal is determined to have failed the logic verification.

[0048] The above logical verification verifies whether the existing enable logic of the first register and the existing enable logic of the target register satisfy a predetermined dependency relationship, thus avoiding the use of candidate signals that do not satisfy this dependency relationship to generate the enable logic circuit of the target register. This improves the accuracy of the available enable signal selection results and reduces the risk of target register malfunctions due to mismatches between candidate signals and the original update conditions of the target register.

[0049] For ease of understanding, please refer to the following: Figure 6 Describe it. Figure 6 This is a schematic diagram illustrating a logic verification according to an exemplary embodiment of the present invention. Figure 6 As shown in the figure, assuming the output signal of the first enabling logic circuit is p and the output signal of the second enabling logic circuit is q, the expected logic between the output signals p and q is p->q, that is, "if p, then q". The truth table of this expected logic is shown in the figure. Then, by connecting an inverter to the q terminal and then combining it with the p terminal through AND logic to form the target logic circuit, we can verify whether p and q meet the expected logic, that is, whether the output of the target logic circuit is always equal to the constant value 0.

[0050] Furthermore, if the first register contains existing enable logic but the target register does not, it can be determined that the candidate signal has failed the logic verification; if the first register does not contain existing enable logic but the target register does, it can be determined that the candidate signal has passed the logic verification; if neither the first register nor the target register contains existing enable logic, it can be determined that the candidate signal has passed the logic verification. In other words, when at least one of the first register and the target register lacks enable logic, the following judgment can be made directly: when the first register contains enable logic but the target register does not, the logic verification result does not meet expectations; when the first register does not contain enable logic but the target register does, the logic verification result meets expectations; when neither the first register nor the target register contains enable logic, the logic verification result meets expectations.

[0051] By using the above method, even when both the first register and the target register do not have existing enable logic, the availability of candidate signals can still be determined based on the existence of existing enable logic in both registers. This improves the logic verification rules for candidate signals, avoids interruptions in the verification process or unclear judgment results due to the absence of existing enable logic in some registers, and enhances the completeness and applicability of the available enable signal screening process.

[0052] Return to reference Figure 1Next, in step S140, useless signals in the extended logic circuit can be removed by logic simplification to generate an enable logic circuit for controlling the clock gating unit corresponding to the target register.

[0053] Here, useless signals can include non-register output signals in the boundary signals and register output signals that fail timing checks and / or logic verifications. In other words, after all checks / verifications are completed, non-register output signals and register output signals that fail checks / verifications can be considered useless signals. They can be removed through logic simplification to generate a simplified logic circuit, which can serve as the gated clock corresponding to the final enable logic control register.

[0054] According to the exemplary embodiment of the present invention, the method for generating register enable logic circuit can first generate an initial logic circuit based on the logical relationship between each control signal in the ODC expression, and extend each control signal to a boundary signal, wherein the type of the boundary signal can be customized according to the requirements. Then, the obtained boundary signal is subjected to timing check and logic verification to ensure that it is consistent with the timing of the target register. Finally, the signals that have passed the check / verification are synthesized to obtain a new logic circuit for controlling the gated clock corresponding to the target register, thereby achieving the purpose of reducing circuit power consumption.

[0055] By processing the ODC expression corresponding to the output of the target register, an enable logic circuit that can be used to control the clock gating unit of the target register is generated. This transforms the ODC expression, which was originally difficult to use directly to control the gated clock, into a practically implementable gating control logic. This reduces unnecessary toggling of the clock signal corresponding to the target register, lowers redundant dynamic power consumption, and improves power optimization, even when the target register output is unobservable for subsequent paths. In short, after applying this invention, an ODC expression can be converted into a usable enable logic circuit, applied to the gating clock of a register, and its power consumption can be saved.

[0056] In a second aspect of an exemplary embodiment of the present invention, an electronic device is provided, the electronic device comprising: a processor; and a memory for storing processor-executable instructions, wherein, when executed by the processor, the processor-executable instructions cause the processor to execute a method for generating register-enabled logic circuits according to an exemplary embodiment of the present invention.

[0057] Figure 7 This is a block diagram illustrating an electronic device according to an exemplary embodiment of the present invention. Figure 7 As shown, the electronic device 10 includes a processor 101 and a memory 102 for storing processor-executable instructions. Here, when executed by the processor, the processor-executable instructions cause the processor to execute a method for generating register-enabled logic circuits according to an exemplary embodiment of the present invention.

[0058] As an example, electronic device 10 is not necessarily a single device, but can be a collection of any means or circuits capable of executing the aforementioned instructions (or instruction sets) individually or in combination. Electronic device 10 can also be part of an integrated control system or system manager, or can be configured to interface with a server locally or remotely (e.g., via wireless transmission).

[0059] In electronic device 10, processor 101 may include a central processing unit (CPU), a graphics processing unit (GPU), a programmable logic device, a dedicated processor system, a microcontroller, or a microprocessor. By way of example and not limitation, processor 101 may also include an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, etc.

[0060] The processor 101 can execute instructions or code stored in the memory 102, which can also store data. Instructions and data can also be sent and received over a network via a network interface device, which can employ any known transmission protocol.

[0061] The memory 102 may be integrated with the processor 101, for example, by placing RAM or flash memory within an integrated circuit microprocessor. Alternatively, the memory 102 may include a separate device, such as an external disk drive, a storage array, or other storage device that can be used by any database system. The memory 102 and the processor 101 may be operatively coupled, or may communicate with each other, for example, via I / O ports, network connections, etc., enabling the processor 101 to read files stored in the memory 102.

[0062] In addition, the electronic device 10 may also include a video display (such as a liquid crystal display) and a user interaction interface (such as a keyboard, mouse, touch input device, etc.). All components of the electronic device 10 can be connected to each other via a bus and / or network.

[0063] In an exemplary embodiment, a computer-readable storage medium may also be provided, which, when executed by a processor of an electronic device, enables the electronic device to perform the method for generating register-enabled logic circuits as described in the exemplary embodiment above. The computer-readable storage medium may be, for example, a memory including instructions. Optionally, the computer-readable storage medium may be: a read-only memory (ROM), a random access memory (RAM), a random access programmable read-only memory (PROM), an electrically erasable programmable read-only memory (EEPROM), a dynamic random access memory (DRAM), a static random access memory (SRAM), flash memory, non-volatile memory, a CD-ROM, a CD-R, a CD+R, a CD-RW, a CD+RW, a DVD-ROM, a DVD-R, a DVD+R, a DVD-RW, a DVD+RW, a DVD-RAM, a BD-ROM, a BD-R, or a BD-R... LTH, BD-RE, Blu-ray or optical disc storage, hard disk drive (HDD), solid-state drive (SSD), card storage (such as multimedia cards, secure digital (SD) cards, or ultra-fast digital (XD) cards), magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid-state drive, and any other device configured to store a computer program and any associated data, data files, and data structures in a non-transitory manner and to provide the computer program and any associated data, data files, and data structures to a processor or computer so that the processor or computer can execute the computer program. The computer program in the aforementioned computer-readable storage medium can run in an environment deployed in computer devices such as clients, hosts, agent devices, servers, etc. Furthermore, in one example, the computer program and any associated data, data files, and data structures are distributed across a networked computer system, such that the computer program and any associated data, data files, and data structures are stored, accessed, and executed in a distributed manner through one or more processors or computers.

[0064] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the claims.

[0065] Furthermore, it should be noted that although several examples of each step have been described above with reference to the specific accompanying drawings, it should be understood that the embodiments of the present invention are not limited to the combinations given in the examples, and the steps appearing in different drawings can be combined, which will not be exhaustive here.

[0066] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the claims.

Claims

1. A method for generating a register-enabled logic circuit, characterized in that, include: Determine the ODC expression corresponding to the output of the target register, and generate the initial logic circuit based on the logical relationship between each control signal in the ODC expression; The control signals in the ODC expression are extended to the boundary signals, and the logic devices passed through during the signal extension process are added to the initial logic circuit to obtain the extended logic circuit containing the boundary signals. A timing check is performed on the register output signal in the boundary signal to determine a candidate signal in the register output signal that satisfies the timing consistency condition with the target register, and the existing enable logic between the first register corresponding to the candidate signal and the target register is logically verified. By removing unwanted signals from the extended logic circuit through logical simplification, an enable logic circuit for controlling the clock gating unit corresponding to the target register is generated. The unwanted signals include non-register output signals from the boundary signals and register output signals that fail the timing check and / or the logic verification. The signal extension of the control signals in the ODC expression includes: Using the control signal in the ODC expression as the starting signal, the fan-in path of the starting signal is traversed in the opposite direction of signal propagation; When a combinational logic device is encountered during the traversal, the combinational logic device is added to the initial logic circuit. When multiple start signals fan-in paths pass through the same logic device, the same logic device is not added repeatedly. If a register is encountered during traversal, the output signal of the encountered register is identified as a boundary signal, and traversal of the current branch path is stopped. The logical verification of the existing enable logic between the first register corresponding to the candidate signal and the target register includes: When both the first register and the target register have existing enable logic, the existing enable logic of the first register is recorded as the first enable logic circuit, and the existing enable logic of the target register is recorded as the second enable logic circuit. The inverted result of the second enabling logic circuit and the first enabling logic circuit are combined into a target logic circuit through an AND logic, and it is determined whether the output of the target logic circuit is always equal to the constant value 0. If the output of the target logic circuit is always equal to the constant value 0, then the candidate signal is determined to have passed the logic verification. If the output of the target logic circuit is not always equal to the constant value 0, then the candidate signal is determined to have failed the logic verification.

2. The method for generating register-enabled logic circuits according to claim 1, characterized in that, The ODC expression is stored in a tree structure, wherein generating an initial logic circuit based on the logical relationships between the control signals in the ODC expression includes: The ODC expression is parsed starting from the root node of the tree structure; When a non-leaf node representing a logic device is resolved, a logic gate corresponding to the non-leaf node is generated in the initial logic circuit. When a leaf node is parsed, the control signal corresponding to the leaf node is used as the input signal of the corresponding logic gate for subsequent signal extension.

3. The method for generating register-enabled logic circuits according to claim 1, characterized in that, When a combinational logic device is encountered during the traversal, the combinational logic device is added to the initial logic circuit, including: When encountering combinational logic devices during the traversal, determine the fan-in size of the combinational logic devices; If the fan-in size meets the preset conditions, then the combinational logic device is added to the initial logic circuit; If the fan-in size does not meet the preset conditions, the output signal of the combinational logic device is determined as a boundary signal, and the traversal of the current branch path is stopped.

4. The method for generating register-enabled logic circuits according to claim 1, characterized in that, Perform timing checks on the register output signals in the boundary signals, including: Determine the clock source and clock polarity of the second register corresponding to the output signal of the register and the target register, respectively; If the clock source and clock polarity of the second register and the target register are consistent, it is determined that the output signal of the register passes the timing check; If the clock source of the second register is inconsistent with the clock source of the target register, or if the clock polarity of the second register is inconsistent with the clock polarity of the target register, it is determined that the register output signal has failed the timing check.

5. The method for generating register-enabled logic circuits according to claim 1, characterized in that, The logical verification of the existing enable logic between the first register corresponding to the candidate signal and the target register also includes: If the first register has existing enable logic and the target register does not have existing enable logic, it is determined that the candidate signal has failed the logic verification. If the first register does not have existing enable logic and the target register has existing enable logic, the candidate signal is determined to pass the logic verification. If neither the first register nor the target register has existing enable logic, the candidate signal is determined to pass the logic verification.

6. The method for generating register-enabled logic circuits according to claim 1, characterized in that, Before performing logical verification on the existing enable logic between the first register corresponding to the candidate signal and the target register, the following steps are also included: Determine whether a feedback loop exists in each register of the first register and the target register, respectively; If a feedback loop exists in each of the registers, it is determined that each register already has enable logic. If there is no feedback loop in each register, it is determined that there is no existing enable logic in each register.

7. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions. Wherein, when the processor-executable instructions are executed by the processor, they cause the processor to execute the method for generating register-enabled logic circuits according to any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that, When the instructions in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device is able to perform the method for generating the register-enabled logic circuit according to any one of claims 1 to 6.

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