Circuit design optimization method based on feasible region optimization and dynamic shrinkage and application thereof

Abstract

The present application belongs to the field of integrated circuit design, and particularly relates to a circuit design optimization method based on feasible region optimization and dynamic shrinkage and application thereof. The present application models the design parameter optimization problem of a circuit as a black box constrained optimization problem, and adopts an improved Bayesian optimization algorithm for design parameter optimization. The scheme on the one hand adopts a newly designed physical feasible region identification mechanism to peel off the "physical dead zone" in the parameter space at an early stage of optimization, and cuts off the abnormal parameter space with extremely low computing overhead, to construct a high-confidence optimization subspace for the Gaussian process. On the other hand, a dynamic feasible region shrinkage mechanism is designed and deeply coupled with the expected improvement acquisition function; and then the search step of the high-sensitive parameter is adaptively adjusted, to ensure that the Bayesian optimization method can realize stable gradient convergence in the narrow extreme value space. Based on this, the present application can overcome the dimension disaster and local stagnation problem of the traditional circuit optimization strategy in the super-high-dimensional circuit optimization.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, specifically relating to a circuit design optimization method based on feasible region optimization and dynamic shrinkage, and the corresponding computer program product, computer storage medium and circuit design optimization device. Background Technology

[0002] As semiconductor process nodes advance towards deeper submicron and nanometer scales, the number of design parameters for high-performance analog integrated circuits continues to increase, with strong coupling relationships existing between underlying parameters such as transistor width and length, bias current, capacitance, resistance, and compensation structures. Taking complex analog circuits such as rail-to-rail operational amplifiers and low-dropout linear regulators as examples, designers typically need to optimize core performance indicators such as DC gain and power supply rejection ratio while meeting constraints such as gain bandwidth, output current, quiescent power consumption, dropout voltage, and load regulation.

[0003] Existing automatic size optimization methods for analog circuits typically use SPICE simulation as a black-box evaluation function and employ Bayesian optimization, evolutionary strategies, or local trust region optimization to search for optimal parameters in the design space. Bayesian optimization can improve sampling efficiency under limited simulation budgets by using Gaussian process surrogate models and acquisition functions. However, when the design variables are highly dimensional and physically constrained, many parameter combinations fall into the "physical dead zone" where simulations fail to converge or performance severely fails to meet constraints. These low-quality samples make it difficult to model the surrogate model and may even cause instability in the Gaussian process covariance matrix, reducing the effectiveness of subsequent sampling. Furthermore, existing optimization frameworks such as CMA-ES, TuRBO, and WEIBO are prone to step size failure, premature trust region collapse, or long-term stagnation when approaching narrow, flat, or strongly constrained extreme regions. Especially in high-dimensional analog circuits, a few sensitive parameters contribute significantly to performance metrics, while a large number of insensitive parameters dilute search resources. Without joint identification of physical feasible boundaries and parameter sensitivity, optimization algorithms tend to repeatedly sample near local optima, making it difficult to further break through performance limits. Summary of the Invention

[0004] To address the curse of dimensionality and local stagnation issues in ultra-high-dimensional circuit optimization, this invention provides a circuit design optimization method based on feasible region optimization and dynamic shrinkage, along with corresponding computer program products, computer storage media, and circuit design optimization devices.

[0005] This invention is achieved using the following technical solution: A circuit design optimization method based on feasible region optimization and dynamic shrinkage includes the following process: Obtain the design conditions for the analog circuit to be optimized, including: design parameters, physical boundaries, performance indicators, and constraints.

[0006] Several initial samples are generated using low-discrepancy sequences. A circuit simulator is then invoked to generate corresponding circuit performance based on the design parameters of the initial samples, thus forming a historical simulation dataset. A surrogate model based on Gaussian processes is trained using this historical simulation dataset.

[0007] Based on the quantiles of the target performance, each simulation sample is divided into high-quality and low-quality samples, and corresponding labels are added. A shallow CART decision tree is used to fit the binary classification simulation samples, and the global importance I of each design parameter is calculated based on the decrease in Gini impurity introduced at the split node for each dimension. CART .

[0008] The objective function is designed starting from the global design space. It iteratively removes low-quality samples from the edges based on label information, maximizing the density of high-quality samples in the remaining subspace, thus obtaining the optimized high-quality subspace B. PRIM And based on the mass gain of each stripping step, the local importance I of each design parameter is calculated. PRIM ; .

[0009] The mixed importance A of each design parameter is obtained by combining global importance and local importance. The adaptive search step size of each design parameter is set according to A so that it is negatively correlated with A.

[0010] With B PRIM As the initial anchor box, the search center is the point that smoothly transitions from the center of the high-quality subspace BPRIM to the current best feasible sample xbest as the optimization process progresses. A dynamic search hyperrectangle is generated by combining the adaptive search step size and the preset dynamic shrinkage factor. Bayesian optimization is performed on the design parameters. The optimization process uses the constraint expectation improvement function with an adaptive relaxation factor as the acquisition function.

[0011] As a further improvement of the present invention, the design parameters to be optimized include transistor width, transistor length, bias current, resistance value, capacitance value and compensation parameters in the circuit.

[0012] As a further improvement of the present invention, the optimized constraints include unity-gain bandwidth, output current, static power consumption, voltage drop, load regulation, and stability margin.

[0013] As a further improvement of this invention, the formula for generating labels for arbitrary simulation samples is: ; in, This is an indicator function; its value is 1 if the condition within the parentheses is true, and 0 otherwise. j For the first j The objective function value of each simulation sample; y 1:nThis represents the set of observations for the currently collected n samples; Quantile (·) denotes the quantile calculation function; q The set quantile ratio threshold; To ultimately give the first j Binary classification labels for each simulated sample; .

[0014] As a further improvement to the present invention, global importance I CART Global importance score of any d-dimensional design parameter used to quickly identify design parameters that have a global impact on circuit performance. The calculation formula is as follows: ; In the above formula, t represents the internal node n in the decision tree. t t is the number of samples that reach the split node t; n is the total number of samples that participate in building the decision tree; t:split on d is the summation condition, which means that only the nodes that use dimension d as the split feature are summed; This represents the decrease in Gini impurity resulting from splitting at node t.

[0015] As a further improvement to this invention, the mixed importance of arbitrary d-dimensional design parameters The calculation formula is as follows: ; in, This represents the local importance score of the design parameters in dimension d; The weighting coefficients are used to balance the two importance scores.

[0016] As a further improvement of the present invention, a preset dynamic contraction factor It is strongly coupled with the optimization state of the iterative process and satisfies the following equation: ; in, T max For the overall assessment budget; t eff The number of effective iterations; exponent This is a hyperparameter representing the nonlinear contraction rate. r min This is a preset minimum shrinkage ratio limit used to prevent the search space from degenerating into a single point.

[0017] As a further improvement to this invention, the acquisition function in Bayesian optimization is as follows: ; in, and , , are the posterior prediction mean and standard deviation of the i-th constrained Gaussian process in the surrogate model, respectively; K represents the number of constrained Gaussian processes in the surrogate model; The cumulative distribution function of the standard normal distribution; r t For constraint relaxation factor; This represents the classic expected improvement function; It is the currently known minimum objective function value. and These are the cumulative distribution function and probability density function of the standard normal distribution, respectively. ; and The candidate design points are respectively represented by the Gaussian process surrogate model. x The posterior predictive mean and posterior predictive standard deviation.

[0018] The present invention also includes a computer storage medium storing a computer program. When the computer program is executed by a processor, it implements the circuit design optimization method based on feasible region optimization and dynamic shrinkage as described above, thereby obtaining the optimal design parameters of the circuit to be designed so as to achieve the best performance indicators.

[0019] The present invention also includes a computer program product, which includes a computer program that, when executed by a processor, implements the circuit design optimization method based on feasible region optimization and dynamic shrinkage as described above, thereby obtaining the optimal design parameters of the circuit to be designed so as to achieve the best performance indicators.

[0020] The present invention also includes a circuit design optimization device, which includes a memory, a processor, and a computer program stored in the memory and running on the processor. When the processor executes the computer program, it implements the circuit design optimization method based on feasible region optimization and dynamic shrinkage as described above, thereby obtaining the optimal design parameters of the circuit to be designed so as to achieve the best performance indicators.

[0021] The technical solution provided by this invention has the following beneficial effects: This invention utilizes initial simulation data to identify regions in the analog circuit design space related to high-performance solutions and eliminates a large number of physical dead zones where simulations fail to converge or performance significantly fails to meet constraints as early as possible. Then, a stable surrogate model is established within the remaining high-confidence subspace, and parameter importance is used to guide the direction and magnitude of contraction in the dynamic search region. During the dead zone removal stage, this invention, on the one hand, uses a CART decision tree to quickly determine which design parameters contribute significantly to the partitioning of high-quality samples from a global perspective; on the other hand, it uses PRIM rules to inductively peel away low-quality boundaries layer by layer from a local perspective while retaining dense regions of high-quality samples. The combination of these two approaches avoids both the coarse boundaries resulting from relying solely on a global tree model and the insufficient understanding of the overall trend caused by relying solely on local peeling.

[0022] After obtaining a high-quality subspace, this invention uses the subspace with dead zones removed as the anchoring range and dynamically adjusts the search region based on the optimization progress and stagnation status. When the algorithm is in its early stages or still shows significant improvement, the search region remains relatively loose to allow for global exploration; when the algorithm enters the mid-to-late stages or approaches the extreme value region, the search region gradually shrinks, and fine-grained searches are performed on sensitive parameters based on mixed importance, thereby improving the ability to exploit extreme values. The acquisition function in Bayesian optimization combines the expected improvement with the constraint feasibility probability, and balances exploration and feasibility through a gradually decaying constraint relaxation factor. Thus, this invention can reduce invalid sampling within a limited SPICE simulation budget, avoid premature contraction of traditional trust region methods, and continuously seek better feasible solutions in strongly constrained, high-dimensional analog circuit size optimization. Attached Figure Description

[0023] Figure 1 This is a flowchart of the circuit design optimization method based on feasible region optimization and dynamic shrinkage provided in Embodiment 1 of the present invention.

[0024] Figure 2 This is a schematic diagram illustrating the principle of this invention in achieving high-quality subspace mining by eliminating physical dead zones.

[0025] Figure 3 This is the circuit diagram of the rail-to-rail operational amplifier used in the simulation experiment.

[0026] Figure 4 This is the circuit diagram of a low-dropout linear regulator used in a simulation experiment.

[0027] Figure 5 The gain convergence curves for the on-orbit operational amplifier optimization task of the present invention and the control group are shown.

[0028] Figure 6 The power supply rejection ratio convergence curves of the present invention and the control group scheme in the low dropout linear regulator optimization task are shown. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0030] Example 1 In this embodiment, when the technicians studied traditional circuit design optimization schemes, they found that there are a large number of infeasible parameter combinations in the optimization of high-dimensional analog circuit parameters. Traditional physical constraints and performance constraints cannot effectively eliminate these parameter combinations, which leads to wasted SPICE simulation resources and instability of the surrogate model. Bayesian optimization is easily misled by the high variance of unknown regions in strongly constrained high-dimensional spaces, thus sampling physical dead zones. Methods such as CMA-ES, TuRBO, and WEIBO are prone to step size failure, premature shrinkage of the trust region, or long-term stagnation in narrow extreme regions. Different circuit parameters have large differences in sensitivity to performance indicators, and uniform step size search leads to insufficient fine-tuning of key parameters and sampling redundancy of non-key parameters.

[0031] Based on the above findings, this embodiment provides a novel circuit design optimization method based on feasible region optimization and dynamic shrinkage. This scheme achieves an effective combination of dimensionality reduction and extreme value fine-tuning in high-dimensional space through lightweight feasible region boundary characterization and dynamic trust region management. It overcomes the curse of dimensionality and local stagnation problems faced by mainstream optimization frameworks when optimizing actual circuit parameter spaces with ultra-high dimensions and stringent physical constraints. Specifically, this embodiment designs a physical feasible region identification mechanism to remove "physical dead zones" in the parameter space early in the optimization process, cutting off abnormal parameter spaces with extremely low computational overhead. This constructs a high-confidence optimization subspace for the Gaussian process (GP), fundamentally ensuring the numerical stability of high-dimensional Bayesian inference. Furthermore, it proposes a dynamic feasible region shrinkage mechanism and deeply couples it with the expected improvement (EI) acquisition function. This enables adaptive adjustment of the search step size for highly sensitive parameters, ensuring that the Bayesian optimization method can achieve stable gradient convergence within a narrow extreme value space.

[0032] In detail, such as Figure 1 As shown, the circuit design optimization method based on feasible region optimization and dynamic shrinkage provided in this embodiment includes the following process: S1: Obtain the design conditions of the analog circuit to be optimized, including: design parameters, physical boundaries, performance indicators and constraints.

[0033] In this embodiment, the design parameter optimization problem of a high-dimensional analog circuit is modeled as an optimization problem with black-box constraints. The design parameters to be optimized are the decision variables of the optimization problem. In this embodiment, the design parameters to be optimized include transistor width, transistor length, bias current, resistance value, capacitance value, and compensation parameters, etc. The d design parameters to be optimized are denoted as follows: x 1. x 2, ..., x d Then the design variable X that needs to be optimized can be expressed as: X = { x 1. x2, ..., x d Each design parameter has upper and lower bounds determined by process rules or design experience, which are essentially a type of physical constraint. The boundary formed by these physical constraints can serve as the initial search boundary B0 for the optimization scheme in this embodiment. Performance indicators are the optimization targets of this invention. The constraints in this embodiment mainly refer to performance constraints, including bit gain bandwidth, output current, static power consumption, voltage drop, load regulation, and stability margin, etc. In this embodiment, each performance indicator to be optimized can be labeled as... f (X), and the first i A physical constraint or performance constraint can be denoted as: g i (X).

[0034] S2: Construct a historical simulation dataset and train a surrogate model; this includes: generating several initial samples using low-discrepancy sequences, calling a circuit simulator to generate corresponding circuit performance based on the design parameters of the initial samples, thus forming a historical simulation dataset. A Gaussian process-based surrogate model is then trained using this historical simulation dataset.

[0035] In this embodiment, Sobol sequence or Latin hypercube sampling is used within the initial search boundary B0 to generate an initial sample set X0. Inputting X0 into a SPICE simulator or equivalent circuit simulation software yields the performance metrics of various design schemes for the corresponding circuit. f (X) and constraint values g i (X). This leads to the construction of a historical simulation dataset. D : D ={( X j, y j , c j )},in, y j Indicates the first j Sample X j The target performance evaluation value; c j Indicates the first j Constraint evaluation results for each sample.

[0036] This embodiment provides a circuit design parameter optimization scheme based on Bayesian optimization (BO). Bayesian optimization, by constructing a probabilistic surrogate model and a data acquisition function, exhibits extremely high optimization efficiency under limited simulation budgets. This embodiment constructs a surrogate model based on a Gaussian process and trains it using historical simulation datasets. The constructed Gaussian process surrogate model is used to output the predicted mean and variance of any candidate design parameter, providing a basis for the subsequent calculation of the data acquisition function. It should be noted that in other embodiments, the Gaussian process surrogate model can also be replaced with a random forest, a Bayesian neural network, or other surrogate models capable of outputting prediction uncertainty.

[0037] S3: Identify high-quality feasible subspaces within the initial search boundary; such as Figure 2 As shown, the process includes: (1) Based on the quantile of the target performance, each simulation sample is divided into high-quality samples and low-quality samples, and corresponding labels are added.

[0038] In this embodiment, for each simulation sample in the historical simulation dataset, the samples are first divided into high-quality samples and low-quality samples according to the quantile of the target performance, and corresponding category labels are added. For example, the top 30% of samples in terms of performance can be labeled as high-quality samples, and the rest as low-quality samples. Therefore, the label generation formula for any simulation sample in this embodiment is: ; in, This is an indicator function; its value is 1 if the condition within the parentheses is true, and 0 otherwise. j For the first j The objective function value of each simulation sample; y 1:n This represents the set of observations for the currently collected n samples; Quantile (·) denotes the quantile calculation function; q The set quantile ratio threshold; To ultimately give the first j Binary classification labels for each simulated sample.

[0039] (2) A shallow CART decision tree is used to fit the binary classification simulation samples, and the global importance I of each design parameter is calculated based on the decrease in Gini impurity introduced at the split node for each dimension. CART .

[0040] In this embodiment, global importance I CART Global importance score of any d-dimensional design parameter used to quickly identify design parameters that have a global impact on circuit performance. The calculation formula is as follows: ; In the above formula, t represents the internal node n in the decision tree. t t is the number of samples that reach the split node t; n is the total number of samples that participate in building the decision tree; t:split on d is the summation condition, which means that only the nodes that use dimension d as the split feature are summed; This represents the decrease in Gini impurity resulting from splitting at node t.

[0041] (3) After the label-based binary classification fitting, the PRIM rule induction method is used to perform local boundary stripping on the current sample space.

[0042] The PRIM rule inductive method selects the dimension and boundary that maximizes the density of high-quality samples for shrinkage each time until the density gain is insufficient or the support of the remaining samples falls below a preset threshold. This process yields the boundary of the high-quality subspace and its local importance.

[0043] Specifically, in this embodiment, the objective function is designed to maximize the density of high-quality samples in the remaining subspace, i.e.: ; in, S after Represents the remaining subspace. ir Representing dimensions d The candidate stripping boundaries (stripping intervals) selected during the boundary stripping process; that is, the stripping dimensions jointly selected by PRIM each time. d With candidate stripping boundary ir , making the remaining subspace S after Maximize the proportion of high-quality samples.

[0044] Then, starting from the global design space, and combining label information, we iteratively remove some low-quality samples from the edges to maximize the density of high-quality samples in the remaining subspace, thus obtaining the optimized high-quality subspace B. PRIM B PRIM This is the high-confidence optimization subspace obtained in this embodiment after physical dead-zone removal. Furthermore, during the physical dead-zone removal process, this embodiment also calculates the local importance I of each design parameter based on the quality gain of each stripping step. PRIM .

[0045] S4: Constructing a dynamically shrinking feasible region based on the importance of mixed parameters; including: (1) The mixed importance A of each design parameter is obtained by combining global importance and local importance.

[0046] To more accurately analyze the sensitivity of circuit performance to design parameters in each dimension, this embodiment weights and fuses the global and local importance of each design to obtain a hybrid importance. Based on this, the hybrid importance of any d-dimensional design parameter is... The calculation formula is as follows: ; in, This represents the global importance score of the design parameters for dimension d; This represents the local importance score of the design parameters in dimension d; To balance the weighting coefficients of the two importance scores, in this embodiment, the weighting coefficients are... Set it to 0.6 to give higher weight to local precise stripping.

[0047] (2) Set the adaptive search step size for each design parameter according to A.

[0048] Considering that different design parameters have varying sensitivities to the same performance objective, differentiated adaptive search step sizes can be designed for different design parameters during optimization. In this embodiment, the search step size for design parameters with higher sensitivity can be designed to be smaller to achieve more refined parameter optimization, while the search step size for design parameters with lower sensitivity can be appropriately increased to improve the search efficiency. In summary, this embodiment can adaptively adjust the search step size of each design parameter based on the mixed importance calculated above, so that the values ​​of the two are negatively correlated.

[0049] (3) Design a constraint expectation improvement function with an adaptive relaxation factor as the final acquisition function.

[0050] Traditional acquisition functions (such as standard EI) are easily misled by high prediction variance in unknown regions in high-dimensional spaces lacking physical boundary constraints, wasting budget in infeasible areas. To address this, this embodiment designs an improved acquisition function that incorporates an adaptive relaxation factor, aiming to strictly limit computational power within a dynamically shrinking safe subspace. Specifically, this embodiment designs the acquisition function in Bayesian optimization. as follows: ; in, and , , are the posterior prediction mean and standard deviation of the i-th constrained Gaussian process in the surrogate model, respectively; K represents the number of constrained Gaussian processes in the surrogate model; The cumulative distribution function of the standard normal distribution; r t For constraint relaxation factor; This represents the classic expected improvement function; It is the currently known minimum objective function value. and These are the cumulative distribution function and probability density function of the standard normal distribution, respectively. ; and The candidate design points are respectively represented by the Gaussian process surrogate model. x The posterior predictive mean and posterior predictive standard deviation.

[0051] S5: Iterative optimization of design parameters based on Bayesian optimization algorithm; including: With B PRIM The initial anchor box is used to progressively move from the center of the high-quality subspace BPRIM towards the current best feasible sample as the optimization process progresses. x best The points of smooth transition are used as the search center. A dynamic search hyperrectangle is generated by combining the adaptive search step size and the preset dynamic shrinkage factor. Bayesian optimization is performed on the design parameters. The optimization process uses the constraint expectation improvement function with an adaptive relaxation factor as the acquisition function.

[0052] Specifically, in this embodiment, a preset dynamic shrinkage factor The Bayesian optimization algorithm is strongly coupled with the optimization state during the iterative process, and the effective number of iterations is crucial. t eff It may moderately regress due to successful improvement, and accelerate its increase with continuous stagnation; correspondingly, the dynamic contraction factor... When successful improvements are made, a moderate rebound occurs (maintaining a relatively wide search area); when continuous stagnation occurs, a rapid decrease occurs (accelerating the contraction of the search area and strengthening the surrounding area). x best (Local mining). And satisfy the following formula: ; in, T max For the overall assessment budget; t eff The number of effective iterations; exponent The nonlinear shrinkage rate hyperparameter is set to 1.5 in this embodiment to provide a moderate nonlinear shrinkage rhythm, which avoids premature collapse of the search region and ensures sufficient local fine sampling in the neighborhood of the optimal solution in the later stage of optimization. r min This is a preset minimum shrinkage ratio limit used to prevent the search space from degenerating into a single point.

[0053] In this embodiment, as the optimization process progresses, the center of the search space gradually transitions smoothly from the optimized high-quality subspace to the currently known optimal solution. By combining mixed importance with asymmetric modulation of the search step size for each dimension of the design parameters, an adaptive dynamic search hyperrectangle is generated in each round. This embodiment is based on the desired improvement in EI and multiplied by the feasibility probability of each constraint to obtain the acquisition function constrained by the desired improvement. Within the strictly constrained dynamic search hyperrectangle, based on the improved acquisition function, this embodiment can more efficiently converge the design parameters to the optimal performance value.

[0054] In this embodiment, during Bayesian optimization, candidate designs are input into the SPICE simulator to obtain target performance and constraint results, and new samples are added to the historical simulation dataset. If a new sample satisfies all constraints and its target performance is better than the current best feasible sample, the best feasible sample is updated, and the effective iteration is slowed down or the local search is expanded. If no improvement is obtained for several consecutive rounds, the stall count is increased and enhanced perturbation sampling centered on the best feasible sample is triggered.

[0055] When the cumulative number of newly added samples reaches a preset threshold, the number of consecutive stalled rounds reaches a preset threshold, or the prediction error of the surrogate model exceeds a preset range, the performance simulation is re-executed based on the updated historical simulation dataset to obtain a new high-quality subspace and mixed importance. Optimization then continues until the simulation budget or convergence condition is met, outputting the optimal feasible design parameters and their corresponding performance metrics.

[0056] Example 2 The circuit design optimization method based on feasible region optimization and dynamic shrinkage provided in Example 1 is essentially a data processing method. In order to better apply this scheme, this example further provides a computer storage medium, a computer program product, and a circuit design optimization device.

[0057] The computer storage medium provided in this embodiment stores a computer program. When the computer program is executed by the processor, it implements the circuit design optimization method based on feasible domain optimization and dynamic shrinkage as in Embodiment 1, thereby obtaining the optimal design parameters of the circuit to be designed so that it can achieve the best performance indicators.

[0058] The computer program product provided in this embodiment includes a computer program. When the computer program is executed by the processor, it implements the circuit design optimization method based on feasible domain optimization and dynamic shrinkage as in Embodiment 1, thereby obtaining the optimal design parameters of the circuit to be designed so that it can achieve the best performance indicators.

[0059] The circuit design optimization device provided in this embodiment includes a memory, a processor, and a computer program stored in the memory and running on the processor. When the processor executes the computer program, it implements the circuit design optimization method based on feasible domain optimization and dynamic shrinkage as in Embodiment 1, thereby obtaining the optimal design parameters of the circuit to be designed so that it can achieve the best performance indicators.

[0060] In practical applications, the circuit design optimization device provided in this embodiment is essentially a computer device. This computer device can employ embedded chips or a computing terminal capable of executing programs. Examples include: smartphones, tablets, laptops, desktop computers, rack servers, blade servers, tower servers, or cabinet servers (including standalone servers or server clusters composed of multiple servers), etc.

[0061] The computer device in this embodiment includes, but is not limited to, a memory and a processor that can be interconnected via a system bus. In this embodiment, the memory (i.e., the readable storage medium) includes flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory can be an internal storage unit of the computer device, such as the hard disk or RAM of the computer device. In other embodiments, the memory can also be an external storage device of the computer device, such as a plug-in hard disk, smart media card (SMC), secure digital card (SD), flash card, etc. Of course, the memory can also include both internal storage units and external storage devices of the computer device. In this embodiment, the memory is typically used to store the operating system and various application software installed on the computer device. Furthermore, the memory can also be used to temporarily store various types of data that have been output or will be output. In some embodiments, the processor may be a central processing unit (CPU), a controller, a microcontroller, a microprocessor, or other data processing chip. The processor is typically used to control the overall operation of a computer device.

[0062] Simulation test 1. Experimental Design To verify the performance of the circuit design optimization method based on feasible region optimization and dynamic shrinkage (referred to as the PRABO method) provided in this invention, technicians conducted experiments in areas such as... Figure 3 The rail-to-rail operational amplifier shown and such Figure 4 The design parameters of the low-dropout linear regulator (LDO) shown were optimized. Rail-to-rail operational amplifiers maintain constant transconductance across the entire input common-mode voltage range, making them widely used in low-voltage analog signal processing front-ends. LDOs are indispensable power management modules in modern SoCs, primarily responsible for providing highly stable and clean supply voltages to noise-sensitive RF or precision analog modules. In the test experiments, both circuits were implemented using TSMC's 65nm process.

[0063] To more clearly demonstrate the advantages of the present invention, the technicians selected the traditional baseline algorithms CM-AES, WEIBO, TuRBO-1, and TuRBO-5 as control groups, and compared the optimization effects of the present invention and the control group solutions in two circuits.

[0064] During the experiment, all optimization algorithms were run on the same hardware environment, and their performance was evaluated using a high-fidelity SPICE simulator. To eliminate random errors, each algorithm was run independently multiple times to obtain the average convergence trajectory.

[0065] 2. Experimental Results and Analysis exist Figure 3 In the circuit shown, circuit gain is used as the performance metric to be optimized. The performance of different schemes after multiple rounds of iterative optimization is as follows: Figure 5 As shown in the figure, analysis of the data reveals that: WEIBO and the two TuRBO schemes quickly fell into long-tail stagnation in the early stages of optimization, with their gain values ​​stuck at a suboptimal plateau. Although the CMA-ES scheme broke the deadlock in the middle of optimization, its final convergence performance remained mediocre.

[0066] In contrast, the PRABO scheme of this invention exhibits overwhelming optimization efficiency. In the very early stages of optimization, PRABO rapidly eliminates a large amount of redundant space through mixed-dimensional filtering, accurately identifying the key parameters most sensitive to gain, resulting in a near-vertical rise in the convergence curve in the initial stages. Subsequently, adaptive constraint relaxation and multi-scale local reinforcement mechanisms concentrate their efforts within a dynamically shrinking high-quality subspace, ultimately achieving a DC gain that represents a performance leap of approximately 15% compared to traditional trust-region baseline algorithms. This fully demonstrates PRABO's absolute advantage in avoiding local optima and accelerating convergence.

[0067] exist Figure 4 In the circuit shown, the power supply rejection ratio (PSRR) is used as the performance indicator to be optimized. The performance of different schemes after multiple rounds of iterative optimization is as follows: Figure 6 As shown in the figure, analysis of the data reveals that: After TuRBO and CMA-ES barely found a local solution that satisfied all constraints in the very early stages of the simulation, their convergence curves became absolutely flat lines, failing to produce any substantial improvement over the entire remaining evaluation budget; this is a classic example of "premature convergence".

[0068] In contrast, the PRABO scheme of this invention demonstrates an extremely powerful ability to break through bottlenecks in this task. In the later stages of optimization, when all comparable algorithms have completely stalled, PRABO successfully triggers its built-in adaptive constraint relaxation and multi-scale local reinforcement mechanism; by using precise perturbation step sizes, it overcomes the barrier of the current local optimum, and the convergence curve exhibits a step-like secondary breakthrough, further widening the final PSRR performance limit by approximately 15% to 20% compared to other schemes. This experimental result strongly verifies that PRABO possesses unparalleled global exploration and limit utilization capabilities when dealing with high-dimensional complex analog circuits.

[0069] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A circuit design optimization method based on feasible region optimization and dynamic shrinkage, characterized in that, It includes: Obtain the design conditions of the analog circuit to be optimized, including: design parameters, physical boundaries, performance indicators, and constraints; Several initial samples are generated using low-difference sequences. A circuit simulator is then called to generate corresponding circuit performance based on the design parameters of the initial samples, thus forming a historical simulation dataset. The surrogate model is trained using the historical simulation dataset. Based on the quantiles of the target performance, each simulation sample is divided into high-quality and low-quality samples, and corresponding labels are added. A shallow CART decision tree is used to fit the binary classification simulation samples, and the global importance I of each design parameter is calculated based on the decrease in Gini impurity introduced at the split node for each dimension. CART ; The objective function is designed starting from the global design space. It iteratively removes low-quality samples from the edges based on label information, maximizing the density of high-quality samples in the remaining subspace, thus obtaining the optimized high-quality subspace B. PRIM And calculate the local importance I of the design parameters based on the mass gain of each stripping operation. PRIM ; The mixed importance A of each design parameter is obtained by combining global importance and local importance. The adaptive search step size of each design parameter is set according to A so that it is negatively correlated with A. With B PRIM As the initial anchor box, it will be used to move from the high-quality subspace B as the optimization process progresses. PRIM The search center is a point that smoothly transitions from the center of the current optimal feasible sample. A dynamic search hyperrectangle is generated by combining the adaptive search step size and the preset dynamic shrinkage factor. Bayesian optimization is performed on the design parameters. The optimization process uses the constraint expectation improvement function with an adaptive relaxation factor as the acquisition function.

2. The circuit design optimization method based on feasible region optimization and dynamic shrinkage as described in claim 1, characterized in that: The design parameters include transistor width, transistor length, bias current, resistance value, capacitance value, and compensation parameters in the circuit. The constraints include unity-gain bandwidth, output current, quiescent power consumption, voltage drop, load regulation, and stability margin.

3. The circuit design optimization method based on feasible region optimization and dynamic shrinkage as described in claim 2, characterized in that: The formula for generating labels for any simulated sample is: ； in, This is an indicator function; its value is 1 if the condition within the parentheses is true, and 0 otherwise. j For the first j The objective function value of each simulation sample; y 1:n This represents the set of observations for the currently collected n samples; Quantile (·) denotes the quantile calculation function; q The set quantile ratio threshold; To ultimately give the first j Binary classification labels for each simulated sample; .

4. The circuit design optimization method based on feasible region optimization and dynamic shrinkage as described in claim 1, characterized in that: Based on global importance I CART Quickly identify design parameters that have a global impact on circuit performance; their calculation formula is as follows: ； In the above formula, This represents the global importance score of the design parameters for dimension d; t represents an internal node n in the decision tree. t t is the number of samples that reach the split node t; n is the total number of samples that participate in building the decision tree; t:split on d is the summation condition, which means that only the nodes that use dimension d as the split feature are summed; This represents the decrease in Gini impurity resulting from splitting at node t.

5. The circuit design optimization method based on feasible region optimization and dynamic shrinkage as described in claim 4, characterized in that, Mixed importance of arbitrary d-dimensional design parameters The calculation formula is as follows: ； in, This represents the local importance score of the design parameters in dimension d; The weighting coefficients are used to balance the two importance scores.

6. The circuit design optimization method based on feasible region optimization and dynamic shrinkage as described in claim 5, characterized in that: Preset dynamic contraction factor It is strongly coupled with the optimization state of the iterative process and satisfies the following equation: ； in, T max For the total assessment budget; t eff The number of effective iterations; exponent This is a hyperparameter representing the nonlinear contraction rate. r min This is a preset minimum shrinkage ratio limit used to prevent the search space from degenerating into a single point.

7. The circuit design optimization method based on feasible region optimization and dynamic shrinkage as described in claim 1, characterized in that: The acquisition function in Bayesian optimization is as follows: ； in, and , , are the posterior prediction mean and standard deviation of the i-th constrained Gaussian process in the surrogate model, respectively; K represents the number of constrained Gaussian processes in the surrogate model; The cumulative distribution function of the standard normal distribution; r t For constraint relaxation factor; This represents the classic expected improvement function; It is the currently known minimum objective function value. and These are the cumulative distribution function and probability density function of the standard normal distribution, respectively. ; and The candidate design points are respectively represented by the Gaussian process surrogate model. x The posterior predictive mean and posterior predictive standard deviation.

8. A computer storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the circuit design optimization method based on feasible region optimization and dynamic shrinkage as described in any one of claims 1-7, thereby obtaining the optimal design parameters of the circuit to be designed so that it achieves the best performance indicators.

9. A computer program product comprising a computer program, characterized in that: When the computer program is executed by the processor, it implements the circuit design optimization method based on feasible region optimization and dynamic shrinkage as described in any one of claims 1-7, thereby obtaining the optimal design parameters of the circuit to be designed so that it achieves the best performance indicators.

10. A circuit design optimization apparatus, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein when the processor executes the computer program, it implements the circuit design optimization method based on feasible region optimization and dynamic shrinkage as described in any one of claims 1-7, thereby obtaining the optimal design parameters of the circuit to be designed so as to achieve the best performance indicators.

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