A power amplifier output matching network optimization method based on a ring impedance domain

Abstract

The application discloses a kind of power amplifier output matching network optimization method based on annular impedance domain, solve the problem that optimization is difficult to converge under wideband scene, target impedance domain shrinks with bandwidth and full-band response is not balanced.The method independently constructs annular optimal impedance domain defined by outer permissible boundary and inner exclusion boundary at each design frequency point, and does not depend on contour intersection;The attribution state of the transformed impedance relative to the double boundary is determined by the ray projection method, and the equal-weight error function is constructed, which converts the optimization target from the point-by-point approximation of the optimal load impedance to the transformed impedance into the corresponding annular optimal impedance domain;Iterative optimization algorithm is used to automatically optimize the output matching network parameters.The application fundamentally eliminates the problem that the target impedance domain shrinks with the increase of bandwidth, and achieves "local performance compromise" in exchange for "global response balance", with high calculation efficiency, suitable for fast design iteration of wideband power amplifier.

Description

Technical Field

[0001] This invention relates to the technical field of radio frequency and microwave power amplifier design, and in particular to a power amplifier output matching network optimization method based on the ring impedance domain. Background Technology

[0002] Power amplifier ( The RF signal amplifier is a core active component in a wireless communication transmission system, responsible for amplifying the input radio frequency signal to the required transmission power level. The core performance indicators include output power ( ), power added efficiency ( ), operating power gain ( And operating bandwidth, etc. These indicators are often interdependent: for example, pursuing higher output power often reduces power-added efficiency. Therefore, One of the design challenges is how to achieve coordinated optimization of multiple performance metrics under broadband conditions.

[0003] Output matching network ( This is located between the output of the final stage transistor and a standard 50Ω load. For any design frequency... 50Ω standard load The impedance presented at the output of the final stage transistor after transformation is denoted as . . The value of directly determines the large-signal operating state of the transistor at that frequency, including performance characteristics such as output power, power-added efficiency, and operating power gain. Therefore, Parameter design and optimization Overall performance is crucial.

[0004] exist In design practice, load traction is usually adopted. Simulation techniques are used to obtain the optimal load impedance of the final-stage transistor at various operating frequencies. And the corresponding performance contour lines. Load traction simulation is performed by systematically traversing... The impedance points on the pie chart record the output power, power-added efficiency, and operating power gain corresponding to each impedance value, thereby enabling... A set of performance contour lines are formed on the pie chart.

[0005] existing Parameter optimization methods can be categorized into the following three types based on their optimization objectives and evaluation methods:

[0006] 1. Direct optimization method based on large-signal simulation:

[0007] This method directly uses large-signal performance indicators such as output power and power-added efficiency as the optimization objective function, and repeatedly calls harmonic balance (…). , Simulation is used to evaluate each group of candidates. The parameter corresponding to Performance. Since each parameter evaluation requires performing a nonlinear large-signal circuit simulation, this method can directly reflect... Performance.

[0008] However, when When the topology is complex and the design bandwidth is wide, the search space dimension is high, and the number of simulation evaluations required increases dramatically. This results in excessively long optimization time and excessive consumption of computational resources, making it difficult to meet the actual engineering needs of rapid design iteration for broadband power amplifiers.

[0009] 2. Indirect optimization method based on discrete optimal impedance point approximation:

[0010] This method first obtains the design frequency points through load traction simulation. Optimal load impedance at Subsequently and The weighted geometric distance between them is used as the error function, utilizing the small signal. Rapid calculation of parameters through simulation and to The parameters are iteratively optimized. This method avoids repeated calls. The simulation has low overhead and high computational efficiency. Furthermore, there are methods that use a single compromise impedance point to replace multiple discrete impedance points. This reduces the difficulty of optimization.

[0011] However, the aforementioned indirect optimization method based on discrete optimal impedance points suffers from significant convergence difficulties in broadband scenarios. This convergence difficulty stems from the combined effects of multiple factors:

[0012] Firstly, It has frequency-varying characteristics, and the optimal impedance points at different frequencies are distributed in The different positions of the pie chart; secondly, in In the circle diagram, and The opposite direction of the movement trajectory as the frequency changes means that an improvement in matching at one frequency may worsen the matching quality at another frequency; thirdly, it is limited by... The network order, finite order Sufficient degrees of freedom are not available across a wide bandwidth to achieve precise frequency-by-frequency matching. These factors make the optimization process prone to conflicting matching requirements, leading to parameter optimization oscillations or failure to converge. Furthermore, if optimization is performed by approximating a single compromise impedance point across the entire bandwidth, although the convergence problem can be alleviated, the matching quality at points far from the compromise point will inevitably be sacrificed, resulting in large in-band performance fluctuations.

[0013] 3. Indirect optimization method based on overlapping impedance domains:

[0014] For the second type of method, frequency-point approximation of discrete... Due to limitations, existing technologies have further proposed the concept of an optimal impedance domain. This method... Extracting multiple frequency points from the pie chart simultaneously satisfying , The load-driven contour lines of various performance indicators are used to define the optimal impedance domain by the overlapping region of these contour lines at all frequency points. Whether or not it falls within the unified overlapping domain is taken as the optimization objective.

[0015] However, the aforementioned indirect optimization method based on overlapping impedance domains has two main problems. Firstly, this method overlaps contour lines at multiple frequency points to form a single optimal impedance domain, but the area of ​​the overlapping region shrinks with increasing bandwidth, even degenerating into an empty set in broadband scenarios, fundamentally losing its ability to guide the optimization process. Secondly, this method only requires… The algorithm enters a unified overlapping domain, but does not consider the relative balance of response levels across different frequencies. Since the large-signal performance of transistors typically decreases gradually with increasing frequency, the performance margin at low frequencies is much larger than at high frequencies. If the optimization results in… Approaching low frequencies If the high-frequency band barely enters the edge of the overlapping domain, it will cause a serious imbalance in the in-band performance response, which is not conducive to system-level thermal management, linearity maintenance and operational stability.

[0016] In summary, existing technologies for optimizing power amplifier output matching networks suffer from several technical problems, including difficulty in achieving convergence, shrinkage of the target impedance domain as bandwidth increases, and unbalanced full-band response. A new optimization method is urgently needed to overcome these shortcomings. Summary of the Invention

[0017] The purpose of this invention is to overcome the shortcomings of the prior art and provide a power amplifier output matching network optimization method based on the ring impedance domain.

[0018] To achieve the above objectives, the technical solution provided by this invention is as follows:

[0019] An optimization method for the output matching network of a power amplifier based on the ring impedance domain includes the following steps:

[0020] S1. Set the operating frequency band range and design frequency point set according to system requirements;

[0021] S2, For the final stage transistor at each design frequency point Perform load traction simulation at each location to obtain... Output power on the circle diagram Power Added Efficiency and operating power gain Performance contour lines;

[0022] S3. Based on the obtained performance contour lines, independently construct the peripheral allowable boundary at each design frequency point. and internal exclusion boundary The two together define the ring-shaped optimal impedance domain. ;

[0023] S4. Determine the output matching network. The topology is defined, the set of parameters to be optimized and its search range are clarified, and the candidate output matching network parameters are initialized.

[0024] S5. Match network parameters based on the current candidate outputs, using small signals. Parametric simulation calculation of transformation impedance at each design frequency point ;

[0025] S6. Calculate the transformation impedance at each design frequency point obtained in step S5. Determine the optimal ring impedance domain constructed in step S3 relative to the corresponding design frequency. The attribution status;

[0026] S7. Based on the assignment status of all transformation impedances determined in step S6, construct and calculate the equal-weight error function. ;

[0027] S8. If the equal weight error function If the error is equal to 0, the preset maximum number of iterations is reached, or the weighted error function no longer decreases after multiple consecutive iterations, then the current candidate output matching network parameters are taken as the optimal output matching network parameters; otherwise, the output matching network parameters are updated and the process returns to step S5.

[0028] Furthermore, in step S3, the outer allowable boundary is constructed. The process includes:

[0029] Determine the output power based on system-level performance requirements. Power Added Efficiency and operating power gain The lower limit performance thresholds are denoted as follows: , and This set of thresholds represents The minimum large-signal performance requirements that must be met at each design frequency;

[0030] Design frequency From the load traction simulation results at the location, extract the results that satisfy the following conditions: , and The three performance contour lines of the condition, each performance contour line at A closed region enclosed on the pie chart represents the corresponding design frequency. The set of impedances that satisfy the corresponding individual performance indicators;

[0031] The intersection of the three closed regions obtained is, in The impedance region on the pie chart that simultaneously meets all three lower limit performance threshold requirements is defined as the design frequency point by its outer boundary. The outer perimeter of the area is permitted. .

[0032] Furthermore, in step S3, an internal exclusion boundary is constructed. The process includes:

[0033] According to the optimal impedance domain of the ring The design requires determining the output power. Power Added Efficiency and operating power gain The upper limit performance thresholds are denoted as follows: , and This set of thresholds is used to define the boundaries of regions with excessively high performance;

[0034] Design frequency From the load traction simulation results at the location, extract the results that satisfy the following conditions: , and The three performance contour lines of the condition are taken as the intersection of the regions enclosed by the three lines;

[0035] The outer boundary of the intersection region is defined as the design frequency. Internal exclusion boundary If the intersection at a certain high-frequency design point is an empty set, then no internal exclusion boundary is set at that design frequency point. The optimal impedance domain of the ring at this design frequency. It degenerates into the area enclosed by the entire peripheral permissible boundary.

[0036] Furthermore, in step S3, a ring-shaped optimal impedance domain is constructed. The process includes:

[0037] Design frequency Permissible boundary at the outer perimeter The enclosed area is denoted as Internal exclusion boundary The enclosed area is denoted as The design frequency The optimal impedance domain of the ring is defined as follows: .

[0038] Furthermore, in step S6, the transformation impedance is determined using the horizontal ray method. Relative to the optimal impedance domain of the ring at the corresponding design frequency The attribution status includes:

[0039] First determine the transformation impedance to be judged. Is it located on the outer permissible boundary? Or internal exclusion boundary Above. Specifically, the outer permissible boundary. and internal exclusion boundary The discrete impedance points obtained from load traction simulation, when connected adjacently, geometrically form a closed polygon. If the impedance is transformed... Located at the outer permissible boundary On any finite short line segment, the transformation impedance is determined. Located at the outer permissible boundary Within; if the impedance is transformed Located within the internal exclusion boundary On any finite short line segment, the transformation impedance is determined. Located within the exclusion boundary Within. After completing the boundary judgment, then perform transformation impedance on impedances not on the boundary. Perform the horizontal ray intersection statistics, as follows:

[0040] From the transformation impedance to be determined Starting from the positive direction of the real part of the impedance, draw a horizontal ray:

[0041] ,in ≥0;

[0042] Statistically analyze the horizontal ray and the outer allowable boundary respectively. and internal exclusion boundary The number of intersections is denoted as and ; and These represent the design frequencies. The real and imaginary parts of the transformed impedance; Here is the parameter for the horizontal ray, representing the distance the horizontal ray extends along the positive direction of the real part of the impedance;

[0043] Based on the odd / even intersection rules of closed polygons in computational geometry, the following attribution determination logic is established:

[0044] like If it is an even number, including 0, then That is, the transformation impedance Located at the outer permissible boundary In addition;

[0045] like It is an odd number and If it is an even number, including 0, then and That is, the transformation impedance Located in the ring optimal impedance domain Within;

[0046] like odd number and If it is an odd number, then That is, the transformation impedance Located within the exclusion boundary Within.

[0047] Furthermore, in step S7, the equal-weighted error function The construction process is as follows:

[0048] External boundary hard constraint: If the transformation impedance at any design frequency point Located at the outer permissible boundary In addition, there is at least one design frequency. Make If the candidate output matching network parameter combination does not meet the minimum large signal performance requirement at the design frequency, then the equal-weighted error function directly takes the maximum value, i.e.:

[0049] ;

[0050] Inner boundary soft penalty: If the transformation impedance at all design frequencies... All have entered the outer allowable boundary, but the transformation impedance at some design frequency points is... Entering the internal exclusion boundary Inside, the boundary is excluded for those who enter the interior. The internal part of the design frequency point transformation impedance Apply soft penalties and define the internal exclusion zone indicator. :

[0051] ;

[0052] Equal weight error function Defined as:

[0053] ;

[0054] in, To design the total number of frequency points, For the first The weights of each design frequency point; all design frequencies use the same weights:

[0055] ;

[0056] This is the scaling factor for the soft penalty.

[0057] Furthermore, the soft penalty scaling factor The constraint condition 0 < is satisfied. <1.

[0058] Furthermore, the equal-weighted error function The following three-level evaluation logic is formed:

[0059] Level 1, i.e. There exists a transformation impedance at at least one design frequency point. Located at the outer permissible boundary In addition, the output matching network parameters are unacceptable; this level corresponds to a violation of the hard constraint on the outer boundary, representing the worst state;

[0060] The second level, namely Transformation impedance at all design frequencies All are located within the outer permissible boundary. Within, but there is a partial transformation impedance. Entering the internal exclusion boundary Internal; this level corresponds to a soft penalty at the inner boundary. The specific value is determined by the boundary of the inner entrance. The number of internal impedance points and their equal-weighted contributions are jointly determined;

[0061] Level 3 Transformation impedance at all design frequencies All are located in the corresponding annular optimal impedance domain The inner part represents the desired full-band cooperative matching state.

[0062] Compared with existing technologies, the principles and advantages of this technical solution are as follows:

[0063] 1. The optimization objective is transformed from "approaching the discrete optimal load impedance point by point" to "transforming the impedance to enter the corresponding ring-shaped optimal impedance domain". The ring-shaped optimal impedance domain provides a target region with area for each frequency point instead of a single target point, significantly reducing the constraint severity of broadband multi-frequency matching. At the same time, the three-level evaluation logic provides a clear search direction for the optimization algorithm, effectively guiding the iterative process to converge to a feasible solution.

[0064] 2. An independent ring-shaped optimal impedance domain is constructed for each design frequency point, independent of the overlap of contour lines at multiple frequency points. The existence and area of ​​the ring-shaped optimal impedance domain at each design frequency point depend only on the load-pulling response of the final stage transistor at the corresponding design frequency point and the set performance threshold, and are independent of the operating bandwidth. Therefore, even in extremely wideband design scenarios, a target impedance domain with a suitable area can still be obtained at each design frequency point.

[0065] 3. By excluding high-performance regions from the target domain through internal exclusion boundaries, the optimizer is prevented from directing impedance transformations towards the performance peaks of each design frequency. Combined with an equal-weighted error evaluation method, all design frequencies are given equal importance in the optimization process, naturally constraining the balance of the full-band response. This strategy proactively abandons the pursuit of optimal performance at a single frequency, instead achieving a more balanced overall broadband performance.

[0066] 4. The ring-shaped optimal impedance domain is directly constructed from the load traction performance contour lines. The outer allowable boundary and the inner exclusion boundary correspond to clearly defined output power, power-added efficiency, and operating power gain performance thresholds, respectively. Therefore, if the transformed impedance enters the ring-shaped optimal impedance domain, it means that the large-signal performance at the design frequency is within the preset target range, and the optimization result has clear physical meaning and interpretability.

[0067] 5. The optimal impedance domain of the ring only needs to be constructed once based on the load traction data before the optimization begins; each evaluation in the optimization iteration only requires small-signal S-parameter simulation and simple ray projection algorithm processing, without repeatedly calling time-consuming harmonic balance simulation, and the computational cost is far lower than that of the direct optimization method. Attached Figure Description

[0068] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0069] Figure 1 This is a schematic diagram of the output stage of a single-channel power amplifier in an embodiment of the present invention;

[0070] Figure 2Schematic diagram of the results of constructing the load traction performance contour lines and the ring-shaped optimal impedance domain at six specified design frequencies ((a) 22 GHz; (b) 24 GHz; (c) 26 GHz; (d) 28 GHz; (e) 30 GHz; (f) 32 GHz; This refers to the output power at the 1dB gain compression point, i.e., the transistor operating in a 1dB gain compression state. value);

[0071] Figure 3 This is a schematic diagram of impedance point attribution determination based on the horizontal ray method in an embodiment of the present invention, where (a) represents the case outside the outer allowable boundary, (b) represents the case inside the ring optimal impedance domain, and (c) represents the case inside the inner exclusion boundary.

[0072] Figure 4 This is a flowchart illustrating the principle of a power amplifier output matching network optimization method based on a ring impedance domain, according to an embodiment of the present invention.

[0073] Figure 5 Two-dimensional comparison diagrams of the initial and optimized transformation impedance distributions at six design frequency points ((a) 22 GHz; (b) 24 GHz; (c) 26 GHz; (d) 28 GHz; (e) 30 GHz; (f) 32 GHz).

[0074] Figure 6 This is a three-dimensional evolution view of the annular optimal impedance domain and the initial and optimized transformed impedance broadband trajectories in an embodiment of the present invention. Detailed Implementation

[0075] The present invention will be further described below with reference to specific embodiments:

[0076] like Figure 1 As shown, the output of the final stage transistor of the single-channel power amplifier is connected to an output matching network, and the other end of the output matching network is connected to a standard 50Ω load. For any design frequency... The impedance presented at the output terminal of the final stage transistor after a 50Ω load is transformed by the output matching network is denoted as . .

[0077] Within a given operating bandwidth, connect the transformation impedances at each design frequency point in frequency order. This can form an impedance transformation trajectory. Due to the actual output matching network... The network order is limited, thus restricting the degrees of freedom it can provide for impedance transformation. The resulting impedance trajectory cannot accurately pass through all the impedances over a large bandwidth. Therefore, this invention does not approximate discrete frequencies one by one. Instead of using a single compromise impedance point as the optimization target, we independently construct a ring-shaped optimal impedance domain based on the load traction contour lines at each design frequency. and the transformation impedance at all design frequencies. Whether they cooperate to enter their respective ring optimal impedance domains As a basis for optimization evaluation.

[0078] like Figure 4 As shown in this embodiment, a power amplifier output matching network optimization method based on the ring impedance domain includes the following steps:

[0079] S1. Set the operating frequency band range according to system requirements. and design frequency set The design frequency points are usually sampled uniformly within the operating frequency band. For example, if the operating frequency band is 22 GHz to 32 GHz, the design frequency points include 6 frequency points: 22 GHz, 24 GHz, 26 GHz, 28 GHz, 30 GHz and 32 GHz.

[0080] S2, For the final stage transistor at each design frequency point Perform load traction simulation at each location to obtain... Output power on the circle diagram Power Added Efficiency and operating power gain The performance contour lines; these performance contour lines are used to characterize the large-signal response characteristics of the final-stage transistor under different load impedance conditions. A family of closed or nearly closed contour lines forms on the pie chart.

[0081] S3. Based on the obtained performance contour lines, independently construct the peripheral allowable boundary at each design frequency point. and internal exclusion boundary The two together define the ring-shaped optimal impedance domain. ;

[0082] In this step, the outer allowable boundary is constructed. The process includes:

[0083] Determine the output power based on system-level performance requirements. Power Added Efficiency and operating power gain The lower limit performance thresholds are denoted as follows: , and This set of thresholds represents The minimum large-signal performance requirements that must be met at each design frequency;

[0084] Design frequency From the load traction simulation results at the location, extract the results that satisfy the following conditions: , and The three performance contour lines of the condition, each performance contour line at A closed region enclosed on the pie chart represents the corresponding design frequency. The set of impedances that satisfy the corresponding individual performance indicators;

[0085] The intersection of the three closed regions obtained is the impedance region that simultaneously satisfies the three lower limit performance threshold requirements on the impedance plane. The outer boundary of this impedance region is defined as the design frequency. The outer perimeter of the area is permitted. .

[0086] Permissible outer boundary The physical meaning lies in: the outer allowable boundary Any impedance point within the impedance region within the specified range will enable the final-stage transistor to operate at the designed frequency. Simultaneously satisfying the output power Power Added Efficiency and operating power gain Minimum performance requirements; if the transformation impedance Located at the outer permissible boundary In addition, it indicates that at this design frequency point If at least one large-signal performance indicator fails to meet the minimum requirements, the corresponding output matching network parameters are unacceptable.

[0087] In this step, we construct the internal exclusion boundary. The process includes:

[0088] According to the optimal impedance domain of the ring The design requires determining the output power. Power Added Efficiency and operating power gain The upper limit performance thresholds are denoted as follows: , and This set of thresholds is used to define the boundaries of regions with excessively high performance;

[0089] Design frequency From the load traction simulation results at the location, extract the results that satisfy the following conditions: , and The three performance contour lines of the condition are taken as the intersection of the regions enclosed by the three lines;

[0090] The outer boundary of the intersection region is defined as the design frequency. Internal exclusion boundary If the intersection at a certain high-frequency design point is an empty set, then no internal exclusion boundary is set at that design frequency point. The optimal impedance domain of the ring at this design frequency. It degenerates into the area enclosed by the entire peripheral permissible boundary.

[0091] Internal exclusion boundary The physical meaning is: internal exclusion boundary The impedance region within this range corresponds to the high-performance response of the transistor, and the impedance transformation... While falling into this category may result in higher single-frequency performance, due to the frequency degradation characteristics of transistor performance, pursuing high-performance response at each design frequency will lead to significantly better performance at low frequencies than at high frequencies, resulting in an uneven response across the entire frequency band.

[0092] In this step, the ring-shaped optimal impedance domain is constructed. The process includes:

[0093] Design frequency Permissible boundary at the outer perimeter The enclosed area is denoted as Internal exclusion boundary The enclosed area is denoted as The design frequency The optimal impedance domain of the ring is defined as follows: This refers to the annular region obtained by removing the region enclosed by the inner exclusion boundary from the area bounded by the outer permissible boundary. The impedance points in this annular region meet the basic large-signal performance requirements and avoid high-performance concentration areas, representing a target impedance range with moderate matching performance at that frequency that is conducive to full-band equalization.

[0094] Each design frequency independently constructs a corresponding ring-shaped optimal impedance domain. The ring-shaped optimal impedance domains at different design frequencies are independent of each other in terms of position, shape, and area, and do not depend on the overlap of contour lines at multiple frequencies. Therefore, the ring-shaped optimal impedance domain... The effectiveness is not affected by the operating bandwidth.

[0095] like Figure 2 As shown, for example, for an operating frequency band of 22 GHz to 32 GHz, the design frequency points include six points: 22 GHz, 24 GHz, 26 GHz, 28 GHz, 30 GHz, and 32 GHz. Peripheral allowable boundaries. Based on the output power ≥31dBm, power-added efficiency ≥40% Operating power gain Determining the overlapping region of performance contour lines ≥6.85 dB; internal exclusion boundary. Based on the output power ≥31.8 dBm, power-added efficiency ≥45% Operating power gain The overlapping region of performance contour lines ≥7 dB was determined. The figure shows the upper and lower limit performance contour lines for output power, power-added efficiency, and operating power gain obtained through load-pull simulation at six design frequencies. Based on this, the outer allowable boundary and inner exclusion boundary at each frequency were determined, as well as the ring-shaped optimal impedance domain constructed by the two. Each sub-figure corresponds to a design frequency, showing the distribution of performance contour lines and the shape and range of the ring-shaped optimal impedance domain at that frequency.

[0096] S4. Determine the output matching network. The topology is defined, the set of parameters to be optimized and its search range are clarified, and the candidate output matching network parameters are initialized.

[0097] S5. Match network parameters based on the current candidate outputs, using small signals. Parametric simulation calculation of transformation impedance at each design frequency point ;

[0098] S6. Calculate the transformation impedance at each design frequency point obtained in step S5. Determine the optimal ring impedance domain constructed in step S3 relative to the corresponding design frequency. The attribution status;

[0099] After obtaining the optimal impedance domain of the ring corresponding to each design frequency, it is necessary to determine the optimal impedance domain for each design frequency. Transformed impedance obtained by candidate output matching network transformation Relative to the peripheral allowable boundary at this design frequency point and internal exclusion boundary The positional relationship. Due to the optimal impedance domain of the ring. It is not a single closed area but rather consists of an outer permissible boundary. and internal exclusion boundary For a shared, ring-shaped region, simply determining whether an impedance point lies within a certain boundary is insufficient to fully characterize its belonging status. This embodiment will transform the impedance. The spatial relationship between the two boundaries serves as the basis for hierarchical evaluation in the subsequent construction of error functions.

[0100] Definition of attribution status:

[0101] For the Given a design frequency point, and assuming the transformation impedance is... ,in and These represent the design frequencies. The real and imaginary parts of the transformed impedance. The imaginary unit is used. This invention will transform the impedance. The attribution status is divided into the following three categories:

[0102] (1) Permissible outer boundary In addition;

[0103] like Then the transformation impedance at this design frequency point If the input fails to enter the allowable region that meets the minimum large-signal performance requirements, it is considered an unacceptable state. In subsequent error functions, this is treated as a hard constraint violation, and the corresponding output matching network parameter combination should be discarded.

[0104] (2) Optimal impedance domain of the ring Inside;

[0105] like and If the impedance point is located inside the outer boundary and outside the inner boundary, then it belongs to... Defined target region. This is the target matching state of the present invention, indicating the transformation impedance. At this design frequency, the basic performance requirements are met, and it is also in a moderate performance range that is conducive to broadband balance.

[0106] (3) Internal exclusion boundary internal;

[0107] like If the impedance point is within the internal exclusion region, then this state, while meeting basic performance requirements, is detrimental to full-band response equalization. This invention does not treat this state as a hard failure, but rather as a soft-penalty state in the subsequent error function, guiding the optimizer to favor... Adjust to Inside.

[0108] In this step, the horizontal ray method is used to determine the transformation impedance. Relative to the optimal impedance domain of the ring at the corresponding design frequency The attribution status includes:

[0109] First determine the transformation impedance to be judged. Is it located on the outer permissible boundary? Or internal exclusion boundary Above. Specifically, the outer permissible boundary. and internal exclusion boundary The discrete impedance points obtained from load traction simulation, when connected adjacently, geometrically form a closed polygon. If the impedance is transformed... Located at the outer permissible boundary On any finite short line segment, the transformation impedance is determined. Located at the outer permissible boundary Within; if the impedance is transformed Located within the internal exclusion boundary On any finite short line segment, the transformation impedance is determined. Located within the exclusion boundary Within. After completing the boundary judgment, then perform transformation impedance on impedances not on the boundary. Perform the horizontal ray intersection statistics, as follows:

[0110] From the transformation impedance to be determined Starting from the positive direction of the real part of the impedance, draw a horizontal ray:

[0111] ,in ≥0;

[0112] Statistically analyze the horizontal ray and the outer allowable boundary respectively. and internal exclusion boundary The number of intersections is denoted as and ; Here is the parameter for the horizontal ray, representing the distance the horizontal ray extends along the positive direction of the real part of the impedance;

[0113] Based on the odd / even intersection rules of closed polygons in computational geometry, the following attribution determination logic is established:

[0114] like If it is an even number, including 0, then That is, the transformation impedance Located at the outer permissible boundary In addition;

[0115] like odd number and If it is an even number, including 0, then and That is, the transformation impedance Located in the ring optimal impedance domain Within;

[0116] like odd number and If it is an odd number, then That is, the transformation impedance Located within the exclusion boundary Within.

[0117] To ensure robustness of the judgment, the following boundary conditions need to be handled in actual calculations: if the ray happens to pass through a vertex of the boundary or coincides with a boundary line segment, it may lead to inaccurate intersection point counting. One or more of the following methods can be used to address this: introduce a minimal perturbation δ (e.g., δ = 10) to the imaginary part of the ray's origin. -10Alternatively, the intersection points located at the boundary vertices can be uniquely processed (counted as only one intersection point or determined based on the direction of adjacent line segments).

[0118] like Figure 3 As shown, Figure 3 Image (a) shows the first type of attribution state: the horizontal ray and the outer permissible boundary. Number of intersections Even numbers (e.g.) = 2), indicating that the impedance point is located at the outer allowable boundary. Externally, the basic large-signal performance requirements are not met at this frequency.

[0119] Figure 3 (b) illustrates the second type of attribution state: horizontal rays and the outer permissible boundary. Number of intersections odd numbers (e.g.) =1), and the internal exclusion boundary Number of intersections Even numbers (e.g.) = 0), indicating that the impedance point is located at the outer allowable boundary. Inside and not within the internal exclusion boundary Internally, it belongs to the ring-shaped optimal impedance domain. This represents the ideal target state.

[0120] Figure 3 Image (c) illustrates the third type of attribution state: the horizontal ray and the outer permissible boundary. and internal exclusion boundary Number of intersections and All are odd numbers (e.g.) = 1, = 1), indicating that the impedance point has entered the internal exclusion boundary. Internally, it should be subject to a soft penalty in the subsequent equal-weighted error function.

[0121] S7. Based on the assignment status of all design frequency points determined in step S6, construct and calculate the equal-weight error function. ;

[0122] Equal weight error function The core design philosophy is: not to transform impedance With optimal load impedance Instead of using the point-to-point geometric distance as the evaluation criterion, the transformed impedance is used. Does it enter the ring optimal impedance domain at the corresponding design frequency? As an evaluation criterion, the traditional "distance minimization" optimization objective is transformed into the "domain affiliation" optimization objective.

[0123] In this step, the equal weight error function The construction process is as follows:

[0124] External boundary hard constraint: If the transformation impedance at any design frequency point Located at the outer permissible boundary In addition, there is at least one design frequency. Make If the candidate output matching network parameter combination does not meet the minimum large signal performance requirement at the design frequency, then the equal-weighted error function directly takes the maximum value, i.e.:

[0125] ;

[0126] This hard constraint on the outer boundary ensures that the basic performance requirements are met, and is the highest priority in the optimization process.

[0127] Inner boundary soft penalty: If the transformation impedance at all design frequencies... All have entered the outer allowable boundary, but the transformation impedance at some design frequency points is... Entering the internal exclusion boundary Inside, the boundary is excluded for those who enter the interior. The internal part of the design frequency point transformation impedance Apply soft penalties and define the internal exclusion zone indicator. :

[0128] ;

[0129] Equal weight error function Defined as:

[0130] ;

[0131] in, To design the total number of frequency points, For the first The weights of each design frequency point; all design frequencies use the same weights:

[0132] ;

[0133] The equal weighting setting ensures that each design frequency point has equal importance in error evaluation, and the assignment deviation at any design frequency point contributes equally to the total error, thus naturally promoting the consistency optimization of the entire frequency band.

[0134] This is a soft-penalty scaling factor, which is an empirical value and must satisfy the constraint 0 < <1, the design basis of this constraint is: when all Transformed impedance at each design frequency point All are located within the outer permissible boundary. Within, but all enter the interior, excluding the boundary. When the internal timeframe (i.e., the worst-case soft penalty situation) is reached, the resulting error value is... Since 0 < <1, therefore This ensures that "all frequencies are within the permissible outer perimeter." Within, but all fall within the internal exclusion boundary The error value of the "internal" state is still strictly less than that of "any transformation impedance". Located at the outer allowable boundary The error value of 1 when "outside" is "outside" reflects that "meeting basic performance requirements" is strictly higher than "avoiding entering the high-performance region" in terms of optimization priority.

[0135] Equal weight error function The following three-level evaluation logic is formed:

[0136] Level 1, i.e. There exists a transformation impedance at at least one design frequency point. Located at the outer allowable boundary In addition, the output matching network parameters are unacceptable; this level corresponds to a violation of the hard constraint on the outer boundary, representing the worst state;

[0137] The second level, namely Transformation impedance at all design frequencies All are located within the outer permissible boundary. Within, but there is a partial transformation impedance. Entering the internal exclusion boundary Internal; this level corresponds to a soft penalty at the inner boundary. The specific value is determined by the boundary of the inner entrance. The number of internal impedance points and their equal-weighted contributions are jointly determined;

[0138] Level 3 Transformation impedance at all design frequencies All are located in the corresponding annular optimal impedance domain The inner part represents the desired full-band cooperative matching state.

[0139] This three-level evaluation logic enables the optimization algorithm to clearly distinguish the output matching network parameter combinations of different quality levels, and establish a clear optimization direction from "unacceptable" to "acceptable but needs improvement" and then to "matching target", which helps guide the iterative search process to converge efficiently to the target solution space.

[0140] S8. If the equal weight error function If the error is equal to 0, the preset maximum number of iterations is reached, or the weighted error function no longer decreases after multiple consecutive iterations, then the current candidate output matching network parameters are taken as the optimal output matching network parameters; otherwise, the output matching network parameters are updated and the process returns to step S5.

[0141] This invention forms a closed-loop optimization process of "performance contour line extraction → construction of the ring optimal impedance domain → transformation impedance calculation → attribution status determination → equal weight error evaluation → parameter iterative update". This process has the following technical features: (1) The ring optimal impedance domain only needs to be constructed once before the optimization starts, and the load traction simulation does not need to be repeated during the optimization iteration process, which ensures the computational efficiency; (2) The calculation of transformation impedance in each iteration is based on small signal S-parameter simulation, which is much faster than harmonic balance simulation; (3) The equal weight error function effectively divides the search space of output matching network parameters through the ring optimal impedance domain constraint, enabling the optimization algorithm to quickly locate the feasible solution region.

[0142] To demonstrate the effectiveness of the method described in this invention, the following section presents two-dimensional frequency point-by-frequency results verification and three-dimensional frequency slice results characterization.

[0143] Two-dimensional frequency-by-frequency verification:

[0144] After obtaining the optimized output matching network parameters, the annular optimal impedance domain at each design frequency is first plotted in the two-dimensional impedance plane (with the real part of impedance as the horizontal axis and the imaginary part of impedance as the vertical axis) corresponding to that design frequency. And simultaneously mark the transformation impedance before and after optimization. The location is used to verify the local fall-off situation at each design frequency point on a frequency-by-frequency basis.

[0145] like Figure 5 As shown, the transformation impedance at all design frequency points before optimization None of them are in the corresponding ring optimal impedance domain Internal; after optimization, the transformation impedance at each design frequency point All successfully entered their corresponding annular optimal impedance domain This result validates the optimal impedance domain of the ring. Constraints and equal-weighted error functions can effectively guide the output matching network parameters to converge toward the target solution space.

[0146] Three-dimensional frequency slice full-band characterization:

[0147] While two-dimensional frequency-by-frequency verification can confirm the local impedance domain at each discrete frequency point, it cannot reflect the continuity of impedance trajectories between different frequencies or the cooperative constraint relationship across the entire frequency band. Therefore, this invention further employs three-dimensional frequency slice plots to characterize the full-band results.

[0148] The coordinates of this three-dimensional frequency slice are set as follows: based on the real part of the transformed impedance. Using the first coordinate axis as an example, the imaginary part of the transformed impedance is used. As the second coordinate axis, with frequency The third coordinate axis is used. The corresponding annular optimal impedance domains are plotted at different frequencies. Slicing (forming a set of ring-shaped target domains arranged along the frequency direction), and comparing the transformation impedance at each design frequency point before and after optimization. Connect them in frequency order to form broadband impedance transformation trajectories before and after optimization, respectively.

[0149] like Figure 6 As shown, the optimal ring impedance domains corresponding to each design frequency point Arranged sequentially along the frequency direction, a target domain sequence with a clear frequency correspondence is formed. A ring-shaped optimal impedance domain can be observed. The shape, area, and position of the transistor gradually change with frequency, reflecting the role of the transistor's frequency-dependent characteristics in the construction of the target domain. The optimized transformation impedance... All are located in the annular optimal impedance domain of their corresponding frequency slices. Within the frequency range, a continuous and smooth impedance trajectory is formed, verifying the synergistic constraint effect of the present invention on the impedance trajectory across the entire frequency band.

[0150] Three-dimensional frequency slice plot as the ring optimal impedance domain The technical characterization methods that complement the optimization method have the following irreplaceable functions: (1) Compared with multiple two-dimensional graphs displayed side by side, three-dimensional graphs can retain complete information on the three dimensions of impedance real part, impedance imaginary part and frequency in the same coordinate system, and directly present the continuous evolution trend of impedance trajectory along the frequency direction; (2) Compared with the direct superposition and display of multiple two-dimensional impedance domains of different frequencies, three-dimensional graphs use frequency coordinates to display the impedance at each design frequency point. Natural separation avoids overlap and confusion between different frequency target domains, maintaining the "design frequency point—" — The one-to-one correspondence between “”; (3) The three-dimensional characterization can prove that the present invention achieves the overall coordinated control of the full-band impedance trajectory, rather than just the isolated domain verification of a few discrete impedance points.

[0151] The above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Therefore, any changes made in accordance with the shape and principle of the present invention should be covered within the protection scope of the present invention.

Claims

1. A method for optimizing the output matching network of a power amplifier based on the ring impedance domain, characterized in that, Includes the following steps: S1. Set the operating frequency band range and design frequency point set according to system requirements; S2, For the final stage transistor at each design frequency point Perform load traction simulation at each location to obtain... Output power on the circle diagram Power Added Efficiency and operating power gain Performance contour lines; S3. Based on the obtained performance contour lines, independently construct the peripheral allowable boundary at each design frequency point. and internal exclusion boundary and from the outer permissible boundary and internal exclusion boundary Together they form a ring-shaped optimal impedance domain ; S4. Determine the output matching network. The topology is defined, the set of parameters to be optimized and its search range are clarified, and the candidate output matching network parameters are initialized. S5. Match network parameters based on the current candidate outputs, using small signals. Parametric simulation calculation of transformation impedance at each design frequency point ; S6. Calculate the transformation impedance at each design frequency point obtained in step S5. Determine the optimal ring impedance domain constructed in step S3 relative to the corresponding design frequency. The attribution status; S7. Based on the assignment status of all transformation impedances determined in step S6, construct and calculate the equal-weight error function. ; S8. If the equal weight error function If the error is equal to 0, the preset maximum number of iterations is reached, or the weighted error function no longer decreases after multiple consecutive iterations, then the current candidate output matching network parameters are taken as the optimal output matching network parameters; otherwise, the output matching network parameters are updated and the process returns to step S5. In step S3, the outer allowable boundary is constructed. The process includes: Determine the output power based on system-level performance requirements. Power Added Efficiency and operating power gain The lower limit performance thresholds are denoted as follows: , and This lower limit performance threshold represents The minimum large-signal performance requirements that must be met at each design frequency; Design frequency From the load traction simulation results at the location, extract the results that satisfy the following conditions: , and The three performance contour lines of the condition, each performance contour line at A closed region enclosed on the pie chart represents the corresponding design frequency. The set of impedances that satisfy the corresponding individual performance indicators; The intersection of the three closed regions obtained is, in The impedance region on the pie chart that simultaneously meets all three lower limit performance threshold requirements is defined as the design frequency point by its outer boundary. The outer perimeter of the area is permitted. ; In step S3, construct the internal exclusion boundary. The process includes: According to the optimal impedance domain of the ring The design requires determining the output power. Power Added Efficiency and operating power gain The upper limit performance thresholds are denoted as follows: , and This upper limit performance threshold is used to define the boundary of areas where performance is too high; Design frequency From the load traction simulation results at the location, extract the results that satisfy the following conditions: , and The three performance contour lines of the condition are taken as the intersection of the regions enclosed by the three lines; The outer boundary of the intersection region is defined as the design frequency. Internal exclusion boundary If the intersection at a certain high-frequency design point is an empty set, then no internal exclusion boundary is set at that design frequency point. The optimal impedance domain of the ring at this design frequency. It degenerates into the area enclosed by the entire outer permissible boundary; In step S3, the ring-shaped optimal impedance domain is constructed. The process includes: Design frequency Permissible boundary at the outer perimeter The enclosed area is denoted as Internal exclusion boundary The enclosed area is denoted as The design frequency The optimal impedance domain of the ring is defined as follows: .

2. The power amplifier output matching network optimization method based on the ring impedance domain according to claim 1, characterized in that, In step S6, the transformation impedance is determined using the horizontal ray method. Relative to the optimal impedance domain of the ring at the corresponding design frequency The attribution status includes: First determine the transformation impedance to be judged. Is it located on the outer permissible boundary? Or internal exclusion boundary Above; if the impedance is transformed Located at the outer permissible boundary On any finite short line segment, the transformation impedance is determined. Located at the outer permissible boundary Within; if the impedance is transformed Located within the internal exclusion boundary On any finite short line segment, the transformation impedance is determined. Located within the exclusion boundary Within; after completing the boundary judgment, then transform the impedance that is not on the boundary. Perform the horizontal ray intersection statistics, as follows: From the transformation impedance to be determined Starting from the positive direction of the real part of the impedance, draw a horizontal ray: ,in ≥0; Statistically analyze the horizontal ray and the outer allowable boundary respectively. and internal exclusion boundary The number of intersections is denoted as and ; and These represent the design frequencies. The real and imaginary parts of the transformed impedance; Here is the parameter for the horizontal ray, representing the distance the horizontal ray extends along the positive direction of the real part of the impedance; Based on the odd / even intersection rules of closed polygons in computational geometry, the following attribution determination logic is established: 1) If If it is an even number, including 0, then That is, the transformation impedance Located at the outer permissible boundary Besides; 2) If odd number and If it is an even number, including 0, then and That is, the transformation impedance Located in the ring optimal impedance domain Within; 3) If odd number and If it is an odd number, then That is, the transformation impedance Located within the exclusion boundary Within.

3. The power amplifier output matching network optimization method based on the ring impedance domain according to claim 2, characterized in that, In step S7, the equal-weighted error function The construction process is as follows: External boundary hard constraint: If the transformation impedance at any design frequency point Located at the outer permissible boundary In addition, there is at least one design frequency. Make If the candidate output matching network parameter combination does not meet the minimum large signal performance requirement at the design frequency, then the equal-weighted error function directly takes the maximum value, i.e.: ； Inner boundary soft penalty: If the transformation impedance at all design frequencies... All have entered the outer allowable boundary, but the transformation impedance at some design frequency points is... Entering the internal exclusion boundary Inside, the boundary is excluded for those who enter the interior. The internal part of the design frequency point transformation impedance Apply soft penalties and define the internal exclusion zone indicator. : ； Equal weight error function Defined as: ； in, To design the total number of frequency points, For the first The weights of each design frequency point; all design frequencies use the same weights: ； This is the scaling factor for the soft penalty.

4. The power amplifier output matching network optimization method based on the ring impedance domain according to claim 3, characterized in that, The soft penalty scaling factor The constraint condition 0 < is satisfied. <1.

5. A method for optimizing the output matching network of a power amplifier based on a ring impedance domain, as described in claim 3 or 4, characterized in that, Equal weight error function The following three-level evaluation logic is formed: Level 1, i.e. There exists a transformation impedance at at least one design frequency point. Located at the outer allowable boundary In addition, the output matching network parameters are unacceptable; this level corresponds to a violation of the hard constraint on the outer boundary, representing the worst state; The second level, namely Transformation impedance at all design frequencies All are located within the outer permissible boundary. Within, but there is a partial transformation impedance. Entering the internal exclusion boundary Internal; this level corresponds to a soft penalty at the inner boundary. The specific value is determined by the boundary of the inner entrance. The number of internal impedance points and their equal-weighted contributions are jointly determined; Level 3 Transformation impedance at all design frequencies All are located in the corresponding annular optimal impedance domain The inner part represents the desired full-band cooperative matching state.

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