A project progress intelligent tracking and resource scheduling method and system

Abstract

The present application relates to the field of project management data processing, and discloses a kind of project progress intelligent tracking and resource scheduling method and system, comprising: analysis project business data and generate the directed acyclic topological graph containing job node;Obtain the discrete timestamp sequence when job node is in state machine migration;According to the timestamp difference of pre- and post- job node Determine handover gap parameter, and calculate the cascade lag weight reflecting the degree of path lag;When cascade lag weight is greater than trigger threshold, the available resource capability vector under non-critical path is reset to the initial resource capability vector of post-job node, and the scheduling instruction is output, the present application captures the asynchronous loss generated by task handover, identifies the invisible link lag in traditional monitoring model, realizes the predictive logic adjustment on resource weight before implicit loss is converted into explicit overdue, effectively eliminates resource idling and improves scheduling accuracy.

Description

Technical Field

[0001] This invention relates to a method and system for intelligent tracking of project progress and resource scheduling, belonging to the field of project management data processing technology. Background Technology

[0002] In current data processing systems for management and forecasting purposes, project cycles are determined and resource scheduling is implemented by constructing task dependency networks. Existing systems periodically collect the completion status values ​​of each execution node, compare them with the planned baseline time, and generate resource compensation instructions. As the dimension of the task topology network increases, the state transition process between nodes creates blind spots in data observation. There is an asynchronous handover gap between the completion process of the preceding task and the warm-up process of the subsequent task. This handover gap consists of logical processes such as information synchronization, rights confirmation, and resource readiness, and cannot be reflected by the progress value of a single node. In the process of multi-level task transmission, the connection resistance generates non-linear accumulation, resulting in timing deviations in resource scheduling.

[0003] By shortening the sampling frequency or lowering the warning threshold to capture deviations, scheduling signals containing redundant noise are often generated. Simply increasing resource redundancy cannot eliminate the implicit losses in the handover process and increases the overall management overhead. Existing processing logic is triggered after implicit losses are transformed into explicit overdue periods, resulting in scheduling instructions being in a state of delayed compensation. Software logic control methods have shortcomings in addressing the limitations of hardware resource allocation topology. For example, Chinese invention patent CN119621272B discloses a cluster job scheduling method and system. It optimizes job completion time by constructing normal and special state scheduling modes through graph neural networks and reinforcement learning. The determination of long-tail jobs depends on the statistical regularity of the preset expected execution time of jobs. Based on the overall statistical identification mechanism, jobs are regarded as independent static nodes, ignoring the dynamic surface losses induced by state machine transitions during task handover. It lacks real-time capture and gradient analysis of discrete timestamp sequences between nodes, and cannot quantify the degree of logical obstruction at the connection point. The scheduling response lags and execution resistance generates timing.

[0004] Therefore, how to quantify the gap loss in the task topology and achieve predictive resource-oriented scheduling based on the attenuation gradient is the technical problem to be solved by this invention. Summary of the Invention

[0005] To address the problems in the background art, the technical solution of the present invention is as follows: A method for intelligent tracking of project progress and resource scheduling, comprising the following steps: Step S101: Receive project business data, parse the directed acyclic topology graph containing multiple job nodes, and associate the baseline job window and nominal capacity vector for each job node. Step S102: Monitor the flow status of data flow in the directed acyclic topology graph, and obtain the discrete timestamp sequence written to the memory by each job node when the state machine transition is triggered. The discrete timestamp sequence includes the first discrete timestamp of the previous job node outputting the closing instruction and the second discrete timestamp of the subsequent job node reading the preheating instruction, which has a direct dependency on the previous job node. Step S103: Calculate the difference between the second discrete timestamp and the first discrete timestamp to obtain the junction gap parameter, which characterizes the degree of obstruction at the logical junction point in the directed acyclic topology graph. Step S104: Read the baseline operation window corresponding to the subsequent operation node, calculate the ratio of the handover gap parameter to the baseline operation window, and obtain the cascade lag weight that reflects the degree of lag of the affected path. Step S105: When the cascading hysteresis weight is greater than the preset trigger threshold, traverse the directed acyclic topology graph to locate the non-critical execution path in an inactive state, and read the available resource capability vector under the non-critical execution path that is not locked by the underlying process. Step S106: Send a release command to sever the mapping relationship between the available resource capability vector and the original non-critical execution path. Calculate the allocation ratio based on the deviation of the cascaded hysteresis weight from the trigger threshold. Merge the extracted available resource capability vector into the initial resource capability vector of the subsequent job node. Output a reset scheduling command containing the updated resource address mapping relationship.

[0006] Preferably, step S104 includes the following sub-steps: Step S1041, accumulating the cascading lag weights of each job node along the critical path of the directed acyclic topology to obtain the global lag evaluation value of the critical path; Step S1042, when the global lag evaluation value exceeds a preset evolution threshold, triggering a resource scheduling warning action, and eliminating asynchronous losses between job nodes with dependencies by adjusting the resource allocation weights in the directed acyclic topology.

[0007] Preferably, the step of obtaining the discrete timestamp sequence in step S102 includes the following sub-steps: Step S1021, by comparing with the baseline job window of each job node, identify state islands in the discrete timestamp sequence that have undergone logical transitions; Step S1022, perform time-domain alignment on the state islands and remove the off-time points caused by abnormal offsets; Step S1023, based on the aligned discrete timestamp sequence, fit the response slope of each job node during the process of switching from preheating to job state.

[0008] Preferably, the step of generating the handover gap parameter in step S103 includes the following sub-steps: step S1031, extracting the first discrete timestamp of the preceding work node in the delivery state; step S1032, extracting the second discrete timestamp of the following work node in the preheating state; step S1033, calculating the absolute time difference between the first discrete timestamp and the second discrete timestamp.

[0009] Preferably, the step of outputting the reset scheduling instruction in step S106 includes the following sub-steps: Step S1061, determining the bottleneck path with the highest propulsion efficiency decay rate in the directed acyclic topology graph according to the cascaded hysteresis weight; Step S1062, retrieving non-critical paths that have resource coupling relationships with the bottleneck path and evaluating the resource redundancy of the non-critical paths; Step S1063, mapping the resource identifiers corresponding to the non-critical paths to the bottleneck paths.

[0010] Preferably, after generating the cascaded hysteresis weights in step S104, the following sub-steps are also included: step S1043, analyzing the evolution trend of the cascaded hysteresis weights within the continuous sampling period; step S1044, when the evolution trend is monotonically increasing and the growth rate exceeds the preset change rate threshold, determining that there is a risk of cascade failure in the directed acyclic topology graph; step S1045, outputting a blocking instruction for the risk of cascade failure.

[0011] Preferably, after outputting the resource scheduling instruction in step S106, the following sub-steps are also included: step S1064, collecting the reset scheduling instructions generated within a preset time period and the corresponding instruction cancellation records, and calculating the instruction cancellation rate; step S1065, establishing a feedback correspondence between the instruction cancellation rate and the trigger threshold, and correcting the value of the trigger threshold based on the correspondence.

[0012] Preferably, the project business data includes priority labels of job nodes and resource constraints; the parsing of the directed acyclic topology graph containing multiple job nodes in step S101 includes the following sub-steps: step S1011, based on the priority labels, determine the weight distribution of each execution path in the directed acyclic topology graph; step S1012, combined with the resource constraints, perform topology constraint verification on the weight distribution.

[0013] Preferably, after correcting the value of the trigger threshold, the following sub-steps are also included: Step S1066, recording the resource flow trajectory after the resource scheduling instruction is triggered; Step S1067, performing correlation analysis between the resource flow trajectory and the time series view composed of discrete timestamp sequences to evaluate the contribution of the resource scheduling instruction to eliminating asynchronous losses between nodes.

[0014] A project progress intelligent tracking and resource scheduling system, used to implement a project progress intelligent tracking and resource scheduling method, includes: The parsing module is used to receive project business data, parse the directed acyclic topology graph containing multiple job nodes, and associate a baseline job window and a nominal capability vector with each job node. The monitoring module is used to monitor the flow status of data in the directed acyclic topology graph and obtain the discrete timestamp sequence written to the memory by each job node when the state machine transition is triggered. The calculation module is used to calculate the difference between the second discrete timestamp and the first discrete timestamp in the discrete timestamp sequence to generate the handover gap parameter, and to generate a cascaded lag weight reflecting the degree of lag of the affected path based on the ratio of the handover gap parameter to the baseline operation window. The reset module is used to read the available resource capability vectors that are not locked by the underlying process in the non-critical execution path when the cascading hysteresis weight is greater than the preset trigger threshold. Based on the deviation of the cascading hysteresis weight from the trigger threshold, the available resource capability vectors are merged into the initial resource capability vector of the subsequent job node, and the reset scheduling instruction containing the updated resource address mapping relationship is output.

[0015] Compared with the prior art, the beneficial effects of the present invention are: 1. In intelligent project progress tracking and resource scheduling, the processor collects the actual timestamps of each execution node entering the preheating, running, closing and delivery states; by comparing with objective time information sequences, a true time sequence view of node state transitions is established. This mechanism replaces the feedback method of manually reporting progress percentages, eliminates data distortion caused by subjective evaluation bias, and the management system extracts underlying data representing project evolution based on real discrete event records, thereby improving the timeliness and accuracy of progress tracking.

[0016] 2. The processor extracts the difference between the closing timestamp of the preceding node and the warm-up timestamp of the corresponding following node to generate a handover gap parameter that characterizes the resistance to task connection. This parameter is combined with the node's baseline execution window, and the generated cascaded lag weight reveals the implicit resource flow loss in the task topology network. By transforming the dispersed task states into quantitative indicators that describe the degree of path obstruction, the system can identify the decay trend of execution momentum in advance before local friction evolves into global delay, breaking the blind spot of traditional monitoring models in observing cross-node connection loss.

[0017] 3. Based on the deviation of the cascaded hysteresis weights, the processor automatically calculates the allocation ratio and adjusts the address mapping of the resource capability vector accordingly. By cutting off the resource locking state of non-critical paths and injecting the released available capabilities into the blocked nodes, the logical redistribution of resource weights is realized. This dynamic reset mechanism based on decay gradients transforms post-event manual remediation into a spontaneous logical response of the system. While ensuring the continuity of the critical path, it improves the resource turnover efficiency of processing equipment in complex management environments. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating the intelligent tracking of project progress and dynamic resource reset scheduling of the present invention. Figure 2 This is the logic diagram for the environmental adaptive threshold determination and closed-loop feedback adjustment of the present invention.

[0019] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0021] A method for intelligent project progress tracking and resource scheduling includes the following steps: Step S101: Receive project business data, parse the directed acyclic topology graph containing multiple job nodes, and associate the baseline job window and nominal capacity vector for each job node. Step S102: Monitor the flow status of data flow in the directed acyclic topology graph, and obtain the discrete timestamp sequence written to the memory by each job node when the state machine transition is triggered. The discrete timestamp sequence includes the first discrete timestamp of the previous job node outputting the closing instruction and the second discrete timestamp of the subsequent job node reading the preheating instruction, which has a direct dependency on the previous job node. Step S103: Calculate the difference between the second discrete timestamp and the first discrete timestamp to obtain the junction gap parameter, which characterizes the degree of obstruction at the logical junction point in the directed acyclic topology graph. Step S104: Read the baseline operation window corresponding to the subsequent operation node, calculate the ratio of the handover gap parameter to the baseline operation window, and obtain the cascade lag weight that reflects the degree of lag of the affected path. Step S105: When the cascading hysteresis weight is greater than the preset trigger threshold, traverse the directed acyclic topology graph to locate the non-critical execution path in an inactive state, and read the available resource capability vector under the non-critical execution path that is not locked by the underlying process. Step S106: Send a release command to sever the mapping relationship between the available resource capability vector and the original non-critical execution path. Calculate the allocation ratio based on the deviation of the cascaded hysteresis weight from the trigger threshold. Merge the extracted available resource capability vector into the initial resource capability vector of the subsequent job node. Output a reset scheduling command containing the updated resource address mapping relationship.

[0022] Preferably, step S104 includes the following sub-steps: Step S1041, accumulating the cascading lag weights of each job node along the critical path of the directed acyclic topology to obtain the global lag evaluation value of the critical path; Step S1042, when the global lag evaluation value exceeds a preset evolution threshold, triggering a resource scheduling warning action, and eliminating asynchronous losses between job nodes with dependencies by adjusting the resource allocation weights in the directed acyclic topology.

[0023] Preferably, the step of obtaining the discrete timestamp sequence in step S102 includes the following sub-steps: Step S1021, by comparing with the baseline job window of each job node, identify state islands in the discrete timestamp sequence that have undergone logical transitions; Step S1022, perform time-domain alignment on the state islands and remove the off-time points caused by abnormal offsets; Step S1023, based on the aligned discrete timestamp sequence, fit the response slope of each job node during the process of switching from preheating to job state.

[0024] Preferably, the step of generating the handover gap parameter in step S103 includes the following sub-steps: step S1031, extracting the first discrete timestamp of the preceding work node in the delivery state; step S1032, extracting the second discrete timestamp of the following work node in the preheating state; step S1033, calculating the absolute time difference between the first discrete timestamp and the second discrete timestamp.

[0025] Preferably, the step of outputting the reset scheduling instruction in step S106 includes the following sub-steps: Step S1061, determining the bottleneck path with the highest propulsion efficiency decay rate in the directed acyclic topology graph according to the cascaded hysteresis weight; Step S1062, retrieving non-critical paths that have resource coupling relationships with the bottleneck path and evaluating the resource redundancy of the non-critical paths; Step S1063, mapping the resource identifiers corresponding to the non-critical paths to the bottleneck paths.

[0026] Preferably, after generating the cascaded hysteresis weights in step S104, the following sub-steps are also included: step S1043, analyzing the evolution trend of the cascaded hysteresis weights within the continuous sampling period; step S1044, when the evolution trend is monotonically increasing and the growth rate exceeds the preset change rate threshold, determining that there is a risk of cascade failure in the directed acyclic topology graph; step S1045, outputting a blocking instruction for the risk of cascade failure.

[0027] Preferably, after outputting the resource scheduling instruction in step S106, the following sub-steps are also included: step S1064, collecting the reset scheduling instructions generated within a preset time period and the corresponding instruction cancellation records, and calculating the instruction cancellation rate; step S1065, establishing a feedback correspondence between the instruction cancellation rate and the trigger threshold, and correcting the value of the trigger threshold based on the correspondence.

[0028] Preferably, the project business data includes priority labels of job nodes and resource constraints; the parsing of the directed acyclic topology graph containing multiple job nodes in step S101 includes the following sub-steps: step S1011, based on the priority labels, determine the weight distribution of each execution path in the directed acyclic topology graph; step S1012, combined with the resource constraints, perform topology constraint verification on the weight distribution.

[0029] Preferably, after correcting the value of the trigger threshold, the following sub-steps are also included: Step S1066, recording the resource flow trajectory after the resource scheduling instruction is triggered; Step S1067, performing correlation analysis between the resource flow trajectory and the time series view composed of discrete timestamp sequences to evaluate the contribution of the resource scheduling instruction to eliminating asynchronous losses between nodes.

[0030] Preferably, a project progress intelligent tracking and resource scheduling system includes: The parsing module is used to receive project business data, parse the directed acyclic topology graph containing multiple job nodes, and associate a baseline job window and a nominal capability vector with each job node. The monitoring module is used to monitor the flow status of data in the directed acyclic topology graph and obtain the discrete timestamp sequence written to the memory by each job node when the state machine transition is triggered. The calculation module is used to calculate the difference between the second discrete timestamp and the first discrete timestamp in the discrete timestamp sequence to generate the handover gap parameter, and to generate a cascaded lag weight reflecting the degree of lag of the affected path based on the ratio of the handover gap parameter to the baseline operation window. The reset module is used to read the available resource capability vectors that are not locked by the underlying process in the non-critical execution path when the cascading hysteresis weight is greater than the preset trigger threshold. Based on the deviation of the cascading hysteresis weight from the trigger threshold, the available resource capability vectors are merged into the initial resource capability vector of the subsequent job node, and the reset scheduling instruction containing the updated resource address mapping relationship is output.

[0031] Example 1: In a complex engineering project management environment with high-dimensional task-dependent networks and dynamic resource constraints, a project progress intelligent tracking and resource scheduling method and system are adopted to perform real-time processing on a directed acyclic graph (DAG) involving multiple job nodes. The parsing module receives project business data containing priority labels and resource constraints, parses and generates a DAG containing multiple job nodes. During the parsing process, the parsing module extracts JSON-formatted business data streams containing unique task identifiers and their preceding dependency lists line by line. Based on this structure, an adjacency matrix is ​​constructed in real time with task nodes as geometric vertices and dependencies as directed edges. Depth-first search (DFS) is then called on this adjacency matrix to perform closed-loop path detection, forcibly cutting all contradictory reverse dependencies, thereby completing the precise mathematical mapping of engineering logic to the DAG. At the same time, a preset baseline job window and nominal capability vector are associated with each job node. The priority label of each job node is used to determine the weight distribution of each execution path in the DAG, and the weight distribution is verified by topological constraints in combination with resource constraints to establish the initial execution baseline.

[0032] Once the directed acyclic graph (DAG) enters the execution state, the monitoring module continuously monitors the data flow status and obtains the discrete timestamp sequence written to memory by each job node when triggering state machine transitions. Within a specific business cycle, the calculation module extracts the first discrete timestamp of the closing instruction output by the preceding job node. And the second discrete timestamp of the preheating command read by the subsequent job node with a direct dependency. ,in These are discrete time points representing the preceding task nodes in the delivery state. For the discrete time points of the subsequent task nodes in the preheating state, the second discrete timestamp is calculated. With the first discrete timestamp The absolute difference is used to obtain the handover gap parameter G, where G represents the degree of obstruction at the logical handover point. Based on this, the calculation module further reads the baseline job window corresponding to the subsequent job node. The benchmark job window The preset value is used, and the handover gap parameter G is calculated against the baseline operation window. The ratio is used to generate cascaded lag weights W, which reflect the degree of path lag, thereby transforming the connection resistance in the observation blind zone into a quantitative indicator describing the degree of path lag.

[0033] When the cascading hysteresis weight W of a specific path is detected to be greater than a preset trigger threshold, During this process, the reset module traverses the directed acyclic graph (DAG) to locate non-critical execution paths that are inactive, and reads the available resource capability vectors that are not locked by the underlying processes along that path. ,in This represents the available computing power or material supply quantity that can be reset and allocated. Specifically, for the non-computing resource of material supply quantity, the system calls the data interface of the underlying Manufacturing Execution System (MES) or Programmable Logic Controller (PLC) through the fieldbus protocol to read in real time the values ​​of idle raw material registers that have not yet been allocated to valid process barcodes at the current physical workstation. These values, along with the surface-level CPU thread occupancy parameter, are encapsulated in a unified data structure, thus forming a multi-dimensional heterogeneous available resource capability vector. The system sends a release command to sever the mapping relationship between this available resource capability vector Vres and the original non-critical execution path, and then determines whether the cascaded hysteresis weight W exceeds the trigger threshold. The deviation is used to calculate the allocation ratio, and the extracted available resource capability vector is then used. By merging the initial resource capability vector of the blocked post-job node into the underlying bus, the injected incremental computing cores are then allocated to the dedicated communication protocol stack and handshake verification module of the blocked post-job node. Through multi-threaded parallel execution of the decryption and disassembly of status data packets, checksum comparison, and bus authority confirmation response logic, the buffer queuing time of inter-node information synchronization data is compressed by orders of magnitude. High-density computing power intervention smooths out the physical handshake time difference in calendar flow. Finally, a reset scheduling instruction containing the updated resource address mapping relationship is output to the execution terminal. This dynamic reset mechanism based on decay gradient promotes the transformation of the management system from lag compensation to predictive logic response. Under the premise of maintaining hardware architecture stability, by coordinating the processing of discrete timestamp sequences and resource capability vectors, it reduces the accumulation of cascading delays in task-dependent networks and improves the resource turnover efficiency of the management predictive data processing system.

[0034] Example 2: Based on a discrete event-driven model and having In a computational simulation environment for processing business data, a historical engineering management log dataset containing 500 job nodes is used as the data source. When collecting discrete timestamp sequences, the computation module adds Gaussian white noise with a mean of 0ms and a standard deviation of 50ms to the signal source to simulate reporting bias and random jitter caused by information synchronization. This aims to establish the system's monitoring stability in a real environment including sampling errors; trigger threshold. The value of defines the reset frequency of the directed acyclic topology (DAG), where To determine the critical threshold for initiating resource scheduling, a Directed Acyclic Graph (DAG) is used to represent a network of job nodes with dependencies. When the threshold is triggered... When the value is 0.05, the underlying bus communication load increases by 35.4% compared to the initial state, and the trigger threshold is reached. When the value is 0.90, the cascading delay accumulation on the critical path increases by 28.7%. The working window is determined to be 0.15 to 0.25 through gradient comparison. Within this range, the management system generates a predictive response before the implicit loss turns into an explicit overdue.

[0035] For a single business operation cycle, the control group maintained a fixed-period polling progress tracking method, while the experimental group extracted the first discrete timestamp of the preceding task node through the monitoring module. The second discrete timestamp is 1024567.8ms and the subsequent job node. It is 1024721.3ms, of which For discrete time points of the preceding task node in the delivery state For discrete time points of subsequent work nodes in the preheating state, the calculation module uses the second discrete timestamp. With the first discrete timestamp The absolute difference determines the handover gap parameter G to be 153.5ms, where G characterizes the degree of obstruction at the logical handover point. The baseline operation window of the subsequent operation node is read. The timeout is set to 800.0 ms, and the cascading lag weight W is determined to be 0.1919, where W is defined as the ratio of the handover gap parameter G to the baseline operation window. The ratio, the reset module identifies the cascade hysteresis weight W as greater than the trigger threshold. Extract the available resource capability vector under non-critical execution paths The nominal unit is 15.0, of which This represents the allocable computing power or material supply, and is incorporated into the nominal capacity vector of the subsequent operation node. The cumulative cascading delay time on the critical path of the experimental group was 412.3 ms, while that of the control group was 1245.6 ms. The resource turnover efficiency was improved by 22.8% compared to the control group. When the handover gap parameter G exceeds the baseline operation window... After being 1.2 times larger, the available resource capacity vector becomes blocked due to the evolution of connection resistance into logical blockage. The slope of the reset direction for improving key performance indicators tends to zero and a deterioration inflection point is generated. This data feedback defines the resource scheduling boundary when the state of the pre-processing and post-processing work nodes is handed over.

[0036] Example 3: This example combines Figures 1 to 2 This document describes a method and system for intelligent project progress tracking and resource scheduling, such as... Figure 1As shown, the process begins with the node operation that receives business data, parses the topology graph, and associates windows and vectors. It then proceeds along the connection to the node operation that monitors the flow status and obtains the discrete timestamp sequence of state transitions. Next, it points to the node operation that calculates the timestamp difference to obtain the logical handover gap parameter. After that, it continues to the node operation that calculates the handover gap parameter and the window ratio to generate lag weights. It then flows further down to the node operation that reads non-critical path resource vectors when the lag weight exceeds the threshold. Finally, the connection leads to the node operation that extracts resource vectors, merges them into the downstream node, and outputs scheduling instructions, thus forming a complete resource reset to scheduling main link.

[0037] like Figure 2 As shown, it includes two parallel front-end data processing branches, left and right. The left branch starts from the node idle state acquisition step, moves down to the background noise benchmark fitting step, and further reaches the local trigger threshold generation step. At the same time, the right branch starts from the instruction cancellation record collection step, flows down to the instruction cancellation rate calculation step, and connects to the feedback correspondence establishment step. The local trigger threshold generation result of the left branch and the feedback correspondence establishment result of the right branch converge downward and are input into the comprehensive node of the local trigger threshold determination logic. After being processed by the determination logic, it is unidirectionally connected downward to the reset to scheduling instruction output step. From the reset to scheduling instruction output step, a dashed feedback path is led back upward to the instruction cancellation record collection step at the top right, thus forming a closed-loop feedback adjustment mechanism.

[0038] Example 4: In a project progress intelligent tracking and resource scheduling system that includes heterogeneous computing clusters and involves multiple parallel job flows, the processor calculates the nominal capacity vector based on the physical computing resources of each job node to establish the initial execution baseline for each job node. Read the nominal clock speed, memory bandwidth, and preset thread utilization limit of each computing node, and determine the initial resource capability vector by normalizing and weighting the above three physical parameters. The numerical values ​​are obtained by distributing standard test data packets to each computing node and acquiring the actual processing time of each computing node for the standard test data packets, and then calculating the measured computing power and initial resource capacity vector. The deviation coefficient is used to correct the initial resource capability vector. To determine the physical input baseline during the resource reset process.

[0039] When the monitoring module detects that the cascaded hysteresis weight W exceeds the trigger threshold At that time, the calculation module extracts the difference between the two to obtain the hysteresis deviation, and determines the reset direction allocation ratio coefficient through the following formula. ,in, Resource capability vector The reset allocation ratio, whose value ranges from 0 to 1, and W is the cascade hysteresis weight. To trigger the threshold, this linear algebraic relationship is established under the engineering mechanics distribution premise of the conservation of the total amount of available redundant resources in the system. By extracting the hysteresis weight deviation exceeding the allowable resistance at the numerator end and setting the available safety weight margin space at the denominator end, an equivalent mapping mechanism is established between the network communication obstruction characteristics and the underlying execution computing power splitting ratio. This ensures that the stripped computing power is precisely proportional to the incremental compensation required for physical handover, avoiding local oscillations caused by excessive computing power allocation. In actual task handover obstruction conditions, the handover gap parameter is very likely to exceed the physical duration of the baseline job window, resulting in the generation of cascaded hysteresis weight W values ​​greater than 1. To maintain the mathematical closure of the boundaries of subsequent resource allocation instructions and prevent the underlying address mapping from going out of bounds, the processor executes a forced boundary limiting procedure after receiving the formula calculation result. Based on the engineering principle that physical resource allocation cannot be over-adjusted, the processor introduces piecewise linear saturation control logic to calculate the reset allocation ratio coefficient. Secondary verification: when When the value is greater than 1, the processor will The output value is forcibly truncated and rewritten to 1; when When the value is less than 0, the processor will forcibly truncate the output value and rewrite it to 0, and the system will then allocate the value according to the determined proportion coefficient. Modifying the corresponding resource address image pointer in memory and resetting the access address of the computing thread of the inactive node to the blocked subsequent job node eliminates logical jumps in resource scheduling and ensures the uniqueness of scheduling instruction output.

[0040] To address the issue of discrete timestamp sequence accumulation during continuous system monitoring, the system employs a sliding time window-based update method to maintain data validity, setting the length of the sliding time window as the baseline operation window. Ten times faster, the monitoring module determines the timeliness of data by comparing the difference between each discrete timestamp in the memory and the current system clock at the end of each sampling period. If the difference exceeds the preset boundary of the sliding time window, the processor resets the corresponding memory address and clears the outdated discrete timestamps, retaining only the data flow record within the window period for fitting the response slope. This method ensures the calculation accuracy of the cascaded delay prediction model under dynamic load conditions, and keeps the project progress tracking system in a stable predictive response state.

[0041] Example 5: In a distributed data processing cluster deployment environment containing heterogeneous computing nodes, the system implements an offline calibration procedure to construct an initial resource capability vector. The quantization mapping table is used to traverse the computing nodes within the cluster and obtain hardware characteristic parameters including processor frequency and storage bandwidth. Benchmark tasks with a preset computing density are distributed to each computing node, and the nominal response time from task distribution to memory write completion is recorded. The computing module determines the contribution ratio between hardware characteristic parameters and nominal response time through multiple linear regression analysis and writes it as a weighting coefficient into the system's non-volatile memory to form a resource capability vector. The static index baseline is used as a basis. When a new job node is connected to the system, the processor retrieves the static index baseline based on the hardware descriptor reported by the node and determines the value of the resource capacity. This process establishes the consistency of the physical dimensions of the resource scheduling logic under different hardware topologies.

[0042] When the system faces dynamic operating conditions involving cross-regional, multi-center resource collaboration, the monitoring module implements a baseline drift compensation procedure before the first activation of a work node in the directed acyclic graph (DAG). The calculation module collects the underlying interrupt response frequency and system call latency of nodes under no-load conditions to determine the background noise benchmark of the communication bus. The surface-level hardware interrupt response is at the microsecond spatiotemporal scale, while the project-level overall benchmark work window is at the hourly or dayly spatiotemporal scale. The two directly reflect the risk of environmental disturbances amplifying control failure. The system adopts a cross-scale characteristic time matching procedure. Based on the principle of discrete event time accumulation equivalence, the processor does not directly use single-time system call latency collection. Instead, it establishes a sliding integral time window with a length of one-tenth of the benchmark work window time span. Within this window, the processor accumulates and integrates the latency of all continuously generated surface and underlying interrupt responses to generate a latency bias constant representing the cumulative amount of overall physical bus resistance. The benchmark work window corresponding to the work node is then read. In conjunction with a background noise benchmark, a dynamic trigger boundary is fitted using smoothing filtering. The processor then sets a preset trigger threshold based on this dynamic trigger boundary. Make corrections to obtain the local trigger threshold for the deployment environment. ,in The calculation module will use the first discrete timestamp obtained as the threshold value after environmental noise correction. With the second discrete timestamp Substituting the difference into the local trigger threshold In the decision-making logic, the calculation result of the cascaded lag weight W is adapted to the network jitter characteristics of nodes in different regions. The system updates the local trigger threshold in real time through periodic detection packets. To maintain the logical stability of resource scheduling instructions during execution.

[0043] Example 6: In a data processing environment involving high-load project task concurrency, the processor traverses the Directed Acyclic Graph (DAG) to filter non-critical execution paths to establish a resource pool available for scheduling. The computing module reads the current execution status of each job node and extracts its logical relaxation time relative to the preset delivery node. The logical relaxation time refers to the longest physical time span that a single current node can be delayed without delaying the final absolute delivery time of the entire topology. Its value is obtained by forward extrapolating the earliest feasible start time of the node using the standard Critical Path Method (CPM) and backward extrapolating its latest start time. The processor linearly superimposes the logical relaxation times within the same execution path chain to determine path redundancy. Furthermore, by querying a real-time status table containing the resource quotas already used by each job node, path redundancy can be identified. The resource utilization rate is greater than the preset safety threshold and lower than the initial resource capacity vector. 50% of the path segments are considered as potential resource supply sources. The processor triggers a secure topology isolation and multi-dimensional capability analysis procedure. Based on the node relaxation limit principle of the classic critical path method, the preset safety threshold is calculated as the difference between the total available float of the current non-critical path of the supplied resources and the estimated delay compensation time of the target subsequent job node. When the difference is greater than zero, a release command is sent. To resolve the physical misalignment between computing power scalar and multi-dimensional resource scheduling, the processor extracts the available resource capability vector. The initial single computing power value is expanded from the underlying bus physical interface protocol into an independent three-dimensional array containing the number of processor computing threads, the available memory block capacity, and the network interface bandwidth limit. When performing the resource merging step, the processor performs linear addition operations on the supply and demand arrays according to the same physical dimension to avoid cross-physical dimension data pollution. This procedure provides a definite resource address search range for the reset module through quantitative evaluation of the topology graph relaxation.

[0044] When the system generates a reset scheduling instruction containing the updated resource address mapping relationship, the processor rewrites the computing power allocation weights between blocked and inactive nodes in the running memory through the task scheduling unit, based on the allocation ratio coefficient. Extracted available resource capability vectors The system is split into discrete processing thread groups, and the instruction access addresses of these thread groups are separated from the execution queue of the original non-critical execution paths. Their physical addresses are mapped to the computing task stacks of the corresponding post-job nodes. Through this targeted tilting of surface computing power towards engineering nodes, the underlying business flow engine of the system can process information-intensive operations such as material purchase order generation, process drawing parsing, and production sequence issuance that are piled up on the blocked node in a very short machine cycle. This significantly increases the throughput of business data parsing and execution by leveraging the substantial increase in computing power density. This physically offsets and compensates for the calendar delays caused by the handover lag in the overall engineering process. After receiving the mapping instruction, the task scheduling unit adjusts the core affinity settings of the processor in real time to increase the weight of the bottleneck node in the next computing cycle. This method of resetting physical addresses at the instruction sequence level solves the problem of resource migration between logical nodes and establishes an execution closed loop from monitoring and analysis to actual resource scheduling.

[0045] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0046] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for intelligent tracking of project progress and resource scheduling, characterized in that, Includes the following steps: Step S101: Receive project business data, parse the directed acyclic topology graph containing multiple job nodes, associate a baseline job window and nominal capacity vector for each job node; calculate the nominal capacity vector based on the physical computing resources of each job node. Read the nominal clock speed, memory bandwidth, and preset thread utilization limit of each computing node, and determine the initial resource capability vector by normalizing and weighting the above three physical parameters. The numerical values ​​are obtained by distributing standard test data packets to each computing node and acquiring the actual processing time of each computing node for the standard test data packets, and then calculating the measured computing power and initial resource capacity vector. The deviation coefficient is used to correct the initial resource capability vector. To determine the physical input baseline for the resource reset process; Step S102: Monitor the flow status of data flow in the directed acyclic topology graph, and obtain the discrete timestamp sequence written to the memory by each job node when the state machine transition is triggered. The discrete timestamp sequence includes the first discrete timestamp of the previous job node outputting the closing instruction and the second discrete timestamp of the subsequent job node reading the preheating instruction, which has a direct dependency on the previous job node. Step S103: Calculate the difference between the second discrete timestamp and the first discrete timestamp to obtain the junction gap parameter, which characterizes the degree of obstruction at the logical junction point in the directed acyclic topology graph. Step S104: Read the baseline operation window corresponding to the subsequent operation node, calculate the ratio of the handover gap parameter to the baseline operation window, and obtain the cascade lag weight that reflects the degree of lag of the affected path. Step S105: When the cascading hysteresis weight is greater than the preset trigger threshold, traverse the directed acyclic topology graph to locate the non-critical execution path in an inactive state, and read the available resource capability vector under the non-critical execution path that is not locked by the underlying process. Step S106: Send a release command to sever the mapping relationship between the available resource capability vector and the original non-critical execution path. Calculate the allocation ratio based on the deviation of the cascading hysteresis weight from the trigger threshold. Merge the extracted available resource capability vector into the initial resource capability vector of the subsequent job node. Output a reset scheduling command containing the updated resource address mapping relationship. The hysteresis deviation is obtained by extracting the difference between the cascading hysteresis weight and the trigger threshold, and the reset allocation ratio coefficient is determined using the following formula. ,in, Initial resource capability vector The reset allocation ratio, whose value ranges from 0 to 1, and W is the cascade hysteresis weight. To trigger the threshold, this linear algebraic relationship is established under the engineering mechanics distribution premise of the conservation of the total amount of available redundant resources in the system. By extracting the hysteresis weight deviation exceeding the allowable resistance at the numerator end and setting the available safety weight margin space at the denominator end, an equivalent mapping mechanism is established between the network communication obstruction characteristics and the underlying execution computing power splitting ratio. This ensures that the stripped computing power is precisely proportional to the incremental compensation required for physical handover, avoiding local oscillations caused by excessive computing power allocation. In actual task handover obstruction conditions, the handover gap parameter is very likely to exceed the physical duration of the baseline job window, resulting in the generation of cascaded hysteresis weight W values ​​greater than 1. To maintain the mathematical closure of the boundaries of subsequent resource allocation instructions and prevent the underlying address mapping from going out of bounds, the processor executes a forced boundary limiting procedure after receiving the formula calculation result. Based on the engineering principle that physical resource allocation cannot be over-adjusted, the processor introduces piecewise linear saturation control logic to calculate the reset allocation ratio coefficient. Secondary verification: when When the value is greater than 1, the processor will The output value is forcibly truncated and rewritten to 1; when When the value is less than 0, the processor will forcibly truncate the output value and rewrite it to 0, and the system will then allocate the value according to the determined proportion coefficient. Modify the corresponding resource address map pointer in memory to reset the access address of the computing thread of the inactive node to the blocked post-job node.

2. The intelligent project progress tracking and resource scheduling method according to claim 1, characterized in that, Step S104 includes the following sub-steps: Step S1041, accumulating the cascading lag weights of each job node along the critical path of the directed acyclic topology to obtain the global lag evaluation value of the critical path; Step S1042, when the global lag evaluation value exceeds the preset evolution threshold, triggering a resource scheduling warning action, and eliminating asynchronous losses between job nodes with dependencies by adjusting the resource allocation weights in the directed acyclic topology.

3. The intelligent project progress tracking and resource scheduling method according to claim 1, characterized in that, The step of obtaining the discrete timestamp sequence in step S102 includes the following sub-steps: Step S1021, identify state islands in the discrete timestamp sequence that have logical transitions by referring to the baseline job window of each job node; Step S1022, perform time-domain alignment on the state islands and remove the off-time points caused by abnormal offsets; Step S1023, fit the response slope of each job node in the process of switching from preheating to job state based on the aligned discrete timestamp sequence.

4. The intelligent project progress tracking and resource scheduling method according to claim 1, characterized in that, The step of generating the handover gap parameter in step S103 includes the following sub-steps: step S1031, extracting the first discrete timestamp of the preceding work node in the delivery state; step S1032, extracting the second discrete timestamp of the following work node in the preheating state; step S1033, calculating the absolute time difference between the first discrete timestamp and the second discrete timestamp.

5. The intelligent project progress tracking and resource scheduling method according to claim 1, characterized in that, The step of outputting the reset scheduling instruction in step S106 includes the following sub-steps: Step S1061, determine the bottleneck path with the highest propulsion efficiency decay rate in the directed acyclic topology graph according to the cascaded hysteresis weight; Step S1062, retrieve non-critical paths that have resource coupling relationships with the bottleneck path, and evaluate the resource redundancy of the non-critical paths; Step S1063, map the resource identifiers corresponding to the non-critical paths to the bottleneck paths.

6. The intelligent project progress tracking and resource scheduling method according to claim 1, characterized in that, After generating the cascaded hysteresis weights in step S104, the following sub-steps are also included: Step S1043, analyze the evolution trend of the cascaded hysteresis weights in the continuous sampling period; Step S1044, when the evolution trend is monotonically increasing and the growth rate exceeds the preset change rate threshold, determine that there is a risk of cascade failure in the directed acyclic topology graph; Step S1045, output the blocking command for the risk of cascade failure.

7. The intelligent project progress tracking and resource scheduling method according to claim 1, characterized in that, After outputting the reset scheduling instruction in step S106, the following sub-steps are also included: Step S1064, collect the reset scheduling instructions generated within a preset time period and the corresponding instruction cancellation records, and calculate the instruction cancellation rate; Step S1065, establish a feedback correspondence between the instruction cancellation rate and the trigger threshold, and correct the value of the trigger threshold according to the correspondence.

8. The intelligent project progress tracking and resource scheduling method according to claim 1, characterized in that, The project business data includes priority labels of job nodes and resource constraints; step S101, parsing the directed acyclic topology graph containing multiple job nodes, includes the following sub-steps: step S1011, based on priority labels, determine the weight distribution of each execution path in the directed acyclic topology graph; step S1012, combined with resource constraints, perform topology constraint verification on the weight distribution.

9. The intelligent project progress tracking and resource scheduling method according to claim 7, characterized in that, After correcting the value of the trigger threshold, the following sub-steps are also included: Step S1066, record the resource flow trajectory after the reset to scheduling instruction is triggered; Step S1067, perform correlation analysis between the resource flow trajectory and the time series view composed of discrete timestamp sequences to evaluate the contribution of the reset to scheduling instruction to eliminating asynchronous losses between nodes.

10. A project progress intelligent tracking and resource scheduling system, used to implement the project progress intelligent tracking and resource scheduling method of claim 1, characterized in that, include: The parsing module receives project business data, parses the directed acyclic topology graph containing multiple job nodes, and associates a baseline job window and nominal capability vector for each job node. The parsing module also calculates the nominal capability vector based on the physical computing resources of each job node, reads the nominal clock speed, memory bandwidth, and preset thread occupancy limit of each computing node, and determines the initial resource capability vector value by normalizing and weighting the above three physical parameters. It distributes standard test data packets to each computing node, obtains the actual processing time of each computing node for the standard test data packets, calculates the deviation coefficient between the actual computing power and the initial resource capability vector, and uses this deviation coefficient to correct the initial resource capability vector to determine the physical input baseline during the resource reset process. The monitoring module is used to monitor the flow status of data in the directed acyclic topology graph and obtain the discrete timestamp sequence written to the memory by each job node when the state machine transition is triggered. The calculation module is used to calculate the difference between the second discrete timestamp and the first discrete timestamp in the discrete timestamp sequence to generate the handover gap parameter, and to generate a cascaded lag weight reflecting the degree of lag of the affected path based on the ratio of the handover gap parameter to the baseline operation window. The reset module is used to read available resource capability vectors that are not locked by underlying processes in non-critical execution paths when the cascading hysteresis weight exceeds a preset trigger threshold. Based on the deviation of the cascading hysteresis weight from the trigger threshold, it merges the available resource capability vectors into the initial resource capability vector of the subsequent job node and outputs a reset scheduling instruction containing the updated resource address mapping relationship. It is also used to extract the difference between the cascading hysteresis weight and the trigger threshold to obtain the hysteresis deviation, and determine the reset allocation ratio coefficient using the following formula. ,in, Initial resource capability vector The reset allocation ratio, whose value ranges from 0 to 1, and W is the cascade hysteresis weight. To trigger the threshold, this linear algebraic relationship is established under the engineering mechanics distribution premise of the conservation of the total amount of available redundant resources in the system. By extracting the hysteresis weight deviation exceeding the allowable resistance at the numerator end and setting the available safety weight margin space at the denominator end, an equivalent mapping mechanism is established between the network communication obstruction characteristics and the underlying execution computing power splitting ratio. This ensures that the stripped computing power is precisely proportional to the incremental compensation required for physical handover, avoiding local oscillations caused by excessive computing power allocation. In actual task handover obstruction conditions, the handover gap parameter is very likely to exceed the physical duration of the baseline job window, resulting in the generation of cascaded hysteresis weight W values ​​greater than 1. To maintain the mathematical closure of the boundaries of subsequent resource allocation instructions and prevent the underlying address mapping from going out of bounds, the processor executes a forced boundary limiting procedure after receiving the formula calculation result. Based on the engineering principle that physical resource allocation cannot be over-adjusted, the processor introduces piecewise linear saturation control logic to calculate the reset allocation ratio coefficient. Secondary verification: when When the value is greater than 1, the processor will The output value is forcibly truncated and rewritten to 1; when When the value is less than 0, the processor will forcibly truncate the output value and rewrite it to 0, and the system will then allocate the value according to the determined proportion coefficient. Modify the corresponding resource address map pointer in memory to reset the access address of the computing thread of the inactive node to the blocked post-job node.

Images