自适应FPGA后处理加速器系统及基于FPGA的目标检测后处理方法
By using an adaptive FPGA post-processing accelerator system that integrates DFL pipeline decoding, confidence filtering, and dynamic congestion control modules, the latency and storage bottlenecks in FPGA target detection post-processing are solved, achieving low-latency and high-efficiency target detection post-processing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- INST OF OPTICS & ELECTRONICS CHINESE ACAD OF SCI
- Filing Date
- 2026-04-28
- Publication Date
- 2026-07-17
AI Technical Summary
Existing FPGA target detection post-processing suffers from bottlenecks such as large DFL decoding latency, fixed confidence filtering thresholds that cannot adapt to dynamic load changes in the NMS module, and the need for data to pass through off-chip memory between modules.
An adaptive FPGA post-processing accelerator system was designed, which integrates a DFL pipeline decoding module, a confidence filtering module, a dual-mode NMS module, and a dynamic congestion control module to achieve low-latency on-chip pipelined processing. The confidence threshold is adjusted through closed-loop feedback to adapt to the dynamic load changes of the NMS module.
It significantly reduces data migration latency and storage bandwidth usage, avoids processing unit congestion, ensures continuous and efficient pipeline operation, and achieves low-latency target detection post-processing.
Smart Images
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