Transformer circuit
By connecting windings Ns3 and Ns4 in parallel in the transformer circuit, the number of winding turns is reduced, which solves the problem of excessive conductive resistance in traditional non-isolated full-bridge resonant transformer circuits and improves voltage conversion efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- LIXIN TECHNOLOGY (SWITZERLAND) CO LTD
- Filing Date
- 2026-06-12
- Publication Date
- 2026-07-17
AI Technical Summary
The high conductivity of traditional non-isolated full-bridge resonant transformer circuits results in low voltage conversion efficiency.
By designing a transformer circuit and using parallel windings Ns3 and Ns4, the number of turns in windings Np and Ns1~Ns4 is reduced, thereby improving voltage conversion efficiency.
This effectively reduces the conductivity resistance of the windings and improves the voltage conversion efficiency of the transformer circuit.
Smart Images
Figure CN122417656A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a transformer technology, and more particularly to a non-isolated transformer circuit. Background Technology
[0002] Traditional non-isolated full-bridge resonant transformer circuits are designed to convert the input voltage to a fixed-ratio output voltage based on the number of winding turns. However, an excessive number of winding turns leads to excessively high conductivity. Therefore, reducing the conductivity of non-isolated full-bridge resonant transformer circuits is an important research topic in this field. Summary of the Invention
[0003] This disclosure provides a transformer circuit, comprising: a first switching group, a first winding, a second winding, a first switch, a second switch, a third winding, a fourth winding, and an output. The first switching group is coupled to a voltage source; the third winding is coupled to a first node; the fourth winding is coupled to the third winding at the first node; the first switch has one end coupled to the third winding and the other end coupled to a voltage source; the second switch has one end coupled to the fourth winding and the other end coupled to a voltage source; the first winding is coupled to the third and fourth windings at the first node; the second winding is coupled to the third, fourth, and first windings at the first node; and an output has one end coupled to the first node and the other end coupled to the first and second switches.
[0004] In some embodiments, the transformer circuit further includes: a primary winding having six times the number of turns of each of the third winding and the fourth winding; a third switch coupled between the first winding and the primary winding; and a fourth switch coupled between the first winding and the primary winding.
[0005] In some embodiments, the primary winding has 3 turns, and each of the third and fourth windings has 0.5 turns.
[0006] In some embodiments, the first switch is turned on during a first period and the second switch is turned off during the first period, and the first switch is turned off during a second period and the second switch is turned on during the second period.
[0007] In some embodiments, during the first period, the current level of a first current signal passing through the third winding is four times the current level of a second current signal passing through the primary winding.
[0008] In some embodiments, the current direction of the second current signal during the first period is opposite to the current direction of the second current signal during the second period.
[0009] In some embodiments, a first winding is coupled to the third winding and the fourth winding and is used to generate a third current signal to the first node, and a second winding is coupled to the third winding, the fourth winding and the first winding and is used to generate a fourth current signal to the first node.
[0010] In some embodiments, the number of turns in the primary winding is 3.
[0011] In some embodiments, during the first period, the current level of the third current signal is three times the current level of the fourth current signal, and during the second period, the current level of the fourth current signal is three times the current level of the third current signal.
[0012] In some embodiments, during the second period, the current level of a fifth current signal through the fourth winding is four times the current level of the third current signal. Attached Figure Description
[0013] Figure 1A This is a schematic diagram of a transformer circuit illustrated according to some embodiments of this case.
[0014] Figure 1B This is a schematic diagram of a transformer circuit illustrated according to some embodiments of this case.
[0015] Figure 2 This is a schematic diagram of a current timing diagram drawn according to some embodiments of this case.
[0016] Figure 3A This is a schematic diagram of a transformer winding as illustrated in some embodiments of this case.
[0017] Figure 3B This is a schematic diagram of a transformer winding as illustrated in some embodiments of this case.
[0018] List of reference numerals
[0019] 100: Transformer circuit
[0020] Vin: Voltage source
[0021] Vo: Output
[0022] S1~S8: Switches
[0023] SP1~SP2: Switching groups
[0024] Cr: Capacitor
[0025] Lr: Equivalent series inductance
[0026] Np, Ns1~Ns4: Windings
[0027] N1~N7: Nodes
[0028] T1~T4: During the period
[0029] MC1: Magnetic core
[0030] MCP11: First side post of the magnetic core
[0031] MCP12: Core post
[0032] MCP13: Second side post of the magnetic core
[0033] IS1~IS4, INP, IN1~IN4: Current signals Detailed Implementation
[0034] In this document, when an element is referred to as a “connection” or “coupled,” it may mean an “electrical connection” or “electrical coupling.” “Connection” or “coupled” can also be used to indicate the operation or interaction between two or more elements. Furthermore, although terms such as “first,” “second,” etc., are used herein to describe different elements, these terms are merely used to distinguish elements or operations described using the same technical terminology. Unless the context clearly indicates otherwise, these terms do not specifically refer to or imply any order or sequence, nor are they intended to limit the invention.
[0035] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology and this invention, and will not be interpreted as having idealized or overly formal meanings unless expressly defined herein.
[0036] The terminology used herein is for the purpose of describing particular embodiments only and is not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It should also be understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.
[0037] The following will disclose several embodiments of this invention with reference to the drawings. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit this invention. That is, these practical details are not necessary in the embodiments disclosed herein. In addition, for the sake of simplicity, some conventional structures and components will be shown in the drawings in a simple schematic manner.
[0038] Figure 1A This is a schematic diagram of a transformer circuit 100 according to some embodiments of the present invention. The transformer circuit 100 includes switches S1-S8, a capacitor Cr, an equivalent series inductance Lr, a primary winding Np, windings Ns1-Ns4, a voltage source Vin, and an output Vo. In some embodiments, windings Ns1-Ns4 may be referred to as secondary windings. During operation, the primary winding Np and windings Ns1-Ns4 induce each other. The equivalent series inductance Lr is the equivalent series inductance of the transformer 100. In some embodiments, switches S1, S4, S5, and S7 may be defined as a first switch group. Switches S2, S3, S6, and S8 may be defined as a second switch group. Windings Ns1-Ns4 are respectively the first winding, the second winding, the third winding, and the fourth winding.
[0039] like Figure 1A As shown, in some embodiments, the transformer circuit 100 is used to adjust the output voltage Vo according to the voltage source Vin and the primary winding Np and windings Ns1~Ns4. One end of the voltage source Vin is coupled to node N1, and the other end of the voltage source Vin is coupled to node N7. In some embodiments, One end of capacitor Cr is coupled to node N2, and the other end of capacitor Cr is coupled to the equivalent series inductance Lr. One end of the equivalent series inductance Lr is coupled to capacitor Cr, and the other end of the equivalent series inductance Lr is coupled to the primary winding Np. One end of the primary winding Np is coupled to the equivalent series inductance Lr, and the other end of the primary winding Np is coupled to node N3.
[0040] One end of switch S1 is coupled to node N1, and the other end of switch S1 is coupled to node N2. One end of switch S2 is coupled to node N1, and the other end of switch S2 is coupled to node N3. One end of switch S3 is coupled to node N2, and the other end of switch S3 is coupled to node N4. One end of switch S4 is coupled to node N3, and the other end of switch S4 is coupled to node N6. In some embodiments, switches S1 and S4 may be referred to as switch group SP1, and switches S2 and S3 may be referred to as switch group SP2.
[0041] One end of winding Ns1 is coupled to node N4, and the other end of winding Ns1 is coupled to node N5. One end of winding Ns2 is coupled to node N5, and the other end of winding Ns2 is coupled to node N6. One end of winding Ns3 is coupled to node N5, and the other end of winding Ns3 is coupled to switch S7. One end of winding Ns4 is coupled to node N5, and the other end of winding Ns4 is coupled to switch S8.
[0042] One end of switch S5 is coupled to node N4, and the other end of switch S5 is coupled to node N7. One end of switch S6 is coupled to node N6, and the other end of switch S6 is coupled to node N7. One end of switch S7 is coupled to winding Ns3, and the other end of switch S7 is coupled to node N7. One end of switch S8 is coupled to winding Ns4, and the other end of switch S8 is coupled to node N7. One end of output Vo is coupled to node N5, and the other end of output Vo is coupled to node N7. One end of voltage source Vin is coupled to node N1, and the other end of voltage source Vin is coupled to node N7.
[0043] exist Figure 1A In the illustrated scenario, current signal IS1 flows from node N1 to node N2, and then from the primary winding Np to node N6. Current signal INP flows through the primary winding Np from node N2 to node N3. Current signal IN1 flows through winding Ns1 from node N4 to node N5. Current signal IN3 flows through winding Ns2 from node N6 to node N5. Current signal IN2 flows through winding Ns3 from node N7 to node N5. The current flowing through output Vo flows from node N5 to node N7. Current signal IS2 flows through node N7 to node N4. In some embodiments, node N7 is coupled to ground.
[0044] Regarding the operation of transformer circuit 100, Figure 2 Detailed description is provided.
[0045] Figure 1B This is a schematic diagram of a transformer circuit 100 illustrated according to some embodiments of this case. The components and coupling relationships in the transformer circuit 100 are shown in... Figure 1A Since they are the same, I will not describe them in detail.
[0046] exist Figure 1BIn the illustrated scenario, current signal IS3 flows from node N1 to node N3, and then from the primary winding Np to node N4. Current signal INP flows through the primary winding Np from node N3 to node N2. Current signal IN1 flows through winding Ns1 from node N4 to node N5. Current signal IN3 flows through winding Ns2 from node N6 to node N5. Current signal IN4 flows through winding Ns4 from node N7 to node N5. The current flowing through the output Vo flows from node N5 to node N7. Current signal IS4 flows through node N7 to node N5. In some embodiments, node N7 is coupled to ground.
[0047] Figure 2 This is a schematic diagram of a current timing diagram drawn according to some embodiments. Please refer to... Figure 1A and Figure 2 During period T1, switches S1 and S4 are turned on, causing the primary winding Np to generate a current signal INP. Specifically, the current level of the current signal INP is i.
[0048] Switch S4 is turned on and generates current signal IS1, which induces current signal IN3 in winding Ns2. Switch S5 is turned on and generates current signal IS2, which induces current signal IN1 in winding Ns1. Switch S7 is turned on, which induces current signal IN2 in winding Ns3.
[0049] During period T1, the current levels of current signals IN1~IN3 are determined by the number of turns of windings Ns1~Ns3, respectively. When the number of turns of the primary winding Np is 6 times the number of turns of each of windings Ns1~Ns3, the current levels of current signals IN1~IN3 are 3, 4, and 1 times the current level of current signal IS1, respectively, and the current levels of current signals IN1~IN3 are 3, 4, and 1 times the current level of current signal INP, respectively. The current level of current signal IS1 is the same as the current level of current signal INP.
[0050] Specifically, when the number of turns of the primary winding Np is 3 and the number of turns of each of the windings Ns1 to Ns3 is 0.5, the current levels of the current signals IS1, IN1 to IN3 are i, 3i, 4i and i, respectively.
[0051] On the other hand, during period T1, switches S2 and S3 are turned off, causing the current level of current signal IS3 to be 0. Switches S6 and S8 are turned off, causing the current levels of current signals IS4 and IN4 to be 0.
[0052] Please refer to Figure 1B and Figure 2During period T2, switches S2 and S3 are turned on, causing the primary winding Np to generate a current signal INP. Specifically, the absolute value of the current level of the current signal INP is i. The direction of the current signal INP is opposite to that during period T1 and period T2.
[0053] Switch S3 is turned on and generates current signal IS3, which induces current signal IN1 in winding Ns1. Switch S6 is turned on and generates current signal IS4, which induces current signal IN3 in winding Ns2. Switch S8 is turned on, which induces current signal IN4 in winding Ns4.
[0054] During period T2, the current levels of current signals IN1, IN3, and IN4 are determined by the number of turns in windings Ns1, Ns2, and Ns4, respectively. When the number of turns in the primary winding Np is six times the number of turns in each of windings Ns1, Ns2, and Ns4, the current levels of current signals IN1, IN3, and IN4 are 1, 3, and 4 times the current level of current signal IS3, respectively. The absolute value of the current level of current signal IS3 is the same as that of current signal INP.
[0055] Specifically, when the number of turns of the primary winding Np is 3, and the number of turns of each of the windings Ns1, Ns2, and Ns4 is 0.5, the current levels of the current signals IS3, IN1, IN3, and IN4 are i, i, 3i, and 4i, respectively.
[0056] On the other hand, during period T2, switches S1 and S4 are turned off, causing the current level of current signal IS1 to be 0. Switches S5 and S7 are turned off, causing current signals IS2 and IN2 to be 0.
[0057] Please refer to Figures 1A to 2 , Figure 1A The arrow in the diagram corresponds to the current direction during period T1. Figure 1B The arrow in the diagram corresponds to the current direction during period T2.
[0058] In some embodiments, please refer to Figure 1A The current level of the current signal IN1 is determined by the number of turns of the windings Np, Ns2, and Ns1. Specifically, when the windings Np, Ns2, and Ns1 have 3, 0.5, and 0.5 turns respectively, the current signal IN1 has a current level of 3i during period T1 and a current level of i during period T2.
[0059] The current level of the current signal IN3 is determined by the number of turns of the windings Np and Ns2. Specifically, when the windings Np and Ns2 have 3 and 0.5 turns respectively, the current signal IN3 has a current level i during period T1 and a current level 3i during period T2.
[0060] The current level of the current signal IN2 is determined by the number of turns of windings Np, Ns2, and Ns3. When windings Np, Ns2, and Ns3 have 3, 0.5, and 0.5 turns respectively, the current signal IN2 has a current level of 4i during period T1 and a current level of 0 during period T2.
[0061] The current level of the current signal IN4 is determined by the number of turns of windings Np, Ns2, and Ns4. When windings Np, Ns2, and Ns4 have 3, 0.5, and 0.5 turns respectively, the current signal IN4 has a current level of 0 during period T1 and a current level of 4i during period T2.
[0062] During period T1, the current level of current signal IS1 is the same as the current level of current signal IN3, and the current level of current signal IS2 is the same as the current level of current signal IN1.
[0063] During period T2, the current level of current signal IS3 is the same as the current level of current signal IN1, and the current level of current signal IS4 is the same as the current level of current signal IN3.
[0064] In some embodiments, the voltage value across the output Vo can be adjusted based on the voltage value of the voltage source Vin and the number of turns of the windings Np, Ns1, Ns2, Ns3 and Ns4.
[0065] The operations in period T3 are similar to those in periods T1 and T2, and the operations in period T4 are also similar to those in periods T1 and T2, so they will not be described in detail.
[0066] Figure 3A This is a schematic diagram of a transformer winding according to some embodiments. Please refer to... Figure 1A and Figure 3A In some embodiments, the transformer circuit 100 further includes a magnetic core MC1. The magnetic core MC1 includes a first core post MCP11, a core middle post MCP12, and a second core post MCP13. The first core post MCP11, the core middle post MCP12, and the second core post MCP13 are arranged sequentially in a horizontal direction. The physical circuit of the primary winding Np includes turns surrounding the core middle post MCP12, wherein the primary winding Np has 3 turns. A portion of the primary winding Np is located between the first core post MCP11 and the core middle post MCP12, and another portion of the primary winding Np is located between the second core post MCP13 and the core middle post MCP12. In various embodiments, the magnetic core MC1 can be, for example, a ferrite core, an iron powder core, a silicon steel sheet, and an amorphous alloy.
[0067] Figure 3BThis is a schematic diagram of transformer windings according to some embodiments. The physical circuit of each of windings Ns1 to Ns4 includes turns surrounding the core center post MCP12, wherein each of windings Ns1 to Ns4 has 0.5 turns. A portion of windings Ns1 and Ns4 is located between the first core side post MCP11 and the core center post MCP12, and a portion of windings Ns2 and Ns3 is located between the second core side post MCP13 and the core center post MCP12. In various embodiments, the core MC2 can be, for example, ferrite, iron powder core, silicon steel sheet, and amorphous alloy.
[0068] The physical circuit of windings Ns1 to Ns4 includes turns surrounding the magnetic core MC1, with each winding having 0.5 turns. One end of the output Vo is coupled to node N5, and the other end of the output Vo is coupled to node N7.
[0069] In some implementations, transformer circuits are designed to convert the input voltage to a fixed proportion of the output voltage based on the number of winding turns. When the number of winding turns is too large, the conductivity resistance increases, thus reducing the voltage conversion efficiency.
[0070] Compared to the above approach, in this embodiment of the invention, the transformer circuit 100 is designed to reduce the number of turns of windings Np and Ns1~Ns4 proportionally by connecting windings Ns3 and Ns4 in parallel, thereby improving the voltage conversion efficiency of the transformer circuit 100.
[0071] The aforementioned operating methods of various parallel winding transformer circuits are for illustrative purposes only; the operating methods of other parallel winding transformer circuits are all within the scope of this case.
[0072] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.
Claims
1. A transformer circuit, characterized in that, Include: A first switch group is coupled to a voltage source; First winding; The second winding; A third winding is coupled to a first node; A fourth winding is coupled to the third winding at the first node; A first switch, one end of which is coupled to the third winding, and the other end of which is coupled to the voltage source; A second switch, one end of which is coupled to the fourth winding, and the other end of which is coupled to the voltage source. The first winding is coupled to the third winding and the fourth winding at the first node. The second winding is coupled to the third winding, the fourth winding and the first winding at the first node; and An output is provided, one end of which is coupled to the first node, and the other end of which is coupled to the first switch and the second switch.
2. The transformer circuit as described in claim 1, further comprising: A primary winding, the number of turns of which is 6 times the number of turns of the third winding and the number of turns of the fourth winding; A third switch is coupled between the first winding and the primary winding; and A fourth switch is coupled between the first winding and the primary winding.
3. The transformer circuit as claimed in claim 2, wherein the number of turns of the primary winding is 3, and the number of turns of each of the third winding and the fourth winding is 0.
5.
4. The transformer circuit of claim 3, wherein the first switch is turned on during a first period, and the second switch is turned off during the first period, and The first switch is turned off during a second period, and the second switch is turned on during the second period.
5. The transformer circuit of claim 4, wherein during the first period, the current level of a first current signal passing through the third winding is four times the current level of a second current signal passing through the primary winding.
6. The transformer circuit of claim 5, wherein the current direction of the second current signal during the first period is opposite to the current direction of the second current signal during the second period.
7. The transformer circuit of claim 6, wherein the first winding is coupled to the third winding and the fourth winding, and is used to generate a third current signal to the first node, and The second winding is coupled to the third winding, the fourth winding and the first winding, and is used to generate a fourth current signal to the first node.
8. The transformer circuit of claim 7, wherein the number of turns of the primary winding is 3.
9. The transformer circuit of claim 7, wherein during the first period, the current level of the third current signal is three times the current level of the fourth current signal, and During the second period, the current level of the fourth current signal is three times the current level of the third current signal.
10. The transformer circuit of claim 7, wherein during the second period, the current level of a fifth current signal through the fourth winding is four times the current level of the third current signal.