Voltage-mode phase interpolators, circuits and chip systems

Abstract

This invention provides a voltage-mode phase interpolator, circuit, and chip system. The voltage-mode phase interpolator includes: a detection and calibration module that generates calibration codewords based on process angle detection of the voltage-mode phase interpolator; and at least one phase interpolation module, including a power supply unit and a phase adjustment unit. The power supply unit receives the calibration codewords and adjusts the output power supply voltage based on the calibration codewords. The phase adjustment unit is connected to the output terminal of the power supply unit and adjusts the edge rate of the clock signal based on the power supply voltage during the phase adjustment of the clock signal. This invention solves the nonlinearity problem caused by process angle deviations in existing voltage-mode phase interpolators.

Description

Technical Field

[0001] This invention relates to the field of optoelectronic communication technology, and in particular to a voltage-mode phase interpolator, circuit, and chip system. Background Technology

[0002] With the rapid development of Internet information technology, the information transmission rate of communication systems is increasing day by day. This explosive progress has placed higher speed and higher precision requirements on the clock link of communication systems. As a functional module for adjusting the clock phase, the phase interpolator (PI) is widely used in phase-locked loop (PLL) circuits and clock data recovery (CDR) circuits.

[0003] With the increase in communication speed, PI controllers need to meet the requirements of both high speed and high precision. The structure of a traditional current-mode PI controller is as follows: Figure 1 As shown, this type of PI has high linearity but high power consumption. The high-precision tail current source occupies a large area, resulting in low area utilization. The structure of a traditional voltage-mode PI is as follows: Figure 2 As shown, the linearity of the PI is compensated by the resistors connected in series in each PI unit. This method occupies a smaller area and consumes less power compared to the current-mode structure. However, the resistor compensation method cannot completely cover the impact of chip process deviations. At the same time, it requires more detailed selection of resistor values ​​and the design steps are complicated.

[0004] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a voltage-mode phase interpolator, circuit and chip system to solve the nonlinearity problem caused by process angle deviation in existing voltage-mode phase interpolators.

[0006] To achieve the above and other related objectives, the present invention provides a voltage-mode phase interpolator, comprising:

[0007] The detection and calibration module generates calibration codewords based on the process angle detection of the voltage-mode phase interpolator;

[0008] At least one phase interpolation module, including a power supply unit and a phase adjustment unit, wherein:

[0009] The power supply unit receives the calibration codeword and adjusts the output power voltage based on the calibration codeword;

[0010] The phase adjustment unit is connected to the output terminal of the power supply unit. During the phase adjustment of the clock signal, the edge rate of the clock signal is adjusted based on the power supply voltage.

[0011] Optionally, the detection and calibration module includes:

[0012] The process angle detection unit generates a temperature-independent detection voltage by performing process angle detection on the voltage-mode phase interpolator.

[0013] The codeword generation unit is connected to the output terminal of the process corner detection unit. It selects the voltage range corresponding to the detection voltage from a number of predefined voltage ranges and outputs the corresponding calibration codeword.

[0014] Each voltage range corresponds one-to-one with each adjustment level of the power supply unit, and each voltage range corresponds to a calibration code word.

[0015] Optionally, the process corner detection unit includes a current source, a first resistor, a first transistor, and a second transistor. The first end of the first resistor is connected to the output terminal of the current source and generates the detection voltage. The second end of the first resistor is connected to the first end of the first transistor. The control terminal of the first transistor is connected to its second end and the control terminal of the second transistor. The second end of the first transistor is connected to the second end of the second transistor. The first end of the second transistor is connected to a reference ground. The current source outputs a positive temperature coefficient current.

[0016] Optionally, the codeword generation unit predefines each voltage range using a first voltage and a second voltage as boundary voltages, wherein the first voltage is the fast process angle voltage corresponding to the voltage-mode phase interpolator, and the second voltage is the slow process angle voltage corresponding to the voltage-mode phase interpolator.

[0017] Optionally, the power supply unit is implemented using a low-dropout linear regulator.

[0018] Optionally, the phase adjustment unit includes:

[0019] Four sets of clock receivers, each receiving one phase of the four-phase clock signal;

[0020] Four sets of phase adjustment components, each of which is connected to the output of the power supply unit and the four sets of clock receivers, adjust the edge rate of the two quadrature clock signals based on the power supply voltage during the process of adjusting the weighting ratio of the two quadrature clock signals.

[0021] Optionally, the phase adjustment component includes:

[0022] The clock selector is connected to the output of four sets of clock receivers and selects two quadrature clock signals from the four-phase clock signals for output.

[0023] The first adjustment link is connected to the output terminal of the power supply unit and the first output terminal of the clock selector to adjust the edge rate and weight of one of the clock signals.

[0024] The second adjustment link is connected to the output terminal of the power supply unit and the second output terminal of the clock selector, and adjusts the edge rate and weight of the other clock signal.

[0025] The output driver is connected to the output terminals of the first and second adjustment links, and outputs the weighted clock signals.

[0026] Optionally, the clock selector is implemented using two 2-to-1 switches.

[0027] Optionally, both the first adjustment link and the second adjustment link include a first inverter, a second inverter, and a weight adjustment unit. The input terminal of the first inverter is connected to the corresponding output terminal of the clock selector, and the output terminal of the first inverter is connected to the input terminal of the output driver via the second inverter and the weight adjustment unit in sequence. The weight adjustment unit is implemented by connecting an adjustable number of inverter chains, and each inverter is powered by the power supply unit. Alternatively, the first adjustment link and the second adjustment link further include a second resistor connected in parallel across the two ends of the first inverter.

[0028] Optionally, the phase adjustment component further includes a first capacitor, a second capacitor, and a third capacitor, wherein the first capacitor is connected between the clock selector and the first adjustment link, the second capacitor is connected between the clock selector and the second adjustment link, and the third capacitor is connected between the two adjustment links and the output driver.

[0029] The present invention also provides a circuit comprising: a voltage-mode phase interpolator as described in any of the preceding claims.

[0030] Optionally, the circuit includes a clock data recovery circuit or a phase-locked loop circuit.

[0031] The present invention also provides a chip system comprising: a voltage-mode phase interpolator as described in any of the above claims, wherein the calibration detection module is disposed outside the chip, and the phase interpolation module is disposed inside the chip.

[0032] Optionally, the chip includes an optoelectronic communication chip.

[0033] As described above, the voltage-mode phase interpolator, circuit, and chip system of the present invention adjust the power supply voltage based on process corner detection, and thereby adjust the edge rate of the clock signal to keep the edge of the output clock continuous, avoiding nonlinearity caused by process corner deviation, thus avoiding the introduction of phase shift error and achieving high-precision phase adjustment; in addition, the power supply voltage of the present invention is lower than the traditional nominal voltage, so the current consumed by the circuit can be reduced, achieving low power consumption. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of a traditional current-mode phase interpolator.

[0035] Figure 2 This is a schematic diagram of a traditional voltage-mode phase interpolator.

[0036] Figure 3 This is a schematic diagram of a voltage-mode phase interpolator in an embodiment of the present invention.

[0037] Figure 4 This is a schematic diagram of the detection and calibration module in one embodiment of the present invention.

[0038] Figure 5 This is a schematic diagram of a process corner detection unit in an embodiment of the present invention.

[0039] Figure 6 for Figure 5 The diagram shows the voltage variation of Vmos with temperature at different process angles in the process angle detection unit.

[0040] Figure 7 for Figure 5 The diagram shows the voltage variation of Vcal with temperature at different process angles in the process angle detection unit.

[0041] Figure 8 This is a schematic diagram of a phase interpolation module in an embodiment of the present invention.

[0042] Figure 9 for Figure 8 The diagram shows the output clock of the PI core changing with the edge rate of the quadrature clock signal under nominal voltage.

[0043] Figure 10 for Figure 8 The diagram shows the output clock of the PI core changing with the edge rate of the quadrature clock signal under the power supply voltage.

[0044] Component labeling: 10-Voltage-mode phase interpolator, 100-Detection and calibration module, 110-Process corner detection unit, 120-Code word generation unit, 200-Phase interpolation module, 210-Power supply unit, 220-Phase adjustment unit, 221-Clock receiver, 222-Phase adjustment assembly, 2221-Clock selector, 2222-First adjustment link, 2223-Second adjustment link, 2224-Output driver, 2225-Weight adjustment unit. Detailed Implementation

[0045] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0046] Please see Figures 3 to 10 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0047] like Figure 3 As shown, this embodiment provides a voltage-mode phase interpolator 10, including a detection and calibration module 100 and at least one phase interpolation module 200.

[0048] In practical applications, the number of phase interpolation modules 200 depends on the number of signal channels in the chip and should be designed according to specific requirements, without too many restrictions. When the number of phase interpolation modules 200 is greater than one, each phase interpolation module 200 shares the same detection and calibration module 100, which can improve the chip area utilization.

[0049] The detection and calibration module 100 generates calibration codewords based on the process angle detection of the voltage-mode phase interpolator 10. In one embodiment, such as... Figure 4 As shown, the detection and calibration module 100 includes a process corner detection unit 110 and a code word generation unit 120.

[0050] The process angle detection unit 110 generates a temperature-independent detection voltage Vcal by performing process angle detection on the voltage-mode phase interpolator 10.

[0051] Specifically, such as Figure 5As shown, the process corner detection unit 110 includes a current source Iptat, a first resistor R1, a first transistor M1, and a second transistor M2, wherein the current source Iptat outputs a positive temperature coefficient current.

[0052] The first terminal of the first resistor R1 is connected to the output terminal of the current source Iptat and generates the detection voltage Vcal. The second terminal of the first resistor R1 is connected to the first terminal of the first transistor M1. The control terminal of the first transistor M1 is connected to its second terminal and the control terminal of the second transistor M2. The second terminal of the first transistor M1 is connected to the second terminal of the second transistor M2. The first terminal of the second transistor M2 is connected to the reference ground. In practical applications, the first transistor M1 is a PMOS transistor, and the second transistor M2 is an NMOS transistor. Correspondingly, the control terminal is the gate terminal, the first terminal is the source terminal, and the second terminal is the drain terminal.

[0053] The first transistor M1 and the second transistor M2 are used for process corner detection. The voltage at the first terminal of the first transistor M1 is denoted as Vmos. This voltage exhibits a negative temperature coefficient under a fixed bias current, as shown in [reference needed]. Figure 6 To eliminate the effects of temperature changes, a positive temperature coefficient voltage is generated by the voltage drop across the first resistor R1 using a positive temperature coefficient current. This compensates for the negative temperature coefficient of Vmos, thus producing a temperature-independent detection voltage Vcal. (See [link to relevant documentation]). Figure 7 It is important to note that, Figure 6 and Figure 7 In the diagram, ss corresponds to the slow process corner voltage, ff corresponds to the fast process corner voltage, and tt corresponds to the typical process corner voltage. In practical applications, Vmos and Vcal are usually between the corresponding fast and slow process corner voltages.

[0054] The codeword generation unit 120 is connected to the output terminal of the process corner detection unit 110. It selects the voltage range corresponding to the detection voltage Vcal from a number of predefined voltage ranges and outputs the corresponding calibration codeword.

[0055] Specifically, the codeword generation unit 120 predefines each voltage range using a first voltage and a second voltage as boundary voltages. The first voltage is the fast process angle voltage corresponding to the voltage-mode phase interpolator 10, and the second voltage is the slow process angle voltage corresponding to the voltage-mode phase interpolator 10. It should be noted that both the fast and slow process angle voltages here are temperature-independent voltages after temperature compensation. Figure 7 The curves shown in ff and ss are shown in the middle.

[0056] Each voltage range corresponds one-to-one with each adjustment level of the power supply unit 210 in the phase interpolation module 200, and each voltage range corresponds to a calibration code. In practical applications, when predefining each voltage range, the range defined by the first voltage and the second voltage can be divided into M equal parts based on the number M (>1) of adjustment levels in the power supply unit 210, thereby predefining each voltage range. It should be noted that each adjustment level of the power supply unit 210 corresponds to a digital code, and the calibration code is the digital code of the adjustment level corresponding to that voltage range.

[0057] like Figure 8 As shown, the phase interpolation module 200 includes a power supply unit 210 and a phase adjustment unit 220. Wherein:

[0058] The power supply unit 210 receives a calibration codeword and adjusts the output power supply voltage based on the calibration codeword. As mentioned above, the power supply unit 210 has M adjustment levels, and different adjustment levels are selected by the calibration codeword to adjust the power supply voltage. In one embodiment, the power supply unit 210 uses a low-dropout linear regulator (LDO), for example, adjusting the power supply voltage by controlling the adjustable resistor division ratio in the LDO using the calibration codeword.

[0059] Phase adjustment unit 220, connected to the output terminal of power supply unit 210, adjusts the edge rate of the clock signal based on the power supply voltage during phase adjustment of the clock signal, ensuring continuous output clock edges and avoiding nonlinearity caused by process corner deviations. In one embodiment, such as... Figure 8 As shown, the phase adjustment unit 220 includes four sets of clock receivers 221 and four sets of phase adjustment components 222.

[0060] Four sets of clock receivers 221 each receive one phase of the four-phase clock signal. For example, the first set of clock receivers 221 receives the clock signal with a 0° phase, the second set of clock receivers 221 receives the clock signal with a 90° phase, the third set of clock receivers 221 receives the clock signal with a 180° phase, and the fourth set of clock receivers 221 receives the clock signal with a 270° phase. By designing each clock receiver 221, the driving capability of each clock signal can be improved.

[0061] Four sets of phase adjustment components 222, wherein each set of phase adjustment components 222 is connected to the output terminal of the power supply unit 210 and the output terminal of the four sets of clock receivers 221. During the process of adjusting the weighting ratio of the two quadrature clock signals, the edge rate of the two quadrature clock signals is adjusted based on the power supply voltage.

[0062] Specifically, such as Figure 8As shown, the phase adjustment component 222 includes a clock selector 2221, a first adjustment link 2222, a second adjustment link 2223, and an output driver 2224. Furthermore, it also includes a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0063] Clock selector 2221, connected to the output of four sets of clock receivers 221, is used to select two quadrature clock signals from the four-phase clock signals for output. More specifically, as... Figure 8 As shown, the clock selector 2221 is implemented using two 2-to-1 switches; wherein the two clock signals connected to each 2-to-1 switch are 180° out of phase, so that two orthogonal clock signals can be output by selecting the two 2-to-1 switches. For example:

[0064] For the clock selector 2221 in the first set of phase adjustment components 222: the two input terminals of the first two-to-one switch receive a clock signal with a 0° phase and a clock signal with a 180° phase, respectively; the two input terminals of the second two-to-one switch receive a clock signal with a 90° phase and a clock signal with a 270° phase, respectively.

[0065] For the clock selector 2221 in the second set of phase adjustment components 222: the two input terminals of the first two-to-one switch receive a clock signal with a 90° phase and a clock signal with a 270° phase, respectively; the two input terminals of the second two-to-one switch receive a clock signal with a 180° phase and a clock signal with a 0° phase, respectively.

[0066] For the clock selector 2221 in the third phase adjustment component 222: the two input terminals of the first two-to-one switch receive a clock signal with a 180° phase and a clock signal with a 0° phase, respectively; the two input terminals of the second two-to-one switch receive a clock signal with a 270° phase and a clock signal with a 90° phase, respectively.

[0067] For the clock selector 2221 in the fourth phase adjustment component 222: the two input terminals of the first two-to-one switch receive a clock signal with a 270° phase and a clock signal with a 90° phase, respectively; the two input terminals of the second two-to-one switch receive a clock signal with a 0° phase and a clock signal with a 180° phase, respectively.

[0068] Any of the above clock selectors 2221 can output two orthogonal clock signals by switching, such as a 0° phase clock signal and a 90° phase clock signal, a 90° phase clock signal and a 180° phase clock signal, a 180° phase clock signal and a 270° phase clock signal, or a 270° phase clock signal and a 0° phase clock signal.

[0069] The first adjustment link 2222 is connected to the output terminal of the power supply unit 210 and the first output terminal of the clock selector 2221, and is used to adjust the edge rate and weight of one of the two quadrature clock signals; when a first capacitor C1 is also included, the first adjustment link 2222 is connected to the first output terminal of the clock selector 2221 via the first capacitor C1. More specifically, as Figure 8 As shown, the first adjustment link 2222 includes a first inverter INV1, a second inverter INV2 and a weight adjustment unit 2225, and further includes a second resistor R2.

[0070] The input terminal of the first inverter INV1 is connected to the first output terminal of the clock selector 2221 (when the first capacitor C1 is included, the input terminal of the first inverter INV1 is connected to the first output terminal of the clock selector 2221 via the first capacitor C1). The output terminal of the first inverter INV1 is connected to the input terminal of the output driver 2224 via the second inverter INV2 and the weight adjustment unit 2225 in sequence. The weight adjustment unit 2225 is implemented by connecting an inverter chain with an adjustable number of inverters. Each inverter (including the first inverter INV1, the second inverter INV2 and all inverters in the weight adjustment unit 2225) is powered by the power supply unit 210. When the second resistor R2 is also included, the second resistor R2 is connected in parallel across the first inverter INV1. In practical applications, the number of connected devices in the weight adjustment unit 2225 can be adjusted by connecting a switch in parallel across each inverter. Of course, other structures that can achieve adjustable number of connected devices are also feasible and are not limited to this. In addition, the number of inverters in the weight adjustment unit 2225 should be designed according to specific requirements, and no restrictions are imposed on it.

[0071] The second adjustment link 2223 is connected to the output terminal of the power supply unit 210 and the second output terminal of the clock selector 2221, and is used to adjust the edge rate and weight of the other clock signal among the two quadrature clock signals. When a second capacitor C2 is also included, the second adjustment link 2223 is connected to the second output terminal of the clock selector 2221 via the second capacitor C2. The structure of the second adjustment link 2223 is the same as that of the first adjustment link 2222, as detailed above, and will not be repeated here.

[0072] When the clock signals are weighted by the first adjustment link 2222 and the second adjustment link 2223, the sum of the number of inverters connected in the two weight adjustment units 2225 is consistent with the total number of inverters in any weight adjustment unit 2225. For example, the total number of inverters in any weight adjustment unit 2225 is K (>1), the number of inverters connected in one weight adjustment unit 2225 is a (≥0), and the number of inverters connected in the other weight adjustment unit 2225 is Ka.

[0073] The output driver 2224 is connected to the output terminals of the first adjustment link 2222 and the second adjustment link 2223, and is used to output a weighted sum of the two clock signals. When a third capacitor C3 is also included, the output driver 2224 is connected to the output terminals of the two adjustment links via the third capacitor C3. In practical applications, the clock signals output from the first adjustment link 2222 and the second adjustment link 2223 are weighted when passing through the third capacitor C3, and the output driver 2224 can drive and enhance the weighted clock signal.

[0074] In this embodiment, during the phase adjustment of the clock signal by the phase adjustment unit 220, both the clock receiver 221 and the output driver 2224 use a nominal voltage of 0.9V, while the PI core composed of the first adjustment link 2222 and the second adjustment link 2223 is supplied with power by the power supply unit 210, wherein the power supply voltage is less than the nominal voltage.

[0075] Using a PI core with a nominal voltage of 0.9V as a comparison, the relationship between the PI output (i.e., pi_out) and the edge rates of the two quadrature clock signals (i.e., CK_i and CK_q) is as follows: Figure 9 As shown; when the PI core is powered by a supply voltage less than 0.9V, the relationship between the edge rates of the PI output (i.e., pi_out) and the two quadrature clock signals (i.e., CK_i and CK_q) is as follows. Figure 10 As shown.

[0076] As shown in the figure, when the edge rates of the two quadrature clock signals are too fast, the PI output exhibits a flat portion at the 1 / 2 amplitude position. This introduces phase shift error, making it impossible to determine whether a phase shift has occurred at that point. However, by supplying power with a voltage lower than the nominal voltage, the edge rates of the two quadrature clock signals can be reduced, keeping the PI output edges continuous and thus not affecting phase shift detection. Compared to the case where the PI core uses a nominal voltage of 0.9V, the use of a power supply voltage lower than 0.9V in this embodiment reduces the current consumed by the circuit, which is beneficial for reducing power consumption.

[0077] This embodiment also provides a circuit including a voltage-mode phase interpolator 10, wherein the voltage-mode phase interpolator 10 is implemented using the structure described above. In practical applications, this circuit can be a clock data recovery (CDR) circuit or a phase-locked loop (PLL) circuit. Of course, other circuits besides the two circuits mentioned above are also feasible and are not limited thereto.

[0078] This embodiment also provides a chip system including a voltage-mode phase interpolator 10, which is implemented using the structure described above. The calibration detection module 100 is located outside the chip, while the phase interpolation module 200 is located inside the chip. In practical applications, the calibration codeword output by the external calibration detection module 100 can be automatically input to the internal phase interpolation module 200, or it can be manually input to the internal phase interpolation module 200. Furthermore, the calibration codeword is typically provided to the phase interpolation module 200 via an internal digital register. As an optional solution, the chip in the chip system is an optoelectronic communication chip, particularly a high-speed optoelectronic communication chip; however, other types of chips are also feasible and not limited to this.

[0079] In summary, the voltage-mode phase interpolator, circuit, and chip system of this invention adjust the power supply voltage based on process corner detection, and thereby adjust the edge rate of the clock signal. This ensures continuous output clock edges, avoids nonlinearity caused by process corner deviations, and thus avoids introducing phase shift errors, achieving high-precision phase adjustment. Furthermore, the power supply voltage of this invention is lower than the traditional nominal voltage, thus reducing circuit current consumption and achieving low power consumption. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0080] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A voltage-mode phase interpolator, characterized in that, include: The detection and calibration module generates calibration codewords based on the process angle detection of the voltage-mode phase interpolator; At least one phase interpolation module, including a power supply unit and a phase adjustment unit, wherein: The power supply unit receives the calibration codeword and adjusts the output power voltage based on the calibration codeword; The phase adjustment unit is connected to the output terminal of the power supply unit. During the phase adjustment of the clock signal, the edge rate of the clock signal is adjusted based on the power supply voltage.

2. The voltage-mode phase interpolator according to claim 1, characterized in that, The detection and calibration module includes: The process angle detection unit generates a temperature-independent detection voltage by performing process angle detection on the voltage-mode phase interpolator. The codeword generation unit is connected to the output terminal of the process corner detection unit. It selects the voltage range corresponding to the detection voltage from a number of predefined voltage ranges and outputs the corresponding calibration codeword. Each voltage range corresponds one-to-one with each adjustment level of the power supply unit, and each voltage range corresponds to a calibration code word.

3. The voltage-mode phase interpolator according to claim 2, characterized in that, The process corner detection unit includes a current source, a first resistor, a first transistor, and a second transistor. The first end of the first resistor is connected to the output terminal of the current source and generates the detection voltage. The second end of the first resistor is connected to the first end of the first transistor. The control terminal of the first transistor is connected to its second end and the control terminal of the second transistor. The second end of the first transistor is connected to the second end of the second transistor. The first end of the second transistor is connected to a reference ground. The current source outputs a positive temperature coefficient current.

4. The voltage-mode phase interpolator according to claim 2, characterized in that, The codeword generation unit predefines each voltage range using a first voltage and a second voltage as boundary voltages, wherein the first voltage is the fast process angle voltage corresponding to the voltage-mode phase interpolator, and the second voltage is the slow process angle voltage corresponding to the voltage-mode phase interpolator.

5. The voltage-mode phase interpolator according to claim 1, characterized in that, The power supply unit is implemented using a low-dropout linear regulator.

6. The voltage-mode phase interpolator according to claim 1, characterized in that, The phase adjustment unit includes: Four sets of clock receivers, each receiving one phase of the four-phase clock signal; Four sets of phase adjustment components, each of which is connected to the output of the power supply unit and the four sets of clock receivers, adjust the edge rate of the two quadrature clock signals based on the power supply voltage during the process of adjusting the weighting ratio of the two quadrature clock signals.

7. The voltage-mode phase interpolator according to claim 6, characterized in that, The phase adjustment component includes: The clock selector is connected to the output of four sets of clock receivers and selects two quadrature clock signals from the four-phase clock signals for output. The first adjustment link is connected to the output terminal of the power supply unit and the first output terminal of the clock selector to adjust the edge rate and weight of one of the clock signals. The second adjustment link is connected to the output terminal of the power supply unit and the second output terminal of the clock selector, and adjusts the edge rate and weight of the other clock signal. The output driver is connected to the output terminals of the first and second adjustment links, and outputs the weighted clock signals.

8. The voltage-mode phase interpolator according to claim 7, characterized in that, The clock selector is implemented using two 2-to-1 switches.

9. The voltage-mode phase interpolator according to claim 7, characterized in that, Both the first adjustment link and the second adjustment link include a first inverter, a second inverter, and a weight adjustment unit. The input terminal of the first inverter is connected to the corresponding output terminal of the clock selector, and the output terminal of the first inverter is connected to the input terminal of the output driver via the second inverter and the weight adjustment unit in sequence. The weight adjustment unit is implemented by connecting an adjustable number of inverter chains, and each inverter is powered by the power supply unit. Alternatively, the first adjustment link and the second adjustment link also include a second resistor connected in parallel across the two ends of the first inverter.

10. The voltage-mode phase interpolator according to any one of claims 7 to 9, characterized in that, The phase adjustment component further includes a first capacitor, a second capacitor, and a third capacitor. The first capacitor is connected between the clock selector and the first adjustment link, the second capacitor is connected between the clock selector and the second adjustment link, and the third capacitor is connected between the two adjustment links and the output driver.

11. A circuit, characterized in that, include: The voltage-mode phase interpolator as described in any one of claims 1 to 10.

12. The circuit according to claim 11, characterized in that, The circuit includes a clock data recovery circuit or a phase-locked loop circuit.

13. A chip system, characterized in that, include: The voltage-mode phase interpolator according to any one of claims 1 to 10, wherein the calibration detection module is disposed outside the chip, and the phase interpolation module is disposed inside the chip.

14. The chip system according to claim 13, characterized in that, The chip includes an optoelectronic communication chip.

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