A system and method for co-processing GOOSE messages based on DSP and FPGA
By using DSP and FPGA to collaboratively process GOOSE messages, the task scheduling delay and hardware resource bottleneck of DSP chips in processing redundant GOOSE messages from multiple networks in smart grids are resolved, achieving efficient and flexible GOOSE message processing and meeting the requirements of ultra-high-speed real-time control.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANJING GUODIAN NANZI POWER GRID AUTOMATION CO LTD
- Filing Date
- 2026-05-15
- Publication Date
- 2026-07-17
AI Technical Summary
In smart grids, DSP chips face challenges such as task scheduling delays, hardware resource bottlenecks, and insufficient adaptability when processing redundant GOOSE messages from multiple networks, making it difficult to meet the requirements of ultra-high-speed real-time control.
The system employs DSP and FPGA to collaboratively process GOOSE messages. The FPGA module performs hardware-level parallel parsing and filtering, while the DSP module executes complex control logic. Combined with the high-speed transmission characteristics of the EMIF bus, it achieves rapid response and flexible adaptation.
It improves the system's real-time performance, reliability, and stability, meets the requirements of ultra-high-speed real-time control, supports flexible adaptation to multiple scenarios, and reduces resource consumption.
Smart Images
Figure CN122419699A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a system and method for collaborative processing of GOOSE messages based on DSP and FPGA, belonging to the field of power system automation control technology. Background Technology
[0002] In the construction of smart grids, traditional power electronic products mostly use DSP chips. However, DSP chip hardware resources usually do not include a "MAC + PHY" module, requiring an external Ethernet chip with an SPI interface to achieve network communication. Therefore, in multi-network redundant GOOSE message processing scenarios, DSP chips face the following problems:
[0003] Task scheduling delay risk: It is necessary to process GOOSE messages from two networks simultaneously. However, the tasks of the DSP are more focused on real-time and parallelism. The single-core DSP achieves "parallelism" by switching serial threads at high speed. Under its existing task priority management and scheduling mechanism, thread blocking and insufficient CPU effective computing time are likely to occur, which will lead to message processing delay and fail to meet the requirements of ultra-high-speed real-time control.
[0004] Hardware resource bottlenecks: The computing power and interface bandwidth of the DSP itself limit the parallel processing capability of multi-channel GOOSE messages; traditional parallel expansion schemes have defects such as low integration and poor stability, while serial expansion interfaces will have limitations in transmission speed, further restricting the parallel processing efficiency of multi-channel GOOSE messages.
[0005] Insufficient adaptability: It is difficult to flexibly adjust parameters such as the number of channels and protocol version of GOOSE processing for application scenarios with different voltage levels and different equipment types.
[0006] In existing technologies, the method of simply relying on DSP to process GOOSE messages has shortcomings in terms of real-time performance, redundancy reliability, and scenario adaptability. Therefore, there is an urgent need for a highly efficient and collaborative processing architecture. Summary of the Invention
[0007] The purpose of this invention is to provide a system and method for collaborative processing of GOOSE messages based on DSP and FPGA. Through the functional division and collaborative interaction between the DSP main control module and the FPGA module, the system achieves ultra-high real-time and fast response to GOOSE messages and supports flexible adaptation to multiple scenarios.
[0008] To achieve the above objectives and solve the above technical problems, the present invention adopts the following technical solution.
[0009] On one hand, the present invention provides a system for collaborative processing of GOOSE messages based on DSP and FPGA, comprising:
[0010] The FPGA module includes: an integrated dual-channel Ethernet interface unit, a packet parsing and filtering unit, an interrupt generation unit, and a counter unit;
[0011] The integrated dual-channel Ethernet interface unit is used to receive redundant GOOSE messages from two communication networks from the GOOSE sender.
[0012] The message parsing and filtering unit is used to perform hardware-level parsing and filtering of redundant GOOSE messages from two communication networks in parallel, and to extract the valid data payload from any one of the communication network GOOSE messages.
[0013] The counter unit is used to embed timing synchronization tags into the valid data payload to generate message data containing timing tags;
[0014] The interrupt generation unit is used to wake up the DSP main control module by an external interrupt signal after the message data containing timing marks is written to the memory unit of the DSP main control module through the EMIF bus.
[0015] The DSP main control module includes: a memory unit and a main control unit;
[0016] The memory unit is used to store message data containing timing tags written by the FPGA module;
[0017] The main control unit is used to respond to an external interrupt signal that wakes it up, read the message data containing timing marks in its memory unit, and send a drive signal to the actuator to perform the corresponding GOOSE response action according to the preset control logic.
[0018] Furthermore, the method for obtaining redundant GOOSE messages in the two communication networks specifically includes:
[0019] The FPGA module connects to the first and second communication networks simultaneously through an integrated dual Ethernet interface unit, and obtains redundant GOOSE messages from the GOOSE sender respectively.
[0020] Wherein: the first communication network and the second communication network receive the same GOOSE message, and one communication network is selected as the primary network and the other communication network is the backup network.
[0021] Furthermore, the message parsing and filtering unit performs hardware-level parsing and filtering on the redundant GOOSE messages from the two communication networks in parallel, and extracts the valid data payload from any one of the communication network GOOSE messages, specifically including:
[0022] Step 1: The message parsing and filtering unit parses the received GOOSE message to obtain the MAC address, GOOSE APPID, PDU length, and data attribute fields;
[0023] Step 2: Perform CRC check on the parsed GOOSE message. If the CRC check passes, proceed to Step 3; if the CRC check fails, mark the CRC check as an error, report the error type to the DSP main control module through the error interrupt line, and cache the error code.
[0024] The CRC verification method specifically includes:
[0025] The received GOOSE message is divided by a pre-agreed standard divisor using modulo 2 division. If the remainder is 0, the verification passes; otherwise, the verification fails.
[0026] Step 3: Perform APPID matching check. If it matches, proceed to step 4; if it does not match, mark the APPID as mismatched, report the error type to the DSP main control module through the error interrupt line, and cache the error code.
[0027] Step 4: Determine if the VLAN ID is a compliant value; if compliant, proceed to Step 5; if not compliant, mark the VLAN ID as invalid, report the error type to the DSP main control module via the error interrupt line, and cache the error code.
[0028] The IEEE 802.1Q protocol specifies that the VLAN ID is 12 bits, and the configurable legal value range is 1 to 4094. 0 and 4095 are reserved values of the protocol and cannot be used for user configuration.
[0029] Step 5: Determine if the destination MAC address matches the whitelist; if it matches, the packet is confirmed as valid, and the valid data payload is located and extracted based on the parsed PDU length and data attribute fields, and an external interrupt signal is triggered to wake up the DSP main control module; if it does not match, the packet is confirmed as invalid and discarded.
[0030] Wherein: the error interrupt line and the valid message interrupt line corresponding to the external interrupt signal are independent physical lines;
[0031] The external interrupt signal is edge-triggered.
[0032] Furthermore, after the actuator receives the drive signal to execute the corresponding GOOSE response action, the DSP main control module generates execution result data containing the execution status and the original message identifier, and sends it back to the FPGA module via the EMIF bus. The FPGA module encapsulates the received execution result data into a GOOSE feedback message and sends it back to the GOOSE sender to complete the control closed loop verification.
[0033] The EMIF bus is configured in asynchronous mode, with a data width of 16 bits or 32 bits and a clock frequency of 80MHz to 120MHz.
[0034] Furthermore, the GOOSE response actions include: outputting a digital signal through the GPIO port, outputting an analog signal through the DAC, and feeding back the device status through the communication interface;
[0035] The execution result data includes: action type, execution success / failure flag, and original message.
[0036] Furthermore, the FPGA module also includes: a parameter configuration interface unit, a shared register group, and a link status acquisition unit;
[0037] The parameter configuration interface unit is used to respond to the configuration instructions issued by the DSP main control module and dynamically adjust the number of GOOSE message processing channels and the protocol version.
[0038] A shared register set, which is mapped to the EMIF bus address space between the FPGA module and the DSP main control module, includes a configuration status register and a link status register.
[0039] The link status acquisition unit is used to periodically acquire and update the connection status information of the first communication network link and the second communication network link;
[0040] The parameter configuration interface unit writes the currently configured number of GOOSE processing channels and protocol version parameters into the configuration status register, and writes the connection status information of the first communication network link and the second communication network link into the link status register.
[0041] Furthermore, the DSP main control module reads the shared register group via interrupt and compares it with the configuration parameters stored locally. When the comparison results are inconsistent or an abnormal connection status of the dual network links is detected, the module reissues configuration instructions or status synchronization instructions to the FPGA module to dynamically adjust the number of GOOSE message processing channels and the protocol version.
[0042] Furthermore, before writing the message data containing timing tags, the FPGA module also needs to perform timing tag appending and CRC update operations, specifically including:
[0043] The counter unit records the corresponding time count value when the GOOSE message is received. The time count value is used as a 4-byte timestamp and appended to the end of the data field of the corresponding parsed GOOSE message to generate an extended message frame.
[0044] For extended message frames containing timestamps, the 32-bit CRC check value of the entire extended message frame is recalculated using the Ethernet standard CRC-32 algorithm.
[0045] The original CRC check field in the extended message frame during parsing is replaced by the calculated new CRC check value to obtain a valid message with the updated CRC check value.
[0046] Valid messages are written into the memory unit of the DSP main control module via the EMIF bus for subsequent reading and use by the DSP main control module.
[0047] Furthermore, when the FPGA module detects a link failure in the first or second communication network, it automatically switches to another normal network channel to receive messages and sends a link switching interrupt to the DSP main control module.
[0048] The FPGA module also predicts the probability of link failure based on historical link failure records and current link quality parameters. If the failure probability exceeds the threshold, it switches to the backup channel in advance.
[0049] The method for obtaining historical link failure records specifically includes:
[0050] The FPGA module maintains historical fault logs of the dual network links in local non-volatile memory, recording the time of each fault occurrence, duration, fault type, and recovery reason, forming a historical fault feature dataset.
[0051] The methods for obtaining the current link quality parameters specifically include:
[0052] The bit error rate and packet loss rate of the current link are calculated at fixed intervals (10ms);
[0053] Wherein: the bit error rate is calculated by comparing the CRC check results before and after message reception, and determining the percentage of messages with check errors per unit time;
[0054] The packet loss rate is calculated by detecting the sequence number continuity of GOOSE packets and determining the percentage of packets with sequence number jumps or missing packets per unit time.
[0055] Methods for predicting link failure probability include:
[0056] The historical fault feature dataset, current bit error rate, current packet loss rate, and current duration of continuous fault-free operation of the primary link are input into a fault probability calculation model using a weighted logistic regression model. The fault probability calculation model outputs a link fault probability value between 0 and 1 by performing linear weighting and Sigmoid function operations.
[0057] Fault probability assessment and early switchover specifically include:
[0058] The failure probability output by the failure probability calculation model is compared with a preset threshold.
[0059] If the failure probability exceeds the threshold, the FPGA module immediately switches the message receiving channel to the backup link and sends a pre-switching interrupt signal to the DSP main control module to synchronize the link switching status.
[0060] During the switching process, the FPGA module performs timing alignment and data buffering on the messages of the dual network links to avoid GOOSE message loss or timing errors, ensuring the continuity of protection actions.
[0061] Secondly, this invention provides a method for collaboratively processing GOOSE messages using DSP and FPGA, and based on the aforementioned system for collaboratively processing GOOSE messages using DSP and FPGA, the method includes the following steps:
[0062] The FPGA module receives redundant GOOSE messages from two communication networks from the GOOSE sender by integrating a dual-channel Ethernet interface unit.
[0063] The message parsing and filtering unit performs hardware-level parsing and filtering on redundant GOOSE messages from two communication networks in parallel, and extracts the valid data payload from any one of the communication network GOOSE messages.
[0064] The counter unit embeds timing synchronization tags into the valid data payload to generate message data containing timing tags;
[0065] After the message data containing timing markers is written to the memory unit of the DSP main control module via the EMIF bus, the DSP main control module is woken up by an external interrupt signal.
[0066] The main control unit of the DSP main control module is awakened in response to an external interrupt signal, reads the message data containing timing marks from the memory unit, and sends drive signals to the actuator according to the preset control logic to execute the corresponding GOOSE response action.
[0067] Compared with existing technologies, the beneficial effects achieved by this invention are as follows: This invention achieves "zero-wait" parsing and filtering of GOOSE messages through the hardware parallel processing capability of the FPGA module, and the external interrupt mechanism ensures the rapid wake-up and data reading of the DSP. Combined with the high-speed transmission characteristics of the EMIF bus, the processing latency is further shortened to meet the requirements of ultra-high-speed real-time control. Based on the functional division principle of FPGA+DSP collaborative processing, this invention allows the DSP main control module to focus on complex control logic execution, while the FPGA module focuses on high-speed data processing and hardware-level control, giving full play to the performance advantages of both. Compared with a single processor system, it can effectively improve performance while reducing the overall system resource consumption, balancing processing speed and power consumption costs.
[0068] This invention achieves network link redundancy and data processing redundancy by combining dual communication network inputs with the dual-channel processing capability of the FPGA. This effectively avoids message loss or control response failure caused by single point of failure, and significantly improves the reliability and stability of system operation.
[0069] This invention also enhances the system's versatility and scenario adaptability. It supports dynamic parameter configuration, which can flexibly adjust parameters such as the number of channels and protocol version for GOOSE message processing according to different application scenarios without requiring large-scale modifications to the hardware or underlying logic. This significantly improves the system's versatility and scalability, making it suitable for various power automation application scenarios. Attached Figure Description
[0070] Figure 1 This is a system architecture block diagram of the present invention based on DSP and FPGA collaborative processing;
[0071] Figure 2 This is a flowchart illustrating the control method of the present invention;
[0072] Figure 3 This is a block diagram of the internal functional modules of the FPGA module of the present invention. Detailed Implementation
[0073] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present invention, rather than limitations on the technical solution of the present invention. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.
[0074] The term "and / or" simply describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Additionally, the character " / " generally indicates that the preceding and following related objects have an "or" relationship.
[0075] Example 1
[0076] like Figure 1 The embodiment shown provides a GOOSE message processing system based on FPGA and DSP collaborative processing, including an FPGA module and a DSP main control module.
[0077] The FPGA module is configured to: implement parallel reception, hardware-level parsing, and filtering of GOOSE messages from dual-channel AB networks (first and second communication networks); achieve network and processing redundancy through dual-channel processing capabilities; and after completing message preprocessing, send a data ready signal to the DSP main control module via an external interrupt, while simultaneously transmitting processed data to the DSP main control module via the EMIF bus, specifically including:
[0078] like Figure 3 As shown, the integrated dual-channel Ethernet interface unit is used to receive redundant GOOSE messages from two communication networks from the GOOSE sender.
[0079] Message parsing and filtering unit: used to perform hardware-level parsing and filtering of redundant GOOSE messages from two communication networks in parallel, and to extract the valid data payload from any one of the GOOSE messages from the communication network.
[0080] Counter unit: used to embed timing synchronization marks into the valid data payload to generate message data containing timing marks;
[0081] Interrupt generation unit: used to wake up the DSP main control module by an external interrupt signal after the message data containing timing marks is written to the memory unit of the DSP main control module through the EMIF bus;
[0082] The EMIF bus is configured in asynchronous mode, with a data width of 32 bits and a clock frequency of 80MHz~120MHz.
[0083] The parameter configuration interface unit is used to respond to the configuration instructions issued by the DSP main control module and dynamically adjust the number of GOOSE message processing channels and the protocol version.
[0084] A shared register set, which is mapped to the EMIF bus address space between the FPGA module and the DSP main control module, includes a configuration status register and a link status register.
[0085] The link status acquisition unit is used to periodically acquire and update the connection status information of the first communication network link and the second communication network link;
[0086] The parameter configuration interface unit writes the currently configured number of GOOSE processing channels and protocol version parameters into the configuration status register, and writes the connection status information of the first communication network link and the second communication network link into the link status register.
[0087] The DSP main control module is configured to: respond to external interrupt signals from the FPGA module, quickly wake up and read preprocessed data transmitted by the FPGA module; perform complex control logic operations based on the received message data, and output corresponding control commands according to the operation results; and support dynamic parameter configuration, specifically including:
[0088] Memory unit: Used to store message data containing timing tags written by the FPGA module;
[0089] Main control unit: In response to being woken up by an external interrupt signal, it reads the message data containing timing marks in its memory unit, and sends drive signals to the actuator to execute the corresponding GOOSE response action according to the preset control logic.
[0090] Example 2
[0091] like Figure 2 The embodiment shown provides a GOOSE message processing method based on FPGA and DSP collaborative processing. Based on the system for GOOSE message processing based on DSP and FPGA collaborative processing described in Embodiment 1, the method includes the following steps:
[0092] Message reception and preprocessing specifically include:
[0093] The FPGA module receives GOOSE message data in parallel via dual-path AB networks, performs hardware-level parsing and validity filtering of the messages, and simultaneously achieves network and processing redundancy through dual-channel processing. It extracts the valid data payload from the GOOSE messages in any one of the networks, specifically:
[0094] Step 1: The message parsing and filtering unit parses the received GOOSE message to obtain the MAC address, GOOSE APPID, PDU length, and data attribute fields;
[0095] Step 2: Perform CRC check on the parsed GOOSE message. If the CRC check passes, proceed to Step 3; if the CRC check fails, mark the CRC check as an error, report the error type to the DSP main control module through the error interrupt line, and cache the error code.
[0096] The CRC verification method specifically includes:
[0097] The received GOOSE message is divided by a pre-agreed standard divisor using modulo 2 division. If the remainder is 0, the verification passes; otherwise, the verification fails.
[0098] Step 3: Perform APPID matching check. If it matches, proceed to step 4; if it does not match, mark the APPID as mismatched, report the error type to the DSP main control module through the error interrupt line, and cache the error code.
[0099] Step 4: Determine if the VLAN ID is a compliant value; if compliant, proceed to Step 5; if not compliant, mark the VLAN ID as invalid, report the error type to the DSP main control module via the error interrupt line, and cache the error code.
[0100] The IEEE 802.1Q protocol specifies that the VLAN ID is 12 bits, and the configurable legal value range is 1 to 4094. 0 and 4095 are reserved values of the protocol and cannot be used for user configuration.
[0101] Step 5: Determine if the destination MAC address matches the whitelist; if it matches, the packet is confirmed as valid, and the valid data payload is located and extracted based on the parsed PDU length and data attribute fields, and an external interrupt signal is triggered to wake up the DSP main control module; if it does not match, the packet is confirmed as invalid and discarded.
[0102] Wherein: the error interrupt line and the valid message interrupt line corresponding to the external interrupt signal are independent physical lines; the external interrupt signal is edge-triggered.
[0103] Timing markers and interrupt triggering, specifically including:
[0104] The FPGA module embeds timing synchronization tags into the valid data payload, generates message data containing timing tags, and writes it to the DSP memory unit via the EMIF bus to trigger an external interrupt.
[0105] Data reading and logical processing specifically include:
[0106] The DSP main control module responds to external interrupt signals to wake up quickly, reads the message data transmitted by the FPGA module, performs complex control logic operations, and sends drive signals to the actuator to perform corresponding GOOSE response actions according to the preset control logic.
[0107] Control execution and feedback, specifically including:
[0108] After the actuator receives the drive signal to execute the corresponding GOOSE response action, the DSP main control module generates execution result data containing the execution status and the original message identifier, and sends it back to the FPGA module through the EMIF bus. The FPGA module encapsulates the received execution result data into a GOOSE feedback message and sends it back to the GOOSE sender to complete the control closed loop verification.
[0109] Before writing message data containing timing tags, the FPGA module also needs to perform timing tag appending and CRC update operations, specifically including:
[0110] The FPGA module records the exact time of receiving the GOOSE message using a counter unit. This count value is then used as a 4-byte timestamp and appended to the end of the parsed GOOSE message data field to generate an extended message frame. Next, the 32-bit CRC checksum of the extended message frame, including the timestamp, is recalculated using the Ethernet standard CRC-32 algorithm. The calculated new CRC checksum replaces the original CRC checksum field in the extended message frame, resulting in a valid message with the updated CRC checksum. Finally, this valid message is written to the memory of the DSP main control module via the EMIF bus for subsequent reading by the DSP main control module. This operation ensures the integrity and timing traceability of the message during transmission.
[0111] Example 3
[0112] In addition to the method for GOOSE message processing based on FPGA and DSP collaborative processing provided in Embodiment 2, this embodiment also includes: parameter configuration and scenario adaptation, specifically: the DSP main control module adjusts the number of channels and protocol version parameters for GOOSE processing according to the configuration instructions of different application scenarios to realize the universality expansion of the system.
[0113] Example 4
[0114] Based on Example 2, this embodiment further optimizes the communication network link switching mechanism. The FPGA module maintains the historical fault log of the dual network links in local non-volatile memory, recording the time, duration, fault type and recovery reason of each fault, forming a historical fault feature dataset. At the same time, the bit error rate and packet loss rate of the current link are statistically analyzed at a fixed period of 10ms.
[0115] The FPGA module takes the historical fault feature dataset, current bit error rate, current packet loss rate, and current duration of continuous fault-free operation of the primary link as inputs and uses a weighted logistic regression model to construct a fault probability calculation model, outputting a link fault probability value between 0 and 1.
[0116] If the probability of failure exceeds the preset threshold (0.7), the FPGA module immediately switches the message receiving channel to the backup link and sends a pre-switching interrupt signal to the DSP main control module to synchronize the link switching status. During the switching process, the FPGA module performs timing alignment and data buffering on the messages of the dual network links to avoid GOOSE message loss or timing disorder, and ensure the continuity of protection actions.
[0117] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.
Claims
1. A system for collaborative processing of GOOSE messages based on DSP and FPGA, characterized in that, include: FPGA module and DSP main control module; The FPGA module includes: an integrated dual-channel Ethernet interface unit, a packet parsing and filtering unit, an interrupt generation unit, and a counter unit; The integrated dual-channel Ethernet interface unit is used to receive redundant GOOSE messages from two communication networks from the GOOSE sender. The message parsing and filtering unit is used to perform hardware-level parsing and filtering of redundant GOOSE messages from two communication networks in parallel, and to extract the valid data payload from any one of the communication network GOOSE messages. The counter unit is used to embed timing synchronization tags into the valid data payload to generate message data containing timing tags; The interrupt generation unit is used to wake up the DSP main control module by an external interrupt signal after the message data containing timing marks is written to the memory unit of the DSP main control module through the EMIF bus. The DSP main control module includes: a memory unit and a main control unit; The memory unit is used to store message data containing timing tags written by the FPGA module; The main control unit is used to respond to an external interrupt signal that wakes it up, read the message data containing timing marks in its memory unit, and send a drive signal to the actuator to perform the corresponding GOOSE response action according to the preset control logic.
2. The system for collaborative processing of GOOSE messages based on DSP and FPGA according to claim 1, characterized in that, The specific method for obtaining redundant GOOSE messages from the two communication networks includes: the FPGA module connects to the first and second communication networks simultaneously through an integrated dual Ethernet interface unit, and obtains redundant GOOSE messages from the GOOSE sender respectively; Wherein: the first communication network and the second communication network receive the same GOOSE message, and one communication network is selected as the primary network and the other communication network is the backup network.
3. The system for collaborative processing of GOOSE messages based on DSP and FPGA according to claim 1, characterized in that, The message parsing and filtering unit performs hardware-level parsing and filtering on redundant GOOSE messages from two communication networks in parallel, and extracts the valid data payload from any one of the communication network GOOSE messages, specifically including: Step 1: The message parsing and filtering unit parses the received GOOSE message to obtain the MAC address, GOOSE APPID, PDU length, and data attribute fields; Step 2: Perform CRC check on the parsed GOOSE message. If the CRC check passes, proceed to Step 3; if the CRC check fails, mark the CRC check as an error, report the error type to the DSP main control module through the error interrupt line, and cache the error code. Step 3: Perform APPID matching check. If it matches, proceed to step 4; if it does not match, mark the APPID as mismatched, report the error type to the DSP main control module through the error interrupt line, and cache the error code. Step 4: Determine if the VLAN ID is a compliant value; if compliant, proceed to Step 5; if not compliant, mark the VLAN ID as invalid, report the error type to the DSP main control module via the error interrupt line, and cache the error code. Step 5: Determine if the destination MAC address matches the whitelist; if it matches, it is confirmed as a valid packet, and the valid data payload is located and extracted based on the parsed PDU length and data attribute fields, and an external interrupt signal is triggered to wake up the DSP main control module; if it does not match, it is confirmed as an invalid packet and discarded; wherein: the error interrupt line and the valid packet interrupt line corresponding to the external interrupt signal are independent physical lines; the external interrupt signal is edge-triggered.
4. The system for collaborative processing of GOOSE messages based on DSP and FPGA as described in claim 1, characterized in that: The FPGA module and the DSP main control module communicate with each other via an EMIF bus. The EMIF bus is configured in asynchronous mode, with a data width of 32 bits and a clock frequency of 80MHz~120MHz. After the actuator receives the drive signal and performs the corresponding GOOSE response action, the DSP main control module generates execution result data containing the execution status and original message identifier, and sends it back to the FPGA module via the EMIF bus; The FPGA module encapsulates the received execution result data into a GOOSE feedback message and sends it back to the GOOSE sender to complete the control loop verification.
5. The system for collaborative processing of GOOSE messages based on DSP and FPGA according to claim 4, characterized in that, The GOOSE response actions include: outputting digital signals via GPIO ports, outputting analog signals via DACs, and feeding back device status via communication interfaces; the execution result data includes: action type, execution success / failure flags, and original message.
6. The system for collaborative processing of GOOSE messages based on DSP and FPGA according to claim 1, characterized in that, The FPGA module also includes: a parameter configuration interface unit, a shared register group, and a link status acquisition unit; The parameter configuration interface unit is used to respond to the configuration instructions issued by the DSP main control module and dynamically adjust the number of GOOSE message processing channels and the protocol version. A shared register set, which is mapped to the EMIF bus address space between the FPGA module and the DSP main control module, includes a configuration status register and a link status register. The link status acquisition unit is used to periodically acquire and update the connection status information of the first communication network link and the second communication network link; the parameter configuration interface unit writes the currently configured number of GOOSE processing channels and protocol version parameters into the configuration status register, and writes the connection status information of the first communication network link and the second communication network link into the link status register.
7. The system for collaborative processing of GOOSE messages based on DSP and FPGA according to claim 6, characterized in that, The DSP main control module reads the shared register group via interrupt and compares it with the configuration parameters stored locally. When the comparison results are inconsistent or an abnormal connection status of the dual network links is detected, the module reissues configuration instructions or status synchronization instructions to the FPGA module to dynamically adjust the number of GOOSE message processing channels and the protocol version.
8. The system for collaborative processing of GOOSE messages based on DSP and FPGA according to claim 1, characterized in that, Before writing message data containing timing tags, the FPGA module also needs to perform timing tag appending and CRC update operations, specifically including: The counter unit records the time count value corresponding to the received GOOSE message, and uses the time count value as a timestamp to append to the end of the data field of the corresponding parsed GOOSE message to generate an extended message frame; for the extended message frame containing the timestamp, the CRC check value of the entire extended message frame is recalculated using the Ethernet standard CRC-32 algorithm. The calculated new CRC check value is used to replace the original CRC check field in the extended message frame during parsing, resulting in a valid message with the updated CRC check value. The valid message is then written into the memory unit of the DSP main control module via the EMIF bus for subsequent reading and use by the DSP main control module.
9. The system for collaborative processing of GOOSE messages based on DSP and FPGA according to claim 1, characterized in that, When the FPGA module detects a link failure in the first or second communication network, it automatically switches to another normal network channel to receive messages and sends a link switching interrupt to the DSP main control module. The FPGA module also predicts the link failure probability based on historical link failure records and current link quality parameters. If the failure probability exceeds a threshold, it switches to the backup channel in advance.
10. A method for co-processing GOOSE messages based on DSP and FPGA, characterized in that, The system based on any one of claims 1 to 9 for collaborative processing of GOOSE messages using DSP and FPGA includes the following steps: The FPGA module receives redundant GOOSE messages from two communication networks from the GOOSE sender by integrating a dual-channel Ethernet interface unit. The message parsing and filtering unit performs hardware-level parsing and filtering on redundant GOOSE messages from two communication networks in parallel, and extracts the valid data payload from any one of the communication network GOOSE messages. The counter unit embeds timing synchronization tags into the valid data payload to generate message data containing timing tags; After the message data containing timing markers is written to the memory unit of the DSP main control module via the EMIF bus, the DSP main control module is woken up by an external interrupt signal. The main control unit of the DSP main control module is awakened in response to an external interrupt signal, reads the message data containing timing marks from the memory unit, and sends drive signals to the actuator according to the preset control logic to execute the corresponding GOOSE response action.